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lib: generic: consolidate common Xilinx code

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Move common code in Xilinx area to consolidated location to remove
redundant code.

Enable A72 and A78 build in Standalone BSP.

lib: generic: Add support for a78 with System Device Tree flow

System Device Tree workflow is AMD-Xilinx workflow whereby the BSP,
libraries and applications in software are derived from a
hardware-design. The hardware-design is used to generate a system
device tree (SDT) that describes information for Linux and other
processing environments.

The xreg/xcpu files are not generated for SDT workflow. Because of
this do not include if SDT symbol is present in BSP.

Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
This commit is contained in:
Ben Levinsky
2023-10-17 19:08:08 +02:00
committed by Arnaud Pouliquen
parent 9dd72ddbfd
commit 45a8edaddd
27 changed files with 153 additions and 646 deletions
Download Patch File Download Diff File Expand all files Collapse all files
cmake/options.cmake
+9
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@@ -74,3 +74,12 @@ option (WITH_FUNC_LINE_LOG "Log with function name, line number prefix" OFF)
option (WITH_DOC "Build with documentation" ON)
set_property (GLOBAL PROPERTY "PROJECT_EC_FLAGS" -Wall -Werror -Wextra)
if ("${PROJECT_MACHINE}" STREQUAL "zynqmp_a53" OR
"${PROJECT_MACHINE}" STREQUAL "zynqmp_a72" OR
"${PROJECT_MACHINE}" STREQUAL "zynqmp_a78" OR
"${PROJECT_MACHINE}" STREQUAL "zynqmp_r5" OR
"${PROJECT_MACHINE}" STREQUAL "microblaze_generic" OR
"${PROJECT_MACHINE}" STREQUAL "zynq7")
add_definitions( -DXLNX_PLATFORM )
endif()
lib/system/generic/CMakeLists.txt
+9 -2
View File
@@ -17,7 +17,14 @@ collect (PROJECT_LIB_SOURCES irq.c)
collect (PROJECT_LIB_SOURCES shmem.c)
collect (PROJECT_LIB_SOURCES time.c)
if (EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${PROJECT_MACHINE})
if ("${PROJECT_MACHINE}" STREQUAL "zynqmp_a53" OR
"${PROJECT_MACHINE}" STREQUAL "zynqmp_a72" OR
"${PROJECT_MACHINE}" STREQUAL "zynqmp_a78" OR
"${PROJECT_MACHINE}" STREQUAL "zynqmp_r5" OR
"${PROJECT_MACHINE}" STREQUAL "microblaze_generic" OR
"${PROJECT_MACHINE}" STREQUAL "zynq7")
add_subdirectory(xlnx)
elseif(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${PROJECT_MACHINE})
add_subdirectory(${PROJECT_MACHINE})
endif (EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${PROJECT_MACHINE})
endif()
lib/system/generic/microblaze_generic/sys.h
-43
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@@ -1,43 +0,0 @@
/*
* Copyright (c) 2017, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/microblaze_generic/sys.h
* @brief generic microblaze system primitives for libmetal.
*/
#ifndef __METAL_GENERIC_SYS__H__
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h"
#endif
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
#ifndef __METAL_GENERIC_MICROBLAZE_SYS__H__
#define __METAL_GENERIC_MICROBLAZE_SYS__H__
#include <metal/compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef METAL_INTERNAL
#ifndef XLNX_MAXIRQS
#define XLNX_MAXIRQS 32
#endif
void metal_weak sys_irq_enable(unsigned int vector);
void metal_weak sys_irq_disable(unsigned int vector);
#endif /* METAL_INTERNAL */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_MICROBLAZE_SYS__H__ */
lib/system/generic/sys.h
+4
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@@ -23,7 +23,11 @@
#include <stdarg.h>
#include <string.h>
#ifdef XLNX_PLATFORM
#include <metal/system/generic/xlnx/sys.h>
#else
#include "./@PROJECT_MACHINE@/sys.h"
#endif
#ifdef __cplusplus
extern "C" {
lib/system/generic/xlnx/CMakeLists.txt
+11
View File
@@ -0,0 +1,11 @@
if ("${PROJECT_MACHINE}" STREQUAL "microblaze_generic")
add_subdirectory(microblaze_generic)
else()
collect (PROJECT_LIB_SOURCES sys.c)
endif()
collect (PROJECT_LIB_HEADERS sys.h)
collect (PROJECT_LIB_SOURCES irq.c)
# vim: expandtab:ts=2:sw=2:smartindent
lib/system/generic/xlnx_common/irq.c → lib/system/generic/xlnx/irq.c
+7 -3
View File
@@ -5,20 +5,24 @@
*/
/*
* @file generic/xlnx_common/irq.c
* @file generic/xlnx/irq.c
* @brief generic libmetal Xilinx irq controller definitions.
*/
#include <metal/errno.h>
#include <metal/irq_controller.h>
#include <metal/sys.h>
#include <metal/log.h>
#include <metal/mutex.h>
#include <metal/list.h>
#include <metal/utilities.h>
#include <metal/alloc.h>
#include <metal/sys.h>
#include <metal/system/generic/xlnx/sys.h>
#ifdef __MICROBLAZE__
#define MAX_IRQS 32
#else
#define MAX_IRQS XLNX_MAXIRQS
#endif
static struct metal_irq irqs[MAX_IRQS]; /**< Linux IRQs array */
lib/system/generic/microblaze_generic/CMakeLists.txt → lib/system/generic/xlnx/microblaze_generic/CMakeLists.txt
-4
View File
@@ -1,10 +1,6 @@
collect (PROJECT_LIB_HEADERS sys.h)
collect (PROJECT_LIB_SOURCES sys.c)
check_include_files(xintc.h HAS_XINTC)
if (HAS_XINTC)
add_definitions(-DHAS_XINTC)
endif(HAS_XINTC)
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
lib/system/generic/microblaze_generic/sys.c → lib/system/generic/xlnx/microblaze_generic/sys.c
+3 -7
View File
@@ -5,19 +5,15 @@
*/
/*
* @file generic/microblaze_generic/sys.c
* @file generic/xlnx/microblaze_generic/sys.c
* @brief machine specific system primitives implementation.
*/
#include <metal/assert.h>
#include <metal/io.h>
#include <metal/sys.h>
#include <stdint.h>
#include <xil_cache.h>
#include <xil_exception.h>
#include <metal/system/generic/xlnx/sys.h>
#ifdef HAS_XINTC
#include <xintc.h>
#include <xparameters.h>
#endif /* HAS_XINTC */
#define MSR_IE 0x2UL /* MicroBlaze status register interrupt enable mask */
lib/system/generic/zynqmp_r5/sys.c → lib/system/generic/xlnx/sys.c
+23 -15
View File
@@ -1,25 +1,37 @@
/*
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
* Copyright (C) 2022, Advanced Micro Devices, Inc.
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/zynqmp_r5/sys.c
* @file generic/xlnx/sys.c
* @brief machine specific system primitives implementation.
*/
#include <metal/compiler.h>
#include <metal/io.h>
#include <metal/sys.h>
#include <stdint.h>
#include "xil_cache.h"
#include "xil_exception.h"
#include <metal/system/generic/xlnx/sys.h>
#include "xil_mmu.h"
/* System Device Tree (SDT) flow does not have the files generated. */
#if (defined(__aarch64__) || defined(ARMA53_32)) && !defined(SDT)
#ifdef VERSAL_NET
#include "xcpu_cortexa78.h"
#elif defined(versal)
#include "xcpu_cortexa72.h"
#else
#include "xreg_cortexa53.h"
#endif /* defined(versal) */
#elif defined(ARMR5)
#include "xil_mpu.h"
#include "xreg_cortexr5.h"
#include "xscugic.h"
#endif /* (defined(__aarch64__) || defined(ARMA53_32)) && !defined(SDT) */
void sys_irq_restore_enable(unsigned int flags)
{
@@ -30,9 +42,9 @@ unsigned int sys_irq_save_disable(void)
{
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
if (state != XIL_EXCEPTION_ALL) {
if (state != XIL_EXCEPTION_ALL)
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
}
return state;
}
@@ -60,10 +72,6 @@ void metal_weak metal_generic_default_poll(void)
metal_asm volatile("wfi");
}
/**
* The code moved to cortexr5/xil_mpu.c:Xil_MemMap()
* NULL in pa masks possible Xil_MemMap() errors.
*/
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
size_t size, unsigned int flags)
{
lib/system/generic/xlnx/sys.h
+87
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@@ -0,0 +1,87 @@
/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/xlnx/sys.h
* @brief generic xlnx system primitives for libmetal.
*/
#ifndef __METAL_GENERIC_SYS__H__
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h"
#endif
#ifndef __MICROBLAZE__
#include "xscugic.h"
#endif
#include <metal/assert.h>
#include <metal/io.h>
#include <metal/sys.h>
#include <stdint.h>
#include <metal/compiler.h>
#include <metal/utilities.h>
#include <xil_cache.h>
#include <xil_exception.h>
#include <xparameters.h>
#ifndef __METAL_GENERIC_XLNX_SYS__H__
#define __METAL_GENERIC_XLNX_SYS__H__
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __MICROBLAZE__
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
#endif
#if defined(SDT) && !defined(__MICROBLAZE__)
#define XPAR_SCUGIC_0_DIST_BASEADDR XPAR_SCUGIC_DIST_BASEADDR
#endif
/**
* @brief metal_xlnx_irq_isr
*
* Xilinx interrupt ISR can be registered to the Xilinx embeddedsw
* IRQ controller driver.
*
* @param[in] arg input argument, interrupt vector id.
*/
void metal_xlnx_irq_isr(void *arg);
/**
* @brief metal_xlnx_irq_int
*
* Xilinx interrupt controller initialization. It will initialize
* the metal Xilinx IRQ controller data structure.
*
* @return 0 for success, or negative value for failure
*/
int metal_xlnx_irq_init(void);
/* Microblaze defines these routines */
#ifdef __MICROBLAZE__
void metal_weak sys_irq_enable(unsigned int vector);
void metal_weak sys_irq_disable(unsigned int vector);
#else
static inline void sys_irq_enable(unsigned int vector)
{
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
static inline void sys_irq_disable(unsigned int vector)
{
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
#endif
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_XLNX_SYS__H__ */
lib/system/generic/xlnx_common/CMakeLists.txt
-7
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@@ -1,7 +0,0 @@
collect (PROJECT_LIB_HEADERS sys.h)
collect (PROJECT_LIB_SOURCES irq.c)
if ("${PROJECT_MACHINE}" STREQUAL "zynqmp_a53" OR "${PROJECT_MACHINE}" STREQUAL "zynqmp_a72")
add_subdirectory(zynqmp_aarch64)
endif ("${PROJECT_MACHINE}" STREQUAL "zynqmp_a53" OR "${PROJECT_MACHINE}" STREQUAL "zynqmp_a72")
lib/system/generic/xlnx_common/sys.h
-47
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@@ -1,47 +0,0 @@
/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/xlnx_common/sys.h
* @brief generic xlnx_common system primitives for libmetal.
*/
#ifndef __METAL_GENERIC_SYS__H__
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h"
#endif
#ifndef __METAL_GENERIC_XLNX_COMMON_SYS__H__
#define __METAL_GENERIC_XLNX_COMMON_SYS__H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief metal_xlnx_irq_isr
*
* Xilinx interrupt ISR can be registered to the Xilinx embeddedsw
* IRQ controller driver.
*
* @param[in] arg input argument, interrupt vector id.
*/
void metal_xlnx_irq_isr(void *arg);
/**
* @brief metal_xlnx_irq_int
*
* Xilinx interrupt controller initialization. It will initialize
* the metal Xilinx IRQ controller data structure.
*
* @return 0 for success, or negative value for failure
*/
int metal_xlnx_irq_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_XLNX_COMMON_SYS__H__ */
lib/system/generic/xlnx_common/zynqmp_aarch64/CMakeLists.txt
-2
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@@ -1,2 +0,0 @@
collect (PROJECT_LIB_HEADERS sys.h)
collect (PROJECT_LIB_SOURCES sys.c)
lib/system/generic/xlnx_common/zynqmp_aarch64/sys.c
-109
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@@ -1,109 +0,0 @@
/*
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/xlnx_common/zynqmp_aarch64/sys.c
* @brief machine specific system primitives implementation.
*/
#include <metal/compiler.h>
#include <metal/io.h>
#include <metal/sys.h>
#include <stdint.h>
#include "xil_cache.h"
#include "xil_exception.h"
#include "xil_mmu.h"
#include "xscugic.h"
#ifdef VERSAL_NET
#include "xcpu_cortexa78.h"
#elif defined(versal)
#include "xcpu_cortexa72.h"
#else
#include "xreg_cortexa53.h"
#endif /* defined(versal) */
void sys_irq_restore_enable(unsigned int flags)
{
Xil_ExceptionEnableMask(~flags);
}
unsigned int sys_irq_save_disable(void)
{
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
if (state != XIL_EXCEPTION_ALL)
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
return state;
}
void metal_machine_cache_flush(void *addr, unsigned int len)
{
if (!addr && !len)
Xil_DCacheFlush();
else
Xil_DCacheFlushRange((intptr_t)addr, len);
}
void metal_machine_cache_invalidate(void *addr, unsigned int len)
{
if (!addr && !len)
Xil_DCacheInvalidate();
else
Xil_DCacheInvalidateRange((intptr_t)addr, len);
}
/**
* @brief poll function until some event happens
*/
void metal_weak metal_generic_default_poll(void)
{
metal_asm volatile("wfi");
}
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
size_t size, unsigned int flags)
{
unsigned long section_offset;
unsigned long ttb_addr;
#if defined(__aarch64__)
unsigned long ttb_size = (pa < 4 * GB) ? 2 * MB : 1 * GB;
#else
unsigned long ttb_size = 1 * MB;
#endif /* defined(__aarch64__) */
if (!flags)
return va;
/* Ensure alignment on a section boundary */
pa &= ~(ttb_size - 1UL);
/*
* Loop through entire region of memory (one MMU section at a time).
* Each section requires a TTB entry.
*/
for (section_offset = 0; section_offset < size; ) {
/* Calculate translation table entry for this memory section */
ttb_addr = (pa + section_offset);
/* Write translation table entry value to entry address */
Xil_SetTlbAttributes(ttb_addr, flags);
#if defined(__aarch64__)
/*
* recalculate if we started below 4GB and going above in
* 64bit mode
*/
if (ttb_addr >= 4 * GB)
ttb_size = 1 * GB;
#endif
section_offset += ttb_size;
}
return va;
}
lib/system/generic/xlnx_common/zynqmp_aarch64/sys.h
-47
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@@ -1,47 +0,0 @@
/*
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/xlnx_common/zynqmp_aarch64/sys.h
* @brief generic zynqmp_aarch64 system primitives for libmetal.
*/
#ifndef __METAL_GENERIC_SYS__H__
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h"
#endif
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
#include "xscugic.h"
#ifndef __METAL_GENERIC_ZYNQMP_XLNX_COMMON_AARCH64_SYS__H__
#define __METAL_GENERIC_ZYNQMP_XLNX_COMMON_AARCH64_SYS__H__
#ifdef __cplusplus
extern "C" {
#endif
#ifdef METAL_INTERNAL
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
static inline void sys_irq_enable(unsigned int vector)
{
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
static inline void sys_irq_disable(unsigned int vector)
{
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
#endif /* METAL_INTERNAL */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_ZYNQMP_XLNX_COMMON_AARCH64_SYS__H__ */
lib/system/generic/zynq7/CMakeLists.txt
-5
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@@ -1,5 +0,0 @@
collect (PROJECT_LIB_HEADERS sys.h)
collect (PROJECT_LIB_SOURCES sys.c)
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
lib/system/generic/zynq7/sys.c
-96
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@@ -1,96 +0,0 @@
/*
* Copyright (c) 2014, Mentor Graphics Corporation
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/zynq7/sys.c
* @brief machine specific system primitives implementation.
*/
#include <metal/compiler.h>
#include <metal/io.h>
#include <metal/sys.h>
#include <stdint.h>
#include "xil_cache.h"
#include "xil_mmu.h"
#include "xil_exception.h"
#include "xscugic.h"
/* Each TTB descriptor covers a 1MB region */
#define ARM_AR_MEM_TTB_SECT_SIZE (1024*1024)
/* Mask off lower bits of addr */
#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
void sys_irq_restore_enable(unsigned int flags)
{
Xil_ExceptionEnableMask(~flags);
}
unsigned int sys_irq_save_disable(void)
{
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
if (state != XIL_EXCEPTION_ALL) {
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
}
return state;
}
void metal_machine_cache_flush(void *addr, unsigned int len)
{
if (!addr && !len)
Xil_DCacheFlush();
else
Xil_DCacheFlushRange((intptr_t)addr, len);
}
void metal_machine_cache_invalidate(void *addr, unsigned int len)
{
if (!addr && !len)
Xil_DCacheInvalidate();
else
Xil_DCacheInvalidateRange((intptr_t)addr, len);
}
/**
* @brief poll function until some event happens
*/
void metal_weak metal_generic_default_poll(void)
{
metal_asm volatile("wfi");
}
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
size_t size, unsigned int flags)
{
unsigned int section_offset;
unsigned int ttb_addr;
if (!flags)
return va;
/*
* Ensure the virtual and physical addresses are aligned on a
* section boundary
*/
pa &= ARM_AR_MEM_TTB_SECT_SIZE_MASK;
/*
* Loop through entire region of memory (one MMU section at a time).
* Each section requires a TTB entry.
*/
for (section_offset = 0; section_offset < size;
section_offset += ARM_AR_MEM_TTB_SECT_SIZE) {
/* Calculate translation table entry for this memory section */
ttb_addr = (pa + section_offset);
/* Write translation table entry value to entry address */
Xil_SetTlbAttributes(ttb_addr, flags);
}
return va;
}
lib/system/generic/zynq7/sys.h
-46
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@@ -1,46 +0,0 @@
/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/zynq7/sys.h
* @brief generic zynq7 system primitives for libmetal.
*/
#ifndef __METAL_GENERIC_SYS__H__
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h"
#endif
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
#include "xscugic.h"
#ifndef __METAL_GENERIC_ZYNQ7_SYS__H__
#define __METAL_GENERIC_ZYNQ7_SYS__H__
#ifdef __cplusplus
extern "C" {
#endif
#ifdef METAL_INTERNAL
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
static inline void sys_irq_enable(unsigned int vector)
{
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
static inline void sys_irq_disable(unsigned int vector)
{
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
#endif /* METAL_INTERNAL */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_ZYNQ7_SYS__H__ */
lib/system/generic/zynqmp_a53/CMakeLists.txt
-3
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@@ -1,3 +0,0 @@
collect (PROJECT_LIB_HEADERS sys.h)
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
lib/system/generic/zynqmp_a53/sys.c
-103
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@@ -1,103 +0,0 @@
/*
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/zynqmp_a53/sys.c
* @brief machine specific system primitives implementation.
*/
#include <metal/compiler.h>
#include <metal/io.h>
#include <metal/sys.h>
#include <metal/utilities.h>
#include <stdint.h>
#include "xil_cache.h"
#include "xil_exception.h"
#include "xil_mmu.h"
#include "xreg_cortexa53.h"
#include "xscugic.h"
void sys_irq_restore_enable(unsigned int flags)
{
Xil_ExceptionEnableMask(~flags);
}
unsigned int sys_irq_save_disable(void)
{
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
if (state != XIL_EXCEPTION_ALL) {
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
}
return state;
}
void metal_machine_cache_flush(void *addr, unsigned int len)
{
if (!addr && !len)
Xil_DCacheFlush();
else
Xil_DCacheFlushRange((intptr_t)addr, len);
}
void metal_machine_cache_invalidate(void *addr, unsigned int len)
{
if (!addr && !len)
Xil_DCacheInvalidate();
else
Xil_DCacheInvalidateRange((intptr_t)addr, len);
}
/**
* @brief poll function until some event happens
*/
void metal_weak metal_generic_default_poll(void)
{
metal_asm volatile("wfi");
}
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
size_t size, unsigned int flags)
{
unsigned long section_offset;
unsigned long ttb_addr;
#if defined(__aarch64__)
unsigned long ttb_size = (pa < 4*GB) ? 2*MB : 1*GB;
#else
unsigned long ttb_size = 1*MB;
#endif
if (!flags)
return va;
/* Ensure alignment on a section boundary */
pa &= ~(ttb_size-1UL);
/*
* Loop through entire region of memory (one MMU section at a time).
* Each section requires a TTB entry.
*/
for (section_offset = 0; section_offset < size; ) {
/* Calculate translation table entry for this memory section */
ttb_addr = (pa + section_offset);
/* Write translation table entry value to entry address */
Xil_SetTlbAttributes(ttb_addr, flags);
#if defined(__aarch64__)
/*
* recalculate if we started below 4GB and going above in
* 64bit mode
*/
if (ttb_addr >= 4*GB) {
ttb_size = 1*GB;
}
#endif
section_offset += ttb_size;
}
return va;
}
lib/system/generic/zynqmp_a53/sys.h
-16
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@@ -1,16 +0,0 @@
/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/zynqmp_a53/sys.h
* @brief generic zynqmp_a53 system primitives for libmetal.
*/
/*
* The header file is still required as generic/sys.h expects
* "./@PROJECT_MACHINE@/sys.h" to still exist.
*/
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/zynqmp_aarch64/sys.h>
lib/system/generic/zynqmp_a72/CMakeLists.txt
-3
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@@ -1,3 +0,0 @@
collect (PROJECT_LIB_HEADERS sys.h)
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
lib/system/generic/zynqmp_a72/sys.h
-17
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@@ -1,17 +0,0 @@
/*
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/zynqmp_a72/sys.h
* @brief generic zynqmp_a72 system primitives for libmetal.
*/
/*
* The header file is still required as generic/sys.h expects
* "./@PROJECT_MACHINE@/sys.h" to still exist.
*/
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/zynqmp_aarch64/sys.h>
lib/system/generic/zynqmp_a78/CMakeLists.txt
-3
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@@ -1,3 +0,0 @@
collect (PROJECT_LIB_HEADERS sys.h)
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
lib/system/generic/zynqmp_a78/sys.h
-17
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@@ -1,17 +0,0 @@
/*
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/zynqmp_a78/sys.h
* @brief generic zynqmp_a78 system primitives for libmetal.
*/
/*
* The header file is still required as generic/sys.h expects
* "./@PROJECT_MACHINE@/sys.h" to still exist.
*/
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/zynqmp_aarch64/sys.h>
lib/system/generic/zynqmp_r5/CMakeLists.txt
-5
View File
@@ -1,5 +0,0 @@
collect (PROJECT_LIB_HEADERS sys.h)
collect (PROJECT_LIB_SOURCES sys.c)
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
lib/system/generic/zynqmp_r5/sys.h
-46
View File
@@ -1,46 +0,0 @@
/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/zynqmp_r5/sys.h
* @brief generic zynqmp_r5 system primitives for libmetal.
*/
#ifndef __METAL_GENERIC_SYS__H__
#error "Include metal/sys.h instead of metal/system/generic/@PROJECT_MACHINE@/sys.h"
#endif
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
#include "xscugic.h"
#ifndef __METAL_GENERIC_ZYNQMP_R5_SYS__H__
#define __METAL_GENERIC_ZYNQMP_R5_SYS__H__
#ifdef __cplusplus
extern "C" {
#endif
#ifdef METAL_INTERNAL
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
static inline void sys_irq_enable(unsigned int vector)
{
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
static inline void sys_irq_disable(unsigned int vector)
{
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
#endif /* METAL_INTERNAL */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_ZYNQMP_R5_SYS__H__ */