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GP-7018: Fixed register opsize for mov to/from segment registers

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ghidorahrex
2026-06-29 12:35:55 -04:00
parent 144d4a1b54
commit f9ed6f4170
1 changed files with 12 additions and 2 deletions
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Ghidra/Processors/x86/data/languages/ia.sinc
+12 -2
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@@ -4035,8 +4035,18 @@ define pcodeop TaskRegister;
@ifdef IA64
:MOV Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x8b; rm64 & Reg64 ... { Reg64 = rm64; }
@endif
:MOV rm16,Sreg is vexMode=0 & byte=0x8c; rm16 & Sreg ... { rm16 = Sreg; }
:MOV Sreg,rm16 is vexMode=0 & byte=0x8e; rm16 & Sreg ... { Sreg=rm16; }
:MOV m16,Sreg is vexMode=0 & byte=0x8c; (mod != 3 & Sreg) ... & m16 { m16 = Sreg; }
:MOV Rmr16,Sreg is vexMode=0 & opsize=0 & byte=0x8c; mod=3 & Rmr16 & Sreg { Rmr16 = Sreg; }
:MOV Rmr32,Sreg is vexMode=0 & opsize=1 & byte=0x8c; mod=3 & Rmr32 & check_Rmr32_dest & Sreg { Rmr32 = zext(Sreg); build check_Rmr32_dest; }
@ifdef IA64
:MOV Rmr64,Sreg is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x8c; mod=3 & Rmr64 & Sreg { Rmr64 = zext(Sreg); }
@endif
:MOV Sreg,m16 is vexMode=0 & byte=0x8e; (mod != 3 & Sreg) ... & m16 { Sreg = m16; }
:MOV Rmr16,Sreg is vexMode=0 & opsize=0 & byte=0x8e; mod=3 & Rmr16 & Sreg { Sreg = Rmr16; }
:MOV Rmr32,Sreg is vexMode=0 & opsize=1 & byte=0x8e; mod=3 & Rmr32 & Sreg { Sreg = Rmr32(0); }
@ifdef IA64
:MOV Rmr64,Sreg is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x8e; mod=3 & Rmr64 & Sreg { Sreg = Rmr64(0); }
@endif
:MOV AL,moffs8 is vexMode=0 & byte=0xa0; AL & moffs8 { AL=moffs8; }
:MOV AX,moffs16 is vexMode=0 & opsize=0 & byte=0xa1; AX & moffs16 { AX=moffs16; }
:MOV EAX,moffs32 is vexMode=0 & opsize=1 & byte=0xa1; EAX & check_EAX_dest & moffs32 { EAX=moffs32; build check_EAX_dest; }