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AArch32: fixed ldrexd

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* fixed addr src register aliased as first dest register of a double word load causing second word load at the value of first load
This commit is contained in:
Sleigh-InSPECtor
2024-05-28 17:09:24 +09:30
committed by ghidorahrex
parent 8aa6ebe243
commit c9be1860c1
1 changed files with 4 additions and 3 deletions
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Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc
+4 -3
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@@ -2868,9 +2868,10 @@ ArmPCRelImmed12: reloff is U23=0 & immed & rotate
:ldrexd^COND Rd,Rd2,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1b & Rn & Rd & Rd2 & c0011=0xf9f
{
build COND;
Rd = *(Rn);
Rd2 = *(Rn + 4);
build COND;
local addr:4 = Rn;
Rd = *(addr);
Rd2 = *(addr + 4);
}
:ldrexh^COND Rd,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xf9f