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Merge branch 'GP-6050_ghidorahrex_PR-8544_cyrozap_fix-xtensa-be' into Ghidra_12.0

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ghidra1
2025-10-31 10:13:48 -04:00
parent c5187ad5f8 3a0736f264
commit c1ee7f257a
2 changed files with 45 additions and 43 deletions
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Ghidra/Processors/Xtensa/data/languages/xtensaArch.sinc
+21 -19
View File
@@ -120,7 +120,7 @@ define token insn(24)
# Signed and unsigned immediates. Named [us]N_L.M, where u and s denote signedness, L and M the
# least and most significant bit of the immediate in the instruction word, and N the length
# (i.e. M-L+1).
u3_21_23 = (0,2)
u3_21_23 = (1,3)
u4_20_23 = (0,3)
s8_16_23 = (0,7) signed
u8_16_23 = (0,7)
@@ -128,31 +128,32 @@ define token insn(24)
s12_12_23 = (0,11) signed
u16_8_23 = (0,15)
s8_6_23 = (0,17) signed
u1_20 = (3,3)
u1_20 = (0,0)
u2_18_19 = (4,5)
u3_17_19 = (4,6)
u3_17_19 = (5,7)
u2_16_17 = (6,7)
u1_16 = (7,7)
u1_15_15 = (8,8)
u2_14_15 = (8,9)
u3_13_15 = (8,10)
u1_16 = (4,4)
u1_15_15 = (11,11)
u2_14_15 = (10,11)
u3_13_15 = (9,11)
u4_12_15 = (8,11)
m0m1_14_14 = (9,9)
u2_12_13 = (10,11)
mw_12_13 = (10,11)
u1_12 = (11,11)
m0m1_14_14 = (10,10)
u2_12_13 = (8,9)
mw_12_13 = (8,9)
u1_12 = (8,8)
u4_8_11 = (12,15)
u8_4_11 = (12,19)
s4_8_11 = (12,15) signed
u1_7_7 = (16,16)
u1_7_7 = (19,19)
u2_6_7 = (16,17)
u3_5_7 = (16,18)
u3_5_7 = (17,19)
u4_4_7 = (16,19)
s4_4_7 = (16,19)
m2m3_6_6 = (17,17)
m2m3_6_6 = (18,18)
u_4_23 = (0,19)
t2_4_5 = (16,17)
u2_4_5 = (18,19)
u1_4 = (19,19)
u1_4 = (16,16)
;
# little-endian -> big-endian 16-bit conversion chart
@@ -169,11 +170,11 @@ define token narrowinsn(16)
n_u4_12_15 = (0,3)
n_s4_12_15 = (0,3) signed
n_u4_8_11 = (4,7)
n_u1_7 = (8,8)
n_u2_6_7 = (8,9)
n_u1_7 = (11,11)
n_u2_6_7 = (10,11)
n_u4_4_7 = (8,11)
n_s3_4_6 = (9,11)
n_u2_4_5 = (10,11)
n_s3_4_6 = (8,10)
n_u2_4_5 = (8,9)
;
@else
@@ -228,6 +229,7 @@ define token insn(24)
s4_4_7 = (4,7)
m2m3_6_6 = (6,6)
u_4_23 = (4,23)
t2_4_5 = (4,5)
u2_4_5 = (4,5)
u1_4 = (4,4)
;
Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc
+24 -24
View File
@@ -1462,7 +1462,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
}
# MUL.AD.* - Signed Multiply, pg. 432.
:mul.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x4 & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mul.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x4 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = as:2;
tm2:2 = m2m3_6_6:2;
M1 = zext(tm1);
@@ -1470,21 +1470,21 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
ACC = sext(M1:2) * sext(M2:2);
}
:mul.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x5 & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mul.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x5 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = as(2);
tm2:2 = m2m3_6_6:2;
M1 = zext(tm1);
M2 = zext(tm2);
ACC = sext(M1:2) * sext(M2:2);
}
:mul.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x6 & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mul.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x6 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = as:2;
tm2:2 = m2m3_6_6(2);
M1 = zext(tm1);
M2 = zext(tm2);
ACC = sext(M1:2) * sext(M2:2);
}
:mul.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x7 & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mul.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x7 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = as(2);
tm2:2 = m2m3_6_6(2);
M1 = zext(tm1);
@@ -1526,7 +1526,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
}
# MUL.AD.* - Signed Multiply, pg. 434.
:mul.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x4 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mul.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x4 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = m0m1_14_14:2;
tm2:2 = m2m3_6_6:2;
M1 = zext(tm1);
@@ -1534,7 +1534,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
ACC = sext(M1:2) * sext(M2:2);
}
:mul.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x5 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mul.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x5 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = m0m1_14_14(2);
tm2:2 = m2m3_6_6:2;
M1 = zext(tm1);
@@ -1542,7 +1542,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
ACC = sext(M1:2) * sext(M2:2);
}
:mul.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x6 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mul.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x6 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = m0m1_14_14:2;
tm2:2 = m2m3_6_6(2);
M1 = zext(tm1);
@@ -1550,7 +1550,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
ACC = sext(M1:2) * sext(M2:2);
}
:mul.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x7 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mul.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x7 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = m0m1_14_14(2);
tm2:2 = m2m3_6_6(2);
M1 = zext(tm1);
@@ -1590,7 +1590,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
ACC = ACC + (sext(M1:2) * sext(M2:2));
}
:mula.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x8 & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x8 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = as:2;
tm2:2 = m2m3_6_6:2;
M1 = zext(tm1);
@@ -1598,21 +1598,21 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
ACC = ACC + (sext(M1:2) * sext(M2:2));
}
:mula.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x9 & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x9 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = as(2);
tm2:2 = m2m3_6_6:2;
M1 = zext(tm1);
M2 = zext(tm2);
ACC = ACC + (sext(M1:2) * sext(M2:2));
}
:mula.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xa & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xa & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = as:2;
tm2:2 = m2m3_6_6(2);
M1 = zext(tm1);
M2 = zext(tm2);
ACC = ACC + (sext(M1:2) * sext(M2:2));
}
:mula.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xb & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xb & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = as(2);
tm2:2 = m2m3_6_6(2);
M1 = zext(tm1);
@@ -1652,7 +1652,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
ACC = ACC + (sext(M1:2) * sext(M2:2));
}
:mula.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x8 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x8 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = m0m1_14_14:2;
tm2:2 = m2m3_6_6:2;
M1 = zext(tm1);
@@ -1660,7 +1660,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
ACC = ACC + (sext(M1:2) * sext(M2:2));
}
:mula.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x9 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x9 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = m0m1_14_14(2);
tm2:2 = m2m3_6_6:2;
M1 = zext(tm1);
@@ -1668,7 +1668,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
ACC = ACC + (sext(M1:2) * sext(M2:2));
}
:mula.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xa & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xa & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = m0m1_14_14:2;
tm2:2 = m2m3_6_6(2);
M1 = zext(tm1);
@@ -1676,7 +1676,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
ACC = ACC + (sext(M1:2) * sext(M2:2));
}
:mula.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xb & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xb & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
tm1:2 = m0m1_14_14(2);
tm2:2 = m2m3_6_6(2);
M1 = zext(tm1);
@@ -1775,7 +1775,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
}
# Signed Mult/Accum, Ld/Autodec MULA.DD.*.LDDEC, pg. 446.
:mula.dd.ll.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 {
:mula.dd.ll.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 {
local vaddr:4 = as - 4;
tm1:2 = m0m1_14_14:2;
tm2:2 = m2m3_6_6:2;
@@ -1786,7 +1786,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
mw_12_13 = *:4 vaddr;
}
:mula.dd.hl.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.dd.hl.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
local vaddr:4 = as - 4;
tm1:2 = m0m1_14_14:2;
tm2:2 = m2m3_6_6(2);
@@ -1797,7 +1797,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
mw_12_13 = *:4 vaddr;
}
:mula.dd.lh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.dd.lh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
local vaddr:4 = as - 4;
tm1:2 = m0m1_14_14(2);
tm2:2 = m2m3_6_6:2;
@@ -1808,7 +1808,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
mw_12_13 = *:4 vaddr;
}
:mula.dd.hh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.dd.hh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
local vaddr:4 = as - 4;
tm1:2 = m0m1_14_14(2);
tm2:2 = m2m3_6_6(2);
@@ -1820,7 +1820,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
}
# Signed Mult/Accum, Ld/Autoinc MULA.DD.*.LDINC, pg. 448.
:mula.da.ll.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.da.ll.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
local vaddr:4 = as + 4;
tm1:2 = m0m1_14_14:2;
tm2:2 = m2m3_6_6:2;
@@ -1831,7 +1831,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
mw_12_13 = *:4 vaddr;
}
:mula.da.hl.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.da.hl.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
local vaddr:4 = as + 4;
tm1:2 = m0m1_14_14:2;
tm2:2 = m2m3_6_6(2);
@@ -1842,7 +1842,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
mw_12_13 = *:4 vaddr;
}
:mula.da.lh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.da.lh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
local vaddr:4 = as + 4;
tm1:2 = m0m1_14_14(2);
tm2:2 = m2m3_6_6:2;
@@ -1853,7 +1853,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
mw_12_13 = *:4 vaddr;
}
:mula.da.hh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
:mula.da.hh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {
local vaddr:4 = as + 4;
tm1:2 = m0m1_14_14(2);
tm2:2 = m2m3_6_6(2);