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https://github.com/NationalSecurityAgency/ghidra.git
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Merge remote-tracking branch 'origin/GP-6501_ghidorahrex_mips32_save_restore--SQUASHED' into patch
This commit is contained in:
ghidra1
@@ -502,6 +502,10 @@ define token instr(32)
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prime = (26,31)
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bit25 = (25,25)
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zero2425 = (24,25)
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svrs_xreg = (23,25)
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svrs_xregb0 = (23,23)
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svrs_xregb1 = (24,24)
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svrs_xregb2 = (25,25)
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zero2325 = (23,25)
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zero1 = (22,25)
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rs32 = (21,25)
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@@ -530,6 +534,7 @@ define token instr(32)
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off21 = (0,20) signed # 21 bit signed offset in conditional branch/link
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off16 = (0,15) signed # 16 bit signed offset in conditional branch/link
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bit21 = (21,21)
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svrs_frame_hi = (19,22)
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bitz19 = (19,20)
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pcrel = (19,20)
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pcrel2 = (18,20)
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@@ -557,8 +562,16 @@ define token instr(32)
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lohiacx = (16,19)
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nd = (17,17)
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tf = (16,16)
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svrs_aregb3 = (18,18)
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svrs_aregb2 = (17,17)
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svrs_aregb1 = (16,16)
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svrs_aregb0 = (15,15)
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svrs_areg = (15,18)
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zero1320 = (13,20)
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zero1315 = (13,15)
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save = (13,13)
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svrs_ra = (12,12)
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szero = (11,25)
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mask = (11,20)
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baser6 = (11,15)
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@@ -600,7 +613,9 @@ define token instr(32)
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ac = (11,12)
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bp = (11,12)
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bit10 = (10,10)
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svrs_s0 = (10,10)
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spec2 = (9,10)
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svrs_s1 = (9,9)
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spec3 = (8,10)
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simmed9 = (7,15)
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zero2 = (7,10)
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@@ -613,7 +628,7 @@ define token instr(32)
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fct2 = (6,10)
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zero5 = (6,10)
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wsbh = (6,10)
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svrs_frame_low = (6,9)
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bp3 = (6,8)
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sel_0608 = (6,8)
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sa2 = (6,7)
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@@ -12,6 +12,14 @@
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define token m16instr (16)
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m16_op=(11,15)
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m16_rd0_0 = (11,15)
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m16_rd0_1 = (11,15)
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m16_rd0_2 = (11,15)
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m16_rd0_3 = (11,15)
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m16_rd0_4 = (11,15)
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m16_rd0_5 = (11,15)
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m16_rd0_6 = (11,15)
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m16_rd0_7 = (11,15)
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m16_i_imm=(0,4)
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m16_rx=(8,10)
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m16_rxa=(8,10)
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@@ -74,6 +82,95 @@ attach variables [ ext_m16r32 m16_i8_r32 ] [
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t8 t9 k0 k1 gp sp s8 ra
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];
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attach variables [ m16_rd0_0 ] [
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Index Random EntryLo0 EntryLo1
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Context PageMask Wired HWREna
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BadVAddr Count EntryHi Compare
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Status Cause EPC PRId
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Config LLAddr WatchLo WatchHi
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XContext cop0_reg21 cop0_reg22 Debug
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DEPC PerfCnt ErrCtl CacheErr
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TagLo TagHi ErrorEPC DESAVE
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];
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attach variables [ m16_rd0_1 ] [
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MVPControl VPEControl TCStatus cop0_reg3.1
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ContextConfig PageGrain SRSConf0 cop0_reg7.1
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cop0_reg8.1 cop0_reg9.1 cop0_reg10.1 cop0_reg11.1
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IntCtl cop0_reg13.1 cop0_reg14.1 EBase
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Config1 cop0_reg17.1 WatchLo.1 WatchHi.1
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cop0_reg20.1 cop0_reg21.1 cop0_reg22.1 TraceControl
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cop0_reg24.1 PerfCnt.1 cop0_reg26.1 CacheErr.1
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DataLo.1 DataHi.1 cop0_reg30.1 cop0_reg31.1
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];
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attach variables [ m16_rd0_2 ] [
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MVPConf0 VPEConf0 TCBind cop0_reg3.2
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cop0_reg4.2 cop0_reg5.2 SRSConf1 cop0_reg7.2
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cop0_reg8.2 cop0_reg9.2 cop0_reg10.2 cop0_reg11.2
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SRSCtl cop0_reg13.2 cop0_reg14.2 cop0_reg15.2
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Config2 cop0_reg17.2 WatchLo.2 WatchHi.2
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cop0_reg20.2 cop0_reg21.2 cop0_reg22.2 TraceControl2
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cop0_reg24.2 PerfCnt.2 cop0_reg26.2 CacheErr.2
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TagLo.2 TagHi.2 cop0_reg30.2 cop0_reg31.2
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];
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attach variables [ m16_rd0_3 ] [
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MVPConf1 VPEConf1 TCRestart cop0_reg3.3
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cop0_reg4.3 cop0_reg5.3 SRSConf2 cop0_reg7.3
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cop0_reg8.3 cop0_reg9.3 cop0_reg10.3 cop0_reg11.3
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SRSMap cop0_reg13.3 cop0_reg14.3 cop0_reg15.3
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Config3 cop0_reg17.3 WatchLo.3 WatchHi.3
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cop0_reg20.3 cop0_reg21.3 cop0_reg22.3 UserTraceData
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cop0_reg24.3 PerfCnt.3 cop0_reg26.3 CacheErr.3
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DataLo.3 DataHi.3 cop0_reg30.3 cop0_reg31.3
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];
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attach variables [ m16_rd0_4 ] [
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cop0_reg0.4 YQMask TCHalt cop0_reg3.4
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cop0_reg4.4 cop0_reg5.4 SRSConf3 cop0_reg7.4
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cop0_reg8.4 cop0_reg9.4 cop0_reg10.4 cop0_reg11.4
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cop0_reg12.4 cop0_reg13.4 cop0_reg14.4 cop0_reg15.4
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cop0_reg16.4 cop0_reg17.4 WatchLo.4 WatchHi.4
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cop0_reg20.4 cop0_reg21.4 cop0_reg22.4 TraceBPC
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cop0_reg24.4 PerfCnt.4 cop0_reg26.4 CacheErr.4
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TagLo.4 TagHi.4 cop0_reg30.4 cop0_reg31.4
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];
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attach variables [ m16_rd0_5 ] [
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cop0_reg0.5 VPESchedule TCContext cop0_reg3.5
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cop0_reg4.5 cop0_reg5.5 SRSConf4 cop0_reg7.5
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cop0_reg8.5 cop0_reg9.5 cop0_reg10.5 cop0_reg11.5
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cop0_reg12.5 cop0_reg13.5 cop0_reg14.5 cop0_reg15.5
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cop0_reg16.5 cop0_reg17.5 WatchLo.5 WatchHi.5
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cop0_reg20.5 cop0_reg21.5 cop0_reg22.5 cop0_reg23.5
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cop0_reg24.5 PerfCnt.5 cop0_reg26.5 CacheErr.5
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DataLo.5 DataHi.5 cop0_reg30.5 cop0_reg31.5
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];
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attach variables [ m16_rd0_6 ] [
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cop0_reg0.6 VPEScheFBack TCSchedule cop0_reg3.6
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cop0_reg4.6 cop0_reg5.6 cop0_reg6.6 cop0_reg7.6
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cop0_reg8.6 cop0_reg9.6 cop0_reg10.6 cop0_reg11.6
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cop0_reg12.6 cop0_reg13.6 cop0_reg14.6 cop0_reg15.6
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cop0_reg16.6 cop0_reg17.6 WatchLo.6 WatchHi.6
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cop0_reg20.6 cop0_reg21.6 cop0_reg22.6 cop0_reg23.6
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cop0_reg24.6 PerfCnt.6 cop0_reg26.6 CacheErr.6
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TagLo.6 TagHi.6 cop0_reg30.6 cop0_reg31.6
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];
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attach variables [ m16_rd0_7 ] [
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cop0_reg0.7 VPEOpt TCScheFBack cop0_reg3.7
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cop0_reg4.7 cop0_reg5.7 cop0_reg6.7 cop0_reg7.7
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cop0_reg8.7 cop0_reg9.7 cop0_reg10.7 cop0_reg11.7
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cop0_reg12.7 cop0_reg13.7 cop0_reg14.7 cop0_reg15.7
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cop0_reg16.7 cop0_reg17.7 WatchLo.7 WatchHi.7
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cop0_reg20.7 cop0_reg21.7 cop0_reg22.7 cop0_reg23.7
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cop0_reg24.7 PerfCnt.7 cop0_reg26.7 CacheErr.7
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DataLo.7 DataHi.7 cop0_reg30.7 cop0_reg31.7
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];
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@ifdef MIPS64
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attach variables [ m16_rxa m16_rya m16_rza m16_mv_rza]
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[ s0_lo s1_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo ];
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@@ -87,6 +184,7 @@ attach variables [ ext_m16r32a m16_i8_r32a ] [
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RZ: m16_rz is m16_rz { export m16_rz; }
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@else # !MIPS64
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attach variables [ m16_rxa m16_rya m16_rza m16_mv_rza ]
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[ s0 s1 v0 v1 a0 a1 a2 a3 ];
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@@ -912,11 +1010,21 @@ E2_REGOFF: imm is ext_imm_2124 & m16_i_imm [ imm = m16_i_imm | (ext_imm_2124 <<
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m16_rx = sext( valOrig | valLoad );
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}
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:mfc0 m16_ry, m16_i_imm, ext_imm_2123 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123 & ext_imm_1620=0 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm {
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m16_ry = getCopReg(0:1,m16_i_imm:1,ext_imm_2123:1);
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m16_RD0: m16_rd0_0 is m16_rd0_0 & ext_imm_2123=0 { export m16_rd0_0; }
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m16_RD0: m16_rd0_1 is m16_rd0_1 & ext_imm_2123=1 { export m16_rd0_1; }
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m16_RD0: m16_rd0_2 is m16_rd0_2 & ext_imm_2123=2 { export m16_rd0_2; }
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m16_RD0: m16_rd0_3 is m16_rd0_3 & ext_imm_2123=3 { export m16_rd0_3; }
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m16_RD0: m16_rd0_4 is m16_rd0_4 & ext_imm_2123=4 { export m16_rd0_4; }
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m16_RD0: m16_rd0_5 is m16_rd0_5 & ext_imm_2123=5 { export m16_rd0_5; }
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m16_RD0: m16_rd0_6 is m16_rd0_6 & ext_imm_2123=6 { export m16_rd0_6; }
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m16_RD0: m16_rd0_7 is m16_rd0_7 & ext_imm_2123=7 { export m16_rd0_7; }
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:mfc0 m16_ry, m16_RD0 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123 & ext_imm_1620=0 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_RD0 {
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m16_ry = zext( m16_RD0:$(SIZETO4) );
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}
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:mtc0 m16_ry, m16_i_imm, ext_imm_2123 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123 & ext_imm_1620=1 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm {
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setCopReg(0:1,m16_ry,m16_i_imm:1,ext_imm_2123:1);
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:mtc0 m16_ry, m16_RD0 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123 & ext_imm_1620=1 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_RD0 {
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setCopReg(0:1, m16_RD0, m16_ry);
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}
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:movz m16_rx, m16_ry, ext_rb is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=1 & m16_shft_f=0b10 {
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@@ -191,11 +191,13 @@ define pcodeop special2;
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# 0100 0010 0000 0000 0000 0000 0001 1000
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:eret is $(AMODE) & prime=0x10 & fct=0x18 & bit25=1 & copfill=0 {
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return[EPC];
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JXWritePC(EPC);
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return[EPC];
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}
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:eretnc is $(AMODE) & prime=0x10 & fct=0x18 & bit25=1 & copfill=1 {
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return[EPC];
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JXWritePC(EPC);
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return[EPC];
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}
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# 0111 11ss ssst tttt mmmm mLLL LL00 0000
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@@ -423,13 +425,13 @@ define pcodeop special2;
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# 0100 1000 000t tttt iiii iiii iiii iiii
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:mfc2 RT, immed is $(AMODE) & prime=0x12 & copop=0 & RT & immed {
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tmp:$(REGSIZE) = getCopReg(2:1, immed:4);
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tmp:4 = getCopReg(2:1, immed:4);
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RT = sext( tmp );
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}
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# 0100 1000 011t tttt iiii iiii iiii iiii
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:mfhc2 RT, immed is $(AMODE) & prime=0x12 & copop=3 & RT & fs & immed {
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tmp:$(REGSIZE) = getCopReg(2:1, immed:4);
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tmp:4 = getCopReg(2:1, immed:4);
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RT = sext(tmp >> 32);
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}
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@@ -450,16 +452,20 @@ define pcodeop special2;
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}
|
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|
||||
# 0100 0000 100t tttt dddd d000 0000 0sss
|
||||
:mtc0 RTsrc, RD0, sel is $(AMODE) & prime=0x10 & copop=4 & RTsrc & RD0 & zero6=0 & sel {
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setCopReg(0:1, RD0, RTsrc, sel:1);
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:mtc0 RTsrc, RD0 is $(AMODE) & prime=0x10 & copop=4 & RTsrc & RD0 & zero6=0 {
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setCopReg(0:1, RD0, RTsrc);
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||||
}
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|
||||
# 0100 1000 100t tttt iiii iiii iiii iiii
|
||||
:mtc2 RTsrc, immed is $(AMODE) & prime=0x12 & copop=4 & RTsrc & immed {
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setCopReg(2:1, immed:4, RTsrc);
|
||||
}
|
||||
|
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:mthc0 RTsrc, RD0, sel is $(AMODE) & prime=0x10 & copop=6 & RTsrc & RD0 & zero6=0 & sel {
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setCopReg(0:1, RD0, RTsrc, sel:1);
|
||||
tmp:4 = RTsrc:$(SIZETO4);
|
||||
low:4 = RD0:4;
|
||||
val:8 = (zext(tmp) << 32) + zext(low);
|
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setCopReg(0:1, RD0, val);
|
||||
}
|
||||
|
||||
# 0100 1000 111t tttt iiii iiii iiii iiii
|
||||
@@ -1747,5 +1753,224 @@ define pcodeop SYNC;
|
||||
signalReservedInstruction(immed:2);
|
||||
}
|
||||
|
||||
rsRa: is svrs_ra=0 {}
|
||||
rsRa: ra is svrs_ra=1 & ra {
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||||
tsp = tsp-$(REGSIZE);
|
||||
MemSrcCast(ra,tsp);
|
||||
}
|
||||
|
||||
svRa: is svrs_ra=0 {}
|
||||
svRa: ra is svrs_ra=1 & ra {
|
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tsp = tsp-$(REGSIZE);
|
||||
MemDestCast(tsp,ra);
|
||||
}
|
||||
|
||||
rs_statReg: is svrs_areg {}
|
||||
rs_statReg: ",a3" is (svrs_areg=1 | svrs_areg=5 | svrs_areg=9 |svrs_areg=0xd) {
|
||||
tsp = tsp-4;
|
||||
MemSrcCast(a3,tsp);
|
||||
}
|
||||
rs_statReg: ",a2-a3" is (svrs_areg=2 | svrs_areg=6 | svrs_areg=0xa) {
|
||||
tsp = tsp-4;
|
||||
MemSrcCast(a3,tsp);
|
||||
tsp = tsp-4;
|
||||
MemSrcCast(a2,tsp);
|
||||
}
|
||||
rs_statReg: ",a1-a3" is (svrs_areg=3 | svrs_areg=7) {
|
||||
tsp = tsp-4;
|
||||
MemSrcCast(a3,tsp);
|
||||
tsp = tsp-4;
|
||||
MemSrcCast(a2,tsp);
|
||||
tsp = tsp-4;
|
||||
MemSrcCast(a1,tsp);
|
||||
}
|
||||
rs_statReg: ",a0-a3" is svrs_areg=0xb {
|
||||
tsp = tsp-4;
|
||||
MemSrcCast(a3,tsp);
|
||||
tsp = tsp-4;
|
||||
MemSrcCast(a2,tsp);
|
||||
tsp = tsp-4;
|
||||
MemSrcCast(a1,tsp);
|
||||
tsp = tsp-4;
|
||||
MemSrcCast(a0,tsp);
|
||||
}
|
||||
|
||||
rsStat: is svrs_areg=0 | svrs_areg=4 | svrs_areg=8 | svrs_areg=0xc | svrs_areg=0xe {}
|
||||
rsStat: rs_statReg is rs_statReg {
|
||||
build rs_statReg;
|
||||
}
|
||||
|
||||
|
||||
sv_statReg: is svrs_areg {}
|
||||
sv_statReg: ",a3" is (svrs_areg=1 | svrs_areg=5 | svrs_areg=9 | svrs_areg=0xd) {
|
||||
tsp = tsp-4;
|
||||
MemDestCast(tsp,a3);
|
||||
}
|
||||
sv_statReg: ",a2-a3" is (svrs_areg=2 | svrs_areg=6 | svrs_areg=0xa) {
|
||||
tsp = tsp-4;
|
||||
MemDestCast(tsp,a3);
|
||||
tsp = tsp-4;
|
||||
MemDestCast(tsp,a2);
|
||||
}
|
||||
sv_statReg: ",a1-a3" is (svrs_areg=3 | svrs_areg=7) {
|
||||
tsp = tsp-4;
|
||||
MemDestCast(tsp,a3);
|
||||
tsp = tsp-4;
|
||||
MemDestCast(tsp,a2);
|
||||
tsp = tsp-4;
|
||||
MemDestCast(tsp,a1);
|
||||
}
|
||||
sv_statReg: ",a0-a3" is svrs_areg=0xb {
|
||||
tsp = tsp-4;
|
||||
MemDestCast(tsp,a3);
|
||||
tsp = tsp-4;
|
||||
MemDestCast(tsp,a2);
|
||||
tsp = tsp-4;
|
||||
MemDestCast(tsp,a1);
|
||||
tsp = tsp-4;
|
||||
MemDestCast(tsp,a0);
|
||||
}
|
||||
|
||||
svStat: is svrs_areg=0 | svrs_areg=4 | svrs_areg=8 | svrs_areg=0xc | svrs_areg=0xe {}
|
||||
svStat: sv_statReg is sv_statReg {
|
||||
build sv_statReg;
|
||||
}
|
||||
|
||||
sv_areg1: is svrs_aregb2=0 {}
|
||||
sv_areg1: "a0," is svrs_aregb2=1 {
|
||||
ptr:$(REGSIZE) = sp;
|
||||
MemDestCast(ptr,a0);
|
||||
}
|
||||
|
||||
sv_areg2: sv_areg1 is sv_areg1 { build sv_areg1; }
|
||||
sv_areg2: "a0-a1," is svrs_aregb3=1 & svrs_aregb2=0 & (svrs_aregb1=0 | svrs_aregb0=0) {
|
||||
ptr:$(REGSIZE) = sp;
|
||||
MemDestCast(ptr,a0);
|
||||
ptr = sp+4;
|
||||
MemDestCast(ptr,a1);
|
||||
}
|
||||
|
||||
sv_areg3: sv_areg2 is sv_areg2 { build sv_areg2; }
|
||||
sv_areg3: "a0-a2," is svrs_aregb3=1 & svrs_aregb2=1 & svrs_aregb1=0 {
|
||||
ptr:$(REGSIZE) = sp;
|
||||
MemDestCast(ptr,a0);
|
||||
ptr = sp+4;
|
||||
MemDestCast(ptr,a1);
|
||||
ptr = sp+8;
|
||||
MemDestCast(ptr,a2);
|
||||
}
|
||||
|
||||
sv_areg4: sv_areg3 is sv_areg3 { build sv_areg3; }
|
||||
sv_areg4: "a0-a3," is svrs_areg=0xe {
|
||||
ptr:$(REGSIZE) = sp;
|
||||
MemDestCast(ptr,a0);
|
||||
ptr = sp+4;
|
||||
MemDestCast(ptr,a1);
|
||||
ptr = sp+8;
|
||||
MemDestCast(ptr,a2);
|
||||
ptr = sp+12;
|
||||
MemDestCast(ptr,a3);
|
||||
}
|
||||
|
||||
svAregs: is svrs_aregb3=0 | svrs_areg=0xb | svrs_areg=0xf {}
|
||||
svAregs: sv_areg4 is sv_areg4 {
|
||||
build sv_areg4;
|
||||
}
|
||||
|
||||
rs_s0: is svrs_s0 {}
|
||||
rs_s0: is svrs_s0=1 { tsp = tsp-$(REGSIZE); MemSrcCast(s0,tsp); }
|
||||
|
||||
rs_s1: is svrs_s1 {}
|
||||
rs_s1: is svrs_s1=1 { tsp = tsp-$(REGSIZE); MemSrcCast(s1,tsp); }
|
||||
|
||||
rs_s8: is svrs_xreg=6 {}
|
||||
rs_s8: is svrs_xreg { tsp = tsp-$(REGSIZE); MemSrcCast(s8,tsp); }
|
||||
|
||||
rs_s7: is svrs_xreg=5 {}
|
||||
rs_s7: is rs_s8 { build rs_s8; tsp = tsp-$(REGSIZE); MemSrcCast(s7,tsp); }
|
||||
|
||||
rs_s6: is svrs_xreg=4 {}
|
||||
rs_s6: is rs_s7 { build rs_s7; tsp = tsp-$(REGSIZE); MemSrcCast(s6,tsp); }
|
||||
|
||||
rs_s5: is svrs_xreg=3 {}
|
||||
rs_s5: is rs_s6 { build rs_s6; tsp = tsp-$(REGSIZE); MemSrcCast(s5,tsp); }
|
||||
|
||||
rs_s4: is svrs_xreg=2 {}
|
||||
rs_s4: is rs_s5 { build rs_s5; tsp = tsp-$(REGSIZE); MemSrcCast(s4,tsp); }
|
||||
|
||||
rs_s3: is svrs_xreg=1 {}
|
||||
rs_s3: is rs_s4 { build rs_s4; tsp = tsp-$(REGSIZE); MemSrcCast(s3,tsp); }
|
||||
|
||||
rs_s2: is svrs_xreg=0 {}
|
||||
rs_s2: is rs_s3 { build rs_s3; tsp = tsp-$(REGSIZE); MemSrcCast(s2,tsp); }
|
||||
|
||||
rsXsregs: is svrs_s0=0 & svrs_s1=0 & svrs_xreg=0 {}
|
||||
rsXsregs: ","svrs_xreg is svrs_s0 & svrs_s1 & svrs_xreg & rs_s2 & rs_s1 & rs_s0 {
|
||||
build rs_s2;
|
||||
build rs_s1;
|
||||
build rs_s0;
|
||||
}
|
||||
|
||||
sv_s0: is svrs_s0 {}
|
||||
sv_s0: is svrs_s0=1 { tsp = tsp-$(REGSIZE); MemDestCast(tsp,s0);}
|
||||
|
||||
sv_s1: is svrs_s1 {}
|
||||
sv_s1: is svrs_s1=1 { tsp = tsp-$(REGSIZE); MemDestCast(tsp,s1); }
|
||||
|
||||
sv_s8: is svrs_xreg=6 {}
|
||||
sv_s8: is svrs_xreg { tsp = tsp-$(REGSIZE); MemDestCast(tsp,s8); }
|
||||
|
||||
sv_s7: is svrs_xreg=5 {}
|
||||
sv_s7: is sv_s8 { build sv_s8; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s7); }
|
||||
|
||||
sv_s6: is svrs_xreg=4 {}
|
||||
sv_s6: is sv_s7 { build sv_s7; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s6); }
|
||||
|
||||
sv_s5: is svrs_xreg=3 {}
|
||||
sv_s5: is sv_s6 { build sv_s6; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s5); }
|
||||
|
||||
sv_s4: is svrs_xreg=2 {}
|
||||
sv_s4: is sv_s5 { build sv_s5; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s4); }
|
||||
|
||||
sv_s3: is svrs_xreg=1 {}
|
||||
sv_s3: is sv_s4 { build sv_s4; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s3); }
|
||||
|
||||
sv_s2: is svrs_xreg=0 {}
|
||||
sv_s2: is sv_s3 { build sv_s3; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s2); }
|
||||
|
||||
svXsregs: is svrs_s0=0 & svrs_s0=0 & svrs_xreg=0 {}
|
||||
svXsregs: ","svrs_xreg is svrs_s0 & svrs_s1 & svrs_xreg & sv_s0 & sv_s1 & sv_s2 {
|
||||
build sv_s2;
|
||||
build sv_s1;
|
||||
build sv_s0;
|
||||
}
|
||||
|
||||
svFramesize: ,val is svrs_frame_hi=0 & svrs_frame_low=0 [val = 128; ] {export *[const]:2 val;}
|
||||
svFramesize: ,val is svrs_frame_hi & svrs_frame_low [val = ((svrs_frame_hi << 4) | svrs_frame_low) << 3;] {export *[const]:2 val;}
|
||||
|
||||
|
||||
:save svRa^svXsregs^svAregs^svFramesize is $(AMODE) & REL6=1 & prime=0x1c & fct=0x1f & save=0x01 & svRa & svXsregs & svAregs & svStat & svFramesize {
|
||||
tsp = sp;
|
||||
build svAregs;
|
||||
build svRa;
|
||||
build svXsregs;
|
||||
build svStat;
|
||||
build svFramesize;
|
||||
|
||||
tmp:2 = svFramesize;
|
||||
sp = sp - zext(tmp);
|
||||
}
|
||||
|
||||
:restore rsRa^rsXsregs^rsStat^svFramesize is $(AMODE) & REL6=1 & prime=0x1c & fct=0x1f & save=0x00 & rsRa & rsXsregs & rsStat & svFramesize {
|
||||
build svFramesize;
|
||||
|
||||
tmp:2 = svFramesize;
|
||||
tsp = sp+zext(tmp);
|
||||
|
||||
build rsRa;
|
||||
build rsXsregs;
|
||||
build rsStat;
|
||||
|
||||
sp = sp+zext(tmp);
|
||||
}
|
||||
@include "mipsfloat.sinc"
|
||||
|
||||
Reference in New Issue
Block a user