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Merge remote-tracking branch 'origin/patch' into Ghidra_12.2

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ghidra1
2026-09-10 19:10:58 -04:00
parent c96374c281 841266bbeb
commit b374d71ef1
7 changed files with 1451 additions and 177 deletions
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Ghidra/Processors/Hexagon/data/languages/hexagon.sinc
+223 -163
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Ghidra/Processors/Hexagon/data/languages/hexagon.slaspec
+5 -3
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@@ -1,12 +1,14 @@
# Qualcomm Hexagon (V79) and HVX (V79)
## KNOWN ISSUES
# 1. Shift amounts may be positive or negative, however in some cases no special handling
# is provided for negative shift amounts.
# 1. Shift amounts may be positive or negative. The register-form shifts model the
# 7-bit signed shift amount explicitly; other forms may still assume a positive amount.
# 2. There are many complex instructions with unimplemented pcode or simple custom pcodeops
#
## NOTES
# 1. Implementation includes V73 system registers, instruction set may be incomplete
# 1. Implementation includes V73 system registers, instruction set may be incomplete.
# Decode additionally covers the V66 ZReg matrix extension and V81 valign4 as
# decode-only stubs (unimpl pcode).
# 2. HVX register pairs may be access with a vector-swap mode (lsb of 5-bit field is 1)
# introduced with Hexagon v67.
# 3. HVX vector register size is 128-bytes (see defines below), paired size is 256-bytes,
Ghidra/Processors/Hexagon/data/languages/hexagon_float.sinc
+4 -4
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@@ -438,7 +438,7 @@ define pcodeop sfinvsqrtaPred; # Pe = exponent class bits of the approximation
# 1 1 0 1 0 1 1 0 0 1 i - - - - - P P i i i i i i i i i d d d d d
:sfmake^":neg" Rd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x19 & Uimm16_21_0513 & Rd5 & $(END_PACKET) {
Rd5 = int2float(-Uimm16_21_0513); # TODO: assumed functionality
Rd5 = (1 << 31) | (((127 - 6) << 23) + (zext(Uimm16_21_0513) << 17));
build EndPacket;
}
@@ -448,7 +448,7 @@ define pcodeop sfinvsqrtaPred; # Pe = exponent class bits of the approximation
# 1 1 0 1 0 1 1 0 0 0 i - - - - - P P i i i i i i i i i d d d d d
:sfmake^":pos" Rd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x18 & Uimm16_21_0513 & Rd5 & $(END_PACKET) {
Rd5 = int2float(Uimm16_21_0513); # TODO: assumed functionality
Rd5 = ((127 - 6) << 23) + (zext(Uimm16_21_0513) << 17);
build EndPacket;
}
@@ -628,7 +628,7 @@ define pcodeop sfinvsqrtaPred; # Pe = exponent class bits of the approximation
# 1 1 0 1 1 0 0 1 0 1 i - - - - - P P i i i i i i i i i d d d d d
:dfmake^":neg" Rdd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x25 & Uimm16_21_0513 & Rdd5 & $(END_PACKET) {
Rdd5 = int2float(-Uimm16_21_0513); # TODO: assumed functionality
Rdd5 = (1:8 << 63) | (((1023:8 - 6) << 52) + (zext(Uimm16_21_0513) << 46));
build EndPacket;
}
@@ -638,7 +638,7 @@ define pcodeop sfinvsqrtaPred; # Pe = exponent class bits of the approximation
# 1 1 0 1 1 0 0 1 0 0 i - - - - - P P i i i i i i i i i d d d d d
:dfmake^":pos" Rdd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x24 & Uimm16_21_0513 & Rdd5 & $(END_PACKET) {
Rdd5 = int2float(Uimm16_21_0513); # TODO: assumed functionality
Rdd5 = ((1023:8 - 6) << 52) + (zext(Uimm16_21_0513) << 46);
build EndPacket;
}
Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc
+16 -7
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@@ -1,7 +1,7 @@
# Qualcomm Hexagon HVX Instruction Set
# NOTES:
# - HVX implementation has been updated through V79
# - HVX implementation has been updated through V81
# - HVX hardware supports either 64-byte or 128-byte vector lengths. See hexagon.slaspec for
# default length of 128-bytes.
@@ -1625,8 +1625,8 @@ define pcodeop vsub_VwVw_carryResult;
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - 0 1 1 P P 1 u u u u u 1 1 1 d d d d d
:assign Vd5,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x7 & Vd5 & Vu_0812 & $(END_PACKET) [ cond=0; ] {
Vd5 = Vu_0812; # Vd5 handles unconditional commit
:assign Vd5,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x3 & op13=0x1 & op0507=0x7 & Vd5 & Vu_0812 & $(END_PACKET) [ cond=0; ] {
Vd5 = Vu_0812; # Vd5 handles unconditional commit
build EndPacket;
}
@@ -1635,7 +1635,7 @@ define pcodeop vsub_VwVw_carryResult;
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 0 d d d d d
:assign Vd5tmp,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x6 & Vd5tmp & Vu_0812 & $(END_PACKET) {
:assign Vd5tmp,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x1 & op13=0x0 & op0507=0x6 & Vd5tmp & Vu_0812 & $(END_PACKET) {
Vd5tmp = Vu_0812;
build EndPacket;
}
@@ -6028,7 +6028,7 @@ define pcodeop Vub_vasr_WuhVub_rnd_sat;
define pcodeop Vsf_equals_Vqf32;
:assign VdSF_0004,VuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x1 & op1617=0x0 & op13=0x1 & op0507=0x0 & VdSF_0004 & VuQF32_0812 & $(END_PACKET) {
:assign VdSF_0004,VuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x4 & op13=0x1 & op0507=0x0 & VdSF_0004 & VuQF32_0812 & $(END_PACKET) {
VdSF_0004 = Vsf_equals_Vqf32(VuQF32_0812);
build EndPacket;
}
@@ -6040,7 +6040,7 @@ define pcodeop Vsf_equals_Vqf32;
define pcodeop Vhf_equals_Vqf16;
:assign VdHF_0004,VuQF16_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x1 & op1617=0x0 & op13=0x1 & op0507=0x3 & VdHF_0004 & VuQF16_0812 & $(END_PACKET) {
:assign VdHF_0004,VuQF16_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x4 & op13=0x1 & op0507=0x3 & VdHF_0004 & VuQF16_0812 & $(END_PACKET) {
VdHF_0004 = Vhf_equals_Vqf16(VuQF16_0812);
build EndPacket;
}
@@ -6052,7 +6052,7 @@ define pcodeop Vhf_equals_Vqf16;
define pcodeop Vhf_equals_Wqf32;
:assign VdHF_0004,VuuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x1 & op1617=0x0 & op13=0x1 & op0507=0x6 & VdHF_0004 & VuuQF32_0812 & $(END_PACKET) {
:assign VdHF_0004,VuuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x4 & op13=0x1 & op0507=0x6 & VdHF_0004 & VuuQF32_0812 & $(END_PACKET) {
VdHF_0004 = Vhf_equals_Wqf32(VuuQF32_0812);
build EndPacket;
}
@@ -6877,4 +6877,13 @@ define pcodeop scatter_release;
scatter_release(VAlignMemAddrRxAIMu);
}
# (hvx,1) valign4 -- "Vd = valign4(Vu, Vv, Rt8)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 0 0 0 0 z z t t t P P 0 u u u u u 1 0 1 d d d d d
define pcodeop valign4;
:valign4 Vd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op2123=0x0 & op13=0x0 & op0507=0x5 & Vd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) {
Vd5 = valign4(Vu_0812,Vz_1923,rt1618);
}
Ghidra/Processors/Hexagon/src/test/java/ghidra/app/plugin/assembler/sleigh/HexagonPacketCoverageTest.java
+419
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Ghidra/Processors/Hexagon/src/test/java/ghidra/app/plugin/assembler/sleigh/HexagonShiftEdgeCasesTest.java
+538
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Ghidra/Processors/Hexagon/src/test/java/ghidra/app/plugin/assembler/sleigh/HexagonStubCoverageTest.java
+246
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