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GP-358_emteere Minor RISV code review changes

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emteere
2020-11-03 15:49:40 -05:00
committed by ghidra1
parent 5fe0f16e10
commit b1e75e0d6f
7 changed files with 51 additions and 65 deletions
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Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc
+28 -28
View File
@@ -2,11 +2,11 @@
# csrrc d,E,s 00003073 0000707f SIMPLE (0, 0)
:csrrc rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op1519
:csrrc rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op1519
{
local tmprs1:$(XLEN) = rs1;
local oldcsr:$(XLEN) = csr:$(XLEN);
rd = oldcsr;
rdDst = oldcsr;
local tmp:$(XLEN) = op1519;
if (tmp == 0) goto inst_next;
local newcsr:$(XLEN) = oldcsr & ~tmprs1;
@@ -15,10 +15,10 @@
# csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0)
:csrrci rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7
:csrrci rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7
{
local oldcsr:$(XLEN) = csr:$(XLEN);
rd = oldcsr;
rdDst = oldcsr;
local tmp:$(XLEN) = op1519;
if (tmp == 0) goto inst_next;
csr = csr & ~tmp;
@@ -26,11 +26,11 @@
# csrrs d,E,s 00002073 0000707f SIMPLE (0, 0)
:csrrs rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519
:csrrs rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519
{
local tmprs1 = rs1;
local oldcsr:$(XLEN) = csr:$(XLEN);
rd = oldcsr;
rdDst = oldcsr;
local tmp:$(XLEN) = op1519;
if (tmp == 0) goto inst_next;
csr = csr | tmprs1;
@@ -38,10 +38,10 @@
# csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0)
:csrrsi rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6
:csrrsi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6
{
local oldcsr:$(XLEN) = csr:$(XLEN);
rd = oldcsr;
rdDst = oldcsr;
local tmp:$(XLEN) = op1519;
if (tmp == 0) goto inst_next;
csr = csr | tmp;
@@ -49,44 +49,44 @@
# csrrw d,E,s 00001073 0000707f SIMPLE (0, 0)
:csrrw rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op1519
:csrrw rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op1519
{
local tmprs1:$(XLEN) = rs1;
local oldcsr:$(XLEN) = csr:$(XLEN);
local tmp:$(XLEN) = op1519;
csr = tmprs1;
if (tmp == 0) goto inst_next;
rd = oldcsr;
rdDst = oldcsr;
}
# csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0)
:csrrwi rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5
:csrrwi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5
{
local oldcsr:$(XLEN) = csr:$(XLEN);
local tmp:$(XLEN) = op1519;
csr = tmp;
if (tmp == 0) goto inst_next;
rd = oldcsr;
rdDst = oldcsr;
}
# frcsr d 00302073 fffff07f SIMPLE (0, 0)
:frcsr rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60
:frcsr rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60
{
rd = fcsr;
rdDst = fcsr;
}
# frflags d 00102073 fffff07f SIMPLE (0, 0)
:frflags rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x20
:frflags rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x20
{
rd = zext(fflags[0,5]);
rdDst = zext(fflags[0,5]);
}
# frrm d 00202073 fffff07f SIMPLE (0, 0)
:frrm rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x40
:frrm rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x40
{
rd = frm;
rdDst = frm;
}
# fscsr s 00301073 fff07fff SIMPLE (0, 0)
@@ -97,9 +97,9 @@
}
# fscsr d,s 00301073 fff0707f SIMPLE (0, 0)
:fscsr rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3
:fscsr rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3
{
rd = fcsr;
rdDst = fcsr;
fcsr = rs1;
}
@@ -112,16 +112,16 @@
}
# fsflags d,s 00101073 fff0707f SIMPLE (0, 0)
:fsflags rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x1
:fsflags rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x1
{
rd = zext(fflags[0,5]);
rdDst = zext(fflags[0,5]);
fflags[0,5] = rs1[0,5];
}
# fsflagsi d,Z 00105073 fff0707f SIMPLE (0, 0)
:fsflagsi rd,op1519 is op1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x1
:fsflagsi rdDst,op1519 is op1519 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x1
{
rd = zext(fflags[0,5]);
rdDst = zext(fflags[0,5]);
local tmp:1 = op1519:1;
fflags[0,5] = tmp[0,5];
}
@@ -142,16 +142,16 @@
}
# fsrm d,s 00201073 fff0707f SIMPLE (0, 0)
:fsrm rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x2
:fsrm rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x2
{
rd = zext(frm[0,3]);
rdDst = zext(frm[0,3]);
frm[0,3] = rs1[0,3];
}
# fsrmi d,Z 00205073 fff0707f SIMPLE (0, 0)
:fsrmi rd,op1519 is op1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x2
:fsrmi rdDst,op1519 is op1519 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x2
{
rd = zext(frm[0,3]);
rdDst = zext(frm[0,3]);
local tmp:1 = op1519:1;
frm[0,3] = tmp[0,3];
}
Ghidra/Processors/RISCV/data/languages/riscv.ldefs
+11 -11
View File
@@ -6,7 +6,7 @@
endian="little"
size="64"
variant="RV64I"
version="1.1"
version="1.2"
slafile="riscv.lp64d.sla"
processorspec="RV64I.pspec"
id="RISCV:LE:64:RV64I">
@@ -18,7 +18,7 @@
endian="little"
size="64"
variant="RV64IC"
version="1.1"
version="1.2"
slafile="riscv.lp64d.sla"
processorspec="RV64IC.pspec"
id="RISCV:LE:64:RV64IC">
@@ -30,7 +30,7 @@
endian="little"
size="64"
variant="RV64G"
version="1.1"
version="1.2"
slafile="riscv.lp64d.sla"
processorspec="RV64G.pspec"
id="RISCV:LE:64:RV64G">
@@ -42,7 +42,7 @@
endian="little"
size="64"
variant="RV64GC"
version="1.1"
version="1.2"
slafile="riscv.lp64d.sla"
processorspec="RV64GC.pspec"
id="RISCV:LE:64:RV64GC">
@@ -54,7 +54,7 @@
endian="little"
size="64"
variant="default"
version="1.1"
version="1.2"
slafile="riscv.lp64d.sla"
processorspec="RV64GC.pspec"
id="RISCV:LE:64:default">
@@ -66,7 +66,7 @@
endian="little"
size="32"
variant="RV32I"
version="1.1"
version="1.2"
slafile="riscv.ilp32d.sla"
processorspec="RV32I.pspec"
id="RISCV:LE:32:RV32I">
@@ -78,7 +78,7 @@
endian="little"
size="32"
variant="RV32IC"
version="1.1"
version="1.2"
slafile="riscv.ilp32d.sla"
processorspec="RV32IC.pspec"
id="RISCV:LE:32:RV32IC">
@@ -90,7 +90,7 @@
endian="little"
size="32"
variant="RV32IMC"
version="1.1"
version="1.2"
slafile="riscv.ilp32d.sla"
processorspec="RV32IMC.pspec"
id="RISCV:LE:32:RV32IMC">
@@ -102,7 +102,7 @@
endian="little"
size="32"
variant="RV32G"
version="1.1"
version="1.2"
slafile="riscv.ilp32d.sla"
processorspec="RV32G.pspec"
id="RISCV:LE:32:RV32G">
@@ -114,7 +114,7 @@
endian="little"
size="32"
variant="RV32GC"
version="1.1"
version="1.2"
slafile="riscv.ilp32d.sla"
processorspec="RV32GC.pspec"
id="RISCV:LE:32:RV32GC">
@@ -126,7 +126,7 @@
endian="little"
size="32"
variant="default"
version="1.1"
version="1.2"
slafile="riscv.ilp32d.sla"
processorspec="RV32GC.pspec"
id="RISCV:LE:32:default">
Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc
+7 -15
View File
@@ -1,10 +1,5 @@
# RISC-V Privileged Instructions
define pcodeop dret;
define pcodeop hret;
define pcodeop mret;
define pcodeop sret;
define pcodeop uret;
define pcodeop wfi;
define pcodeop sfence.vm;
define pcodeop sfence.vma;
@@ -15,33 +10,30 @@ define pcodeop sfence.vma;
# dret 7b200073 ffffffff SIMPLE (0, 0)
:dret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0xf640
{
dret();
}
# hret 20200073 ffffffff SIMPLE (0, 0)
:hret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x4040
{
hret();
return [dpc];
}
# hret 20200073 ffffffff SIMPLE (0, 0)
# deprecated instruction in latest spec
#:hret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x4040
# mret 30200073 ffffffff SIMPLE (0, 0)
:mret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x6040
{
mret();
return [mepc];
}
# sret 10200073 ffffffff SIMPLE (0, 0)
:sret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2040
{
sret();
return [sepc];
}
# uret 00200073 ffffffff SIMPLE (0, 0)
:uret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x40
{
uret();
return [uepc];
}
Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc
+1 -4
View File
@@ -43,13 +43,12 @@ define register offset=0x2000 size=$(XLEN) [ zero ra sp gp tp t0 t1 t2
s0 s1 a0 a1 a2 a3 a4 a5
a6 a7 s2 s3 s4 s5 s6 s7
s8 s9 s10 s11 t3 t4 t5 t6 ];
@if FPSIZE != "0"
# register numbers 0x1020-0x103f
define register offset=0x3000 size=$(FLEN) [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7
fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5
fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7
fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];
@endif
#TODO fix
@define VLEN "256"
@@ -799,7 +798,6 @@ attach variables [ cr0204s cr0709s cd0709s ]
[ s0 s1 a0 a1 a2 a3 a4 a5 ];
@if FPSIZE != "0"
attach variables [ fr0711 fr1519 fr2024 fr2731 ]
[ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5
fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];
@@ -810,7 +808,6 @@ attach variables [ cfr0206 cfr0711 ]
attach variables [ cfr0204s cfr0709s ]
[ fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 ];
@endif
attach variables [ v0711 v1519 v2024 ]
Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc
+3 -1
View File
@@ -342,7 +342,9 @@
# unimp c0001073 ffffffff SIMPLE (0, 0)
:unimp is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op1531=0x18000
{
unimp();
local excaddr:$(XLEN) = inst_start;
local target:$(XLEN) = unimp(excaddr);
goto [target];
}
Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc
-2
View File
@@ -99,7 +99,6 @@
@endif
@if ADDRSIZE == "32"
@if FPSIZE != "0"
# c.flw CD,Ck(Cs) 00006000 0000e003 DWORD|DREF (32, 4)
:c.flw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x3 & clwimm
{
@@ -115,7 +114,6 @@
cfrd = *[ram]:$(SFLEN) ea;
}
@endif
@endif
@if ADDRSIZE == "32" || ADDRSIZE == "64"
@if FPSIZE == "64"
Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
+1 -4
View File
@@ -32,6 +32,7 @@ rs3: zero is zero & op2731=0 { export 0:$(XLEN); }
rd: r0711 is r0711 { export r0711; }
rd: zero is r0711 & zero & op0711=0 { export 0:$(XLEN); }
rdDst: r0711 is r0711 { export r0711; }
rs1W: r1519 is r1519 { local tmp:$(WXLEN) = r1519:$(WXLEN); export tmp; }
@@ -75,7 +76,6 @@ rdL: zero is r0711 & zero & op0711=0 { export 0:8; }
# fmt: ".q" is op2526=3 { export $(QFLEN):1; }
@if FPSIZE != "0"
frd: fr0711 is fr0711 { export fr0711; }
frs1: fr1519 is fr1519 { export fr1519; }
frs2: fr2024 is fr2024 { export fr2024; }
@@ -102,7 +102,6 @@ macro fassignS(dest, src) {
dest = zext(src);
@endif
}
@endif
macro assignW(dest, src) {
@@ -184,13 +183,11 @@ crd: zero is zero & cop0711=0 { export 0:$(XLEN); }
crs2: cr0206 is cr0206 { export cr0206; }
crs2: zero is cr0206 & zero & cop0206=0 { export 0:$(XLEN); }
@if FPSIZE != "0"
cfrs1: cfr0711 is cfr0711 { export cfr0711; }
cfrd: cfr0711 is cfr0711 { export cfr0711; }
cfrs2: cfr0206 is cfr0206 { export cfr0206; }
@endif
#ATTN Not doing tables for the RVC registers since there is no
# zero register to worry about