Merge remote-tracking branch 'origin/GP-1234_ghidorahrex_update_processor_manuals--SQUASHED'

2026-05-29 03:45:30 +08:00 · 2021-09-16 07:54:32 -04:00
parent d590f10238 3cbe4ee78d
commit b0a223e17b
2 changed files with 699 additions and 688 deletions
@@ -1578,120 +1578,123 @@ XSAVES64, 2040
 XSETBV, 2043
 XTEST, 2045

-@24594.pdf [AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Rev 3.28 September 2019 (24594)]
-BLCFILL, 129
-BLCI, 131
-BLCIC, 133
-BLCMSK, 135
-BLCS, 137
-BLSIC, 143
-CLZERO, 183
-LLWPCB, 247
-LOOPNZ, 252
-LOOPZ, 252
-LWPINS, 254
-LWPVAL, 256
-MONITORX, 263
-MWAITX, 289
-PREFETCH, 314
-SLWPCB, 369
-T1MSKC, 377
-TZMSK, 383
-UD0, 385
-UD1, 385
-UD2, 385
-CLGI, 400
-INVLPGA, 410
-SKINIT, 449
-STGI, 457
-VMLOAD, 476
-VMMCALL, 478
-VMRUN, 479
-VMSAVE, 484
-@26568.pdf [AMD64 Architecture Programmer's Manual Volume 4: 128-Bit and 256-Bit Media Instructions, Rev 3.23 Feb 2019 (26568)]
+@24594.pdf [AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Rev 3.32 March 2021 (24594)]
+BLCFILL, 135
+BLCI, 137
+BLCIC, 139
+BLCMSK, 141
+BLCS, 143
+BLSFILL, 145
+BLSIC, 149
+CLZERO, 190
+LLWPCB, 255
+LOOPNZ, 260
+LOOPZ, 260
+LWPINS, 262
+LWPVAL, 264
+MONITORX, 271
+MWAITX, 297
+PREFETCH, 323
+SLWPCB, 380
+T1MSKC, 388
+TZMSK, 394
+UD0, 396
+UD1, 396
+UD2, 396
+CLGI, 414
+INVLPGA, 428
+SKINIT, 496
+STGI, 504
+VMLOAD, 524
+VMMCALL, 526
+VMRUN, 527
+VMSAVE, 532
+
+@26568.pdf [AMD64 Architecture Programmer's Manual Volume 4: 128-Bit and 256-Bit Media Instructions, Rev 3.24 May 2020 (26568)]
 EXTRQ, 181
 INSERTQ, 196
 MOVNTSD, 260
 MOVNTSS, 262
-VPHSUBD, 387
-VPOR, 473
-VSTMXCSR, 614
-VBROADCASTI128, 638
-VFMADDPD, 655
-VFMADDPS, 658
-VFMADDSD, 661
-VFMADDSS, 664
-VFMADDSUBPD, 667
-VFMADDSUBPS, 670
-VFMADDPD, 673
-VFMADDPS, 676
-VFMSUBPD, 679
-VFMSUBPS, 682
-VFMSUBSD, 685
-VFMSUBSS, 688
-VFNMADDPD, 691
-VFNMADDPS, 694
-VFNMADDSD, 697
-VFNMADDSS, 700
-VFNMSUBPD, 703
-VFNMSUBPS, 706
-VFNMSUBSD, 709
-VFNMSUBSS, 712
-VFRCZPD, 715
-VFRCZPS, 717
-VFRCZSD, 719
-VFRCZSS, 721
-VPCMOV, 749
-VPCOMB, 751
-VPCOMD, 753
-VPCOMQ, 755
-VPCOMUB, 757
-VPCOMUD, 759
-VPCOMUQ, 761
-VPCOMUW, 763
-VPCOMW, 765
-VPERMIL2PD, 773
-VPERMIL2PS, 777
-VPHADDBD, 802
-VPHADDBQ, 804
-VPHADDBW, 806
-VPHADDDQ, 808
-VPHADDUBD, 810
-VPHADDUBQ, 812
-VPHADDUBW, 814
-VPHADDUDQ, 816
-VPHADDUWD, 818
-VPHADDUWQ, 820
-VPHADDWD, 822
-VPHADDWQ, 824
-VPHSUBBW, 826
-VPHSUBDQ, 828
-VPHSUBWD, 830
-VPMACSDD, 832
-VPMACSDQH, 834
-VPMACSDQL, 836
-VPMACSSDD, 838
-VPMACSSDQH, 840
-VPMACSSDQL, 842
-VPMACSSWD, 844
-VPMACSSWW, 846
-VPMACSWD, 848
-VPMACSWW, 850
-VPMADCSSWD, 852
-VPMADCSWD, 854
-VPPERM, 860
-VPROTB, 862
-VPROTD, 864
-VPROTQ, 866
-VPROTW, 868
-VPSHAB, 870
-VPSHAD, 872
-VPSHAQ, 874
-VPSHAW, 876
-VPSHLB, 878
-VPSHLD, 880
-VPSHLQ, 882
-VPSHLW, 884
+VPHSUBD, 388
+VPOR, 474
+VSTMXCSR, 615
+VBROADCASTI128, 639
+VFMADDPD, 656
+VFMADDPS, 659
+VFMADDSD, 662
+VFMADDSS, 665
+VFMADDSUBPD, 668
+VFMADDSUBPS, 671
+VFMADDPD, 674
+VFMADDPS, 677
+VFMSUBPD, 680
+VFMSUBPS, 683
+VFMSUBSD, 686
+VFMSUBSS, 689
+VFNMADDPD, 692
+VFNMADDPS, 695
+VFNMADDSD, 698
+VFNMADDSS, 701
+VFNMSUBPD, 704
+VFNMSUBPS, 707
+VFNMSUBSD, 710
+VFNMSUBSS, 713
+VFRCZPD, 716
+VFRCZPS, 718
+VFRCZSD, 720
+VFRCZSS, 722
+VPCMOV, 750
+VPCOMB, 752
+VPCOMD, 754
+VPCOMQ, 756
+VPCOMUB, 758
+VPCOMUD, 760
+VPCOMUQ, 762
+VPCOMUW, 764
+VPCOMW, 766
+VPERMIL2PD, 774
+VPERMIL2PS, 778
+VPHADDBD, 803
+VPHADDBQ, 805
+VPHADDBW, 807
+VPHADDDQ, 809
+VPHADDUBD, 811
+VPHADDUBQ, 813
+VPHADDUBW, 815
+VPHADDUDQ, 817
+VPHADDUWD, 819
+VPHADDUWQ, 821
+VPHADDWD, 823
+VPHADDWQ, 825
+VPHSUBBW, 827
+VPHSUBDQ, 829
+VPHSUBWD, 831
+VPMACSDD, 833
+VPMACSDQH, 835
+VPMACSDQL, 837
+VPMACSSDD, 839
+VPMACSSDQH, 841
+VPMACSSDQL, 843
+VPMACSSWD, 845
+VPMACSSWW, 847
+VPMACSWD, 849
+VPMACSWW, 851
+VPMADCSSWD, 853
+VPMADCSWD, 855
+VPPERM, 861
+VPROTB, 863
+VPROTD, 865
+VPROTQ, 867
+VPROTW, 869
+VPSHAB, 871
+VPSHAD, 873
+VPSHAQ, 875
+VPSHAW, 877
+VPSHLB, 879
+VPSHLD, 881
+VPSHLQ, 883
+VPSHLW, 885
+
@26569_APM_V5.pdf [AMD64 Architecture Programmer's Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions, Rev 3.15 May 2018 (26569)]
 FEMMS, 48
 PAVGUSB, 100
@@ -1718,6 +1721,7 @@ PI2FD, 164
 PI2FW, 166
 PMULHRW, 182
 PSWAPD, 231
+
@AMD64_128-bit_SSE5_Instructions.pdf [AMD64 Technology 128-Bit SSE5 Instruction Set, Rev 3.01 August 2007 (43479)]
 COMPD, 32
 COMPS, 35
@@ -1796,6 +1800,7 @@ PSHLB, 231
 PSHLD, 233
 PSHLQ, 236
 PSHLW, 238
+
@326019-074.pdf [Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3C: System Programming Guide, Part 3, 326019-074US April 2021]
 INVEPT, 157
 INVVPID, 160