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Merge remote-tracking branch 'origin/patch'

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Ryan Kurtz
2025-05-02 15:17:36 -04:00
parent 8985f7d526 838c773253
commit 87b1dbb8dc
3 changed files with 42 additions and 23 deletions
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Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
+23 -15
View File
@@ -2257,24 +2257,31 @@ is b_2531=0x6b & b_2324=1 & b_2122=1 & b_1620=0x1f & b_1015=0 & aa_Xn=31 & b_000
# CONSTRUCT xd503309f/mask=xfffff3ff MATCHED 3 DOCUMENTED OPCODES
# AUNIT --inst xd503309f/mask=xfffff3ff --status nodest
:dsb CRm_CRx
is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_CRx & CRm_32 & CRm_10=0 & Op2=4 & Rt=0x1f
:dsb CRm_dbarrier_op
is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10 & Op2=4 & Rt=0x1f
{
types:1 = 0x0;
types:1 = CRm_10;
domain:1 = CRm_32;
DataSynchronizationBarrier(domain, types);
nXS:1 = 0;
DataSynchronizationBarrier(domain, types, nXS);
}
# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503309f/mask=xfffff0ff
# CONSTRUCT xd503309f/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES
# AUNIT --inst xd503309f/mask=xfffff0ff --status nodest
:dsb CRm_dbarrier_op
is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10=2 & Op2=4 & Rt=0x1f
:ssbb
is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_CRx=0 & CRm_32 & CRm_10 & Op2=4 & Rt=0x1f
{
types:1 = 0x3; #MBReqTypes_All
types:1 = CRm_10;
domain:1 = CRm_32;
DataSynchronizationBarrier(domain, types);
nXS:1 = 0;
DataSynchronizationBarrier(domain, types, nXS);
}
:pssbb
is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_CRx=4 & CRm_32 & CRm_10 & Op2=4 & Rt=0x1f
{
types:1 = CRm_10;
domain:1 = CRm_32;
nXS:1 = 0;
DataSynchronizationBarrier(domain, types, nXS);
}
# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503323f/mask=xfffff3ff
@@ -2283,11 +2290,12 @@ is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CR
# b_0031=11010101000000110011..1000111111
:dsb CRm_32
is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10 & Op2=1 & Rt=0x1f
is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_32 & CRm_10=2 & Op2=1 & Rt=0x1f
{
types:1 = CRm_10;
types:1 = 0x3; # MBReqTypes_All
domain:1 = CRm_32;
DataSynchronizationBarrier(domain, types);
nXS:1 = 1;
DataSynchronizationBarrier(domain, types, nXS);
}
# C6.2.118 EON (shifted register) page C6-1468 line 87407 MATCH x4a200000/mask=x7f200000
Ghidra/Processors/ARM/data/languages/ARM.sinc
+1 -1
View File
@@ -23,7 +23,7 @@ define register offset=0x0078 size=1 [ ISAModeSwitch ]; # generic name for TB T
@define FPSCR_V "fpscr[28,1]"
@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)
define register offset=0x00B0 size=4 [ fpsid fpscr fpexc mvfr0 mvfr1 ];
define register offset=0x00B0 size=4 [ fpsid fpscr fpexc mvfr0 mvfr1 mvfr2 fpinst fpinst2 ];
@endif
define register offset=0x0100 size=10 [ fp0 fp1 fp2 fp3 fp4 fp5 fp6 fp7 ]; # eight 80-bit floating registers
Ghidra/Processors/ARM/data/languages/ARMneon.sinc
+18 -7
View File
@@ -4326,10 +4326,19 @@ define pcodeop VectorCopyNarrow;
@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)
:vmrs^COND VRd,fpscr is COND & ( ($(AMODE) & ARMcond=1 & c1627=0xef1 & c0011=0xa10) |
($(TMODE_E) & thv_c1627=0xef1 & thv_c0011=0xa10)) & fpscr & VRd
vmrsReg: fpsid is (($(AMODE) & c1619=0) | (TMode=1 & thv_c1619=0)) & fpsid { export fpsid; }
vmrsReg: fpscr is (($(AMODE) & c1619=1) | (TMode=1 & thv_c1619=1)) & fpscr { export fpscr; }
vmrsReg: mvfr2 is (($(AMODE) & c1619=5) | (TMode=1 & thv_c1619=5)) & mvfr2 { export mvfr2; }
vmrsReg: mvfr1 is (($(AMODE) & c1619=6) | (TMode=1 & thv_c1619=6)) & mvfr1 { export mvfr1; }
vmrsReg: mvfr0 is (($(AMODE) & c1619=7) | (TMode=1 & thv_c1619=7)) & mvfr0 { export mvfr0; }
vmrsReg: fpexc is (($(AMODE) & c1619=8) | (TMode=1 & thv_c1619=8)) & fpexc { export fpexc; }
vmrsReg: fpinst is (($(AMODE) & c1619=9) | (TMode=1 & thv_c1619=9)) & fpinst { export mvfr1; }
vmrsReg: fpinst2 is (($(AMODE) & c1619=0xa) | (TMode=1 & thv_c1619=0xa)) & fpinst2 { export mvfr0; }
:vmrs^COND VRd,vmrsReg is COND & ( ($(AMODE) & ARMcond=1 & c2027=0xef & c0011=0xa10) |
($(TMODE_E) & thv_c2027=0xef & thv_c0011=0xa10)) & vmrsReg & VRd
{
VRd = fpscr;
VRd = vmrsReg;
}
apsr: "apsr" is epsilon {}
@@ -4344,11 +4353,13 @@ apsr: "apsr" is epsilon {}
OV = $(FPSCR_V);
}
:vmsr^COND fpscr,VRd is ( ($(AMODE) & ARMcond=1 & c1627=0xee1 & c0011=0xa10) |
($(TMODE_E) & thv_c1627=0xee1 & thv_c0011=0xa10)
) & COND & VRd & fpscr
:vmsr^COND vmrsReg,VRd is ( ($(AMODE) & ARMcond=1 & c2027=0xee & c0011=0xa10) |
($(TMODE_E) & thv_c2027=0xee & thv_c0011=0xa10)
) & COND & VRd & vmrsReg
{
fpscr = VRd;
vmrsReg = VRd;
}
@endif # VFPv2 || VFPv3 || SIMD