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SuperH4: fix fpu registers order

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This commit is contained in:
MetalliC
2025-05-23 15:03:55 +03:00
committed by GitHub
parent cd30a59a1c
commit 53d7e1608f
1 changed files with 6 additions and 6 deletions
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Ghidra/Processors/SuperH4/data/languages/SuperH4_le.cspec
+6 -6
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@@ -29,30 +29,30 @@
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="fr5"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="fr4"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="fr7"/>
<register name="fr5"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="fr6"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="fr9"/>
<register name="fr7"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="fr8"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="fr11"/>
<register name="fr9"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="fr10"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="fr11"/>
</pentry>
<pentry minsize="5" maxsize="8" metatype="float">
<register name="dr4"/>
</pentry>