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Merge remote-tracking branch 'origin/GP-5780_ghidorahrex_x86_missing_instructions--SQUASHED' into patch

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Ryan Kurtz
2026-06-08 15:31:29 -04:00
parent c1b34a9ec1 2c3ca6df4c
commit 41a8a40901
7 changed files with 324 additions and 7 deletions
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Ghidra/Processors/x86/certification.manifest
+2
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@@ -22,6 +22,7 @@ data/languages/bmi1.sinc||GHIDRA||||END|
data/languages/bmi2.sinc||GHIDRA||||END|
data/languages/cet.sinc||GHIDRA||||END|
data/languages/clwb.sinc||GHIDRA||||END|
data/languages/cmpccxadd.sinc||GHIDRA||||END|
data/languages/fma.sinc||GHIDRA||||END|
data/languages/ia.sinc||GHIDRA||||END|
data/languages/lockable.sinc||GHIDRA||||END|
@@ -61,6 +62,7 @@ data/languages/old/x86smmV2.trans||GHIDRA||||END|
data/languages/old/x86smmV3.lang||GHIDRA||||END|
data/languages/old/x86smmV3.trans||GHIDRA||||END|
data/languages/pclmulqdq.sinc||GHIDRA||||END|
data/languages/rao.sinc||GHIDRA||||END|
data/languages/rdrand.sinc||GHIDRA||||END|
data/languages/sgx.sinc||GHIDRA||||END|
data/languages/sha.sinc||GHIDRA||||END|
Ghidra/Processors/x86/data/languages/cmpccxadd.sinc
+27
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@@ -0,0 +1,27 @@
####
#### CMPccXADD instructions
####
@ifdef IA64
:CMP^cc^"XADD" m32, Reg32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32 & row=0xe & cc; Reg32 ... & m32 {
local op1 = m32;
local op2 = Reg32;
subflags(op1, op2);
local tmp = op1 - op2;
resultflags(tmp);
build cc;
if (!cc) goto inst_next;
m32 = vexVVVV_r32;
}
:CMP^cc^"XADD" m64, Reg64, vexVVVV_r64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64 & row=0xe & cc; Reg64 ... & m64 {
local op1 = m64;
local op2 = Reg64;
subflags(op1, op2);
local tmp = op1 - op2;
resultflags(tmp);
build cc;
if (!cc) goto inst_next;
m64 = vexVVVV_r64;
}
@endif
Ghidra/Processors/x86/data/languages/ia.sinc
+204 -7
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File diff suppressed because it is too large Load Diff
Ghidra/Processors/x86/data/languages/rao.sinc
+44
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@@ -0,0 +1,44 @@
####
#### RAO-INT instructions
####
:AADD m32,Reg32 is vexMode=0 & rexprefix=0 & $(PRE_NO) & byte=0x0F; byte=0x38; byte=0xFC; Reg32 ... & m32 {
m32 = m32 + Reg32;
}
@ifdef IA64
:AADD m64,Reg64 is $(REX_W) & $(PRE_NO) & byte=0x0F; byte=0x38; byte=0xFC; Reg64 ... & m64 {
m64 = m64 + Reg64;
}
@endif
:AAND m32,Reg32 is vexMode=0 & rexprefix=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xFC; Reg32 ... & m32 {
m32 = m32 & Reg32;
}
@ifdef IA64
:AAND m64,Reg64 is $(REX_W) & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xFC; Reg64 ... & m64 {
m64 = m64 & Reg64;
}
@endif
:AOR m32,Reg32 is vexMode=0 & rexprefix=0 & $(PRE_F2) & byte=0x0F; byte=0x38; byte=0xFC; Reg32 ... & m32 {
m32 = m32 | Reg32;
}
@ifdef IA64
:AOR m64,Reg64 is $(REX_W) & $(PRE_F2) & byte=0x0F; byte=0x38; byte=0xFC; Reg64 ... & m64 {
m64 = m64 | Reg64;
}
@endif
:AXOR m32,Reg32 is vexMode=0 & rexprefix=0 & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xFC; Reg32 ... & m32 {
m32 = m32 ^ Reg32;
}
@ifdef IA64
:AXOR m64,Reg64 is $(REX_W) & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xFC; Reg64 ... & m64 {
m64 = m64 ^ Reg64;
}
@endif
Ghidra/Processors/x86/data/languages/sgx.sinc
+45
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@@ -255,3 +255,48 @@ define pcodeop enclu_unknown;
<done>
}
define pcodeop enclv_edecvirtchild;
define pcodeop enclv_eincvirtchild;
define pcodeop enclv_esetcontext;
define pcodeop enclv_unknown;
:ENCLV is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc0 {
if ( EAX != 0x0 ) goto <leaf_1>;
RAX = enclv_edecvirtchild( RBX, RCX );
ZF = (RAX != 0);
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<leaf_1>
if ( EAX != 0x1 ) goto <leaf_2>;
RAX = enclv_eincvirtchild( RBX, RCX );
ZF = (RAX != 0);
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<leaf_2>
if ( EAX != 0x2 ) goto <unknown>;
RAX = enclv_esetcontext( RCX, RDX );
ZF = (RAX != 0);
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<unknown>
enclv_unknown();
<done>
}
Ghidra/Processors/x86/data/languages/x86-64.slaspec
+1
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@@ -3,4 +3,5 @@
with : lockprefx=0 {
@include "sgx.sinc"
@include "fma.sinc"
@include "cmpccxadd.sinc"
}
Ghidra/Processors/x86/data/languages/x86.slaspec
+1
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@@ -18,4 +18,5 @@ with : lockprefx=0 {
@include "smx.sinc"
@include "cet.sinc"
@include "rdrand.sinc"
@include "rao.sinc"
}