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'origin/GP-3789_ghidorahrex_PowerPC_move_legacy_instructions' into patch
(Closes #5243)
This commit is contained in:
Ryan Kurtz
2024-01-18 06:59:19 -05:00
parent 8a76c1bb57 c37276f08b
commit 363ee48dfa
6 changed files with 732 additions and 746 deletions
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Ghidra/Processors/PowerPC/certification.manifest
+1
View File
@@ -14,6 +14,7 @@ data/languages/evx.sinc||GHIDRA||||END|
data/languages/g2.sinc||GHIDRA||||END|
data/languages/lmwInstructions.sinc||GHIDRA||||END|
data/languages/lswInstructions.sinc||GHIDRA||||END|
data/languages/mulhwInstructions.sinc||GHIDRA||||END|
data/languages/old/oldPPC.lang||GHIDRA||||END|
data/languages/old/oldPPC.trans||GHIDRA||||END|
data/languages/ppc.dwarf||GHIDRA||||END|
Ghidra/Processors/PowerPC/data/languages/4xx.sinc
+126
View File
@@ -5,3 +5,129 @@
S = dataCacheRead(RA_OR_ZERO,B);
}
# ========================================================================
# PowerISA II: Chapter 10. Legacy Move Assist Instruction [Category: Legacy Move Assist]
# CMT: Determine Leftmost Zero Byte
# FORM: X-form
# binutils: 476.d: 1a4: 7c 83 28 9c dlmzb r3,r4,r5
# binutils: titan.d: 158: 7c 22 00 9c dlmzb r2,r1,r0
define pcodeop DetermineLeftmostZeroByte;
:dlmzb S,A,B is OP=31 & S & A & B & XOP_1_10=78 & Rc=0
{
# search from left for the first occurrence of null byte
# low 32 bits of RS concatenated with low 32 bits of RB
@ifdef BIT_64
tmpD:8 = zext( S:4 );
@else
tmpD:8 = zext( S );
@endif
tmpD = tmpD << 32;
@ifdef BIT_64
tmpD = tmpD | zext( B:4 );
@else
tmpD = tmpD | zext( B );
@endif
tmpX:8 = 0;
<unmatched>
if ( tmpX == 8 ) goto <done_searching>;
tmpX = tmpX + 1;
if ( ( ( tmpD << ( (tmpX-1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto <unmatched>;
<done_searching>
# place byte number in register A and low 7 bits of XER
@ifdef BIT_64
A = tmpX;
XER = ( XER & 0xFFFFFFFFFFFFFF80 ) | tmpX;
@else
A = tmpX:4;
XER = ( XER & 0xFFFFFF80 ) | tmpX:4;
@endif
}
# PowerISA II: Chapter 10. Legacy Move Assist Instruction [Category: Legacy Move Assist]
# CMT: Determine Leftmost Zero Byte
# FORM: X-form
# binutils: 476.d: 1a8: 7c 83 28 9d dlmzb\. r3,r4,r5
# binutils: titan.d: 15c: 7c 22 00 9d dlmzb\. r2,r1,r0
define pcodeop DetermineLeftmostZeroByte1;
:dlmzb. S,A,B is OP=31 & S & A & B & XOP_1_10=78 & Rc=1
{
# search from left for the first occurrence of null byte
# low 32 bits of RS concatenated with low 32 bits of RB
@ifdef BIT_64
tmpD:8 = zext( S:4 );
@else
tmpD:8 = zext( S );
@endif
tmpD = tmpD << 32;
@ifdef BIT_64
tmpD = tmpD | zext( B:4 );
@else
tmpD = tmpD | zext( B );
@endif
tmpX:8 = 0;
tmpY:8 = 0;
<unmatched>
if ( tmpX == 8 ) goto <done_searching>;
tmpX = tmpX + 1;
if ( ( ( tmpD << ( (tmpX - 1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto <unmatched>;
# matched
tmpY = 1;
<done_searching>
# place byte number in register A and low 7 bits of XER
@ifdef BIT_64
A = tmpX;
XER = ( XER & 0xFFFFFFFFFFFFFF80 ) | tmpX;
@else
A = tmpX:4;
XER = ( XER & 0xFFFFFF80 ) | tmpX:4;
@endif
# Rc section
# Set bit 35 of CR to SO
cr0 = (cr0 & 0xe) | zext( xer_so & 1);
# Set bits 32:34 of CR
if ( tmpY != 1 ) goto <no_match>;
if ( tmpX >= 5 ) goto <high_bytes>;
cr0 = ( cr0 & 0x1 ) | 4;
goto <finished>;
<high_bytes>
cr0 = ( cr0 & 0x1 ) | 8;
goto <finished>;
<no_match>
cr0 = ( cr0 & 0x1 ) | 2;
<finished>
}
#icread 0,r0 0x7c 00 07 cc
:icread RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=998 & BIT_0=0 & RA_OR_ZERO
{
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
instructionCacheRead(ea);
}
Ghidra/Processors/PowerPC/data/languages/mulhwInstructions.sinc
+583
View File
File diff suppressed because it is too large Load Diff
Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
+21 -21
View File
@@ -5,7 +5,7 @@
endian="big"
size="32"
variant="default"
version="1.5"
version="1.6"
slafile="ppc_32_be.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -21,7 +21,7 @@
endian="little"
size="32"
variant="default"
version="1.5"
version="1.6"
slafile="ppc_32_le.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -37,7 +37,7 @@
endian="big"
size="64"
variant="default"
version="1.5"
version="1.6"
slafile="ppc_64_be.sla"
processorspec="ppc_64.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -53,7 +53,7 @@
endian="big"
size="32"
variant="64-32addr"
version="1.5"
version="1.6"
slafile="ppc_64_be.sla"
processorspec="ppc_64.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -69,7 +69,7 @@
endian="little"
size="32"
variant="64-32addr"
version="1.5"
version="1.6"
slafile="ppc_64_le.sla"
processorspec="ppc_64.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -86,7 +86,7 @@
endian="little"
size="64"
variant="default"
version="1.5"
version="1.6"
slafile="ppc_64_le.sla"
processorspec="ppc_64.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -101,7 +101,7 @@
endian="big"
size="32"
variant="4xx"
version="1.5"
version="1.6"
slafile="ppc_32_4xx_be.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -116,7 +116,7 @@
endian="little"
size="32"
variant="4xx"
version="1.5"
version="1.6"
slafile="ppc_32_4xx_le.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -132,7 +132,7 @@
endian="big"
size="32"
variant="MPC8270"
version="1.5"
version="1.6"
slafile="ppc_32_quicciii_be.sla"
processorspec="ppc_32_mpc8270.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -147,7 +147,7 @@
endian="big"
size="32"
variant="PowerQUICC-III"
version="1.5"
version="1.6"
slafile="ppc_32_quicciii_be.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -162,7 +162,7 @@
endian="little"
size="32"
variant="PowerQUICC-III"
version="1.5"
version="1.6"
slafile="ppc_32_quicciii_le.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -178,7 +178,7 @@
endian="big"
size="32"
variant="PowerQUICC-III-e500"
version="1.5"
version="1.6"
slafile="ppc_32_e500_be.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -194,7 +194,7 @@
endian="little"
size="32"
variant="PowerQUICC-III-e500"
version="1.5"
version="1.6"
slafile="ppc_32_e500_le.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -240,7 +240,7 @@
endian="big"
size="32"
variant="PowerISA-64-32addr"
version="1.5"
version="1.6"
slafile="ppc_64_isa_be.sla"
processorspec="ppc_64.pspec"
manualindexfile="../manuals/PowerISA.idx"
@@ -256,7 +256,7 @@
endian="little"
size="32"
variant="PowerISA-64-32addr"
version="1.5"
version="1.6"
slafile="ppc_64_isa_le.sla"
processorspec="ppc_64.pspec"
manualindexfile="../manuals/PowerISA.idx"
@@ -273,7 +273,7 @@
endian="big"
size="32"
variant="PowerISA-Altivec-64-32addr"
version="1.5"
version="1.6"
slafile="ppc_64_isa_altivec_be.sla"
processorspec="ppc_64.pspec"
manualindexfile="../manuals/PowerISA.idx"
@@ -289,7 +289,7 @@
endian="little"
size="32"
variant="PowerISA-Altivec-64-32addr"
version="1.5"
version="1.6"
slafile="ppc_64_isa_altivec_le.sla"
processorspec="ppc_64.pspec"
manualindexfile="../manuals/PowerISA.idx"
@@ -306,7 +306,7 @@
endian="big"
size="64"
variant="PowerISA-Altivec"
version="1.5"
version="1.6"
slafile="ppc_64_isa_altivec_be.sla"
processorspec="ppc_64.pspec"
manualindexfile="../manuals/PowerISA.idx"
@@ -321,7 +321,7 @@
endian="little"
size="64"
variant="PowerISA-Altivec"
version="1.5"
version="1.6"
slafile="ppc_64_isa_altivec_le.sla"
processorspec="ppc_64.pspec"
manualindexfile="../manuals/PowerISA.idx"
@@ -336,7 +336,7 @@
endian="big"
size="32"
variant="PowerISA-VLE-64-32addr"
version="1.5"
version="1.6"
slafile="ppc_64_isa_vle_be.sla"
processorspec="ppc_64.pspec"
manualindexfile="../manuals/PowerISA.idx"
@@ -351,7 +351,7 @@
endian="big"
size="32"
variant="PowerISA-VLE-Altivec-64-32addr"
version="1.5"
version="1.6"
slafile="ppc_64_isa_altivec_vle_be.sla"
processorspec="ppc_64.pspec"
manualindexfile="../manuals/PowerISA.idx"
Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc
+1 -605
View File
File diff suppressed because it is too large Load Diff
Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
-120
View File
@@ -784,126 +784,6 @@ define pcodeop MoveFromDeviceControlRegisterUserModeIndexed;
}
# ========================================================================
# PowerISA II: Chapter 10. Legacy Move Assist Instruction [Category: Legacy Move Assist]
# CMT: Determine Leftmost Zero Byte
# FORM: X-form
# binutils: 476.d: 1a4: 7c 83 28 9c dlmzb r3,r4,r5
# binutils: titan.d: 158: 7c 22 00 9c dlmzb r2,r1,r0
define pcodeop DetermineLeftmostZeroByte;
:dlmzb S,A,B is OP=31 & S & A & B & XOP_1_10=78 & Rc=0
{
# search from left for the first occurrence of null byte
# low 32 bits of RS concatenated with low 32 bits of RB
@ifdef BIT_64
tmpD:8 = zext( S:4 );
@else
tmpD:8 = zext( S );
@endif
tmpD = tmpD << 32;
@ifdef BIT_64
tmpD = tmpD | zext( B:4 );
@else
tmpD = tmpD | zext( B );
@endif
tmpX:8 = 0;
<unmatched>
if ( tmpX == 8 ) goto <done_searching>;
tmpX = tmpX + 1;
if ( ( ( tmpD << ( (tmpX-1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto <unmatched>;
<done_searching>
# place byte number in register A and low 7 bits of XER
@ifdef BIT_64
A = tmpX;
XER = ( XER & 0xFFFFFFFFFFFFFF80 ) | tmpX;
@else
A = tmpX:4;
XER = ( XER & 0xFFFFFF80 ) | tmpX:4;
@endif
}
# PowerISA II: Chapter 10. Legacy Move Assist Instruction [Category: Legacy Move Assist]
# CMT: Determine Leftmost Zero Byte
# FORM: X-form
# binutils: 476.d: 1a8: 7c 83 28 9d dlmzb\. r3,r4,r5
# binutils: titan.d: 15c: 7c 22 00 9d dlmzb\. r2,r1,r0
define pcodeop DetermineLeftmostZeroByte1;
:dlmzb. S,A,B is OP=31 & S & A & B & XOP_1_10=78 & Rc=1
{
# search from left for the first occurrence of null byte
# low 32 bits of RS concatenated with low 32 bits of RB
@ifdef BIT_64
tmpD:8 = zext( S:4 );
@else
tmpD:8 = zext( S );
@endif
tmpD = tmpD << 32;
@ifdef BIT_64
tmpD = tmpD | zext( B:4 );
@else
tmpD = tmpD | zext( B );
@endif
tmpX:8 = 0;
tmpY:8 = 0;
<unmatched>
if ( tmpX == 8 ) goto <done_searching>;
tmpX = tmpX + 1;
if ( ( ( tmpD << ( (tmpX - 1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto <unmatched>;
# matched
tmpY = 1;
<done_searching>
# place byte number in register A and low 7 bits of XER
@ifdef BIT_64
A = tmpX;
XER = ( XER & 0xFFFFFFFFFFFFFF80 ) | tmpX;
@else
A = tmpX:4;
XER = ( XER & 0xFFFFFF80 ) | tmpX:4;
@endif
# Rc section
# Set bit 35 of CR to SO
cr0 = (cr0 & 0xe) | zext( xer_so & 1);
# Set bits 32:34 of CR
if ( tmpY != 1 ) goto <no_match>;
if ( tmpX >= 5 ) goto <high_bytes>;
cr0 = ( cr0 & 0x1 ) | 4;
goto <finished>;
<high_bytes>
cr0 = ( cr0 & 0x1 ) | 8;
goto <finished>;
<no_match>
cr0 = ( cr0 & 0x1 ) | 2;
<finished>
}
# ========================================================================
# PowerISA II: 4.6.5 Floating-Point Move Instructions