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GT-3523_emteere_PR-1430_Alackaj_master fixing patterns file and review

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for merge into master
This commit is contained in:
emteere
2020-06-26 14:54:05 -04:00
parent cfc4c8c92c
commit 2a30ec7112
2 changed files with 21 additions and 46 deletions
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Ghidra/Processors/V850/certification.manifest
+7 -4
View File
@@ -1,10 +1,6 @@
##VERSION: 2.0
Module.manifest||GHIDRA||||END|
build.gradle||GHIDRA||||END|
data/languages/V850.cspec||GHIDRA||||END|
data/languages/V850.ldefs||GHIDRA||||END|
data/languages/V850.pspec||GHIDRA||||END|
data/languages/V850.slaspec||GHIDRA||||END|
data/languages/Helpers/Conditions.sinc||GHIDRA||||END|
data/languages/Helpers/Extras.sinc||GHIDRA||||END|
data/languages/Helpers/Macros.sinc||GHIDRA||||END|
@@ -16,4 +12,11 @@ data/languages/Instructions/Float.sinc||GHIDRA||||END|
data/languages/Instructions/Load_Store.sinc||GHIDRA||||END|
data/languages/Instructions/Logic.sinc||GHIDRA||||END|
data/languages/Instructions/Special.sinc||GHIDRA||||END|
data/languages/V850.cspec||GHIDRA||||END|
data/languages/V850.ldefs||GHIDRA||||END|
data/languages/V850.opinion||GHIDRA||||END|
data/languages/V850.pspec||GHIDRA||||END|
data/languages/V850.slaspec||GHIDRA||||END|
data/manuals/v850.idx||GHIDRA||||END|
data/patterns/V850_patterns.xml||GHIDRA||||END|
data/patterns/patternconstraints.xml||GHIDRA||||END|
Ghidra/Processors/V850/data/patterns/V850_patterns.xml
+14 -42
View File
@@ -1,5 +1,7 @@
<patternlist>
<patternpairs totalbits="48" postbits="32">
<patternpairs totalbits="31" postbits="15">
<!-- totalbits = total # of bits pre/post that must be a 0/1 not '.' -->
<!-- postbits = number of bits that are 0/1 not '.' that must come from post pattern bits -->
<prepatterns>
<data>01111111 00000000</data> <!-- jmp [lp] -->
</prepatterns>
@@ -7,26 +9,14 @@
<data>10...... 00000111 ...00001 ........</data> <!-- PREPARE list12, imm5 -->
<data>10...... 00000111 ...00011 ........</data> <!-- PREPARE list12, imm5, sp -->
<data>00000011 00011110 ........ ........</data> <!-- ADDI imm16, sp, sp -->
<data>10...... 00000111 ...01011 ........ ........ ........</data> <!-- PREPARE list12, imm5, simm16 -->
<data>10...... 00000111 ...10011 ........ ........ ........</data> <!-- PREPARE list12, imm5, imm16 -->
<data>10...... 00000111 ...11011 ........ ........ ........ ........ ........</data> <!-- PREPARE list12, imm5, imm32 -->
<codeboundary/>
<possiblefuncstart/>
</postpatterns>
</patternpairs>
<patternpairs totalbits="64" postbits="48">
<prepatterns>
<data>01111111 00000000</data> <!-- jmp [lp] -->
</prepatterns>
<postpatterns>
<data>10...... 00000111 ...01011 ........ ........ .........</data> <!-- PREPARE list12, imm5, simm16 -->
<data>10...... 00000111 ...10011 ........ ........ .........</data> <!-- PREPARE list12, imm5, imm16 -->
</postpatterns>
</patternpairs>
<patternpairs totalbits="80" postbits="64">
<prepatterns>
<data>01111111 00000000</data> <!-- jmp [lp] -->
</prepatterns>
<postpatterns>
<data>10...... 00000111 ...11011 ........ ........ ......... ........ .........</data> <!-- PREPARE list12, imm5, imm32 -->
</postpatterns>
</patternpairs>
<patternpairs totalbits="64" postbits="32">
<patternpairs totalbits="25" postbits="15">
<prepatterns>
<data>01...... 00000110 ........ ........</data> <!-- DISPOSE imm5, list12, [reg1] -->
<data>11100000 00000111 01001010 00000001</data> <!-- FERET -->
@@ -37,29 +27,11 @@
<data>10...... 00000111 ...00001 ........</data> <!-- PREPARE list12, imm5 -->
<data>10...... 00000111 ...00011 ........</data> <!-- PREPARE list12, imm5, sp -->
<data>00000011 00011110 ........ ........</data> <!-- ADDI imm16, sp, sp -->
<data>10...... 00000111 ...11011 ........ ........ ........ ........ ........</data> <!-- PREPARE list12, imm5, imm32 -->
<data>10...... 00000111 ...01011 ........ ........ ........</data> <!-- PREPARE list12, imm5, simm16 -->
<data>10...... 00000111 ...10011 ........ ........ ........</data> <!-- PREPARE list12, imm5, imm16 -->
<codeboundary/>
<possiblefuncstart/>
</postpatterns>
</patternpairs>
<patternpairs totalbits="80" postbits="48">
<prepatterns>
<data>01...... 00000110 ........ ........</data> <!-- DISPOSE imm5, list12, [reg1] -->
<data>11100000 00000111 01001010 00000001</data> <!-- FERET -->
<data>11100000 00000111 01001000 00000001</data> <!-- EIRET -->
<data>11100000 00000111 01000100 00000001</data> <!-- CTRET -->
</prepatterns>
<postpatterns>
<data>10...... 00000111 ...01011 ........ ........ .........</data> <!-- PREPARE list12, imm5, simm16 -->
<data>10...... 00000111 ...10011 ........ ........ .........</data> <!-- PREPARE list12, imm5, imm16 -->
</postpatterns>
</patternpairs>
<patternpairs totalbits="96" postbits="64">
<prepatterns>
<data>01...... 00000110 ........ ........</data> <!-- DISPOSE imm5, list12, [reg1] -->
<data>11100000 00000111 01001010 00000001</data> <!-- FERET -->
<data>11100000 00000111 01001000 00000001</data> <!-- EIRET -->
<data>11100000 00000111 01000100 00000001</data> <!-- CTRET -->
</prepatterns>
<postpatterns>
<data>10...... 00000111 ...11011 ........ ........ ......... ........ .........</data> <!-- PREPARE list12, imm5, imm32 -->
</postpatterns>
</patternpairs>
</patternlist>