mirror of
https://gitlab.com/etherlab.org/ethercat.git
synced 2026-02-06 03:41:52 +08:00
291 lines
8.8 KiB
C++
291 lines
8.8 KiB
C++
/*****************************************************************************
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*
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* $Id$
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*
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* Copyright (C) 2006-2009 Florian Pose, Ingenieurgemeinschaft IgH
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*
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* This file is part of the IgH EtherCAT Master.
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*
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* The IgH EtherCAT Master is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*
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* The IgH EtherCAT Master is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
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* Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with the IgH EtherCAT Master; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* ---
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*
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* The license mentioned above concerns the source code only. Using the
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* EtherCAT technology and brand is only permitted in compliance with the
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* industrial property and similar rights of Beckhoff Automation GmbH.
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*
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****************************************************************************/
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#include <iostream>
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#include <map>
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#include <algorithm>
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using namespace std;
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#include "CommandGraph.h"
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#include "MasterDevice.h"
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/*****************************************************************************/
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CommandGraph::CommandGraph():
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Command("graph", "Output the bus topology as a graph.")
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{
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}
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/*****************************************************************************/
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string CommandGraph::helpString(const string &binaryBaseName) const
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{
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stringstream str;
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str
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<< binaryBaseName << " " << getName() << " [OPTIONS]" << endl
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<< binaryBaseName << " " << getName() << " [OPTIONS] <INFO>" << endl
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<< endl
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<< getBriefDescription() << endl
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<< endl
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<< "The bus is output in DOT language (see" << endl
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<< "http://www.graphviz.org/doc/info/lang.html), which can" << endl
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<< "be processed with the tools from the Graphviz" << endl
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<< "package. Example:" << endl
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<< endl
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<< " ethercat graph | dot -Tsvg > bus.svg" << endl
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<< endl
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<< "See 'man dot' for more information." << endl
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<< endl
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<< "Additional information at edges and nodes is selected via" << endl
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<< "the first argument:" << endl
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<< " DC - DC timing" << endl
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<< " CRC - CRC error register information" << endl
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<< endl;
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return str.str();
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}
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/****************************************************************************/
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enum Info {
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None,
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DC,
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CRC
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};
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#define REG_SIZE (20)
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struct CrcInfo {
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unsigned int crc[EC_MAX_PORTS];
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unsigned int phy[EC_MAX_PORTS];
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unsigned int fwd[EC_MAX_PORTS];
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unsigned int lnk[EC_MAX_PORTS];
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};
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void CommandGraph::execute(const StringVector &args)
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{
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Info info = None;
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ec_ioctl_master_t master;
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typedef vector<ec_ioctl_slave_t> SlaveVector;
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SlaveVector slaves;
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typedef vector<CrcInfo> CrcInfoVector;
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CrcInfoVector crcInfos;
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ec_ioctl_slave_t slave;
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SlaveVector::const_iterator si;
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map<int, string> portMedia;
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map<int, string>::const_iterator mi;
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map<int, int> mediaWeights;
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map<int, int>::const_iterator wi;
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portMedia[EC_PORT_MII] = "MII";
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mediaWeights[EC_PORT_MII] = 1;
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portMedia[EC_PORT_EBUS] = "EBUS";
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mediaWeights[EC_PORT_EBUS] = 5;
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if (args.size() > 1) {
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stringstream err;
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err << "'" << getName() << "' takes either one or no arguments!";
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throwInvalidUsageException(err);
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}
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if (args.size() == 1) {
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string arg = args[0];
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transform(arg.begin(), arg.end(),
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arg.begin(), (int (*) (int)) std::toupper);
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if (arg == "DC") {
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info = DC;
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}
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else if (arg == "CRC") {
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info = CRC;
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}
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else {
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stringstream err;
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err << "Unknown argument \"" << args[0] << "\"!";
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throwInvalidUsageException(err);
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}
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}
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MasterDevice m(getSingleMasterIndex());
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m.open(MasterDevice::Read);
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m.getMaster(&master);
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for (unsigned int i = 0; i < master.slave_count; i++) {
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m.getSlave(&slave, i);
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slaves.push_back(slave);
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}
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if (info == CRC) {
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uint8_t data[REG_SIZE];
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ec_ioctl_slave_reg_t io;
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io.emergency = 0;
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io.address = 0x0300;
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io.size = REG_SIZE;
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io.data = data;
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for (unsigned int i = 0; i < master.slave_count; i++) {
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io.slave_position = i;
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try {
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m.readReg(&io);
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} catch (MasterDeviceException &e) {
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throw e;
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}
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CrcInfo crcInfo;
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for (int port = 0; port < EC_MAX_PORTS; port++) {
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crcInfo.crc[port] = io.data[ 0 + port * 2];
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crcInfo.phy[port] = io.data[ 1 + port * 2];
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crcInfo.fwd[port] = io.data[ 8 + port];
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crcInfo.lnk[port] = io.data[16 + port];
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}
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crcInfos.push_back(crcInfo);
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}
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}
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cout << "/* EtherCAT bus graph. Generated by 'ethercat graph'. */" << endl
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<< endl
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<< "strict graph bus {" << endl
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<< " rankdir=\"LR\"" << endl
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<< " ranksep=0.8" << endl
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<< " nodesep=0.8" << endl
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<< " node [fontname=\"Helvetica\"]" << endl
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<< " edge [fontname=\"Helvetica\",fontsize=\"10\"]" << endl
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<< endl
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<< " master [label=\"EtherCAT\\nMaster\"]" << endl;
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if (slaves.size()) {
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cout << " master -- slave0";
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mi = portMedia.find(slaves.front().ports[0].desc);
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if (mi != portMedia.end())
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cout << "[label=\"" << mi->second << "\"]";
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cout << endl;
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}
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cout << endl;
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uint16_t alias = 0x0000;
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uint16_t pos = 0;
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for (si = slaves.begin(); si != slaves.end(); si++) {
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if (si->alias) {
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alias = si->alias;
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pos = 0;
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}
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cout << " slave" << si->position << " [shape=\"box\""
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<< ",label=\"" << si->position
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<< " / " << alias << ":" << pos;
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if (string(si->order).size())
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cout << "\\n" << si->order;
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if (info == DC && si->dc_supported) {
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cout << "\\nDC: ";
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if (si->has_dc_system_time) {
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switch (si->dc_range) {
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case EC_DC_32:
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cout << "32 bit";
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break;
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case EC_DC_64:
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cout << "64 bit";
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break;
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default:
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break;
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}
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} else {
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cout << "Delay meas.";
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}
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cout << "\\nDelay: " << si->transmission_delay << " ns";
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}
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cout << "\"]" << endl;
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for (int port = 1; port < EC_MAX_PORTS; port++) {
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uint16_t next_pos = si->ports[port].next_slave;
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if (next_pos == 0xffff) {
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continue;
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}
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if (next_pos >= slaves.size()) {
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cerr << "Invalid next slave pointer." << endl;
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continue;
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}
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ec_ioctl_slave_t *next = &slaves[next_pos];
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cout << " slave" << si->position << " -- "
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<< "slave" << next_pos << " [taillabel=\"" << port;
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if (info == DC && si->dc_supported) {
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cout << " [" << si->ports[port].delay_to_next_dc << "]";
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}
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if (info == CRC) {
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CrcInfo *crcInfo = &crcInfos[si->position];
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cout << " [" << crcInfo->crc[port] << "/"
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<< crcInfo->fwd[port] << "]";
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}
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cout << "\",headlabel=\"0";
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if (info == DC && next->dc_supported) {
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cout << " [" << next->ports[0].delay_to_next_dc << "]";
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}
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if (info == CRC) {
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CrcInfo *crcInfo = &crcInfos[next_pos];
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cout << " [" << crcInfo->crc[0] << "/"
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<< crcInfo->fwd[0] << "]";
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}
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cout << "\"";
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mi = portMedia.find(si->ports[port].desc);
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if (mi == portMedia.end() && next) {
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/* Try medium of next-hop slave. */
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mi = portMedia.find(next->ports[0].desc);
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}
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if (mi != portMedia.end())
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cout << ",label=\"" << mi->second << "\"";
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wi = mediaWeights.find(si->ports[port].desc);
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if (wi != mediaWeights.end())
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cout << ",weight=\"" << wi->second << "\"";
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cout << "]" << endl;
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}
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cout << endl;
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pos++;
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}
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cout << "}" << endl;
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}
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/*****************************************************************************/
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