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Merge branch '226-issue-splitting-domain-into-several-datagrams' into 'stable-1.6'
Prevent creating too large datagrams See merge request etherlab.org/ethercat!205
This commit is contained in:
+10
-2
@@ -1,6 +1,6 @@
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/*****************************************************************************
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*
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* Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH
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* Copyright (C) 2006-2026 Florian Pose, Ingenieurgemeinschaft IgH
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*
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* This file is part of the IgH EtherCAT Master.
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*
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@@ -145,8 +145,16 @@ int ec_datagram_prealloc(
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)
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{
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if (datagram->data_origin == EC_ORIG_EXTERNAL
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|| size <= datagram->mem_size)
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|| size <= datagram->mem_size) {
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return 0;
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}
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if (size > EC_MAX_DATA_SIZE) {
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EC_ERR("%s(datagram = %p, size = %zu): Exceeding the"
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" maximum datagram size of %u bytes.\n",
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__func__, datagram, size, EC_MAX_DATA_SIZE);
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return -EOVERFLOW;
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}
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if (datagram->data) {
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kfree(datagram->data);
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@@ -1,6 +1,6 @@
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/*****************************************************************************
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*
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* Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH
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* Copyright (C) 2006-2026 Florian Pose, Ingenieurgemeinschaft IgH
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*
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* This file is part of the IgH EtherCAT Master.
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*
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@@ -77,13 +77,13 @@ void ec_fmmu_config_page(
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sync->physical_start_address, fmmu->sync_index,
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fmmu->dir == EC_DIR_INPUT ? "in" : "out");
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EC_WRITE_U32(data, fmmu->logical_start_address);
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EC_WRITE_U16(data + 4, fmmu->data_size); // size of fmmu
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EC_WRITE_U8 (data + 6, 0x00); // logical start bit
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EC_WRITE_U8 (data + 7, 0x07); // logical end bit
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EC_WRITE_U16(data + 8, sync->physical_start_address);
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EC_WRITE_U8 (data + 10, 0x00); // physical start bit
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EC_WRITE_U8 (data + 11, fmmu->dir == EC_DIR_INPUT ? 0x01 : 0x02);
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EC_WRITE_U32(data, fmmu->logical_start_address);
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EC_WRITE_U16(data + 4, fmmu->data_size); // size of fmmu
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EC_WRITE_U8(data + 6, 0x00); // logical start bit
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EC_WRITE_U8(data + 7, 0x07); // logical end bit
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EC_WRITE_U16(data + 8, sync->physical_start_address);
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EC_WRITE_U8(data + 10, 0x00); // physical start bit
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EC_WRITE_U8(data + 11, fmmu->dir == EC_DIR_INPUT ? 0x01 : 0x02);
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EC_WRITE_U16(data + 12, 0x0001); // enable
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EC_WRITE_U16(data + 14, 0x0000); // reserved
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}
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@@ -1,6 +1,6 @@
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/*****************************************************************************
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*
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* Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH
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* Copyright (C) 2006-2026 Florian Pose, Ingenieurgemeinschaft IgH
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*
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* This file is part of the IgH EtherCAT Master.
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*
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@@ -25,8 +25,8 @@
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/****************************************************************************/
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#ifndef __EC_FMMU_CONFIG_H__
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#define __EC_FMMU_CONFIG_H__
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#ifndef MASTER_FMMU_CONFIG_H_
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#define MASTER_FMMU_CONFIG_H_
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#include "globals.h"
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#include "sync.h"
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@@ -55,4 +55,4 @@ void ec_fmmu_config_page(const ec_fmmu_config_t *, const ec_sync_t *,
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/****************************************************************************/
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#endif
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#endif // MASTER_FMMU_CONFIG_H_
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