mirror of
https://gitlab.com/etherlab.org/ethercat.git
synced 2026-08-18 00:57:23 +08:00
Added all drivers for kernel 3.16.
This commit is contained in:
Florian Pose
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -85,6 +85,8 @@ noinst_HEADERS = \
|
||||
8139too-3.12-orig.c \
|
||||
8139too-3.14-ethercat.c \
|
||||
8139too-3.14-orig.c \
|
||||
8139too-3.16-ethercat.c \
|
||||
8139too-3.16-orig.c \
|
||||
8139too-3.2-ethercat.c \
|
||||
8139too-3.2-orig.c \
|
||||
8139too-3.4-ethercat.c \
|
||||
@@ -123,6 +125,8 @@ noinst_HEADERS = \
|
||||
e100-3.12-orig.c \
|
||||
e100-3.14-ethercat.c \
|
||||
e100-3.14-orig.c \
|
||||
e100-3.16-ethercat.c \
|
||||
e100-3.16-orig.c \
|
||||
e100-3.4-ethercat.c \
|
||||
e100-3.4-orig.c \
|
||||
e100-3.6-ethercat.c \
|
||||
@@ -157,6 +161,8 @@ noinst_HEADERS = \
|
||||
r8169-3.12-orig.c \
|
||||
r8169-3.14-ethercat.c \
|
||||
r8169-3.14-orig.c \
|
||||
r8169-3.16-ethercat.c \
|
||||
r8169-3.16-orig.c \
|
||||
r8169-3.2-ethercat.c \
|
||||
r8169-3.2-orig.c \
|
||||
r8169-3.4-ethercat.c \
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -66,6 +66,8 @@ EXTRA_DIST = \
|
||||
e1000-3.12-orig.h \
|
||||
e1000-3.14-ethercat.h \
|
||||
e1000-3.14-orig.h \
|
||||
e1000-3.16-ethercat.h \
|
||||
e1000-3.16-orig.h \
|
||||
e1000-3.4-ethercat.h \
|
||||
e1000-3.4-orig.h \
|
||||
e1000-3.6-ethercat.h \
|
||||
@@ -108,6 +110,8 @@ EXTRA_DIST = \
|
||||
e1000_ethtool-3.12-orig.c \
|
||||
e1000_ethtool-3.14-ethercat.c \
|
||||
e1000_ethtool-3.14-orig.c \
|
||||
e1000_ethtool-3.16-ethercat.c \
|
||||
e1000_ethtool-3.16-orig.c \
|
||||
e1000_ethtool-3.4-ethercat.c \
|
||||
e1000_ethtool-3.4-orig.c \
|
||||
e1000_ethtool-3.6-ethercat.c \
|
||||
@@ -186,6 +190,10 @@ EXTRA_DIST = \
|
||||
e1000_hw-3.14-ethercat.h \
|
||||
e1000_hw-3.14-orig.c \
|
||||
e1000_hw-3.14-orig.h \
|
||||
e1000_hw-3.16-ethercat.c \
|
||||
e1000_hw-3.16-ethercat.h \
|
||||
e1000_hw-3.16-orig.c \
|
||||
e1000_hw-3.16-orig.h \
|
||||
e1000_hw-3.4-ethercat.c \
|
||||
e1000_hw-3.4-ethercat.h \
|
||||
e1000_hw-3.4-orig.c \
|
||||
@@ -234,6 +242,8 @@ EXTRA_DIST = \
|
||||
e1000_main-3.12-orig.c \
|
||||
e1000_main-3.14-ethercat.c \
|
||||
e1000_main-3.14-orig.c \
|
||||
e1000_main-3.16-ethercat.c \
|
||||
e1000_main-3.16-orig.c \
|
||||
e1000_main-3.4-ethercat.c \
|
||||
e1000_main-3.4-orig.c \
|
||||
e1000_main-3.6-ethercat.c \
|
||||
@@ -276,6 +286,8 @@ EXTRA_DIST = \
|
||||
e1000_osdep-3.12-orig.h \
|
||||
e1000_osdep-3.14-ethercat.h \
|
||||
e1000_osdep-3.14-orig.h \
|
||||
e1000_osdep-3.16-ethercat.h \
|
||||
e1000_osdep-3.16-orig.h \
|
||||
e1000_osdep-3.4-ethercat.h \
|
||||
e1000_osdep-3.4-orig.h \
|
||||
e1000_osdep-3.6-ethercat.h \
|
||||
@@ -318,6 +330,8 @@ EXTRA_DIST = \
|
||||
e1000_param-3.12-orig.c \
|
||||
e1000_param-3.14-ethercat.c \
|
||||
e1000_param-3.14-orig.c \
|
||||
e1000_param-3.16-ethercat.c \
|
||||
e1000_param-3.16-orig.c \
|
||||
e1000_param-3.4-ethercat.c \
|
||||
e1000_param-3.4-orig.c \
|
||||
e1000_param-3.6-ethercat.c \
|
||||
|
||||
@@ -0,0 +1,372 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Intel PRO/1000 Linux driver
|
||||
Copyright(c) 1999 - 2006 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
Linux NICS <linux.nics@intel.com>
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* Linux PRO/1000 Ethernet Driver main header file */
|
||||
|
||||
#ifndef _E1000_H_
|
||||
#define _E1000_H_
|
||||
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/pagemap.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <linux/capability.h>
|
||||
#include <linux/in.h>
|
||||
#include <linux/ip.h>
|
||||
#include <linux/ipv6.h>
|
||||
#include <linux/tcp.h>
|
||||
#include <linux/udp.h>
|
||||
#include <net/pkt_sched.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <net/checksum.h>
|
||||
#include <linux/mii.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/if_vlan.h>
|
||||
#include "../ecdev.h"
|
||||
|
||||
|
||||
#define BAR_0 0
|
||||
#define BAR_1 1
|
||||
#define BAR_5 5
|
||||
|
||||
#define INTEL_E1000_ETHERNET_DEVICE(device_id) {\
|
||||
PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
|
||||
|
||||
struct e1000_adapter;
|
||||
|
||||
#include "e1000_hw-3.16-ethercat.h"
|
||||
|
||||
#define E1000_MAX_INTR 10
|
||||
|
||||
/*
|
||||
* Count for polling __E1000_RESET condition every 10-20msec.
|
||||
*/
|
||||
#define E1000_CHECK_RESET_COUNT 50
|
||||
|
||||
/* TX/RX descriptor defines */
|
||||
#define E1000_DEFAULT_TXD 256
|
||||
#define E1000_MAX_TXD 256
|
||||
#define E1000_MIN_TXD 48
|
||||
#define E1000_MAX_82544_TXD 4096
|
||||
|
||||
#define E1000_DEFAULT_RXD 256
|
||||
#define E1000_MAX_RXD 256
|
||||
#define E1000_MIN_RXD 48
|
||||
#define E1000_MAX_82544_RXD 4096
|
||||
|
||||
#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
|
||||
#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
|
||||
|
||||
/* this is the size past which hardware will drop packets when setting LPE=0 */
|
||||
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
|
||||
|
||||
/* Supported Rx Buffer Sizes */
|
||||
#define E1000_RXBUFFER_128 128 /* Used for packet split */
|
||||
#define E1000_RXBUFFER_256 256 /* Used for packet split */
|
||||
#define E1000_RXBUFFER_512 512
|
||||
#define E1000_RXBUFFER_1024 1024
|
||||
#define E1000_RXBUFFER_2048 2048
|
||||
#define E1000_RXBUFFER_4096 4096
|
||||
#define E1000_RXBUFFER_8192 8192
|
||||
#define E1000_RXBUFFER_16384 16384
|
||||
|
||||
/* SmartSpeed delimiters */
|
||||
#define E1000_SMARTSPEED_DOWNSHIFT 3
|
||||
#define E1000_SMARTSPEED_MAX 15
|
||||
|
||||
/* Packet Buffer allocations */
|
||||
#define E1000_PBA_BYTES_SHIFT 0xA
|
||||
#define E1000_TX_HEAD_ADDR_SHIFT 7
|
||||
#define E1000_PBA_TX_MASK 0xFFFF0000
|
||||
|
||||
/* Flow Control Watermarks */
|
||||
#define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */
|
||||
#define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */
|
||||
|
||||
#define E1000_FC_PAUSE_TIME 0xFFFF /* pause for the max or until send xon */
|
||||
|
||||
/* How many Tx Descriptors do we need to call netif_wake_queue ? */
|
||||
#define E1000_TX_QUEUE_WAKE 16
|
||||
/* How many Rx Buffers do we bundle into one write to the hardware ? */
|
||||
#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
|
||||
|
||||
#define AUTO_ALL_MODES 0
|
||||
#define E1000_EEPROM_82544_APM 0x0004
|
||||
#define E1000_EEPROM_APME 0x0400
|
||||
|
||||
#ifndef E1000_MASTER_SLAVE
|
||||
/* Switch to override PHY master/slave setting */
|
||||
#define E1000_MASTER_SLAVE e1000_ms_hw_default
|
||||
#endif
|
||||
|
||||
#define E1000_MNG_VLAN_NONE (-1)
|
||||
|
||||
/* wrapper around a pointer to a socket buffer,
|
||||
* so a DMA handle can be stored along with the buffer
|
||||
*/
|
||||
struct e1000_buffer {
|
||||
struct sk_buff *skb;
|
||||
dma_addr_t dma;
|
||||
struct page *page;
|
||||
unsigned long time_stamp;
|
||||
u16 length;
|
||||
u16 next_to_watch;
|
||||
unsigned int segs;
|
||||
unsigned int bytecount;
|
||||
u16 mapped_as_page;
|
||||
};
|
||||
|
||||
struct e1000_tx_ring {
|
||||
/* pointer to the descriptor ring memory */
|
||||
void *desc;
|
||||
/* physical address of the descriptor ring */
|
||||
dma_addr_t dma;
|
||||
/* length of descriptor ring in bytes */
|
||||
unsigned int size;
|
||||
/* number of descriptors in the ring */
|
||||
unsigned int count;
|
||||
/* next descriptor to associate a buffer with */
|
||||
unsigned int next_to_use;
|
||||
/* next descriptor to check for DD status bit */
|
||||
unsigned int next_to_clean;
|
||||
/* array of buffer information structs */
|
||||
struct e1000_buffer *buffer_info;
|
||||
|
||||
u16 tdh;
|
||||
u16 tdt;
|
||||
bool last_tx_tso;
|
||||
};
|
||||
|
||||
struct e1000_rx_ring {
|
||||
/* pointer to the descriptor ring memory */
|
||||
void *desc;
|
||||
/* physical address of the descriptor ring */
|
||||
dma_addr_t dma;
|
||||
/* length of descriptor ring in bytes */
|
||||
unsigned int size;
|
||||
/* number of descriptors in the ring */
|
||||
unsigned int count;
|
||||
/* next descriptor to associate a buffer with */
|
||||
unsigned int next_to_use;
|
||||
/* next descriptor to check for DD status bit */
|
||||
unsigned int next_to_clean;
|
||||
/* array of buffer information structs */
|
||||
struct e1000_buffer *buffer_info;
|
||||
struct sk_buff *rx_skb_top;
|
||||
|
||||
/* cpu for rx queue */
|
||||
int cpu;
|
||||
|
||||
u16 rdh;
|
||||
u16 rdt;
|
||||
};
|
||||
|
||||
#define E1000_DESC_UNUSED(R) \
|
||||
((((R)->next_to_clean > (R)->next_to_use) \
|
||||
? 0 : (R)->count) + (R)->next_to_clean - (R)->next_to_use - 1)
|
||||
|
||||
#define E1000_RX_DESC_EXT(R, i) \
|
||||
(&(((union e1000_rx_desc_extended *)((R).desc))[i]))
|
||||
#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
|
||||
#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
|
||||
#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
|
||||
#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
|
||||
|
||||
/* board specific private data structure */
|
||||
|
||||
struct e1000_adapter {
|
||||
unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
|
||||
u16 mng_vlan_id;
|
||||
u32 bd_number;
|
||||
u32 rx_buffer_len;
|
||||
u32 wol;
|
||||
u32 smartspeed;
|
||||
u32 en_mng_pt;
|
||||
u16 link_speed;
|
||||
u16 link_duplex;
|
||||
spinlock_t stats_lock;
|
||||
unsigned int total_tx_bytes;
|
||||
unsigned int total_tx_packets;
|
||||
unsigned int total_rx_bytes;
|
||||
unsigned int total_rx_packets;
|
||||
/* Interrupt Throttle Rate */
|
||||
u32 itr;
|
||||
u32 itr_setting;
|
||||
u16 tx_itr;
|
||||
u16 rx_itr;
|
||||
|
||||
u8 fc_autoneg;
|
||||
|
||||
/* TX */
|
||||
struct e1000_tx_ring *tx_ring; /* One per active queue */
|
||||
unsigned int restart_queue;
|
||||
u32 txd_cmd;
|
||||
u32 tx_int_delay;
|
||||
u32 tx_abs_int_delay;
|
||||
u32 gotcl;
|
||||
u64 gotcl_old;
|
||||
u64 tpt_old;
|
||||
u64 colc_old;
|
||||
u32 tx_timeout_count;
|
||||
u32 tx_fifo_head;
|
||||
u32 tx_head_addr;
|
||||
u32 tx_fifo_size;
|
||||
u8 tx_timeout_factor;
|
||||
atomic_t tx_fifo_stall;
|
||||
bool pcix_82544;
|
||||
bool detect_tx_hung;
|
||||
bool dump_buffers;
|
||||
|
||||
/* RX */
|
||||
bool (*clean_rx)(struct e1000_adapter *adapter,
|
||||
struct e1000_rx_ring *rx_ring,
|
||||
int *work_done, int work_to_do);
|
||||
void (*alloc_rx_buf)(struct e1000_adapter *adapter,
|
||||
struct e1000_rx_ring *rx_ring,
|
||||
int cleaned_count);
|
||||
struct e1000_rx_ring *rx_ring; /* One per active queue */
|
||||
struct napi_struct napi;
|
||||
|
||||
int num_tx_queues;
|
||||
int num_rx_queues;
|
||||
|
||||
u64 hw_csum_err;
|
||||
u64 hw_csum_good;
|
||||
u32 alloc_rx_buff_failed;
|
||||
u32 rx_int_delay;
|
||||
u32 rx_abs_int_delay;
|
||||
bool rx_csum;
|
||||
u32 gorcl;
|
||||
u64 gorcl_old;
|
||||
|
||||
/* OS defined structs */
|
||||
struct net_device *netdev;
|
||||
struct pci_dev *pdev;
|
||||
|
||||
/* structs defined in e1000_hw.h */
|
||||
struct e1000_hw hw;
|
||||
struct e1000_hw_stats stats;
|
||||
struct e1000_phy_info phy_info;
|
||||
struct e1000_phy_stats phy_stats;
|
||||
|
||||
u32 test_icr;
|
||||
struct e1000_tx_ring test_tx_ring;
|
||||
struct e1000_rx_ring test_rx_ring;
|
||||
|
||||
int msg_enable;
|
||||
|
||||
/* to not mess up cache alignment, always add to the bottom */
|
||||
bool tso_force;
|
||||
bool smart_power_down; /* phy smart power down */
|
||||
bool quad_port_a;
|
||||
unsigned long flags;
|
||||
u32 eeprom_wol;
|
||||
|
||||
/* for ioport free */
|
||||
int bars;
|
||||
int need_ioport;
|
||||
|
||||
bool discarding;
|
||||
|
||||
struct work_struct reset_task;
|
||||
struct delayed_work watchdog_task;
|
||||
struct delayed_work fifo_stall_task;
|
||||
struct delayed_work phy_info_task;
|
||||
|
||||
ec_device_t *ecdev;
|
||||
unsigned long ec_watchdog_jiffies;
|
||||
};
|
||||
|
||||
enum e1000_state_t {
|
||||
__E1000_TESTING,
|
||||
__E1000_RESETTING,
|
||||
__E1000_DOWN
|
||||
};
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
struct net_device *e1000_get_hw_dev(struct e1000_hw *hw);
|
||||
#define e_dbg(format, arg...) \
|
||||
netdev_dbg(e1000_get_hw_dev(hw), format, ## arg)
|
||||
#define e_err(msglvl, format, arg...) \
|
||||
netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
|
||||
#define e_info(msglvl, format, arg...) \
|
||||
netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
|
||||
#define e_warn(msglvl, format, arg...) \
|
||||
netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
|
||||
#define e_notice(msglvl, format, arg...) \
|
||||
netif_notice(adapter, msglvl, adapter->netdev, format, ## arg)
|
||||
#define e_dev_info(format, arg...) \
|
||||
dev_info(&adapter->pdev->dev, format, ## arg)
|
||||
#define e_dev_warn(format, arg...) \
|
||||
dev_warn(&adapter->pdev->dev, format, ## arg)
|
||||
#define e_dev_err(format, arg...) \
|
||||
dev_err(&adapter->pdev->dev, format, ## arg)
|
||||
|
||||
extern char e1000_driver_name[];
|
||||
extern const char e1000_driver_version[];
|
||||
|
||||
int e1000_up(struct e1000_adapter *adapter);
|
||||
void e1000_down(struct e1000_adapter *adapter);
|
||||
void e1000_reinit_locked(struct e1000_adapter *adapter);
|
||||
void e1000_reset(struct e1000_adapter *adapter);
|
||||
int e1000_set_spd_dplx(struct e1000_adapter *adapter, u32 spd, u8 dplx);
|
||||
int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
|
||||
int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
|
||||
void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
|
||||
void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
|
||||
void e1000_update_stats(struct e1000_adapter *adapter);
|
||||
bool e1000_has_link(struct e1000_adapter *adapter);
|
||||
void e1000_power_up_phy(struct e1000_adapter *);
|
||||
void e1000_set_ethtool_ops(struct net_device *netdev);
|
||||
void e1000_check_options(struct e1000_adapter *adapter);
|
||||
char *e1000_get_hw_dev_name(struct e1000_hw *hw);
|
||||
|
||||
#endif /* _E1000_H_ */
|
||||
@@ -0,0 +1,367 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Intel PRO/1000 Linux driver
|
||||
Copyright(c) 1999 - 2006 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
Linux NICS <linux.nics@intel.com>
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* Linux PRO/1000 Ethernet Driver main header file */
|
||||
|
||||
#ifndef _E1000_H_
|
||||
#define _E1000_H_
|
||||
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/pagemap.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <linux/capability.h>
|
||||
#include <linux/in.h>
|
||||
#include <linux/ip.h>
|
||||
#include <linux/ipv6.h>
|
||||
#include <linux/tcp.h>
|
||||
#include <linux/udp.h>
|
||||
#include <net/pkt_sched.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <net/checksum.h>
|
||||
#include <linux/mii.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/if_vlan.h>
|
||||
|
||||
#define BAR_0 0
|
||||
#define BAR_1 1
|
||||
#define BAR_5 5
|
||||
|
||||
#define INTEL_E1000_ETHERNET_DEVICE(device_id) {\
|
||||
PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
|
||||
|
||||
struct e1000_adapter;
|
||||
|
||||
#include "e1000_hw.h"
|
||||
|
||||
#define E1000_MAX_INTR 10
|
||||
|
||||
/*
|
||||
* Count for polling __E1000_RESET condition every 10-20msec.
|
||||
*/
|
||||
#define E1000_CHECK_RESET_COUNT 50
|
||||
|
||||
/* TX/RX descriptor defines */
|
||||
#define E1000_DEFAULT_TXD 256
|
||||
#define E1000_MAX_TXD 256
|
||||
#define E1000_MIN_TXD 48
|
||||
#define E1000_MAX_82544_TXD 4096
|
||||
|
||||
#define E1000_DEFAULT_RXD 256
|
||||
#define E1000_MAX_RXD 256
|
||||
#define E1000_MIN_RXD 48
|
||||
#define E1000_MAX_82544_RXD 4096
|
||||
|
||||
#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
|
||||
#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
|
||||
|
||||
/* this is the size past which hardware will drop packets when setting LPE=0 */
|
||||
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
|
||||
|
||||
/* Supported Rx Buffer Sizes */
|
||||
#define E1000_RXBUFFER_128 128 /* Used for packet split */
|
||||
#define E1000_RXBUFFER_256 256 /* Used for packet split */
|
||||
#define E1000_RXBUFFER_512 512
|
||||
#define E1000_RXBUFFER_1024 1024
|
||||
#define E1000_RXBUFFER_2048 2048
|
||||
#define E1000_RXBUFFER_4096 4096
|
||||
#define E1000_RXBUFFER_8192 8192
|
||||
#define E1000_RXBUFFER_16384 16384
|
||||
|
||||
/* SmartSpeed delimiters */
|
||||
#define E1000_SMARTSPEED_DOWNSHIFT 3
|
||||
#define E1000_SMARTSPEED_MAX 15
|
||||
|
||||
/* Packet Buffer allocations */
|
||||
#define E1000_PBA_BYTES_SHIFT 0xA
|
||||
#define E1000_TX_HEAD_ADDR_SHIFT 7
|
||||
#define E1000_PBA_TX_MASK 0xFFFF0000
|
||||
|
||||
/* Flow Control Watermarks */
|
||||
#define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */
|
||||
#define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */
|
||||
|
||||
#define E1000_FC_PAUSE_TIME 0xFFFF /* pause for the max or until send xon */
|
||||
|
||||
/* How many Tx Descriptors do we need to call netif_wake_queue ? */
|
||||
#define E1000_TX_QUEUE_WAKE 16
|
||||
/* How many Rx Buffers do we bundle into one write to the hardware ? */
|
||||
#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
|
||||
|
||||
#define AUTO_ALL_MODES 0
|
||||
#define E1000_EEPROM_82544_APM 0x0004
|
||||
#define E1000_EEPROM_APME 0x0400
|
||||
|
||||
#ifndef E1000_MASTER_SLAVE
|
||||
/* Switch to override PHY master/slave setting */
|
||||
#define E1000_MASTER_SLAVE e1000_ms_hw_default
|
||||
#endif
|
||||
|
||||
#define E1000_MNG_VLAN_NONE (-1)
|
||||
|
||||
/* wrapper around a pointer to a socket buffer,
|
||||
* so a DMA handle can be stored along with the buffer
|
||||
*/
|
||||
struct e1000_buffer {
|
||||
struct sk_buff *skb;
|
||||
dma_addr_t dma;
|
||||
struct page *page;
|
||||
unsigned long time_stamp;
|
||||
u16 length;
|
||||
u16 next_to_watch;
|
||||
unsigned int segs;
|
||||
unsigned int bytecount;
|
||||
u16 mapped_as_page;
|
||||
};
|
||||
|
||||
struct e1000_tx_ring {
|
||||
/* pointer to the descriptor ring memory */
|
||||
void *desc;
|
||||
/* physical address of the descriptor ring */
|
||||
dma_addr_t dma;
|
||||
/* length of descriptor ring in bytes */
|
||||
unsigned int size;
|
||||
/* number of descriptors in the ring */
|
||||
unsigned int count;
|
||||
/* next descriptor to associate a buffer with */
|
||||
unsigned int next_to_use;
|
||||
/* next descriptor to check for DD status bit */
|
||||
unsigned int next_to_clean;
|
||||
/* array of buffer information structs */
|
||||
struct e1000_buffer *buffer_info;
|
||||
|
||||
u16 tdh;
|
||||
u16 tdt;
|
||||
bool last_tx_tso;
|
||||
};
|
||||
|
||||
struct e1000_rx_ring {
|
||||
/* pointer to the descriptor ring memory */
|
||||
void *desc;
|
||||
/* physical address of the descriptor ring */
|
||||
dma_addr_t dma;
|
||||
/* length of descriptor ring in bytes */
|
||||
unsigned int size;
|
||||
/* number of descriptors in the ring */
|
||||
unsigned int count;
|
||||
/* next descriptor to associate a buffer with */
|
||||
unsigned int next_to_use;
|
||||
/* next descriptor to check for DD status bit */
|
||||
unsigned int next_to_clean;
|
||||
/* array of buffer information structs */
|
||||
struct e1000_buffer *buffer_info;
|
||||
struct sk_buff *rx_skb_top;
|
||||
|
||||
/* cpu for rx queue */
|
||||
int cpu;
|
||||
|
||||
u16 rdh;
|
||||
u16 rdt;
|
||||
};
|
||||
|
||||
#define E1000_DESC_UNUSED(R) \
|
||||
((((R)->next_to_clean > (R)->next_to_use) \
|
||||
? 0 : (R)->count) + (R)->next_to_clean - (R)->next_to_use - 1)
|
||||
|
||||
#define E1000_RX_DESC_EXT(R, i) \
|
||||
(&(((union e1000_rx_desc_extended *)((R).desc))[i]))
|
||||
#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
|
||||
#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
|
||||
#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
|
||||
#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
|
||||
|
||||
/* board specific private data structure */
|
||||
|
||||
struct e1000_adapter {
|
||||
unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
|
||||
u16 mng_vlan_id;
|
||||
u32 bd_number;
|
||||
u32 rx_buffer_len;
|
||||
u32 wol;
|
||||
u32 smartspeed;
|
||||
u32 en_mng_pt;
|
||||
u16 link_speed;
|
||||
u16 link_duplex;
|
||||
spinlock_t stats_lock;
|
||||
unsigned int total_tx_bytes;
|
||||
unsigned int total_tx_packets;
|
||||
unsigned int total_rx_bytes;
|
||||
unsigned int total_rx_packets;
|
||||
/* Interrupt Throttle Rate */
|
||||
u32 itr;
|
||||
u32 itr_setting;
|
||||
u16 tx_itr;
|
||||
u16 rx_itr;
|
||||
|
||||
u8 fc_autoneg;
|
||||
|
||||
/* TX */
|
||||
struct e1000_tx_ring *tx_ring; /* One per active queue */
|
||||
unsigned int restart_queue;
|
||||
u32 txd_cmd;
|
||||
u32 tx_int_delay;
|
||||
u32 tx_abs_int_delay;
|
||||
u32 gotcl;
|
||||
u64 gotcl_old;
|
||||
u64 tpt_old;
|
||||
u64 colc_old;
|
||||
u32 tx_timeout_count;
|
||||
u32 tx_fifo_head;
|
||||
u32 tx_head_addr;
|
||||
u32 tx_fifo_size;
|
||||
u8 tx_timeout_factor;
|
||||
atomic_t tx_fifo_stall;
|
||||
bool pcix_82544;
|
||||
bool detect_tx_hung;
|
||||
bool dump_buffers;
|
||||
|
||||
/* RX */
|
||||
bool (*clean_rx)(struct e1000_adapter *adapter,
|
||||
struct e1000_rx_ring *rx_ring,
|
||||
int *work_done, int work_to_do);
|
||||
void (*alloc_rx_buf)(struct e1000_adapter *adapter,
|
||||
struct e1000_rx_ring *rx_ring,
|
||||
int cleaned_count);
|
||||
struct e1000_rx_ring *rx_ring; /* One per active queue */
|
||||
struct napi_struct napi;
|
||||
|
||||
int num_tx_queues;
|
||||
int num_rx_queues;
|
||||
|
||||
u64 hw_csum_err;
|
||||
u64 hw_csum_good;
|
||||
u32 alloc_rx_buff_failed;
|
||||
u32 rx_int_delay;
|
||||
u32 rx_abs_int_delay;
|
||||
bool rx_csum;
|
||||
u32 gorcl;
|
||||
u64 gorcl_old;
|
||||
|
||||
/* OS defined structs */
|
||||
struct net_device *netdev;
|
||||
struct pci_dev *pdev;
|
||||
|
||||
/* structs defined in e1000_hw.h */
|
||||
struct e1000_hw hw;
|
||||
struct e1000_hw_stats stats;
|
||||
struct e1000_phy_info phy_info;
|
||||
struct e1000_phy_stats phy_stats;
|
||||
|
||||
u32 test_icr;
|
||||
struct e1000_tx_ring test_tx_ring;
|
||||
struct e1000_rx_ring test_rx_ring;
|
||||
|
||||
int msg_enable;
|
||||
|
||||
/* to not mess up cache alignment, always add to the bottom */
|
||||
bool tso_force;
|
||||
bool smart_power_down; /* phy smart power down */
|
||||
bool quad_port_a;
|
||||
unsigned long flags;
|
||||
u32 eeprom_wol;
|
||||
|
||||
/* for ioport free */
|
||||
int bars;
|
||||
int need_ioport;
|
||||
|
||||
bool discarding;
|
||||
|
||||
struct work_struct reset_task;
|
||||
struct delayed_work watchdog_task;
|
||||
struct delayed_work fifo_stall_task;
|
||||
struct delayed_work phy_info_task;
|
||||
};
|
||||
|
||||
enum e1000_state_t {
|
||||
__E1000_TESTING,
|
||||
__E1000_RESETTING,
|
||||
__E1000_DOWN
|
||||
};
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
struct net_device *e1000_get_hw_dev(struct e1000_hw *hw);
|
||||
#define e_dbg(format, arg...) \
|
||||
netdev_dbg(e1000_get_hw_dev(hw), format, ## arg)
|
||||
#define e_err(msglvl, format, arg...) \
|
||||
netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
|
||||
#define e_info(msglvl, format, arg...) \
|
||||
netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
|
||||
#define e_warn(msglvl, format, arg...) \
|
||||
netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
|
||||
#define e_notice(msglvl, format, arg...) \
|
||||
netif_notice(adapter, msglvl, adapter->netdev, format, ## arg)
|
||||
#define e_dev_info(format, arg...) \
|
||||
dev_info(&adapter->pdev->dev, format, ## arg)
|
||||
#define e_dev_warn(format, arg...) \
|
||||
dev_warn(&adapter->pdev->dev, format, ## arg)
|
||||
#define e_dev_err(format, arg...) \
|
||||
dev_err(&adapter->pdev->dev, format, ## arg)
|
||||
|
||||
extern char e1000_driver_name[];
|
||||
extern const char e1000_driver_version[];
|
||||
|
||||
int e1000_up(struct e1000_adapter *adapter);
|
||||
void e1000_down(struct e1000_adapter *adapter);
|
||||
void e1000_reinit_locked(struct e1000_adapter *adapter);
|
||||
void e1000_reset(struct e1000_adapter *adapter);
|
||||
int e1000_set_spd_dplx(struct e1000_adapter *adapter, u32 spd, u8 dplx);
|
||||
int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
|
||||
int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
|
||||
void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
|
||||
void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
|
||||
void e1000_update_stats(struct e1000_adapter *adapter);
|
||||
bool e1000_has_link(struct e1000_adapter *adapter);
|
||||
void e1000_power_up_phy(struct e1000_adapter *);
|
||||
void e1000_set_ethtool_ops(struct net_device *netdev);
|
||||
void e1000_check_options(struct e1000_adapter *adapter);
|
||||
char *e1000_get_hw_dev_name(struct e1000_hw *hw);
|
||||
|
||||
#endif /* _E1000_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,109 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Intel PRO/1000 Linux driver
|
||||
Copyright(c) 1999 - 2006 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
Linux NICS <linux.nics@intel.com>
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* glue for the OS independent part of e1000
|
||||
* includes register access macros
|
||||
*/
|
||||
|
||||
#ifndef _E1000_OSDEP_H_
|
||||
#define _E1000_OSDEP_H_
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#define CONFIG_RAM_BASE 0x60000
|
||||
#define GBE_CONFIG_OFFSET 0x0
|
||||
|
||||
#define GBE_CONFIG_RAM_BASE \
|
||||
((unsigned int)(CONFIG_RAM_BASE + GBE_CONFIG_OFFSET))
|
||||
|
||||
#define GBE_CONFIG_BASE_VIRT \
|
||||
((void __iomem *)phys_to_virt(GBE_CONFIG_RAM_BASE))
|
||||
|
||||
#define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \
|
||||
(iowrite16_rep(base + offset, data, count))
|
||||
|
||||
#define GBE_CONFIG_FLASH_READ(base, offset, count, data) \
|
||||
(ioread16_rep(base + (offset << 1), data, count))
|
||||
|
||||
#define er32(reg) \
|
||||
(readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \
|
||||
? E1000_##reg : E1000_82542_##reg)))
|
||||
|
||||
#define ew32(reg, value) \
|
||||
(writel((value), (hw->hw_addr + ((hw->mac_type >= e1000_82543) \
|
||||
? E1000_##reg : E1000_82542_##reg))))
|
||||
|
||||
#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
|
||||
writel((value), ((a)->hw_addr + \
|
||||
(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
|
||||
((offset) << 2))))
|
||||
|
||||
#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
|
||||
readl((a)->hw_addr + \
|
||||
(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
|
||||
((offset) << 2)))
|
||||
|
||||
#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
|
||||
#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
|
||||
|
||||
#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
|
||||
writew((value), ((a)->hw_addr + \
|
||||
(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
|
||||
((offset) << 1))))
|
||||
|
||||
#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
|
||||
readw((a)->hw_addr + \
|
||||
(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
|
||||
((offset) << 1)))
|
||||
|
||||
#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
|
||||
writeb((value), ((a)->hw_addr + \
|
||||
(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
|
||||
(offset))))
|
||||
|
||||
#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
|
||||
readb((a)->hw_addr + \
|
||||
(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
|
||||
(offset)))
|
||||
|
||||
#define E1000_WRITE_FLUSH() er32(STATUS)
|
||||
|
||||
#define E1000_WRITE_ICH_FLASH_REG(a, reg, value) ( \
|
||||
writel((value), ((a)->flash_address + reg)))
|
||||
|
||||
#define E1000_READ_ICH_FLASH_REG(a, reg) ( \
|
||||
readl((a)->flash_address + reg))
|
||||
|
||||
#define E1000_WRITE_ICH_FLASH_REG16(a, reg, value) ( \
|
||||
writew((value), ((a)->flash_address + reg)))
|
||||
|
||||
#define E1000_READ_ICH_FLASH_REG16(a, reg) ( \
|
||||
readw((a)->flash_address + reg))
|
||||
|
||||
#endif /* _E1000_OSDEP_H_ */
|
||||
@@ -0,0 +1,109 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Intel PRO/1000 Linux driver
|
||||
Copyright(c) 1999 - 2006 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
Linux NICS <linux.nics@intel.com>
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* glue for the OS independent part of e1000
|
||||
* includes register access macros
|
||||
*/
|
||||
|
||||
#ifndef _E1000_OSDEP_H_
|
||||
#define _E1000_OSDEP_H_
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#define CONFIG_RAM_BASE 0x60000
|
||||
#define GBE_CONFIG_OFFSET 0x0
|
||||
|
||||
#define GBE_CONFIG_RAM_BASE \
|
||||
((unsigned int)(CONFIG_RAM_BASE + GBE_CONFIG_OFFSET))
|
||||
|
||||
#define GBE_CONFIG_BASE_VIRT \
|
||||
((void __iomem *)phys_to_virt(GBE_CONFIG_RAM_BASE))
|
||||
|
||||
#define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \
|
||||
(iowrite16_rep(base + offset, data, count))
|
||||
|
||||
#define GBE_CONFIG_FLASH_READ(base, offset, count, data) \
|
||||
(ioread16_rep(base + (offset << 1), data, count))
|
||||
|
||||
#define er32(reg) \
|
||||
(readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \
|
||||
? E1000_##reg : E1000_82542_##reg)))
|
||||
|
||||
#define ew32(reg, value) \
|
||||
(writel((value), (hw->hw_addr + ((hw->mac_type >= e1000_82543) \
|
||||
? E1000_##reg : E1000_82542_##reg))))
|
||||
|
||||
#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
|
||||
writel((value), ((a)->hw_addr + \
|
||||
(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
|
||||
((offset) << 2))))
|
||||
|
||||
#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
|
||||
readl((a)->hw_addr + \
|
||||
(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
|
||||
((offset) << 2)))
|
||||
|
||||
#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
|
||||
#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
|
||||
|
||||
#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
|
||||
writew((value), ((a)->hw_addr + \
|
||||
(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
|
||||
((offset) << 1))))
|
||||
|
||||
#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
|
||||
readw((a)->hw_addr + \
|
||||
(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
|
||||
((offset) << 1)))
|
||||
|
||||
#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
|
||||
writeb((value), ((a)->hw_addr + \
|
||||
(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
|
||||
(offset))))
|
||||
|
||||
#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
|
||||
readb((a)->hw_addr + \
|
||||
(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
|
||||
(offset)))
|
||||
|
||||
#define E1000_WRITE_FLUSH() er32(STATUS)
|
||||
|
||||
#define E1000_WRITE_ICH_FLASH_REG(a, reg, value) ( \
|
||||
writel((value), ((a)->flash_address + reg)))
|
||||
|
||||
#define E1000_READ_ICH_FLASH_REG(a, reg) ( \
|
||||
readl((a)->flash_address + reg))
|
||||
|
||||
#define E1000_WRITE_ICH_FLASH_REG16(a, reg, value) ( \
|
||||
writew((value), ((a)->flash_address + reg)))
|
||||
|
||||
#define E1000_READ_ICH_FLASH_REG16(a, reg) ( \
|
||||
readw((a)->flash_address + reg))
|
||||
|
||||
#endif /* _E1000_OSDEP_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -2,9 +2,9 @@
|
||||
|
||||
set -x
|
||||
|
||||
KERNELDIR=/data/kernel/linux-3.14.12
|
||||
PREVER=3.12
|
||||
KERNELVER=3.14
|
||||
KERNELDIR=/data/kernel/linux-3.16.6
|
||||
PREVER=3.14
|
||||
KERNELVER=3.16
|
||||
|
||||
for f in $KERNELDIR/drivers/net/ethernet/intel/e1000/*.[ch]; do
|
||||
echo $f
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,88 @@
|
||||
/* Intel PRO/1000 Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*/
|
||||
|
||||
#ifndef _E1000E_80003ES2LAN_H_
|
||||
#define _E1000E_80003ES2LAN_H_
|
||||
|
||||
#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
|
||||
#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
|
||||
#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
|
||||
#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
|
||||
|
||||
#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
|
||||
#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
|
||||
#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
|
||||
|
||||
#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
|
||||
#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
|
||||
#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
|
||||
|
||||
#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
|
||||
#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
|
||||
|
||||
#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */
|
||||
#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
|
||||
|
||||
#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
|
||||
#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
|
||||
|
||||
/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
|
||||
#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */
|
||||
#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
|
||||
#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
|
||||
#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
|
||||
#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
|
||||
|
||||
/* PHY Specific Control Register 2 (Page 0, Register 26) */
|
||||
#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */
|
||||
|
||||
/* MAC Specific Control Register (Page 2, Register 21) */
|
||||
/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
|
||||
#define GG82563_MSCR_TX_CLK_MASK 0x0007
|
||||
#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
|
||||
#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
|
||||
#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
|
||||
|
||||
#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
|
||||
|
||||
/* DSP Distance Register (Page 5, Register 26)
|
||||
* 0 = <50M
|
||||
* 1 = 50-80M
|
||||
* 2 = 80-100M
|
||||
* 3 = 110-140M
|
||||
* 4 = >140M
|
||||
*/
|
||||
#define GG82563_DSPD_CABLE_LENGTH 0x0007
|
||||
|
||||
/* Kumeran Mode Control Register (Page 193, Register 16) */
|
||||
#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
|
||||
|
||||
/* Max number of times Kumeran read/write should be validated */
|
||||
#define GG82563_MAX_KMRN_RETRY 0x5
|
||||
|
||||
/* Power Management Control Register (Page 193, Register 20) */
|
||||
/* 1=Enable SERDES Electrical Idle */
|
||||
#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
|
||||
|
||||
/* In-Band Control Register (Page 194, Register 18) */
|
||||
#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,88 @@
|
||||
/* Intel PRO/1000 Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*/
|
||||
|
||||
#ifndef _E1000E_80003ES2LAN_H_
|
||||
#define _E1000E_80003ES2LAN_H_
|
||||
|
||||
#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
|
||||
#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
|
||||
#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
|
||||
#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
|
||||
|
||||
#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
|
||||
#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
|
||||
#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
|
||||
|
||||
#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
|
||||
#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
|
||||
#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
|
||||
|
||||
#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
|
||||
#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
|
||||
|
||||
#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */
|
||||
#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
|
||||
|
||||
#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
|
||||
#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
|
||||
|
||||
/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
|
||||
#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */
|
||||
#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
|
||||
#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
|
||||
#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
|
||||
#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
|
||||
|
||||
/* PHY Specific Control Register 2 (Page 0, Register 26) */
|
||||
#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */
|
||||
|
||||
/* MAC Specific Control Register (Page 2, Register 21) */
|
||||
/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
|
||||
#define GG82563_MSCR_TX_CLK_MASK 0x0007
|
||||
#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
|
||||
#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
|
||||
#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
|
||||
|
||||
#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
|
||||
|
||||
/* DSP Distance Register (Page 5, Register 26)
|
||||
* 0 = <50M
|
||||
* 1 = 50-80M
|
||||
* 2 = 80-100M
|
||||
* 3 = 110-140M
|
||||
* 4 = >140M
|
||||
*/
|
||||
#define GG82563_DSPD_CABLE_LENGTH 0x0007
|
||||
|
||||
/* Kumeran Mode Control Register (Page 193, Register 16) */
|
||||
#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
|
||||
|
||||
/* Max number of times Kumeran read/write should be validated */
|
||||
#define GG82563_MAX_KMRN_RETRY 0x5
|
||||
|
||||
/* Power Management Control Register (Page 193, Register 20) */
|
||||
/* 1=Enable SERDES Electrical Idle */
|
||||
#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
|
||||
|
||||
/* In-Band Control Register (Page 194, Register 18) */
|
||||
#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,53 @@
|
||||
/* Intel PRO/1000 Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*/
|
||||
|
||||
#ifndef _E1000E_82571_H_
|
||||
#define _E1000E_82571_H_
|
||||
|
||||
#define ID_LED_RESERVED_F746 0xF746
|
||||
#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
|
||||
(ID_LED_OFF1_ON2 << 8) | \
|
||||
(ID_LED_DEF1_DEF2 << 4) | \
|
||||
(ID_LED_DEF1_DEF2))
|
||||
|
||||
#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
|
||||
#define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */
|
||||
|
||||
/* Intr Throttling - RW */
|
||||
#define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n)))
|
||||
|
||||
#define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */
|
||||
#define E1000_EIAC_MASK_82574 0x01F00000
|
||||
|
||||
#define E1000_IVAR_INT_ALLOC_VALID 0x8
|
||||
|
||||
/* Manageability Operation Mode mask */
|
||||
#define E1000_NVM_INIT_CTRL2_MNGM 0x6000
|
||||
|
||||
#define E1000_BASE1000T_STATUS 10
|
||||
#define E1000_IDLE_ERROR_COUNT_MASK 0xFF
|
||||
#define E1000_RECEIVE_ERROR_COUNTER 21
|
||||
#define E1000_RECEIVE_ERROR_MAX 0xFFFF
|
||||
bool e1000_check_phy_82574(struct e1000_hw *hw);
|
||||
bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
|
||||
void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,53 @@
|
||||
/* Intel PRO/1000 Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*/
|
||||
|
||||
#ifndef _E1000E_82571_H_
|
||||
#define _E1000E_82571_H_
|
||||
|
||||
#define ID_LED_RESERVED_F746 0xF746
|
||||
#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
|
||||
(ID_LED_OFF1_ON2 << 8) | \
|
||||
(ID_LED_DEF1_DEF2 << 4) | \
|
||||
(ID_LED_DEF1_DEF2))
|
||||
|
||||
#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
|
||||
#define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */
|
||||
|
||||
/* Intr Throttling - RW */
|
||||
#define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n)))
|
||||
|
||||
#define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */
|
||||
#define E1000_EIAC_MASK_82574 0x01F00000
|
||||
|
||||
#define E1000_IVAR_INT_ALLOC_VALID 0x8
|
||||
|
||||
/* Manageability Operation Mode mask */
|
||||
#define E1000_NVM_INIT_CTRL2_MNGM 0x6000
|
||||
|
||||
#define E1000_BASE1000T_STATUS 10
|
||||
#define E1000_IDLE_ERROR_COUNT_MASK 0xFF
|
||||
#define E1000_RECEIVE_ERROR_COUNTER 21
|
||||
#define E1000_RECEIVE_ERROR_MAX 0xFFFF
|
||||
bool e1000_check_phy_82574(struct e1000_hw *hw);
|
||||
bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
|
||||
void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
|
||||
|
||||
#endif
|
||||
@@ -40,6 +40,10 @@ EXTRA_DIST = \
|
||||
80003es2lan-3.14-ethercat.h \
|
||||
80003es2lan-3.14-orig.c \
|
||||
80003es2lan-3.14-orig.h \
|
||||
80003es2lan-3.16-ethercat.c \
|
||||
80003es2lan-3.16-ethercat.h \
|
||||
80003es2lan-3.16-orig.c \
|
||||
80003es2lan-3.16-orig.h \
|
||||
80003es2lan-3.4-ethercat.c \
|
||||
80003es2lan-3.4-orig.c \
|
||||
80003es2lan-3.6-ethercat.c \
|
||||
@@ -68,6 +72,10 @@ EXTRA_DIST = \
|
||||
82571-3.14-ethercat.h \
|
||||
82571-3.14-orig.c \
|
||||
82571-3.14-orig.h \
|
||||
82571-3.16-ethercat.c \
|
||||
82571-3.16-ethercat.h \
|
||||
82571-3.16-orig.c \
|
||||
82571-3.16-orig.h \
|
||||
82571-3.2-ethercat.c \
|
||||
82571-3.2-orig.c \
|
||||
82571-3.4-ethercat.c \
|
||||
@@ -93,6 +101,8 @@ EXTRA_DIST = \
|
||||
defines-3.12-orig.h \
|
||||
defines-3.14-ethercat.h \
|
||||
defines-3.14-orig.h \
|
||||
defines-3.16-ethercat.h \
|
||||
defines-3.16-orig.h \
|
||||
defines-3.2-ethercat.h \
|
||||
defines-3.2-orig.h \
|
||||
defines-3.4-ethercat.h \
|
||||
@@ -117,6 +127,8 @@ EXTRA_DIST = \
|
||||
e1000-3.12-orig.h \
|
||||
e1000-3.14-ethercat.h \
|
||||
e1000-3.14-orig.h \
|
||||
e1000-3.16-ethercat.h \
|
||||
e1000-3.16-orig.h \
|
||||
e1000-3.2-ethercat.h \
|
||||
e1000-3.2-orig.h \
|
||||
e1000-3.4-ethercat.h \
|
||||
@@ -153,6 +165,8 @@ EXTRA_DIST = \
|
||||
ethtool-3.12-orig.c \
|
||||
ethtool-3.14-ethercat.c \
|
||||
ethtool-3.14-orig.c \
|
||||
ethtool-3.16-ethercat.c \
|
||||
ethtool-3.16-orig.c \
|
||||
ethtool-3.2-ethercat.c \
|
||||
ethtool-3.2-orig.c \
|
||||
ethtool-3.4-ethercat.c \
|
||||
@@ -177,6 +191,8 @@ EXTRA_DIST = \
|
||||
hw-3.12-orig.h \
|
||||
hw-3.14-ethercat.h \
|
||||
hw-3.14-orig.h \
|
||||
hw-3.16-ethercat.h \
|
||||
hw-3.16-orig.h \
|
||||
hw-3.2-ethercat.h \
|
||||
hw-3.2-orig.h \
|
||||
hw-3.4-ethercat.h \
|
||||
@@ -207,6 +223,10 @@ EXTRA_DIST = \
|
||||
ich8lan-3.14-ethercat.h \
|
||||
ich8lan-3.14-orig.c \
|
||||
ich8lan-3.14-orig.h \
|
||||
ich8lan-3.16-ethercat.c \
|
||||
ich8lan-3.16-ethercat.h \
|
||||
ich8lan-3.16-orig.c \
|
||||
ich8lan-3.16-orig.h \
|
||||
ich8lan-3.2-ethercat.c \
|
||||
ich8lan-3.2-orig.c \
|
||||
ich8lan-3.4-ethercat.c \
|
||||
@@ -239,6 +259,10 @@ EXTRA_DIST = \
|
||||
mac-3.14-ethercat.h \
|
||||
mac-3.14-orig.c \
|
||||
mac-3.14-orig.h \
|
||||
mac-3.16-ethercat.c \
|
||||
mac-3.16-ethercat.h \
|
||||
mac-3.16-orig.c \
|
||||
mac-3.16-orig.h \
|
||||
mac-3.4-ethercat.c \
|
||||
mac-3.4-orig.c \
|
||||
mac-3.6-ethercat.c \
|
||||
@@ -257,6 +281,10 @@ EXTRA_DIST = \
|
||||
manage-3.14-ethercat.h \
|
||||
manage-3.14-orig.c \
|
||||
manage-3.14-orig.h \
|
||||
manage-3.16-ethercat.c \
|
||||
manage-3.16-ethercat.h \
|
||||
manage-3.16-orig.c \
|
||||
manage-3.16-orig.h \
|
||||
manage-3.4-ethercat.c \
|
||||
manage-3.4-orig.c \
|
||||
manage-3.6-ethercat.c \
|
||||
@@ -279,6 +307,8 @@ EXTRA_DIST = \
|
||||
netdev-3.12-orig.c \
|
||||
netdev-3.14-ethercat.c \
|
||||
netdev-3.14-orig.c \
|
||||
netdev-3.16-ethercat.c \
|
||||
netdev-3.16-orig.c \
|
||||
netdev-3.2-ethercat.c \
|
||||
netdev-3.2-orig.c \
|
||||
netdev-3.4-ethercat.c \
|
||||
@@ -299,6 +329,10 @@ EXTRA_DIST = \
|
||||
nvm-3.14-ethercat.h \
|
||||
nvm-3.14-orig.c \
|
||||
nvm-3.14-orig.h \
|
||||
nvm-3.16-ethercat.c \
|
||||
nvm-3.16-ethercat.h \
|
||||
nvm-3.16-orig.c \
|
||||
nvm-3.16-orig.h \
|
||||
nvm-3.4-ethercat.c \
|
||||
nvm-3.4-orig.c \
|
||||
nvm-3.6-ethercat.c \
|
||||
@@ -321,6 +355,8 @@ EXTRA_DIST = \
|
||||
param-3.12-orig.c \
|
||||
param-3.14-ethercat.c \
|
||||
param-3.14-orig.c \
|
||||
param-3.16-ethercat.c \
|
||||
param-3.16-orig.c \
|
||||
param-3.2-ethercat.c \
|
||||
param-3.2-orig.c \
|
||||
param-3.4-ethercat.c \
|
||||
@@ -351,6 +387,10 @@ EXTRA_DIST = \
|
||||
phy-3.14-ethercat.h \
|
||||
phy-3.14-orig.c \
|
||||
phy-3.14-orig.h \
|
||||
phy-3.16-ethercat.c \
|
||||
phy-3.16-ethercat.h \
|
||||
phy-3.16-orig.c \
|
||||
phy-3.16-orig.h \
|
||||
phy-3.2-ethercat.c \
|
||||
phy-3.2-orig.c \
|
||||
phy-3.4-ethercat.c \
|
||||
@@ -365,12 +405,16 @@ EXTRA_DIST = \
|
||||
ptp-3.12-orig.c \
|
||||
ptp-3.14-ethercat.c \
|
||||
ptp-3.14-orig.c \
|
||||
ptp-3.16-ethercat.c \
|
||||
ptp-3.16-orig.c \
|
||||
regs-3.10-ethercat.h \
|
||||
regs-3.10-orig.h \
|
||||
regs-3.12-ethercat.h \
|
||||
regs-3.12-orig.h \
|
||||
regs-3.14-ethercat.h \
|
||||
regs-3.14-orig.h \
|
||||
regs-3.16-ethercat.h \
|
||||
regs-3.16-orig.h \
|
||||
update.sh
|
||||
|
||||
BUILT_SOURCES = \
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,290 @@
|
||||
/* Intel PRO/1000 Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*/
|
||||
|
||||
#ifndef _E1000E_ICH8LAN_H_
|
||||
#define _E1000E_ICH8LAN_H_
|
||||
|
||||
#define ICH_FLASH_GFPREG 0x0000
|
||||
#define ICH_FLASH_HSFSTS 0x0004
|
||||
#define ICH_FLASH_HSFCTL 0x0006
|
||||
#define ICH_FLASH_FADDR 0x0008
|
||||
#define ICH_FLASH_FDATA0 0x0010
|
||||
#define ICH_FLASH_PR0 0x0074
|
||||
|
||||
/* Requires up to 10 seconds when MNG might be accessing part. */
|
||||
#define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000
|
||||
#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
|
||||
#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
|
||||
#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
|
||||
#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
|
||||
|
||||
#define ICH_CYCLE_READ 0
|
||||
#define ICH_CYCLE_WRITE 2
|
||||
#define ICH_CYCLE_ERASE 3
|
||||
|
||||
#define FLASH_GFPREG_BASE_MASK 0x1FFF
|
||||
#define FLASH_SECTOR_ADDR_SHIFT 12
|
||||
|
||||
#define ICH_FLASH_SEG_SIZE_256 256
|
||||
#define ICH_FLASH_SEG_SIZE_4K 4096
|
||||
#define ICH_FLASH_SEG_SIZE_8K 8192
|
||||
#define ICH_FLASH_SEG_SIZE_64K 65536
|
||||
|
||||
#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
|
||||
/* FW established a valid mode */
|
||||
#define E1000_ICH_FWSM_FW_VALID 0x00008000
|
||||
#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
|
||||
#define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
|
||||
|
||||
#define E1000_ICH_MNG_IAMT_MODE 0x2
|
||||
|
||||
#define E1000_FWSM_WLOCK_MAC_MASK 0x0380
|
||||
#define E1000_FWSM_WLOCK_MAC_SHIFT 7
|
||||
#define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */
|
||||
|
||||
/* Shared Receive Address Registers */
|
||||
#define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8))
|
||||
#define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8))
|
||||
|
||||
#define E1000_H2ME 0x05B50 /* Host to ME */
|
||||
#define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */
|
||||
#define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */
|
||||
|
||||
#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
|
||||
(ID_LED_OFF1_OFF2 << 8) | \
|
||||
(ID_LED_OFF1_ON2 << 4) | \
|
||||
(ID_LED_DEF1_DEF2))
|
||||
|
||||
#define E1000_ICH_NVM_SIG_WORD 0x13
|
||||
#define E1000_ICH_NVM_SIG_MASK 0xC000
|
||||
#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
|
||||
#define E1000_ICH_NVM_SIG_VALUE 0x80
|
||||
|
||||
#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
|
||||
|
||||
/* FEXT register bit definition */
|
||||
#define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004
|
||||
|
||||
#define E1000_FEXTNVM_SW_CONFIG 1
|
||||
#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */
|
||||
|
||||
#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
|
||||
#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
|
||||
|
||||
#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
|
||||
#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
|
||||
#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
|
||||
|
||||
#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100
|
||||
#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200
|
||||
|
||||
#define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
|
||||
|
||||
#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
|
||||
|
||||
#define E1000_ICH_RAR_ENTRIES 7
|
||||
#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
|
||||
#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
|
||||
|
||||
#define PHY_PAGE_SHIFT 5
|
||||
#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
|
||||
((reg) & MAX_PHY_REG_ADDRESS))
|
||||
#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
|
||||
#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
|
||||
|
||||
#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
|
||||
#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
|
||||
#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
|
||||
|
||||
/* PHY Wakeup Registers and defines */
|
||||
#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
|
||||
#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
|
||||
#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
|
||||
#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
|
||||
#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
|
||||
#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
|
||||
#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
|
||||
#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
|
||||
#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
|
||||
#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
|
||||
|
||||
#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
|
||||
#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
|
||||
#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
|
||||
#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
|
||||
#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
|
||||
#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
|
||||
#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
|
||||
|
||||
#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
|
||||
#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
|
||||
#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
|
||||
#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
|
||||
#define HV_STATS_PAGE 778
|
||||
/* Half-duplex collision counts */
|
||||
#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */
|
||||
#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
|
||||
#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */
|
||||
#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
|
||||
#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */
|
||||
#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
|
||||
#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */
|
||||
#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
|
||||
#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */
|
||||
#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
|
||||
#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
|
||||
#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
|
||||
#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */
|
||||
#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
|
||||
|
||||
#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
|
||||
|
||||
#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
|
||||
#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
|
||||
|
||||
/* SMBus Control Phy Register */
|
||||
#define CV_SMB_CTRL PHY_REG(769, 23)
|
||||
#define CV_SMB_CTRL_FORCE_SMBUS 0x0001
|
||||
|
||||
/* I218 Ultra Low Power Configuration 1 Register */
|
||||
#define I218_ULP_CONFIG1 PHY_REG(779, 16)
|
||||
#define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */
|
||||
#define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */
|
||||
#define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */
|
||||
#define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */
|
||||
#define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */
|
||||
#define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */
|
||||
#define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */
|
||||
|
||||
/* SMBus Address Phy Register */
|
||||
#define HV_SMB_ADDR PHY_REG(768, 26)
|
||||
#define HV_SMB_ADDR_MASK 0x007F
|
||||
#define HV_SMB_ADDR_PEC_EN 0x0200
|
||||
#define HV_SMB_ADDR_VALID 0x0080
|
||||
#define HV_SMB_ADDR_FREQ_MASK 0x1100
|
||||
#define HV_SMB_ADDR_FREQ_LOW_SHIFT 8
|
||||
#define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12
|
||||
|
||||
/* Strapping Option Register - RO */
|
||||
#define E1000_STRAP 0x0000C
|
||||
#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
|
||||
#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
|
||||
#define E1000_STRAP_SMT_FREQ_MASK 0x00003000
|
||||
#define E1000_STRAP_SMT_FREQ_SHIFT 12
|
||||
|
||||
/* OEM Bits Phy Register */
|
||||
#define HV_OEM_BITS PHY_REG(768, 25)
|
||||
#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
|
||||
#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
|
||||
#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
|
||||
|
||||
/* KMRN Mode Control */
|
||||
#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
|
||||
#define HV_KMRN_MDIO_SLOW 0x0400
|
||||
|
||||
/* KMRN FIFO Control and Status */
|
||||
#define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
|
||||
#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
|
||||
#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
|
||||
|
||||
/* PHY Power Management Control */
|
||||
#define HV_PM_CTRL PHY_REG(770, 17)
|
||||
#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
|
||||
#define HV_PM_CTRL_K1_ENABLE 0x4000
|
||||
|
||||
#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */
|
||||
|
||||
/* Inband Control */
|
||||
#define I217_INBAND_CTRL PHY_REG(770, 18)
|
||||
#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00
|
||||
#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8
|
||||
|
||||
/* PHY Low Power Idle Control */
|
||||
#define I82579_LPI_CTRL PHY_REG(772, 20)
|
||||
#define I82579_LPI_CTRL_100_ENABLE 0x2000
|
||||
#define I82579_LPI_CTRL_1000_ENABLE 0x4000
|
||||
#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
|
||||
#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80
|
||||
|
||||
/* Extended Management Interface (EMI) Registers */
|
||||
#define I82579_EMI_ADDR 0x10
|
||||
#define I82579_EMI_DATA 0x11
|
||||
#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
|
||||
#define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */
|
||||
#define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */
|
||||
#define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
|
||||
#define I82579_RX_CONFIG 0x3412 /* Receive configuration */
|
||||
#define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */
|
||||
#define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */
|
||||
#define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */
|
||||
#define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */
|
||||
#define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */
|
||||
#define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */
|
||||
#define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */
|
||||
#define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */
|
||||
#define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */
|
||||
#define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */
|
||||
#define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
|
||||
#define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */
|
||||
#define I217_RX_CONFIG 0xB20C /* Receive configuration */
|
||||
|
||||
#define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */
|
||||
#define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */
|
||||
|
||||
/* Intel Rapid Start Technology Support */
|
||||
#define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70)
|
||||
#define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
|
||||
#define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
|
||||
#define I217_SxCTRL_ENABLE_LPI_RESET 0x1000
|
||||
#define I217_CGFREG PHY_REG(772, 29)
|
||||
#define I217_CGFREG_ENABLE_MTA_RESET 0x0002
|
||||
#define I217_MEMPWR PHY_REG(772, 26)
|
||||
#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
|
||||
|
||||
/* Receive Address Initial CRC Calculation */
|
||||
#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
|
||||
|
||||
/* Latency Tolerance Reporting */
|
||||
#define E1000_LTRV 0x000F8
|
||||
#define E1000_LTRV_SCALE_MAX 5
|
||||
#define E1000_LTRV_SCALE_FACTOR 5
|
||||
#define E1000_LTRV_REQ_SHIFT 15
|
||||
#define E1000_LTRV_NOSNOOP_SHIFT 16
|
||||
#define E1000_LTRV_SEND (1 << 30)
|
||||
|
||||
/* Proprietary Latency Tolerance Reporting PCI Capability */
|
||||
#define E1000_PCI_LTR_CAP_LPT 0xA8
|
||||
|
||||
void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
|
||||
void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
|
||||
bool state);
|
||||
void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
|
||||
void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
|
||||
void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
|
||||
void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
|
||||
s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
|
||||
void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
|
||||
s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
|
||||
s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
|
||||
s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data);
|
||||
s32 e1000_set_eee_pchlan(struct e1000_hw *hw);
|
||||
s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx);
|
||||
#endif /* _E1000E_ICH8LAN_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,290 @@
|
||||
/* Intel PRO/1000 Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*/
|
||||
|
||||
#ifndef _E1000E_ICH8LAN_H_
|
||||
#define _E1000E_ICH8LAN_H_
|
||||
|
||||
#define ICH_FLASH_GFPREG 0x0000
|
||||
#define ICH_FLASH_HSFSTS 0x0004
|
||||
#define ICH_FLASH_HSFCTL 0x0006
|
||||
#define ICH_FLASH_FADDR 0x0008
|
||||
#define ICH_FLASH_FDATA0 0x0010
|
||||
#define ICH_FLASH_PR0 0x0074
|
||||
|
||||
/* Requires up to 10 seconds when MNG might be accessing part. */
|
||||
#define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000
|
||||
#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
|
||||
#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
|
||||
#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
|
||||
#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
|
||||
|
||||
#define ICH_CYCLE_READ 0
|
||||
#define ICH_CYCLE_WRITE 2
|
||||
#define ICH_CYCLE_ERASE 3
|
||||
|
||||
#define FLASH_GFPREG_BASE_MASK 0x1FFF
|
||||
#define FLASH_SECTOR_ADDR_SHIFT 12
|
||||
|
||||
#define ICH_FLASH_SEG_SIZE_256 256
|
||||
#define ICH_FLASH_SEG_SIZE_4K 4096
|
||||
#define ICH_FLASH_SEG_SIZE_8K 8192
|
||||
#define ICH_FLASH_SEG_SIZE_64K 65536
|
||||
|
||||
#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
|
||||
/* FW established a valid mode */
|
||||
#define E1000_ICH_FWSM_FW_VALID 0x00008000
|
||||
#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
|
||||
#define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
|
||||
|
||||
#define E1000_ICH_MNG_IAMT_MODE 0x2
|
||||
|
||||
#define E1000_FWSM_WLOCK_MAC_MASK 0x0380
|
||||
#define E1000_FWSM_WLOCK_MAC_SHIFT 7
|
||||
#define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */
|
||||
|
||||
/* Shared Receive Address Registers */
|
||||
#define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8))
|
||||
#define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8))
|
||||
|
||||
#define E1000_H2ME 0x05B50 /* Host to ME */
|
||||
#define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */
|
||||
#define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */
|
||||
|
||||
#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
|
||||
(ID_LED_OFF1_OFF2 << 8) | \
|
||||
(ID_LED_OFF1_ON2 << 4) | \
|
||||
(ID_LED_DEF1_DEF2))
|
||||
|
||||
#define E1000_ICH_NVM_SIG_WORD 0x13
|
||||
#define E1000_ICH_NVM_SIG_MASK 0xC000
|
||||
#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
|
||||
#define E1000_ICH_NVM_SIG_VALUE 0x80
|
||||
|
||||
#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
|
||||
|
||||
/* FEXT register bit definition */
|
||||
#define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004
|
||||
|
||||
#define E1000_FEXTNVM_SW_CONFIG 1
|
||||
#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */
|
||||
|
||||
#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
|
||||
#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
|
||||
|
||||
#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
|
||||
#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
|
||||
#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
|
||||
|
||||
#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100
|
||||
#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200
|
||||
|
||||
#define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
|
||||
|
||||
#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
|
||||
|
||||
#define E1000_ICH_RAR_ENTRIES 7
|
||||
#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
|
||||
#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
|
||||
|
||||
#define PHY_PAGE_SHIFT 5
|
||||
#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
|
||||
((reg) & MAX_PHY_REG_ADDRESS))
|
||||
#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
|
||||
#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
|
||||
|
||||
#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
|
||||
#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
|
||||
#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
|
||||
|
||||
/* PHY Wakeup Registers and defines */
|
||||
#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
|
||||
#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
|
||||
#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
|
||||
#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
|
||||
#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
|
||||
#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
|
||||
#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
|
||||
#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
|
||||
#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
|
||||
#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
|
||||
|
||||
#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
|
||||
#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
|
||||
#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
|
||||
#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
|
||||
#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
|
||||
#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
|
||||
#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
|
||||
|
||||
#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
|
||||
#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
|
||||
#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
|
||||
#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
|
||||
#define HV_STATS_PAGE 778
|
||||
/* Half-duplex collision counts */
|
||||
#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */
|
||||
#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
|
||||
#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */
|
||||
#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
|
||||
#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */
|
||||
#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
|
||||
#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */
|
||||
#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
|
||||
#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */
|
||||
#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
|
||||
#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
|
||||
#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
|
||||
#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */
|
||||
#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
|
||||
|
||||
#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
|
||||
|
||||
#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
|
||||
#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
|
||||
|
||||
/* SMBus Control Phy Register */
|
||||
#define CV_SMB_CTRL PHY_REG(769, 23)
|
||||
#define CV_SMB_CTRL_FORCE_SMBUS 0x0001
|
||||
|
||||
/* I218 Ultra Low Power Configuration 1 Register */
|
||||
#define I218_ULP_CONFIG1 PHY_REG(779, 16)
|
||||
#define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */
|
||||
#define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */
|
||||
#define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */
|
||||
#define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */
|
||||
#define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */
|
||||
#define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */
|
||||
#define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */
|
||||
|
||||
/* SMBus Address Phy Register */
|
||||
#define HV_SMB_ADDR PHY_REG(768, 26)
|
||||
#define HV_SMB_ADDR_MASK 0x007F
|
||||
#define HV_SMB_ADDR_PEC_EN 0x0200
|
||||
#define HV_SMB_ADDR_VALID 0x0080
|
||||
#define HV_SMB_ADDR_FREQ_MASK 0x1100
|
||||
#define HV_SMB_ADDR_FREQ_LOW_SHIFT 8
|
||||
#define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12
|
||||
|
||||
/* Strapping Option Register - RO */
|
||||
#define E1000_STRAP 0x0000C
|
||||
#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
|
||||
#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
|
||||
#define E1000_STRAP_SMT_FREQ_MASK 0x00003000
|
||||
#define E1000_STRAP_SMT_FREQ_SHIFT 12
|
||||
|
||||
/* OEM Bits Phy Register */
|
||||
#define HV_OEM_BITS PHY_REG(768, 25)
|
||||
#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
|
||||
#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
|
||||
#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
|
||||
|
||||
/* KMRN Mode Control */
|
||||
#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
|
||||
#define HV_KMRN_MDIO_SLOW 0x0400
|
||||
|
||||
/* KMRN FIFO Control and Status */
|
||||
#define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
|
||||
#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
|
||||
#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
|
||||
|
||||
/* PHY Power Management Control */
|
||||
#define HV_PM_CTRL PHY_REG(770, 17)
|
||||
#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
|
||||
#define HV_PM_CTRL_K1_ENABLE 0x4000
|
||||
|
||||
#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */
|
||||
|
||||
/* Inband Control */
|
||||
#define I217_INBAND_CTRL PHY_REG(770, 18)
|
||||
#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00
|
||||
#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8
|
||||
|
||||
/* PHY Low Power Idle Control */
|
||||
#define I82579_LPI_CTRL PHY_REG(772, 20)
|
||||
#define I82579_LPI_CTRL_100_ENABLE 0x2000
|
||||
#define I82579_LPI_CTRL_1000_ENABLE 0x4000
|
||||
#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
|
||||
#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80
|
||||
|
||||
/* Extended Management Interface (EMI) Registers */
|
||||
#define I82579_EMI_ADDR 0x10
|
||||
#define I82579_EMI_DATA 0x11
|
||||
#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
|
||||
#define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */
|
||||
#define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */
|
||||
#define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
|
||||
#define I82579_RX_CONFIG 0x3412 /* Receive configuration */
|
||||
#define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */
|
||||
#define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */
|
||||
#define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */
|
||||
#define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */
|
||||
#define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */
|
||||
#define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */
|
||||
#define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */
|
||||
#define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */
|
||||
#define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */
|
||||
#define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */
|
||||
#define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
|
||||
#define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */
|
||||
#define I217_RX_CONFIG 0xB20C /* Receive configuration */
|
||||
|
||||
#define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */
|
||||
#define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */
|
||||
|
||||
/* Intel Rapid Start Technology Support */
|
||||
#define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70)
|
||||
#define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
|
||||
#define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
|
||||
#define I217_SxCTRL_ENABLE_LPI_RESET 0x1000
|
||||
#define I217_CGFREG PHY_REG(772, 29)
|
||||
#define I217_CGFREG_ENABLE_MTA_RESET 0x0002
|
||||
#define I217_MEMPWR PHY_REG(772, 26)
|
||||
#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
|
||||
|
||||
/* Receive Address Initial CRC Calculation */
|
||||
#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
|
||||
|
||||
/* Latency Tolerance Reporting */
|
||||
#define E1000_LTRV 0x000F8
|
||||
#define E1000_LTRV_SCALE_MAX 5
|
||||
#define E1000_LTRV_SCALE_FACTOR 5
|
||||
#define E1000_LTRV_REQ_SHIFT 15
|
||||
#define E1000_LTRV_NOSNOOP_SHIFT 16
|
||||
#define E1000_LTRV_SEND (1 << 30)
|
||||
|
||||
/* Proprietary Latency Tolerance Reporting PCI Capability */
|
||||
#define E1000_PCI_LTR_CAP_LPT 0xA8
|
||||
|
||||
void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
|
||||
void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
|
||||
bool state);
|
||||
void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
|
||||
void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
|
||||
void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
|
||||
void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
|
||||
s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
|
||||
void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
|
||||
s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
|
||||
s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
|
||||
s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data);
|
||||
s32 e1000_set_eee_pchlan(struct e1000_hw *hw);
|
||||
s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx);
|
||||
#endif /* _E1000E_ICH8LAN_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,68 @@
|
||||
/* Intel PRO/1000 Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*/
|
||||
|
||||
#ifndef _E1000E_MAC_H_
|
||||
#define _E1000E_MAC_H_
|
||||
|
||||
s32 e1000e_blink_led_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
|
||||
s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
|
||||
s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
|
||||
s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
|
||||
s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
|
||||
s32 e1000e_force_mac_fc(struct e1000_hw *hw);
|
||||
s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
|
||||
s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
|
||||
void e1000_set_lan_id_single_port(struct e1000_hw *hw);
|
||||
s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
|
||||
s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
|
||||
u16 *duplex);
|
||||
s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw,
|
||||
u16 *speed, u16 *duplex);
|
||||
s32 e1000e_id_led_init_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_led_on_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_led_off_generic(struct e1000_hw *hw);
|
||||
void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
|
||||
u8 *mc_addr_list, u32 mc_addr_count);
|
||||
s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
|
||||
s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
|
||||
s32 e1000e_setup_led_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_setup_link_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_validate_mdi_setting_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_validate_mdi_setting_crossover_generic(struct e1000_hw *hw);
|
||||
|
||||
void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
|
||||
void e1000_clear_vfta_generic(struct e1000_hw *hw);
|
||||
void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
|
||||
void e1000e_put_hw_semaphore(struct e1000_hw *hw);
|
||||
s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
|
||||
void e1000e_reset_adaptive(struct e1000_hw *hw);
|
||||
void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
|
||||
void e1000e_update_adaptive(struct e1000_hw *hw);
|
||||
void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
|
||||
|
||||
void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
|
||||
u32 e1000e_rar_get_count_generic(struct e1000_hw *hw);
|
||||
int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
|
||||
void e1000e_config_collision_dist_generic(struct e1000_hw *hw);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,68 @@
|
||||
/* Intel PRO/1000 Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*/
|
||||
|
||||
#ifndef _E1000E_MAC_H_
|
||||
#define _E1000E_MAC_H_
|
||||
|
||||
s32 e1000e_blink_led_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
|
||||
s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
|
||||
s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
|
||||
s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
|
||||
s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
|
||||
s32 e1000e_force_mac_fc(struct e1000_hw *hw);
|
||||
s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
|
||||
s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
|
||||
void e1000_set_lan_id_single_port(struct e1000_hw *hw);
|
||||
s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
|
||||
s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
|
||||
u16 *duplex);
|
||||
s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw,
|
||||
u16 *speed, u16 *duplex);
|
||||
s32 e1000e_id_led_init_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_led_on_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_led_off_generic(struct e1000_hw *hw);
|
||||
void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
|
||||
u8 *mc_addr_list, u32 mc_addr_count);
|
||||
s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
|
||||
s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
|
||||
s32 e1000e_setup_led_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_setup_link_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_validate_mdi_setting_generic(struct e1000_hw *hw);
|
||||
s32 e1000e_validate_mdi_setting_crossover_generic(struct e1000_hw *hw);
|
||||
|
||||
void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
|
||||
void e1000_clear_vfta_generic(struct e1000_hw *hw);
|
||||
void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
|
||||
void e1000e_put_hw_semaphore(struct e1000_hw *hw);
|
||||
s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
|
||||
void e1000e_reset_adaptive(struct e1000_hw *hw);
|
||||
void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
|
||||
void e1000e_update_adaptive(struct e1000_hw *hw);
|
||||
void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
|
||||
|
||||
void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
|
||||
u32 e1000e_rar_get_count_generic(struct e1000_hw *hw);
|
||||
int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
|
||||
void e1000e_config_collision_dist_generic(struct e1000_hw *hw);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,344 @@
|
||||
/* Intel PRO/1000 Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*/
|
||||
|
||||
#include "e1000-3.16-ethercat.h"
|
||||
|
||||
/**
|
||||
* e1000_calculate_checksum - Calculate checksum for buffer
|
||||
* @buffer: pointer to EEPROM
|
||||
* @length: size of EEPROM to calculate a checksum for
|
||||
*
|
||||
* Calculates the checksum for some buffer on a specified length. The
|
||||
* checksum calculated is returned.
|
||||
**/
|
||||
static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
|
||||
{
|
||||
u32 i;
|
||||
u8 sum = 0;
|
||||
|
||||
if (!buffer)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < length; i++)
|
||||
sum += buffer[i];
|
||||
|
||||
return (u8)(0 - sum);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_mng_enable_host_if - Checks host interface is enabled
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
|
||||
*
|
||||
* This function checks whether the HOST IF is enabled for command operation
|
||||
* and also checks whether the previous command is completed. It busy waits
|
||||
* in case of previous command is not completed.
|
||||
**/
|
||||
static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
|
||||
{
|
||||
u32 hicr;
|
||||
u8 i;
|
||||
|
||||
if (!hw->mac.arc_subsystem_valid) {
|
||||
e_dbg("ARC subsystem not valid.\n");
|
||||
return -E1000_ERR_HOST_INTERFACE_COMMAND;
|
||||
}
|
||||
|
||||
/* Check that the host interface is enabled. */
|
||||
hicr = er32(HICR);
|
||||
if (!(hicr & E1000_HICR_EN)) {
|
||||
e_dbg("E1000_HOST_EN bit disabled.\n");
|
||||
return -E1000_ERR_HOST_INTERFACE_COMMAND;
|
||||
}
|
||||
/* check the previous command is completed */
|
||||
for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
|
||||
hicr = er32(HICR);
|
||||
if (!(hicr & E1000_HICR_C))
|
||||
break;
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
|
||||
e_dbg("Previous command timeout failed .\n");
|
||||
return -E1000_ERR_HOST_INTERFACE_COMMAND;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000e_check_mng_mode_generic - Generic check management mode
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Reads the firmware semaphore register and returns true (>0) if
|
||||
* manageability is enabled, else false (0).
|
||||
**/
|
||||
bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
|
||||
{
|
||||
u32 fwsm = er32(FWSM);
|
||||
|
||||
return (fwsm & E1000_FWSM_MODE_MASK) ==
|
||||
(E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Enables packet filtering on transmit packets if manageability is enabled
|
||||
* and host interface is enabled.
|
||||
**/
|
||||
bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
|
||||
{
|
||||
struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
|
||||
u32 *buffer = (u32 *)&hw->mng_cookie;
|
||||
u32 offset;
|
||||
s32 ret_val, hdr_csum, csum;
|
||||
u8 i, len;
|
||||
|
||||
hw->mac.tx_pkt_filtering = true;
|
||||
|
||||
/* No manageability, no filtering */
|
||||
if (!hw->mac.ops.check_mng_mode(hw)) {
|
||||
hw->mac.tx_pkt_filtering = false;
|
||||
return hw->mac.tx_pkt_filtering;
|
||||
}
|
||||
|
||||
/* If we can't read from the host interface for whatever
|
||||
* reason, disable filtering.
|
||||
*/
|
||||
ret_val = e1000_mng_enable_host_if(hw);
|
||||
if (ret_val) {
|
||||
hw->mac.tx_pkt_filtering = false;
|
||||
return hw->mac.tx_pkt_filtering;
|
||||
}
|
||||
|
||||
/* Read in the header. Length and offset are in dwords. */
|
||||
len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
|
||||
offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
|
||||
for (i = 0; i < len; i++)
|
||||
*(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF,
|
||||
offset + i);
|
||||
hdr_csum = hdr->checksum;
|
||||
hdr->checksum = 0;
|
||||
csum = e1000_calculate_checksum((u8 *)hdr,
|
||||
E1000_MNG_DHCP_COOKIE_LENGTH);
|
||||
/* If either the checksums or signature don't match, then
|
||||
* the cookie area isn't considered valid, in which case we
|
||||
* take the safe route of assuming Tx filtering is enabled.
|
||||
*/
|
||||
if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
|
||||
hw->mac.tx_pkt_filtering = true;
|
||||
return hw->mac.tx_pkt_filtering;
|
||||
}
|
||||
|
||||
/* Cookie area is valid, make the final check for filtering. */
|
||||
if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
|
||||
hw->mac.tx_pkt_filtering = false;
|
||||
|
||||
return hw->mac.tx_pkt_filtering;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_mng_write_cmd_header - Writes manageability command header
|
||||
* @hw: pointer to the HW structure
|
||||
* @hdr: pointer to the host interface command header
|
||||
*
|
||||
* Writes the command header after does the checksum calculation.
|
||||
**/
|
||||
static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
|
||||
struct e1000_host_mng_command_header *hdr)
|
||||
{
|
||||
u16 i, length = sizeof(struct e1000_host_mng_command_header);
|
||||
|
||||
/* Write the whole command header structure with new checksum. */
|
||||
|
||||
hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
|
||||
|
||||
length >>= 2;
|
||||
/* Write the relevant command block into the ram area. */
|
||||
for (i = 0; i < length; i++) {
|
||||
E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i, *((u32 *)hdr + i));
|
||||
e1e_flush();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_mng_host_if_write - Write to the manageability host interface
|
||||
* @hw: pointer to the HW structure
|
||||
* @buffer: pointer to the host interface buffer
|
||||
* @length: size of the buffer
|
||||
* @offset: location in the buffer to write to
|
||||
* @sum: sum of the data (not checksum)
|
||||
*
|
||||
* This function writes the buffer content at the offset given on the host if.
|
||||
* It also does alignment considerations to do the writes in most efficient
|
||||
* way. Also fills up the sum of the buffer in *buffer parameter.
|
||||
**/
|
||||
static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
|
||||
u16 length, u16 offset, u8 *sum)
|
||||
{
|
||||
u8 *tmp;
|
||||
u8 *bufptr = buffer;
|
||||
u32 data = 0;
|
||||
u16 remaining, i, j, prev_bytes;
|
||||
|
||||
/* sum = only sum of the data and it is not checksum */
|
||||
|
||||
if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
|
||||
return -E1000_ERR_PARAM;
|
||||
|
||||
tmp = (u8 *)&data;
|
||||
prev_bytes = offset & 0x3;
|
||||
offset >>= 2;
|
||||
|
||||
if (prev_bytes) {
|
||||
data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
|
||||
for (j = prev_bytes; j < sizeof(u32); j++) {
|
||||
*(tmp + j) = *bufptr++;
|
||||
*sum += *(tmp + j);
|
||||
}
|
||||
E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
|
||||
length -= j - prev_bytes;
|
||||
offset++;
|
||||
}
|
||||
|
||||
remaining = length & 0x3;
|
||||
length -= remaining;
|
||||
|
||||
/* Calculate length in DWORDs */
|
||||
length >>= 2;
|
||||
|
||||
/* The device driver writes the relevant command block into the
|
||||
* ram area.
|
||||
*/
|
||||
for (i = 0; i < length; i++) {
|
||||
for (j = 0; j < sizeof(u32); j++) {
|
||||
*(tmp + j) = *bufptr++;
|
||||
*sum += *(tmp + j);
|
||||
}
|
||||
|
||||
E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
|
||||
}
|
||||
if (remaining) {
|
||||
for (j = 0; j < sizeof(u32); j++) {
|
||||
if (j < remaining)
|
||||
*(tmp + j) = *bufptr++;
|
||||
else
|
||||
*(tmp + j) = 0;
|
||||
|
||||
*sum += *(tmp + j);
|
||||
}
|
||||
E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
|
||||
* @hw: pointer to the HW structure
|
||||
* @buffer: pointer to the host interface
|
||||
* @length: size of the buffer
|
||||
*
|
||||
* Writes the DHCP information to the host interface.
|
||||
**/
|
||||
s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
|
||||
{
|
||||
struct e1000_host_mng_command_header hdr;
|
||||
s32 ret_val;
|
||||
u32 hicr;
|
||||
|
||||
hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
|
||||
hdr.command_length = length;
|
||||
hdr.reserved1 = 0;
|
||||
hdr.reserved2 = 0;
|
||||
hdr.checksum = 0;
|
||||
|
||||
/* Enable the host interface */
|
||||
ret_val = e1000_mng_enable_host_if(hw);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
/* Populate the host interface with the contents of "buffer". */
|
||||
ret_val = e1000_mng_host_if_write(hw, buffer, length,
|
||||
sizeof(hdr), &(hdr.checksum));
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
/* Write the manageability command header */
|
||||
ret_val = e1000_mng_write_cmd_header(hw, &hdr);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
/* Tell the ARC a new command is pending. */
|
||||
hicr = er32(HICR);
|
||||
ew32(HICR, hicr | E1000_HICR_C);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000e_enable_mng_pass_thru - Check if management passthrough is needed
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Verifies the hardware needs to leave interface enabled so that frames can
|
||||
* be directed to and from the management interface.
|
||||
**/
|
||||
bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
|
||||
{
|
||||
u32 manc;
|
||||
u32 fwsm, factps;
|
||||
|
||||
manc = er32(MANC);
|
||||
|
||||
if (!(manc & E1000_MANC_RCV_TCO_EN))
|
||||
return false;
|
||||
|
||||
if (hw->mac.has_fwsm) {
|
||||
fwsm = er32(FWSM);
|
||||
factps = er32(FACTPS);
|
||||
|
||||
if (!(factps & E1000_FACTPS_MNGCG) &&
|
||||
((fwsm & E1000_FWSM_MODE_MASK) ==
|
||||
(e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))
|
||||
return true;
|
||||
} else if ((hw->mac.type == e1000_82574) ||
|
||||
(hw->mac.type == e1000_82583)) {
|
||||
u16 data;
|
||||
|
||||
factps = er32(FACTPS);
|
||||
e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
|
||||
|
||||
if (!(factps & E1000_FACTPS_MNGCG) &&
|
||||
((data & E1000_NVM_INIT_CTRL2_MNGM) ==
|
||||
(e1000_mng_mode_pt << 13)))
|
||||
return true;
|
||||
} else if ((manc & E1000_MANC_SMBUS_EN) &&
|
||||
!(manc & E1000_MANC_ASF_EN)) {
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
@@ -0,0 +1,65 @@
|
||||
/* Intel PRO/1000 Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*/
|
||||
|
||||
#ifndef _E1000E_MANAGE_H_
|
||||
#define _E1000E_MANAGE_H_
|
||||
|
||||
bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
|
||||
bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
|
||||
s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
|
||||
bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
|
||||
|
||||
enum e1000_mng_mode {
|
||||
e1000_mng_mode_none = 0,
|
||||
e1000_mng_mode_asf,
|
||||
e1000_mng_mode_pt,
|
||||
e1000_mng_mode_ipmi,
|
||||
e1000_mng_mode_host_if_only
|
||||
};
|
||||
|
||||
#define E1000_FACTPS_MNGCG 0x20000000
|
||||
|
||||
#define E1000_FWSM_MODE_MASK 0xE
|
||||
#define E1000_FWSM_MODE_SHIFT 1
|
||||
|
||||
#define E1000_MNG_IAMT_MODE 0x3
|
||||
#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
|
||||
#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
|
||||
#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
|
||||
#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
|
||||
#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
|
||||
#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
|
||||
|
||||
#define E1000_VFTA_ENTRY_SHIFT 5
|
||||
#define E1000_VFTA_ENTRY_MASK 0x7F
|
||||
#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
|
||||
|
||||
#define E1000_HICR_EN 0x01 /* Enable bit - RO */
|
||||
/* Driver sets this bit when done to put command in RAM */
|
||||
#define E1000_HICR_C 0x02
|
||||
#define E1000_HICR_SV 0x04 /* Status Validity */
|
||||
#define E1000_HICR_FW_RESET_ENABLE 0x40
|
||||
#define E1000_HICR_FW_RESET 0x80
|
||||
|
||||
/* Intel(R) Active Management Technology signature */
|
||||
#define E1000_IAMT_SIGNATURE 0x544D4149
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,344 @@
|
||||
/* Intel PRO/1000 Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*/
|
||||
|
||||
#include "e1000.h"
|
||||
|
||||
/**
|
||||
* e1000_calculate_checksum - Calculate checksum for buffer
|
||||
* @buffer: pointer to EEPROM
|
||||
* @length: size of EEPROM to calculate a checksum for
|
||||
*
|
||||
* Calculates the checksum for some buffer on a specified length. The
|
||||
* checksum calculated is returned.
|
||||
**/
|
||||
static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
|
||||
{
|
||||
u32 i;
|
||||
u8 sum = 0;
|
||||
|
||||
if (!buffer)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < length; i++)
|
||||
sum += buffer[i];
|
||||
|
||||
return (u8)(0 - sum);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_mng_enable_host_if - Checks host interface is enabled
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
|
||||
*
|
||||
* This function checks whether the HOST IF is enabled for command operation
|
||||
* and also checks whether the previous command is completed. It busy waits
|
||||
* in case of previous command is not completed.
|
||||
**/
|
||||
static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
|
||||
{
|
||||
u32 hicr;
|
||||
u8 i;
|
||||
|
||||
if (!hw->mac.arc_subsystem_valid) {
|
||||
e_dbg("ARC subsystem not valid.\n");
|
||||
return -E1000_ERR_HOST_INTERFACE_COMMAND;
|
||||
}
|
||||
|
||||
/* Check that the host interface is enabled. */
|
||||
hicr = er32(HICR);
|
||||
if (!(hicr & E1000_HICR_EN)) {
|
||||
e_dbg("E1000_HOST_EN bit disabled.\n");
|
||||
return -E1000_ERR_HOST_INTERFACE_COMMAND;
|
||||
}
|
||||
/* check the previous command is completed */
|
||||
for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
|
||||
hicr = er32(HICR);
|
||||
if (!(hicr & E1000_HICR_C))
|
||||
break;
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
|
||||
e_dbg("Previous command timeout failed .\n");
|
||||
return -E1000_ERR_HOST_INTERFACE_COMMAND;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000e_check_mng_mode_generic - Generic check management mode
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Reads the firmware semaphore register and returns true (>0) if
|
||||
* manageability is enabled, else false (0).
|
||||
**/
|
||||
bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
|
||||
{
|
||||
u32 fwsm = er32(FWSM);
|
||||
|
||||
return (fwsm & E1000_FWSM_MODE_MASK) ==
|
||||
(E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Enables packet filtering on transmit packets if manageability is enabled
|
||||
* and host interface is enabled.
|
||||
**/
|
||||
bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
|
||||
{
|
||||
struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
|
||||
u32 *buffer = (u32 *)&hw->mng_cookie;
|
||||
u32 offset;
|
||||
s32 ret_val, hdr_csum, csum;
|
||||
u8 i, len;
|
||||
|
||||
hw->mac.tx_pkt_filtering = true;
|
||||
|
||||
/* No manageability, no filtering */
|
||||
if (!hw->mac.ops.check_mng_mode(hw)) {
|
||||
hw->mac.tx_pkt_filtering = false;
|
||||
return hw->mac.tx_pkt_filtering;
|
||||
}
|
||||
|
||||
/* If we can't read from the host interface for whatever
|
||||
* reason, disable filtering.
|
||||
*/
|
||||
ret_val = e1000_mng_enable_host_if(hw);
|
||||
if (ret_val) {
|
||||
hw->mac.tx_pkt_filtering = false;
|
||||
return hw->mac.tx_pkt_filtering;
|
||||
}
|
||||
|
||||
/* Read in the header. Length and offset are in dwords. */
|
||||
len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
|
||||
offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
|
||||
for (i = 0; i < len; i++)
|
||||
*(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF,
|
||||
offset + i);
|
||||
hdr_csum = hdr->checksum;
|
||||
hdr->checksum = 0;
|
||||
csum = e1000_calculate_checksum((u8 *)hdr,
|
||||
E1000_MNG_DHCP_COOKIE_LENGTH);
|
||||
/* If either the checksums or signature don't match, then
|
||||
* the cookie area isn't considered valid, in which case we
|
||||
* take the safe route of assuming Tx filtering is enabled.
|
||||
*/
|
||||
if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
|
||||
hw->mac.tx_pkt_filtering = true;
|
||||
return hw->mac.tx_pkt_filtering;
|
||||
}
|
||||
|
||||
/* Cookie area is valid, make the final check for filtering. */
|
||||
if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
|
||||
hw->mac.tx_pkt_filtering = false;
|
||||
|
||||
return hw->mac.tx_pkt_filtering;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_mng_write_cmd_header - Writes manageability command header
|
||||
* @hw: pointer to the HW structure
|
||||
* @hdr: pointer to the host interface command header
|
||||
*
|
||||
* Writes the command header after does the checksum calculation.
|
||||
**/
|
||||
static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
|
||||
struct e1000_host_mng_command_header *hdr)
|
||||
{
|
||||
u16 i, length = sizeof(struct e1000_host_mng_command_header);
|
||||
|
||||
/* Write the whole command header structure with new checksum. */
|
||||
|
||||
hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
|
||||
|
||||
length >>= 2;
|
||||
/* Write the relevant command block into the ram area. */
|
||||
for (i = 0; i < length; i++) {
|
||||
E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i, *((u32 *)hdr + i));
|
||||
e1e_flush();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_mng_host_if_write - Write to the manageability host interface
|
||||
* @hw: pointer to the HW structure
|
||||
* @buffer: pointer to the host interface buffer
|
||||
* @length: size of the buffer
|
||||
* @offset: location in the buffer to write to
|
||||
* @sum: sum of the data (not checksum)
|
||||
*
|
||||
* This function writes the buffer content at the offset given on the host if.
|
||||
* It also does alignment considerations to do the writes in most efficient
|
||||
* way. Also fills up the sum of the buffer in *buffer parameter.
|
||||
**/
|
||||
static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
|
||||
u16 length, u16 offset, u8 *sum)
|
||||
{
|
||||
u8 *tmp;
|
||||
u8 *bufptr = buffer;
|
||||
u32 data = 0;
|
||||
u16 remaining, i, j, prev_bytes;
|
||||
|
||||
/* sum = only sum of the data and it is not checksum */
|
||||
|
||||
if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
|
||||
return -E1000_ERR_PARAM;
|
||||
|
||||
tmp = (u8 *)&data;
|
||||
prev_bytes = offset & 0x3;
|
||||
offset >>= 2;
|
||||
|
||||
if (prev_bytes) {
|
||||
data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
|
||||
for (j = prev_bytes; j < sizeof(u32); j++) {
|
||||
*(tmp + j) = *bufptr++;
|
||||
*sum += *(tmp + j);
|
||||
}
|
||||
E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
|
||||
length -= j - prev_bytes;
|
||||
offset++;
|
||||
}
|
||||
|
||||
remaining = length & 0x3;
|
||||
length -= remaining;
|
||||
|
||||
/* Calculate length in DWORDs */
|
||||
length >>= 2;
|
||||
|
||||
/* The device driver writes the relevant command block into the
|
||||
* ram area.
|
||||
*/
|
||||
for (i = 0; i < length; i++) {
|
||||
for (j = 0; j < sizeof(u32); j++) {
|
||||
*(tmp + j) = *bufptr++;
|
||||
*sum += *(tmp + j);
|
||||
}
|
||||
|
||||
E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
|
||||
}
|
||||
if (remaining) {
|
||||
for (j = 0; j < sizeof(u32); j++) {
|
||||
if (j < remaining)
|
||||
*(tmp + j) = *bufptr++;
|
||||
else
|
||||
*(tmp + j) = 0;
|
||||
|
||||
*sum += *(tmp + j);
|
||||
}
|
||||
E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
|
||||
* @hw: pointer to the HW structure
|
||||
* @buffer: pointer to the host interface
|
||||
* @length: size of the buffer
|
||||
*
|
||||
* Writes the DHCP information to the host interface.
|
||||
**/
|
||||
s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
|
||||
{
|
||||
struct e1000_host_mng_command_header hdr;
|
||||
s32 ret_val;
|
||||
u32 hicr;
|
||||
|
||||
hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
|
||||
hdr.command_length = length;
|
||||
hdr.reserved1 = 0;
|
||||
hdr.reserved2 = 0;
|
||||
hdr.checksum = 0;
|
||||
|
||||
/* Enable the host interface */
|
||||
ret_val = e1000_mng_enable_host_if(hw);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
/* Populate the host interface with the contents of "buffer". */
|
||||
ret_val = e1000_mng_host_if_write(hw, buffer, length,
|
||||
sizeof(hdr), &(hdr.checksum));
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
/* Write the manageability command header */
|
||||
ret_val = e1000_mng_write_cmd_header(hw, &hdr);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
/* Tell the ARC a new command is pending. */
|
||||
hicr = er32(HICR);
|
||||
ew32(HICR, hicr | E1000_HICR_C);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000e_enable_mng_pass_thru - Check if management passthrough is needed
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Verifies the hardware needs to leave interface enabled so that frames can
|
||||
* be directed to and from the management interface.
|
||||
**/
|
||||
bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
|
||||
{
|
||||
u32 manc;
|
||||
u32 fwsm, factps;
|
||||
|
||||
manc = er32(MANC);
|
||||
|
||||
if (!(manc & E1000_MANC_RCV_TCO_EN))
|
||||
return false;
|
||||
|
||||
if (hw->mac.has_fwsm) {
|
||||
fwsm = er32(FWSM);
|
||||
factps = er32(FACTPS);
|
||||
|
||||
if (!(factps & E1000_FACTPS_MNGCG) &&
|
||||
((fwsm & E1000_FWSM_MODE_MASK) ==
|
||||
(e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))
|
||||
return true;
|
||||
} else if ((hw->mac.type == e1000_82574) ||
|
||||
(hw->mac.type == e1000_82583)) {
|
||||
u16 data;
|
||||
|
||||
factps = er32(FACTPS);
|
||||
e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
|
||||
|
||||
if (!(factps & E1000_FACTPS_MNGCG) &&
|
||||
((data & E1000_NVM_INIT_CTRL2_MNGM) ==
|
||||
(e1000_mng_mode_pt << 13)))
|
||||
return true;
|
||||
} else if ((manc & E1000_MANC_SMBUS_EN) &&
|
||||
!(manc & E1000_MANC_ASF_EN)) {
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
@@ -0,0 +1,65 @@
|
||||
/* Intel PRO/1000 Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*/
|
||||
|
||||
#ifndef _E1000E_MANAGE_H_
|
||||
#define _E1000E_MANAGE_H_
|
||||
|
||||
bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
|
||||
bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
|
||||
s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
|
||||
bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
|
||||
|
||||
enum e1000_mng_mode {
|
||||
e1000_mng_mode_none = 0,
|
||||
e1000_mng_mode_asf,
|
||||
e1000_mng_mode_pt,
|
||||
e1000_mng_mode_ipmi,
|
||||
e1000_mng_mode_host_if_only
|
||||
};
|
||||
|
||||
#define E1000_FACTPS_MNGCG 0x20000000
|
||||
|
||||
#define E1000_FWSM_MODE_MASK 0xE
|
||||
#define E1000_FWSM_MODE_SHIFT 1
|
||||
|
||||
#define E1000_MNG_IAMT_MODE 0x3
|
||||
#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
|
||||
#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
|
||||
#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
|
||||
#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
|
||||
#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
|
||||
#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
|
||||
|
||||
#define E1000_VFTA_ENTRY_SHIFT 5
|
||||
#define E1000_VFTA_ENTRY_MASK 0x7F
|
||||
#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
|
||||
|
||||
#define E1000_HICR_EN 0x01 /* Enable bit - RO */
|
||||
/* Driver sets this bit when done to put command in RAM */
|
||||
#define E1000_HICR_C 0x02
|
||||
#define E1000_HICR_SV 0x04 /* Status Validity */
|
||||
#define E1000_HICR_FW_RESET_ENABLE 0x40
|
||||
#define E1000_HICR_FW_RESET 0x80
|
||||
|
||||
/* Intel(R) Active Management Technology signature */
|
||||
#define E1000_IAMT_SIGNATURE 0x544D4149
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user