mirror of
https://gitlab.com/etherlab.org/ethercat.git
synced 2026-02-06 11:51:45 +08:00
Patched igb for 5.14
This commit is contained in:
Bjarne von Horn
@@ -44,6 +44,8 @@ EXTRA_DIST = \
|
||||
e1000_82575-5.10-ethercat.h \
|
||||
e1000_82575-5.10-orig.c \
|
||||
e1000_82575-5.10-orig.h \
|
||||
e1000_82575-5.14-ethercat.c \
|
||||
e1000_82575-5.14-ethercat.h \
|
||||
e1000_82575-5.14-orig.c \
|
||||
e1000_82575-5.14-orig.h \
|
||||
e1000_82575-5.15-ethercat.c \
|
||||
@@ -58,6 +60,7 @@ EXTRA_DIST = \
|
||||
e1000_defines-4.4-orig.h \
|
||||
e1000_defines-5.10-ethercat.h \
|
||||
e1000_defines-5.10-orig.h \
|
||||
e1000_defines-5.14-ethercat.h \
|
||||
e1000_defines-5.14-orig.h \
|
||||
e1000_defines-5.15-ethercat.h \
|
||||
e1000_defines-5.15-orig.h \
|
||||
@@ -69,6 +72,7 @@ EXTRA_DIST = \
|
||||
e1000_hw-4.4-orig.h \
|
||||
e1000_hw-5.10-ethercat.h \
|
||||
e1000_hw-5.10-orig.h \
|
||||
e1000_hw-5.14-ethercat.h \
|
||||
e1000_hw-5.14-orig.h \
|
||||
e1000_hw-5.15-ethercat.h \
|
||||
e1000_hw-5.15-orig.h \
|
||||
@@ -88,6 +92,8 @@ EXTRA_DIST = \
|
||||
e1000_i210-5.10-ethercat.h \
|
||||
e1000_i210-5.10-orig.c \
|
||||
e1000_i210-5.10-orig.h \
|
||||
e1000_i210-5.14-ethercat.c \
|
||||
e1000_i210-5.14-ethercat.h \
|
||||
e1000_i210-5.14-orig.c \
|
||||
e1000_i210-5.14-orig.h \
|
||||
e1000_i210-5.15-ethercat.c \
|
||||
@@ -110,6 +116,8 @@ EXTRA_DIST = \
|
||||
e1000_mac-5.10-ethercat.h \
|
||||
e1000_mac-5.10-orig.c \
|
||||
e1000_mac-5.10-orig.h \
|
||||
e1000_mac-5.14-ethercat.c \
|
||||
e1000_mac-5.14-ethercat.h \
|
||||
e1000_mac-5.14-orig.c \
|
||||
e1000_mac-5.14-orig.h \
|
||||
e1000_mac-5.15-ethercat.c \
|
||||
@@ -132,6 +140,8 @@ EXTRA_DIST = \
|
||||
e1000_mbx-5.10-ethercat.h \
|
||||
e1000_mbx-5.10-orig.c \
|
||||
e1000_mbx-5.10-orig.h \
|
||||
e1000_mbx-5.14-ethercat.c \
|
||||
e1000_mbx-5.14-ethercat.h \
|
||||
e1000_mbx-5.14-orig.c \
|
||||
e1000_mbx-5.14-orig.h \
|
||||
e1000_mbx-5.15-ethercat.c \
|
||||
@@ -154,6 +164,8 @@ EXTRA_DIST = \
|
||||
e1000_nvm-5.10-ethercat.h \
|
||||
e1000_nvm-5.10-orig.c \
|
||||
e1000_nvm-5.10-orig.h \
|
||||
e1000_nvm-5.14-ethercat.c \
|
||||
e1000_nvm-5.14-ethercat.h \
|
||||
e1000_nvm-5.14-orig.c \
|
||||
e1000_nvm-5.14-orig.h \
|
||||
e1000_nvm-5.15-ethercat.c \
|
||||
@@ -176,6 +188,8 @@ EXTRA_DIST = \
|
||||
e1000_phy-5.10-ethercat.h \
|
||||
e1000_phy-5.10-orig.c \
|
||||
e1000_phy-5.10-orig.h \
|
||||
e1000_phy-5.14-ethercat.c \
|
||||
e1000_phy-5.14-ethercat.h \
|
||||
e1000_phy-5.14-orig.c \
|
||||
e1000_phy-5.14-orig.h \
|
||||
e1000_phy-5.15-ethercat.c \
|
||||
@@ -190,6 +204,7 @@ EXTRA_DIST = \
|
||||
e1000_regs-4.4-orig.h \
|
||||
e1000_regs-5.10-ethercat.h \
|
||||
e1000_regs-5.10-orig.h \
|
||||
e1000_regs-5.14-ethercat.h \
|
||||
e1000_regs-5.14-orig.h \
|
||||
e1000_regs-5.15-ethercat.h \
|
||||
e1000_regs-5.15-orig.h \
|
||||
@@ -201,6 +216,7 @@ EXTRA_DIST = \
|
||||
igb-4.4-orig.h \
|
||||
igb-5.10-ethercat.h \
|
||||
igb-5.10-orig.h \
|
||||
igb-5.14-ethercat.h \
|
||||
igb-5.14-orig.h \
|
||||
igb-5.15-ethercat.h \
|
||||
igb-5.15-orig.h \
|
||||
@@ -212,6 +228,7 @@ EXTRA_DIST = \
|
||||
igb_ethtool-4.4-orig.c \
|
||||
igb_ethtool-5.10-ethercat.c \
|
||||
igb_ethtool-5.10-orig.c \
|
||||
igb_ethtool-5.14-ethercat.c \
|
||||
igb_ethtool-5.14-orig.c \
|
||||
igb_ethtool-5.15-ethercat.c \
|
||||
igb_ethtool-5.15-orig.c \
|
||||
@@ -223,6 +240,7 @@ EXTRA_DIST = \
|
||||
igb_hwmon-4.4-orig.c \
|
||||
igb_hwmon-5.10-ethercat.c \
|
||||
igb_hwmon-5.10-orig.c \
|
||||
igb_hwmon-5.14-ethercat.c \
|
||||
igb_hwmon-5.14-orig.c \
|
||||
igb_hwmon-5.15-ethercat.c \
|
||||
igb_hwmon-5.15-orig.c \
|
||||
@@ -234,6 +252,7 @@ EXTRA_DIST = \
|
||||
igb_main-4.4-orig.c \
|
||||
igb_main-5.10-ethercat.c \
|
||||
igb_main-5.10-orig.c \
|
||||
igb_main-5.14-ethercat.c \
|
||||
igb_main-5.14-orig.c \
|
||||
igb_main-5.15-ethercat.c \
|
||||
igb_main-5.15-orig.c \
|
||||
@@ -245,6 +264,7 @@ EXTRA_DIST = \
|
||||
igb_ptp-4.4-orig.c \
|
||||
igb_ptp-5.10-ethercat.c \
|
||||
igb_ptp-5.10-orig.c \
|
||||
igb_ptp-5.14-ethercat.c \
|
||||
igb_ptp-5.14-orig.c \
|
||||
igb_ptp-5.15-ethercat.c \
|
||||
igb_ptp-5.15-orig.c \
|
||||
|
||||
2926
devices/igb/e1000_82575-5.14-ethercat.c
Normal file
2926
devices/igb/e1000_82575-5.14-ethercat.c
Normal file
File diff suppressed because it is too large
Load Diff
265
devices/igb/e1000_82575-5.14-ethercat.h
Normal file
265
devices/igb/e1000_82575-5.14-ethercat.h
Normal file
@@ -0,0 +1,265 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright(c) 2007 - 2018 Intel Corporation. */
|
||||
|
||||
#ifndef _E1000_82575_H_
|
||||
#define _E1000_82575_H_
|
||||
|
||||
void igb_shutdown_serdes_link_82575(struct e1000_hw *hw);
|
||||
void igb_power_up_serdes_link_82575(struct e1000_hw *hw);
|
||||
void igb_power_down_phy_copper_82575(struct e1000_hw *hw);
|
||||
void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
|
||||
s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
|
||||
u8 *data);
|
||||
s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
|
||||
u8 data);
|
||||
|
||||
#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
|
||||
(ID_LED_DEF1_DEF2 << 8) | \
|
||||
(ID_LED_DEF1_DEF2 << 4) | \
|
||||
(ID_LED_OFF1_ON2))
|
||||
|
||||
#define E1000_RAR_ENTRIES_82575 16
|
||||
#define E1000_RAR_ENTRIES_82576 24
|
||||
#define E1000_RAR_ENTRIES_82580 24
|
||||
#define E1000_RAR_ENTRIES_I350 32
|
||||
|
||||
#define E1000_SW_SYNCH_MB 0x00000100
|
||||
#define E1000_STAT_DEV_RST_SET 0x00100000
|
||||
#define E1000_CTRL_DEV_RST 0x20000000
|
||||
|
||||
/* SRRCTL bit definitions */
|
||||
#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
|
||||
#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
|
||||
#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
|
||||
#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
|
||||
#define E1000_SRRCTL_DROP_EN 0x80000000
|
||||
#define E1000_SRRCTL_TIMESTAMP 0x40000000
|
||||
|
||||
|
||||
#define E1000_MRQC_ENABLE_RSS_MQ 0x00000002
|
||||
#define E1000_MRQC_ENABLE_VMDQ 0x00000003
|
||||
#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
|
||||
#define E1000_MRQC_ENABLE_VMDQ_RSS_MQ 0x00000005
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
|
||||
|
||||
#define E1000_EICR_TX_QUEUE ( \
|
||||
E1000_EICR_TX_QUEUE0 | \
|
||||
E1000_EICR_TX_QUEUE1 | \
|
||||
E1000_EICR_TX_QUEUE2 | \
|
||||
E1000_EICR_TX_QUEUE3)
|
||||
|
||||
#define E1000_EICR_RX_QUEUE ( \
|
||||
E1000_EICR_RX_QUEUE0 | \
|
||||
E1000_EICR_RX_QUEUE1 | \
|
||||
E1000_EICR_RX_QUEUE2 | \
|
||||
E1000_EICR_RX_QUEUE3)
|
||||
|
||||
/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
|
||||
#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
|
||||
#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
|
||||
|
||||
/* Receive Descriptor - Advanced */
|
||||
union e1000_adv_rx_desc {
|
||||
struct {
|
||||
__le64 pkt_addr; /* Packet buffer address */
|
||||
__le64 hdr_addr; /* Header buffer address */
|
||||
} read;
|
||||
struct {
|
||||
struct {
|
||||
struct {
|
||||
__le16 pkt_info; /* RSS type, Packet type */
|
||||
__le16 hdr_info; /* Split Head, buf len */
|
||||
} lo_dword;
|
||||
union {
|
||||
__le32 rss; /* RSS Hash */
|
||||
struct {
|
||||
__le16 ip_id; /* IP id */
|
||||
__le16 csum; /* Packet Checksum */
|
||||
} csum_ip;
|
||||
} hi_dword;
|
||||
} lower;
|
||||
struct {
|
||||
__le32 status_error; /* ext status/error */
|
||||
__le16 length; /* Packet length */
|
||||
__le16 vlan; /* VLAN tag */
|
||||
} upper;
|
||||
} wb; /* writeback */
|
||||
};
|
||||
|
||||
#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
|
||||
#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
|
||||
#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
|
||||
#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
|
||||
|
||||
/* Transmit Descriptor - Advanced */
|
||||
union e1000_adv_tx_desc {
|
||||
struct {
|
||||
__le64 buffer_addr; /* Address of descriptor's data buf */
|
||||
__le32 cmd_type_len;
|
||||
__le32 olinfo_status;
|
||||
} read;
|
||||
struct {
|
||||
__le64 rsvd; /* Reserved */
|
||||
__le32 nxtseq_seed;
|
||||
__le32 status;
|
||||
} wb;
|
||||
};
|
||||
|
||||
/* Adv Transmit Descriptor Config Masks */
|
||||
#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
|
||||
#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
|
||||
#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
|
||||
#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
|
||||
#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
|
||||
#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
|
||||
#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
|
||||
#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
|
||||
#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
|
||||
#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
|
||||
|
||||
/* Context descriptors */
|
||||
struct e1000_adv_tx_context_desc {
|
||||
__le32 vlan_macip_lens;
|
||||
__le32 seqnum_seed;
|
||||
__le32 type_tucmd_mlhl;
|
||||
__le32 mss_l4len_idx;
|
||||
};
|
||||
|
||||
#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
|
||||
#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
|
||||
/* IPSec Encrypt Enable for ESP */
|
||||
#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
|
||||
#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
|
||||
/* Adv ctxt IPSec SA IDX mask */
|
||||
/* Adv ctxt IPSec ESP len mask */
|
||||
|
||||
/* Additional Transmit Descriptor Control definitions */
|
||||
#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
|
||||
/* Tx Queue Arbitration Priority 0=low, 1=high */
|
||||
|
||||
/* Additional Receive Descriptor Control definitions */
|
||||
#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
|
||||
|
||||
/* Direct Cache Access (DCA) definitions */
|
||||
#define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
|
||||
#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
|
||||
|
||||
#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
|
||||
#define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
|
||||
#define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
|
||||
#define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
|
||||
#define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
|
||||
|
||||
#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
|
||||
#define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
|
||||
#define E1000_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
|
||||
#define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
|
||||
#define E1000_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
|
||||
|
||||
/* Additional DCA related definitions, note change in position of CPUID */
|
||||
#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
|
||||
#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
|
||||
#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
|
||||
#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
|
||||
|
||||
/* ETQF register bit definitions */
|
||||
#define E1000_ETQF_FILTER_ENABLE BIT(26)
|
||||
#define E1000_ETQF_1588 BIT(30)
|
||||
#define E1000_ETQF_IMM_INT BIT(29)
|
||||
#define E1000_ETQF_QUEUE_ENABLE BIT(31)
|
||||
#define E1000_ETQF_QUEUE_SHIFT 16
|
||||
#define E1000_ETQF_QUEUE_MASK 0x00070000
|
||||
#define E1000_ETQF_ETYPE_MASK 0x0000FFFF
|
||||
|
||||
/* FTQF register bit definitions */
|
||||
#define E1000_FTQF_VF_BP 0x00008000
|
||||
#define E1000_FTQF_1588_TIME_STAMP 0x08000000
|
||||
#define E1000_FTQF_MASK 0xF0000000
|
||||
#define E1000_FTQF_MASK_PROTO_BP 0x10000000
|
||||
#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
|
||||
|
||||
#define E1000_NVM_APME_82575 0x0400
|
||||
#define MAX_NUM_VFS 8
|
||||
|
||||
#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
|
||||
#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
|
||||
#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
|
||||
#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
|
||||
#define E1000_DTXSWC_VMDQ_LOOPBACK_EN BIT(31) /* global VF LB enable */
|
||||
|
||||
/* Easy defines for setting default pool, would normally be left a zero */
|
||||
#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
|
||||
#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
|
||||
|
||||
/* Other useful VMD_CTL register defines */
|
||||
#define E1000_VT_CTL_IGNORE_MAC BIT(28)
|
||||
#define E1000_VT_CTL_DISABLE_DEF_POOL BIT(29)
|
||||
#define E1000_VT_CTL_VM_REPL_EN BIT(30)
|
||||
|
||||
/* Per VM Offload register setup */
|
||||
#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
|
||||
#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
|
||||
#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
|
||||
#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
|
||||
#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
|
||||
#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
|
||||
#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
|
||||
#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
|
||||
#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
|
||||
#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
|
||||
|
||||
#define E1000_DVMOLR_HIDEVLAN 0x20000000 /* Hide vlan enable */
|
||||
#define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
|
||||
#define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */
|
||||
|
||||
#define E1000_VLVF_ARRAY_SIZE 32
|
||||
#define E1000_VLVF_VLANID_MASK 0x00000FFF
|
||||
#define E1000_VLVF_POOLSEL_SHIFT 12
|
||||
#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
|
||||
#define E1000_VLVF_LVLAN 0x00100000
|
||||
#define E1000_VLVF_VLANID_ENABLE 0x80000000
|
||||
|
||||
#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
|
||||
#define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
|
||||
|
||||
#define E1000_IOVCTL 0x05BBC
|
||||
#define E1000_IOVCTL_REUSE_VFQ 0x00000001
|
||||
|
||||
#define E1000_RPLOLR_STRVLAN 0x40000000
|
||||
#define E1000_RPLOLR_STRCRC 0x80000000
|
||||
|
||||
#define E1000_DTXCTL_8023LL 0x0004
|
||||
#define E1000_DTXCTL_VLAN_ADDED 0x0008
|
||||
#define E1000_DTXCTL_OOS_ENABLE 0x0010
|
||||
#define E1000_DTXCTL_MDP_EN 0x0020
|
||||
#define E1000_DTXCTL_SPOOF_INT 0x0040
|
||||
|
||||
#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT BIT(14)
|
||||
|
||||
#define ALL_QUEUES 0xFFFF
|
||||
|
||||
/* RX packet buffer size defines */
|
||||
#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
|
||||
void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
|
||||
void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
|
||||
void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
|
||||
u16 igb_rxpbs_adjust_82580(u32 data);
|
||||
s32 igb_read_emi_reg(struct e1000_hw *, u16 addr, u16 *data);
|
||||
s32 igb_set_eee_i350(struct e1000_hw *, bool adv1G, bool adv100M);
|
||||
s32 igb_set_eee_i354(struct e1000_hw *, bool adv1G, bool adv100M);
|
||||
s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status);
|
||||
|
||||
#define E1000_I2C_THERMAL_SENSOR_ADDR 0xF8
|
||||
#define E1000_EMC_INTERNAL_DATA 0x00
|
||||
#define E1000_EMC_INTERNAL_THERM_LIMIT 0x20
|
||||
#define E1000_EMC_DIODE1_DATA 0x01
|
||||
#define E1000_EMC_DIODE1_THERM_LIMIT 0x19
|
||||
#define E1000_EMC_DIODE2_DATA 0x23
|
||||
#define E1000_EMC_DIODE2_THERM_LIMIT 0x1A
|
||||
#define E1000_EMC_DIODE3_DATA 0x2A
|
||||
#define E1000_EMC_DIODE3_THERM_LIMIT 0x30
|
||||
#endif
|
||||
1078
devices/igb/e1000_defines-5.14-ethercat.h
Normal file
1078
devices/igb/e1000_defines-5.14-ethercat.h
Normal file
File diff suppressed because it is too large
Load Diff
554
devices/igb/e1000_hw-5.14-ethercat.h
Normal file
554
devices/igb/e1000_hw-5.14-ethercat.h
Normal file
File diff suppressed because it is too large
Load Diff
912
devices/igb/e1000_i210-5.14-ethercat.c
Normal file
912
devices/igb/e1000_i210-5.14-ethercat.c
Normal file
File diff suppressed because it is too large
Load Diff
74
devices/igb/e1000_i210-5.14-ethercat.h
Normal file
74
devices/igb/e1000_i210-5.14-ethercat.h
Normal file
@@ -0,0 +1,74 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright(c) 2007 - 2018 Intel Corporation. */
|
||||
|
||||
#ifndef _E1000_I210_H_
|
||||
#define _E1000_I210_H_
|
||||
|
||||
s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
|
||||
void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
|
||||
s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data);
|
||||
s32 igb_read_invm_version(struct e1000_hw *hw,
|
||||
struct e1000_fw_version *invm_ver);
|
||||
s32 igb_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data);
|
||||
s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data);
|
||||
s32 igb_init_nvm_params_i210(struct e1000_hw *hw);
|
||||
bool igb_get_flash_presence_i210(struct e1000_hw *hw);
|
||||
s32 igb_pll_workaround_i210(struct e1000_hw *hw);
|
||||
s32 igb_get_cfg_done_i210(struct e1000_hw *hw);
|
||||
|
||||
#define E1000_STM_OPCODE 0xDB00
|
||||
#define E1000_EEPROM_FLASH_SIZE_WORD 0x11
|
||||
|
||||
#define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \
|
||||
(u8)((invm_dword) & 0x7)
|
||||
#define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \
|
||||
(u8)(((invm_dword) & 0x0000FE00) >> 9)
|
||||
#define INVM_DWORD_TO_WORD_DATA(invm_dword) \
|
||||
(u16)(((invm_dword) & 0xFFFF0000) >> 16)
|
||||
|
||||
enum E1000_INVM_STRUCTURE_TYPE {
|
||||
E1000_INVM_UNINITIALIZED_STRUCTURE = 0x00,
|
||||
E1000_INVM_WORD_AUTOLOAD_STRUCTURE = 0x01,
|
||||
E1000_INVM_CSR_AUTOLOAD_STRUCTURE = 0x02,
|
||||
E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE = 0x03,
|
||||
E1000_INVM_RSA_KEY_SHA256_STRUCTURE = 0x04,
|
||||
E1000_INVM_INVALIDATED_STRUCTURE = 0x0F,
|
||||
};
|
||||
|
||||
#define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8
|
||||
#define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1
|
||||
#define E1000_INVM_ULT_BYTES_SIZE 8
|
||||
#define E1000_INVM_RECORD_SIZE_IN_BYTES 4
|
||||
#define E1000_INVM_VER_FIELD_ONE 0x1FF8
|
||||
#define E1000_INVM_VER_FIELD_TWO 0x7FE000
|
||||
#define E1000_INVM_IMGTYPE_FIELD 0x1F800000
|
||||
|
||||
#define E1000_INVM_MAJOR_MASK 0x3F0
|
||||
#define E1000_INVM_MINOR_MASK 0xF
|
||||
#define E1000_INVM_MAJOR_SHIFT 4
|
||||
|
||||
#define ID_LED_DEFAULT_I210 ((ID_LED_OFF1_ON2 << 8) | \
|
||||
(ID_LED_DEF1_DEF2 << 4) | \
|
||||
(ID_LED_OFF1_OFF2))
|
||||
#define ID_LED_DEFAULT_I210_SERDES ((ID_LED_DEF1_DEF2 << 8) | \
|
||||
(ID_LED_DEF1_DEF2 << 4) | \
|
||||
(ID_LED_OFF1_ON2))
|
||||
|
||||
/* NVM offset defaults for i211 device */
|
||||
#define NVM_INIT_CTRL_2_DEFAULT_I211 0X7243
|
||||
#define NVM_INIT_CTRL_4_DEFAULT_I211 0x00C1
|
||||
#define NVM_LED_1_CFG_DEFAULT_I211 0x0184
|
||||
#define NVM_LED_0_2_CFG_DEFAULT_I211 0x200C
|
||||
|
||||
/* PLL Defines */
|
||||
#define E1000_PCI_PMCSR 0x44
|
||||
#define E1000_PCI_PMCSR_D3 0x03
|
||||
#define E1000_MAX_PLL_TRIES 5
|
||||
#define E1000_PHY_PLL_UNCONF 0xFF
|
||||
#define E1000_PHY_PLL_FREQ_PAGE 0xFC
|
||||
#define E1000_PHY_PLL_FREQ_REG 0x000E
|
||||
#define E1000_INVM_DEFAULT_AL 0x202F
|
||||
#define E1000_INVM_AUTOLOAD 0x0A
|
||||
#define E1000_INVM_PLL_WO_VAL 0x0010
|
||||
|
||||
#endif
|
||||
1681
devices/igb/e1000_mac-5.14-ethercat.c
Normal file
1681
devices/igb/e1000_mac-5.14-ethercat.c
Normal file
File diff suppressed because it is too large
Load Diff
68
devices/igb/e1000_mac-5.14-ethercat.h
Normal file
68
devices/igb/e1000_mac-5.14-ethercat.h
Normal file
@@ -0,0 +1,68 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright(c) 2007 - 2018 Intel Corporation. */
|
||||
|
||||
#ifndef _E1000_MAC_H_
|
||||
#define _E1000_MAC_H_
|
||||
|
||||
#include "e1000_hw-5.14-ethercat.h"
|
||||
|
||||
#include "e1000_phy-5.14-ethercat.h"
|
||||
#include "e1000_nvm-5.14-ethercat.h"
|
||||
#include "e1000_defines-5.14-ethercat.h"
|
||||
#include "e1000_i210-5.14-ethercat.h"
|
||||
|
||||
/* Functions that should not be called directly from drivers but can be used
|
||||
* by other files in this 'shared code'
|
||||
*/
|
||||
s32 igb_blink_led(struct e1000_hw *hw);
|
||||
s32 igb_check_for_copper_link(struct e1000_hw *hw);
|
||||
s32 igb_cleanup_led(struct e1000_hw *hw);
|
||||
s32 igb_config_fc_after_link_up(struct e1000_hw *hw);
|
||||
s32 igb_disable_pcie_master(struct e1000_hw *hw);
|
||||
s32 igb_force_mac_fc(struct e1000_hw *hw);
|
||||
s32 igb_get_auto_rd_done(struct e1000_hw *hw);
|
||||
s32 igb_get_bus_info_pcie(struct e1000_hw *hw);
|
||||
s32 igb_get_hw_semaphore(struct e1000_hw *hw);
|
||||
s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
|
||||
u16 *duplex);
|
||||
s32 igb_id_led_init(struct e1000_hw *hw);
|
||||
s32 igb_led_off(struct e1000_hw *hw);
|
||||
void igb_update_mc_addr_list(struct e1000_hw *hw,
|
||||
u8 *mc_addr_list, u32 mc_addr_count);
|
||||
s32 igb_setup_link(struct e1000_hw *hw);
|
||||
s32 igb_validate_mdi_setting(struct e1000_hw *hw);
|
||||
s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
|
||||
u32 offset, u8 data);
|
||||
|
||||
void igb_clear_hw_cntrs_base(struct e1000_hw *hw);
|
||||
void igb_clear_vfta(struct e1000_hw *hw);
|
||||
void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
|
||||
s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, u32 vind,
|
||||
bool vlan_on, bool vlvf_bypass);
|
||||
void igb_config_collision_dist(struct e1000_hw *hw);
|
||||
void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
|
||||
void igb_mta_set(struct e1000_hw *hw, u32 hash_value);
|
||||
void igb_put_hw_semaphore(struct e1000_hw *hw);
|
||||
void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
|
||||
s32 igb_check_alt_mac_addr(struct e1000_hw *hw);
|
||||
|
||||
bool igb_enable_mng_pass_thru(struct e1000_hw *hw);
|
||||
|
||||
enum e1000_mng_mode {
|
||||
e1000_mng_mode_none = 0,
|
||||
e1000_mng_mode_asf,
|
||||
e1000_mng_mode_pt,
|
||||
e1000_mng_mode_ipmi,
|
||||
e1000_mng_mode_host_if_only
|
||||
};
|
||||
|
||||
#define E1000_FACTPS_MNGCG 0x20000000
|
||||
|
||||
#define E1000_FWSM_MODE_MASK 0xE
|
||||
#define E1000_FWSM_MODE_SHIFT 1
|
||||
|
||||
#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
|
||||
|
||||
void e1000_init_function_pointers_82575(struct e1000_hw *hw);
|
||||
|
||||
#endif
|
||||
474
devices/igb/e1000_mbx-5.14-ethercat.c
Normal file
474
devices/igb/e1000_mbx-5.14-ethercat.c
Normal file
@@ -0,0 +1,474 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright(c) 2007 - 2018 Intel Corporation. */
|
||||
|
||||
#include "e1000_mbx-5.14-ethercat.h"
|
||||
|
||||
/**
|
||||
* igb_read_mbx - Reads a message from the mailbox
|
||||
* @hw: pointer to the HW structure
|
||||
* @msg: The message buffer
|
||||
* @size: Length of buffer
|
||||
* @mbx_id: id of mailbox to read
|
||||
* @unlock: skip locking or not
|
||||
*
|
||||
* returns SUCCESS if it successfully read message from buffer
|
||||
**/
|
||||
s32 igb_read_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id,
|
||||
bool unlock)
|
||||
{
|
||||
struct e1000_mbx_info *mbx = &hw->mbx;
|
||||
s32 ret_val = -E1000_ERR_MBX;
|
||||
|
||||
/* limit read to size of mailbox */
|
||||
if (size > mbx->size)
|
||||
size = mbx->size;
|
||||
|
||||
if (mbx->ops.read)
|
||||
ret_val = mbx->ops.read(hw, msg, size, mbx_id, unlock);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_write_mbx - Write a message to the mailbox
|
||||
* @hw: pointer to the HW structure
|
||||
* @msg: The message buffer
|
||||
* @size: Length of buffer
|
||||
* @mbx_id: id of mailbox to write
|
||||
*
|
||||
* returns SUCCESS if it successfully copied message into the buffer
|
||||
**/
|
||||
s32 igb_write_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)
|
||||
{
|
||||
struct e1000_mbx_info *mbx = &hw->mbx;
|
||||
s32 ret_val = 0;
|
||||
|
||||
if (size > mbx->size)
|
||||
ret_val = -E1000_ERR_MBX;
|
||||
|
||||
else if (mbx->ops.write)
|
||||
ret_val = mbx->ops.write(hw, msg, size, mbx_id);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_check_for_msg - checks to see if someone sent us mail
|
||||
* @hw: pointer to the HW structure
|
||||
* @mbx_id: id of mailbox to check
|
||||
*
|
||||
* returns SUCCESS if the Status bit was found or else ERR_MBX
|
||||
**/
|
||||
s32 igb_check_for_msg(struct e1000_hw *hw, u16 mbx_id)
|
||||
{
|
||||
struct e1000_mbx_info *mbx = &hw->mbx;
|
||||
s32 ret_val = -E1000_ERR_MBX;
|
||||
|
||||
if (mbx->ops.check_for_msg)
|
||||
ret_val = mbx->ops.check_for_msg(hw, mbx_id);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_check_for_ack - checks to see if someone sent us ACK
|
||||
* @hw: pointer to the HW structure
|
||||
* @mbx_id: id of mailbox to check
|
||||
*
|
||||
* returns SUCCESS if the Status bit was found or else ERR_MBX
|
||||
**/
|
||||
s32 igb_check_for_ack(struct e1000_hw *hw, u16 mbx_id)
|
||||
{
|
||||
struct e1000_mbx_info *mbx = &hw->mbx;
|
||||
s32 ret_val = -E1000_ERR_MBX;
|
||||
|
||||
if (mbx->ops.check_for_ack)
|
||||
ret_val = mbx->ops.check_for_ack(hw, mbx_id);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_check_for_rst - checks to see if other side has reset
|
||||
* @hw: pointer to the HW structure
|
||||
* @mbx_id: id of mailbox to check
|
||||
*
|
||||
* returns SUCCESS if the Status bit was found or else ERR_MBX
|
||||
**/
|
||||
s32 igb_check_for_rst(struct e1000_hw *hw, u16 mbx_id)
|
||||
{
|
||||
struct e1000_mbx_info *mbx = &hw->mbx;
|
||||
s32 ret_val = -E1000_ERR_MBX;
|
||||
|
||||
if (mbx->ops.check_for_rst)
|
||||
ret_val = mbx->ops.check_for_rst(hw, mbx_id);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_unlock_mbx - unlock the mailbox
|
||||
* @hw: pointer to the HW structure
|
||||
* @mbx_id: id of mailbox to check
|
||||
*
|
||||
* returns SUCCESS if the mailbox was unlocked or else ERR_MBX
|
||||
**/
|
||||
s32 igb_unlock_mbx(struct e1000_hw *hw, u16 mbx_id)
|
||||
{
|
||||
struct e1000_mbx_info *mbx = &hw->mbx;
|
||||
s32 ret_val = -E1000_ERR_MBX;
|
||||
|
||||
if (mbx->ops.unlock)
|
||||
ret_val = mbx->ops.unlock(hw, mbx_id);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_poll_for_msg - Wait for message notification
|
||||
* @hw: pointer to the HW structure
|
||||
* @mbx_id: id of mailbox to write
|
||||
*
|
||||
* returns SUCCESS if it successfully received a message notification
|
||||
**/
|
||||
static s32 igb_poll_for_msg(struct e1000_hw *hw, u16 mbx_id)
|
||||
{
|
||||
struct e1000_mbx_info *mbx = &hw->mbx;
|
||||
int countdown = mbx->timeout;
|
||||
|
||||
if (!countdown || !mbx->ops.check_for_msg)
|
||||
goto out;
|
||||
|
||||
while (countdown && mbx->ops.check_for_msg(hw, mbx_id)) {
|
||||
countdown--;
|
||||
if (!countdown)
|
||||
break;
|
||||
udelay(mbx->usec_delay);
|
||||
}
|
||||
|
||||
/* if we failed, all future posted messages fail until reset */
|
||||
if (!countdown)
|
||||
mbx->timeout = 0;
|
||||
out:
|
||||
return countdown ? 0 : -E1000_ERR_MBX;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_poll_for_ack - Wait for message acknowledgement
|
||||
* @hw: pointer to the HW structure
|
||||
* @mbx_id: id of mailbox to write
|
||||
*
|
||||
* returns SUCCESS if it successfully received a message acknowledgement
|
||||
**/
|
||||
static s32 igb_poll_for_ack(struct e1000_hw *hw, u16 mbx_id)
|
||||
{
|
||||
struct e1000_mbx_info *mbx = &hw->mbx;
|
||||
int countdown = mbx->timeout;
|
||||
|
||||
if (!countdown || !mbx->ops.check_for_ack)
|
||||
goto out;
|
||||
|
||||
while (countdown && mbx->ops.check_for_ack(hw, mbx_id)) {
|
||||
countdown--;
|
||||
if (!countdown)
|
||||
break;
|
||||
udelay(mbx->usec_delay);
|
||||
}
|
||||
|
||||
/* if we failed, all future posted messages fail until reset */
|
||||
if (!countdown)
|
||||
mbx->timeout = 0;
|
||||
out:
|
||||
return countdown ? 0 : -E1000_ERR_MBX;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_read_posted_mbx - Wait for message notification and receive message
|
||||
* @hw: pointer to the HW structure
|
||||
* @msg: The message buffer
|
||||
* @size: Length of buffer
|
||||
* @mbx_id: id of mailbox to write
|
||||
*
|
||||
* returns SUCCESS if it successfully received a message notification and
|
||||
* copied it into the receive buffer.
|
||||
**/
|
||||
static s32 igb_read_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size,
|
||||
u16 mbx_id)
|
||||
{
|
||||
struct e1000_mbx_info *mbx = &hw->mbx;
|
||||
s32 ret_val = -E1000_ERR_MBX;
|
||||
|
||||
if (!mbx->ops.read)
|
||||
goto out;
|
||||
|
||||
ret_val = igb_poll_for_msg(hw, mbx_id);
|
||||
|
||||
if (!ret_val)
|
||||
ret_val = mbx->ops.read(hw, msg, size, mbx_id, true);
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_write_posted_mbx - Write a message to the mailbox, wait for ack
|
||||
* @hw: pointer to the HW structure
|
||||
* @msg: The message buffer
|
||||
* @size: Length of buffer
|
||||
* @mbx_id: id of mailbox to write
|
||||
*
|
||||
* returns SUCCESS if it successfully copied message into the buffer and
|
||||
* received an ack to that message within delay * timeout period
|
||||
**/
|
||||
static s32 igb_write_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size,
|
||||
u16 mbx_id)
|
||||
{
|
||||
struct e1000_mbx_info *mbx = &hw->mbx;
|
||||
s32 ret_val = -E1000_ERR_MBX;
|
||||
|
||||
/* exit if either we can't write or there isn't a defined timeout */
|
||||
if (!mbx->ops.write || !mbx->timeout)
|
||||
goto out;
|
||||
|
||||
/* send msg */
|
||||
ret_val = mbx->ops.write(hw, msg, size, mbx_id);
|
||||
|
||||
/* if msg sent wait until we receive an ack */
|
||||
if (!ret_val)
|
||||
ret_val = igb_poll_for_ack(hw, mbx_id);
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
static s32 igb_check_for_bit_pf(struct e1000_hw *hw, u32 mask)
|
||||
{
|
||||
u32 mbvficr = rd32(E1000_MBVFICR);
|
||||
s32 ret_val = -E1000_ERR_MBX;
|
||||
|
||||
if (mbvficr & mask) {
|
||||
ret_val = 0;
|
||||
wr32(E1000_MBVFICR, mask);
|
||||
}
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_check_for_msg_pf - checks to see if the VF has sent mail
|
||||
* @hw: pointer to the HW structure
|
||||
* @vf_number: the VF index
|
||||
*
|
||||
* returns SUCCESS if the VF has set the Status bit or else ERR_MBX
|
||||
**/
|
||||
static s32 igb_check_for_msg_pf(struct e1000_hw *hw, u16 vf_number)
|
||||
{
|
||||
s32 ret_val = -E1000_ERR_MBX;
|
||||
|
||||
if (!igb_check_for_bit_pf(hw, E1000_MBVFICR_VFREQ_VF1 << vf_number)) {
|
||||
ret_val = 0;
|
||||
hw->mbx.stats.reqs++;
|
||||
}
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_check_for_ack_pf - checks to see if the VF has ACKed
|
||||
* @hw: pointer to the HW structure
|
||||
* @vf_number: the VF index
|
||||
*
|
||||
* returns SUCCESS if the VF has set the Status bit or else ERR_MBX
|
||||
**/
|
||||
static s32 igb_check_for_ack_pf(struct e1000_hw *hw, u16 vf_number)
|
||||
{
|
||||
s32 ret_val = -E1000_ERR_MBX;
|
||||
|
||||
if (!igb_check_for_bit_pf(hw, E1000_MBVFICR_VFACK_VF1 << vf_number)) {
|
||||
ret_val = 0;
|
||||
hw->mbx.stats.acks++;
|
||||
}
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_check_for_rst_pf - checks to see if the VF has reset
|
||||
* @hw: pointer to the HW structure
|
||||
* @vf_number: the VF index
|
||||
*
|
||||
* returns SUCCESS if the VF has set the Status bit or else ERR_MBX
|
||||
**/
|
||||
static s32 igb_check_for_rst_pf(struct e1000_hw *hw, u16 vf_number)
|
||||
{
|
||||
u32 vflre = rd32(E1000_VFLRE);
|
||||
s32 ret_val = -E1000_ERR_MBX;
|
||||
|
||||
if (vflre & BIT(vf_number)) {
|
||||
ret_val = 0;
|
||||
wr32(E1000_VFLRE, BIT(vf_number));
|
||||
hw->mbx.stats.rsts++;
|
||||
}
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_obtain_mbx_lock_pf - obtain mailbox lock
|
||||
* @hw: pointer to the HW structure
|
||||
* @vf_number: the VF index
|
||||
*
|
||||
* return SUCCESS if we obtained the mailbox lock
|
||||
**/
|
||||
static s32 igb_obtain_mbx_lock_pf(struct e1000_hw *hw, u16 vf_number)
|
||||
{
|
||||
s32 ret_val = -E1000_ERR_MBX;
|
||||
u32 p2v_mailbox;
|
||||
int count = 10;
|
||||
|
||||
do {
|
||||
/* Take ownership of the buffer */
|
||||
wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_PFU);
|
||||
|
||||
/* reserve mailbox for vf use */
|
||||
p2v_mailbox = rd32(E1000_P2VMAILBOX(vf_number));
|
||||
if (p2v_mailbox & E1000_P2VMAILBOX_PFU) {
|
||||
ret_val = 0;
|
||||
break;
|
||||
}
|
||||
udelay(1000);
|
||||
} while (count-- > 0);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_release_mbx_lock_pf - release mailbox lock
|
||||
* @hw: pointer to the HW structure
|
||||
* @vf_number: the VF index
|
||||
*
|
||||
* return SUCCESS if we released the mailbox lock
|
||||
**/
|
||||
static s32 igb_release_mbx_lock_pf(struct e1000_hw *hw, u16 vf_number)
|
||||
{
|
||||
u32 p2v_mailbox;
|
||||
|
||||
/* drop PF lock of mailbox, if set */
|
||||
p2v_mailbox = rd32(E1000_P2VMAILBOX(vf_number));
|
||||
if (p2v_mailbox & E1000_P2VMAILBOX_PFU)
|
||||
wr32(E1000_P2VMAILBOX(vf_number),
|
||||
p2v_mailbox & ~E1000_P2VMAILBOX_PFU);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_write_mbx_pf - Places a message in the mailbox
|
||||
* @hw: pointer to the HW structure
|
||||
* @msg: The message buffer
|
||||
* @size: Length of buffer
|
||||
* @vf_number: the VF index
|
||||
*
|
||||
* returns SUCCESS if it successfully copied message into the buffer
|
||||
**/
|
||||
static s32 igb_write_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size,
|
||||
u16 vf_number)
|
||||
{
|
||||
s32 ret_val;
|
||||
u16 i;
|
||||
|
||||
/* lock the mailbox to prevent pf/vf race condition */
|
||||
ret_val = igb_obtain_mbx_lock_pf(hw, vf_number);
|
||||
if (ret_val)
|
||||
goto out_no_write;
|
||||
|
||||
/* flush msg and acks as we are overwriting the message buffer */
|
||||
igb_check_for_msg_pf(hw, vf_number);
|
||||
igb_check_for_ack_pf(hw, vf_number);
|
||||
|
||||
/* copy the caller specified message to the mailbox memory buffer */
|
||||
for (i = 0; i < size; i++)
|
||||
array_wr32(E1000_VMBMEM(vf_number), i, msg[i]);
|
||||
|
||||
/* Interrupt VF to tell it a message has been sent and release buffer*/
|
||||
wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS);
|
||||
|
||||
/* update stats */
|
||||
hw->mbx.stats.msgs_tx++;
|
||||
|
||||
out_no_write:
|
||||
return ret_val;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_read_mbx_pf - Read a message from the mailbox
|
||||
* @hw: pointer to the HW structure
|
||||
* @msg: The message buffer
|
||||
* @size: Length of buffer
|
||||
* @vf_number: the VF index
|
||||
* @unlock: unlock the mailbox when done?
|
||||
*
|
||||
* This function copies a message from the mailbox buffer to the caller's
|
||||
* memory buffer. The presumption is that the caller knows that there was
|
||||
* a message due to a VF request so no polling for message is needed.
|
||||
**/
|
||||
static s32 igb_read_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size,
|
||||
u16 vf_number, bool unlock)
|
||||
{
|
||||
s32 ret_val;
|
||||
u16 i;
|
||||
|
||||
/* lock the mailbox to prevent pf/vf race condition */
|
||||
ret_val = igb_obtain_mbx_lock_pf(hw, vf_number);
|
||||
if (ret_val)
|
||||
goto out_no_read;
|
||||
|
||||
/* copy the message to the mailbox memory buffer */
|
||||
for (i = 0; i < size; i++)
|
||||
msg[i] = array_rd32(E1000_VMBMEM(vf_number), i);
|
||||
|
||||
/* Acknowledge the message and release mailbox lock (or not) */
|
||||
if (unlock)
|
||||
wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK);
|
||||
else
|
||||
wr32(E1000_P2VMAILBOX(vf_number),
|
||||
E1000_P2VMAILBOX_ACK | E1000_P2VMAILBOX_PFU);
|
||||
|
||||
/* update stats */
|
||||
hw->mbx.stats.msgs_rx++;
|
||||
|
||||
out_no_read:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_init_mbx_params_pf - set initial values for pf mailbox
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Initializes the hw->mbx struct to correct values for pf mailbox
|
||||
*/
|
||||
s32 igb_init_mbx_params_pf(struct e1000_hw *hw)
|
||||
{
|
||||
struct e1000_mbx_info *mbx = &hw->mbx;
|
||||
|
||||
mbx->timeout = 0;
|
||||
mbx->usec_delay = 0;
|
||||
|
||||
mbx->size = E1000_VFMAILBOX_SIZE;
|
||||
|
||||
mbx->ops.read = igb_read_mbx_pf;
|
||||
mbx->ops.write = igb_write_mbx_pf;
|
||||
mbx->ops.read_posted = igb_read_posted_mbx;
|
||||
mbx->ops.write_posted = igb_write_posted_mbx;
|
||||
mbx->ops.check_for_msg = igb_check_for_msg_pf;
|
||||
mbx->ops.check_for_ack = igb_check_for_ack_pf;
|
||||
mbx->ops.check_for_rst = igb_check_for_rst_pf;
|
||||
mbx->ops.unlock = igb_release_mbx_lock_pf;
|
||||
|
||||
mbx->stats.msgs_tx = 0;
|
||||
mbx->stats.msgs_rx = 0;
|
||||
mbx->stats.reqs = 0;
|
||||
mbx->stats.acks = 0;
|
||||
mbx->stats.rsts = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
59
devices/igb/e1000_mbx-5.14-ethercat.h
Normal file
59
devices/igb/e1000_mbx-5.14-ethercat.h
Normal file
@@ -0,0 +1,59 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright(c) 2007 - 2018 Intel Corporation. */
|
||||
|
||||
#ifndef _E1000_MBX_H_
|
||||
#define _E1000_MBX_H_
|
||||
|
||||
#include "e1000_hw-5.14-ethercat.h"
|
||||
|
||||
#define E1000_P2VMAILBOX_STS 0x00000001 /* Initiate message send to VF */
|
||||
#define E1000_P2VMAILBOX_ACK 0x00000002 /* Ack message recv'd from VF */
|
||||
#define E1000_P2VMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
|
||||
#define E1000_P2VMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */
|
||||
#define E1000_P2VMAILBOX_RVFU 0x00000010 /* Reset VFU - used when VF stuck */
|
||||
|
||||
#define E1000_MBVFICR_VFREQ_MASK 0x000000FF /* bits for VF messages */
|
||||
#define E1000_MBVFICR_VFREQ_VF1 0x00000001 /* bit for VF 1 message */
|
||||
#define E1000_MBVFICR_VFACK_MASK 0x00FF0000 /* bits for VF acks */
|
||||
#define E1000_MBVFICR_VFACK_VF1 0x00010000 /* bit for VF 1 ack */
|
||||
|
||||
#define E1000_VFMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */
|
||||
|
||||
/* If it's a E1000_VF_* msg then it originates in the VF and is sent to the
|
||||
* PF. The reverse is true if it is E1000_PF_*.
|
||||
* Message ACK's are the value or'd with 0xF0000000
|
||||
*/
|
||||
/* Messages below or'd with this are the ACK */
|
||||
#define E1000_VT_MSGTYPE_ACK 0x80000000
|
||||
/* Messages below or'd with this are the NACK */
|
||||
#define E1000_VT_MSGTYPE_NACK 0x40000000
|
||||
/* Indicates that VF is still clear to send requests */
|
||||
#define E1000_VT_MSGTYPE_CTS 0x20000000
|
||||
#define E1000_VT_MSGINFO_SHIFT 16
|
||||
/* bits 23:16 are used for exra info for certain messages */
|
||||
#define E1000_VT_MSGINFO_MASK (0xFF << E1000_VT_MSGINFO_SHIFT)
|
||||
|
||||
#define E1000_VF_RESET 0x01 /* VF requests reset */
|
||||
#define E1000_VF_SET_MAC_ADDR 0x02 /* VF requests to set MAC addr */
|
||||
/* VF requests to clear all unicast MAC filters */
|
||||
#define E1000_VF_MAC_FILTER_CLR (0x01 << E1000_VT_MSGINFO_SHIFT)
|
||||
/* VF requests to add unicast MAC filter */
|
||||
#define E1000_VF_MAC_FILTER_ADD (0x02 << E1000_VT_MSGINFO_SHIFT)
|
||||
#define E1000_VF_SET_MULTICAST 0x03 /* VF requests to set MC addr */
|
||||
#define E1000_VF_SET_VLAN 0x04 /* VF requests to set VLAN */
|
||||
#define E1000_VF_SET_LPE 0x05 /* VF requests to set VMOLR.LPE */
|
||||
#define E1000_VF_SET_PROMISC 0x06 /*VF requests to clear VMOLR.ROPE/MPME*/
|
||||
#define E1000_VF_SET_PROMISC_MULTICAST (0x02 << E1000_VT_MSGINFO_SHIFT)
|
||||
|
||||
#define E1000_PF_CONTROL_MSG 0x0100 /* PF control message */
|
||||
|
||||
s32 igb_read_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id,
|
||||
bool unlock);
|
||||
s32 igb_write_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id);
|
||||
s32 igb_check_for_msg(struct e1000_hw *hw, u16 mbx_id);
|
||||
s32 igb_check_for_ack(struct e1000_hw *hw, u16 mbx_id);
|
||||
s32 igb_check_for_rst(struct e1000_hw *hw, u16 mbx_id);
|
||||
s32 igb_unlock_mbx(struct e1000_hw *hw, u16 mbx_id);
|
||||
s32 igb_init_mbx_params_pf(struct e1000_hw *hw);
|
||||
|
||||
#endif /* _E1000_MBX_H_ */
|
||||
782
devices/igb/e1000_nvm-5.14-ethercat.c
Normal file
782
devices/igb/e1000_nvm-5.14-ethercat.c
Normal file
File diff suppressed because it is too large
Load Diff
36
devices/igb/e1000_nvm-5.14-ethercat.h
Normal file
36
devices/igb/e1000_nvm-5.14-ethercat.h
Normal file
@@ -0,0 +1,36 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright(c) 2007 - 2018 Intel Corporation. */
|
||||
|
||||
#ifndef _E1000_NVM_H_
|
||||
#define _E1000_NVM_H_
|
||||
|
||||
s32 igb_acquire_nvm(struct e1000_hw *hw);
|
||||
void igb_release_nvm(struct e1000_hw *hw);
|
||||
s32 igb_read_mac_addr(struct e1000_hw *hw);
|
||||
s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num);
|
||||
s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num,
|
||||
u32 part_num_size);
|
||||
s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
|
||||
s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
|
||||
s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
|
||||
s32 igb_validate_nvm_checksum(struct e1000_hw *hw);
|
||||
s32 igb_update_nvm_checksum(struct e1000_hw *hw);
|
||||
|
||||
struct e1000_fw_version {
|
||||
u32 etrack_id;
|
||||
u16 eep_major;
|
||||
u16 eep_minor;
|
||||
u16 eep_build;
|
||||
|
||||
u8 invm_major;
|
||||
u8 invm_minor;
|
||||
u8 invm_img_type;
|
||||
|
||||
bool or_valid;
|
||||
u16 or_major;
|
||||
u16 or_build;
|
||||
u16 or_patch;
|
||||
};
|
||||
void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers);
|
||||
|
||||
#endif
|
||||
2631
devices/igb/e1000_phy-5.14-ethercat.c
Normal file
2631
devices/igb/e1000_phy-5.14-ethercat.c
Normal file
File diff suppressed because it is too large
Load Diff
145
devices/igb/e1000_phy-5.14-ethercat.h
Normal file
145
devices/igb/e1000_phy-5.14-ethercat.h
Normal file
@@ -0,0 +1,145 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright(c) 2007 - 2018 Intel Corporation. */
|
||||
|
||||
#ifndef _E1000_PHY_H_
|
||||
#define _E1000_PHY_H_
|
||||
|
||||
enum e1000_ms_type {
|
||||
e1000_ms_hw_default = 0,
|
||||
e1000_ms_force_master,
|
||||
e1000_ms_force_slave,
|
||||
e1000_ms_auto
|
||||
};
|
||||
|
||||
enum e1000_smart_speed {
|
||||
e1000_smart_speed_default = 0,
|
||||
e1000_smart_speed_on,
|
||||
e1000_smart_speed_off
|
||||
};
|
||||
|
||||
s32 igb_check_downshift(struct e1000_hw *hw);
|
||||
s32 igb_check_reset_block(struct e1000_hw *hw);
|
||||
s32 igb_copper_link_setup_igp(struct e1000_hw *hw);
|
||||
s32 igb_copper_link_setup_m88(struct e1000_hw *hw);
|
||||
s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw);
|
||||
s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
|
||||
s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
|
||||
s32 igb_get_cable_length_m88(struct e1000_hw *hw);
|
||||
s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw);
|
||||
s32 igb_get_cable_length_igp_2(struct e1000_hw *hw);
|
||||
s32 igb_get_phy_id(struct e1000_hw *hw);
|
||||
s32 igb_get_phy_info_igp(struct e1000_hw *hw);
|
||||
s32 igb_get_phy_info_m88(struct e1000_hw *hw);
|
||||
s32 igb_phy_sw_reset(struct e1000_hw *hw);
|
||||
s32 igb_phy_hw_reset(struct e1000_hw *hw);
|
||||
s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
|
||||
s32 igb_setup_copper_link(struct e1000_hw *hw);
|
||||
s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
|
||||
u32 usec_interval, bool *success);
|
||||
void igb_power_up_phy_copper(struct e1000_hw *hw);
|
||||
void igb_power_down_phy_copper(struct e1000_hw *hw);
|
||||
s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
|
||||
s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw);
|
||||
s32 igb_initialize_M88E1543_phy(struct e1000_hw *hw);
|
||||
s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
|
||||
s32 igb_copper_link_setup_82580(struct e1000_hw *hw);
|
||||
s32 igb_get_phy_info_82580(struct e1000_hw *hw);
|
||||
s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
|
||||
s32 igb_get_cable_length_82580(struct e1000_hw *hw);
|
||||
s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_check_polarity_m88(struct e1000_hw *hw);
|
||||
|
||||
/* IGP01E1000 Specific Registers */
|
||||
#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
|
||||
#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
|
||||
#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
|
||||
#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
|
||||
#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
|
||||
#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
|
||||
#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
|
||||
#define IGP01E1000_PHY_POLARITY_MASK 0x0078
|
||||
#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
|
||||
#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
|
||||
#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
|
||||
|
||||
#define I82580_ADDR_REG 16
|
||||
#define I82580_CFG_REG 22
|
||||
#define I82580_CFG_ASSERT_CRS_ON_TX BIT(15)
|
||||
#define I82580_CFG_ENABLE_DOWNSHIFT (3u << 10) /* auto downshift 100/10 */
|
||||
#define I82580_CTRL_REG 23
|
||||
#define I82580_CTRL_DOWNSHIFT_MASK (7u << 10)
|
||||
|
||||
/* 82580 specific PHY registers */
|
||||
#define I82580_PHY_CTRL_2 18
|
||||
#define I82580_PHY_LBK_CTRL 19
|
||||
#define I82580_PHY_STATUS_2 26
|
||||
#define I82580_PHY_DIAG_STATUS 31
|
||||
|
||||
/* I82580 PHY Status 2 */
|
||||
#define I82580_PHY_STATUS2_REV_POLARITY 0x0400
|
||||
#define I82580_PHY_STATUS2_MDIX 0x0800
|
||||
#define I82580_PHY_STATUS2_SPEED_MASK 0x0300
|
||||
#define I82580_PHY_STATUS2_SPEED_1000MBPS 0x0200
|
||||
#define I82580_PHY_STATUS2_SPEED_100MBPS 0x0100
|
||||
|
||||
/* I82580 PHY Control 2 */
|
||||
#define I82580_PHY_CTRL2_MANUAL_MDIX 0x0200
|
||||
#define I82580_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
|
||||
#define I82580_PHY_CTRL2_MDIX_CFG_MASK 0x0600
|
||||
|
||||
/* I82580 PHY Diagnostics Status */
|
||||
#define I82580_DSTATUS_CABLE_LENGTH 0x03FC
|
||||
#define I82580_DSTATUS_CABLE_LENGTH_SHIFT 2
|
||||
|
||||
/* 82580 PHY Power Management */
|
||||
#define E1000_82580_PHY_POWER_MGMT 0xE14
|
||||
#define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */
|
||||
#define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */
|
||||
#define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */
|
||||
#define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */
|
||||
|
||||
/* Enable flexible speed on link-up */
|
||||
#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
|
||||
#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
|
||||
#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
|
||||
#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
|
||||
#define IGP01E1000_PSSR_MDIX 0x0800
|
||||
#define IGP01E1000_PSSR_SPEED_MASK 0xC000
|
||||
#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
|
||||
#define IGP02E1000_PHY_CHANNEL_NUM 4
|
||||
#define IGP02E1000_PHY_AGC_A 0x11B1
|
||||
#define IGP02E1000_PHY_AGC_B 0x12B1
|
||||
#define IGP02E1000_PHY_AGC_C 0x14B1
|
||||
#define IGP02E1000_PHY_AGC_D 0x18B1
|
||||
#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
|
||||
#define IGP02E1000_AGC_LENGTH_MASK 0x7F
|
||||
#define IGP02E1000_AGC_RANGE 15
|
||||
|
||||
#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
|
||||
|
||||
/* SFP modules ID memory locations */
|
||||
#define E1000_SFF_IDENTIFIER_OFFSET 0x00
|
||||
#define E1000_SFF_IDENTIFIER_SFF 0x02
|
||||
#define E1000_SFF_IDENTIFIER_SFP 0x03
|
||||
|
||||
#define E1000_SFF_ETH_FLAGS_OFFSET 0x06
|
||||
/* Flags for SFP modules compatible with ETH up to 1Gb */
|
||||
struct e1000_sfp_flags {
|
||||
u8 e1000_base_sx:1;
|
||||
u8 e1000_base_lx:1;
|
||||
u8 e1000_base_cx:1;
|
||||
u8 e1000_base_t:1;
|
||||
u8 e100_base_lx:1;
|
||||
u8 e100_base_fx:1;
|
||||
u8 e10_base_bx10:1;
|
||||
u8 e10_base_px:1;
|
||||
};
|
||||
|
||||
#endif
|
||||
419
devices/igb/e1000_regs-5.14-ethercat.h
Normal file
419
devices/igb/e1000_regs-5.14-ethercat.h
Normal file
@@ -0,0 +1,419 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright(c) 2007 - 2018 Intel Corporation. */
|
||||
|
||||
#ifndef _E1000_REGS_H_
|
||||
#define _E1000_REGS_H_
|
||||
|
||||
#define E1000_CTRL 0x00000 /* Device Control - RW */
|
||||
#define E1000_STATUS 0x00008 /* Device Status - RO */
|
||||
#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
|
||||
#define E1000_EERD 0x00014 /* EEPROM Read - RW */
|
||||
#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
|
||||
#define E1000_MDIC 0x00020 /* MDI Control - RW */
|
||||
#define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
|
||||
#define E1000_SCTL 0x00024 /* SerDes Control - RW */
|
||||
#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
|
||||
#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
|
||||
#define E1000_FCT 0x00030 /* Flow Control Type - RW */
|
||||
#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
|
||||
#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
|
||||
#define E1000_TSSDP 0x0003C /* Time Sync SDP Configuration Register - RW */
|
||||
#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
|
||||
#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
|
||||
#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
|
||||
#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
|
||||
#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
|
||||
#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
|
||||
#define E1000_RCTL 0x00100 /* RX Control - RW */
|
||||
#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
|
||||
#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
|
||||
#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
|
||||
#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
|
||||
#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
|
||||
#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
|
||||
#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
|
||||
#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
|
||||
#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
|
||||
#define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
|
||||
#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
|
||||
#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
|
||||
#define E1000_TCTL 0x00400 /* TX Control - RW */
|
||||
#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
|
||||
#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
|
||||
#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
|
||||
#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
|
||||
#define E1000_LEDMUX 0x08130 /* LED MUX Control */
|
||||
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
|
||||
#define E1000_PBS 0x01008 /* Packet Buffer Size */
|
||||
#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
|
||||
#define E1000_EEMNGCTL_I210 0x12030 /* MNG EEprom Control */
|
||||
#define E1000_EEARBC_I210 0x12024 /* EEPROM Auto Read Bus Control */
|
||||
#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
|
||||
#define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
|
||||
#define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */
|
||||
#define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */
|
||||
#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
|
||||
#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
|
||||
#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
|
||||
#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
|
||||
#define E1000_I2CBB_EN 0x00000100 /* I2C - Bit Bang Enable */
|
||||
#define E1000_I2C_CLK_OUT 0x00000200 /* I2C- Clock */
|
||||
#define E1000_I2C_DATA_OUT 0x00000400 /* I2C- Data Out */
|
||||
#define E1000_I2C_DATA_OE_N 0x00000800 /* I2C- Data Output Enable */
|
||||
#define E1000_I2C_DATA_IN 0x00001000 /* I2C- Data In */
|
||||
#define E1000_I2C_CLK_OE_N 0x00002000 /* I2C- Clock Output Enable */
|
||||
#define E1000_I2C_CLK_IN 0x00004000 /* I2C- Clock In */
|
||||
#define E1000_MPHY_ADDR_CTRL 0x0024 /* GbE MPHY Address Control */
|
||||
#define E1000_MPHY_DATA 0x0E10 /* GBE MPHY Data */
|
||||
#define E1000_MPHY_STAT 0x0E0C /* GBE MPHY Statistics */
|
||||
|
||||
/* IEEE 1588 TIMESYNCH */
|
||||
#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
|
||||
#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
|
||||
#define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
|
||||
#define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */
|
||||
#define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */
|
||||
#define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */
|
||||
#define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */
|
||||
#define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */
|
||||
#define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */
|
||||
#define E1000_SYSTIML 0x0B600 /* System time register Low - RO */
|
||||
#define E1000_SYSTIMH 0x0B604 /* System time register High - RO */
|
||||
#define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */
|
||||
#define E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */
|
||||
#define E1000_TRGTTIML0 0x0B644 /* Target Time Register 0 Low - RW */
|
||||
#define E1000_TRGTTIMH0 0x0B648 /* Target Time Register 0 High - RW */
|
||||
#define E1000_TRGTTIML1 0x0B64C /* Target Time Register 1 Low - RW */
|
||||
#define E1000_TRGTTIMH1 0x0B650 /* Target Time Register 1 High - RW */
|
||||
#define E1000_FREQOUT0 0x0B654 /* Frequency Out 0 Control Register - RW */
|
||||
#define E1000_FREQOUT1 0x0B658 /* Frequency Out 1 Control Register - RW */
|
||||
#define E1000_AUXSTMPL0 0x0B65C /* Auxiliary Time Stamp 0 Register Low - RO */
|
||||
#define E1000_AUXSTMPH0 0x0B660 /* Auxiliary Time Stamp 0 Register High - RO */
|
||||
#define E1000_AUXSTMPL1 0x0B664 /* Auxiliary Time Stamp 1 Register Low - RO */
|
||||
#define E1000_AUXSTMPH1 0x0B668 /* Auxiliary Time Stamp 1 Register High - RO */
|
||||
#define E1000_SYSTIMR 0x0B6F8 /* System time register Residue */
|
||||
#define E1000_TSICR 0x0B66C /* Interrupt Cause Register */
|
||||
#define E1000_TSIM 0x0B674 /* Interrupt Mask Register */
|
||||
|
||||
/* Filtering Registers */
|
||||
#define E1000_SAQF(_n) (0x5980 + 4 * (_n))
|
||||
#define E1000_DAQF(_n) (0x59A0 + 4 * (_n))
|
||||
#define E1000_SPQF(_n) (0x59C0 + 4 * (_n))
|
||||
#define E1000_FTQF(_n) (0x59E0 + 4 * (_n))
|
||||
#define E1000_SAQF0 E1000_SAQF(0)
|
||||
#define E1000_DAQF0 E1000_DAQF(0)
|
||||
#define E1000_SPQF0 E1000_SPQF(0)
|
||||
#define E1000_FTQF0 E1000_FTQF(0)
|
||||
#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
|
||||
#define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
|
||||
|
||||
#define E1000_RQDPC(_n) (0x0C030 + ((_n) * 0x40))
|
||||
|
||||
/* DMA Coalescing registers */
|
||||
#define E1000_DMACR 0x02508 /* Control Register */
|
||||
#define E1000_DMCTXTH 0x03550 /* Transmit Threshold */
|
||||
#define E1000_DMCTLX 0x02514 /* Time to Lx Request */
|
||||
#define E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */
|
||||
#define E1000_DMCCNT 0x05DD4 /* Current Rx Count */
|
||||
#define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */
|
||||
#define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */
|
||||
|
||||
/* TX Rate Limit Registers */
|
||||
#define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select - WO */
|
||||
#define E1000_RTTBCNRM 0x3690 /* Tx BCN Rate-scheduler MMW */
|
||||
#define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config - WO */
|
||||
|
||||
/* Split and Replication RX Control - RW */
|
||||
#define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
|
||||
|
||||
/* Thermal sensor configuration and status registers */
|
||||
#define E1000_THMJT 0x08100 /* Junction Temperature */
|
||||
#define E1000_THLOWTC 0x08104 /* Low Threshold Control */
|
||||
#define E1000_THMIDTC 0x08108 /* Mid Threshold Control */
|
||||
#define E1000_THHIGHTC 0x0810C /* High Threshold Control */
|
||||
#define E1000_THSTAT 0x08110 /* Thermal Sensor Status */
|
||||
|
||||
/* Convenience macros
|
||||
*
|
||||
* Note: "_n" is the queue number of the register to be written to.
|
||||
*
|
||||
* Example usage:
|
||||
* E1000_RDBAL_REG(current_rx_queue)
|
||||
*/
|
||||
#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) \
|
||||
: (0x0C000 + ((_n) * 0x40)))
|
||||
#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) \
|
||||
: (0x0C004 + ((_n) * 0x40)))
|
||||
#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) \
|
||||
: (0x0C008 + ((_n) * 0x40)))
|
||||
#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) \
|
||||
: (0x0C00C + ((_n) * 0x40)))
|
||||
#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) \
|
||||
: (0x0C010 + ((_n) * 0x40)))
|
||||
#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) \
|
||||
: (0x0C018 + ((_n) * 0x40)))
|
||||
#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) \
|
||||
: (0x0C028 + ((_n) * 0x40)))
|
||||
#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) \
|
||||
: (0x0E000 + ((_n) * 0x40)))
|
||||
#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) \
|
||||
: (0x0E004 + ((_n) * 0x40)))
|
||||
#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) \
|
||||
: (0x0E008 + ((_n) * 0x40)))
|
||||
#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) \
|
||||
: (0x0E010 + ((_n) * 0x40)))
|
||||
#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) \
|
||||
: (0x0E018 + ((_n) * 0x40)))
|
||||
#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \
|
||||
: (0x0E028 + ((_n) * 0x40)))
|
||||
#define E1000_RXCTL(_n) ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
|
||||
(0x0C014 + ((_n) * 0x40)))
|
||||
#define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
|
||||
#define E1000_TXCTL(_n) ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
|
||||
(0x0E014 + ((_n) * 0x40)))
|
||||
#define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)
|
||||
#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \
|
||||
: (0x0E038 + ((_n) * 0x40)))
|
||||
#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) \
|
||||
: (0x0E03C + ((_n) * 0x40)))
|
||||
|
||||
#define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
|
||||
#define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
|
||||
|
||||
#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
|
||||
#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
|
||||
#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
|
||||
#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
|
||||
#define E1000_DTXCTL 0x03590 /* DMA TX Control - RW */
|
||||
#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
|
||||
#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
|
||||
#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
|
||||
#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
|
||||
#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
|
||||
#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
|
||||
#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
|
||||
#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
|
||||
#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
|
||||
#define E1000_COLC 0x04028 /* Collision Count - R/clr */
|
||||
#define E1000_DC 0x04030 /* Defer Count - R/clr */
|
||||
#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
|
||||
#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
|
||||
#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
|
||||
#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
|
||||
#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
|
||||
#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
|
||||
#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
|
||||
#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
|
||||
#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
|
||||
#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
|
||||
#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
|
||||
#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
|
||||
#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
|
||||
#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
|
||||
#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
|
||||
#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
|
||||
#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
|
||||
#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
|
||||
#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
|
||||
#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
|
||||
#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
|
||||
#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
|
||||
#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
|
||||
#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
|
||||
#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
|
||||
#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
|
||||
#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
|
||||
#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
|
||||
#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
|
||||
#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
|
||||
#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
|
||||
#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
|
||||
#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
|
||||
#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
|
||||
#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
|
||||
#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
|
||||
#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
|
||||
#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
|
||||
#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
|
||||
#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
|
||||
#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
|
||||
#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
|
||||
#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
|
||||
#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
|
||||
#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
|
||||
#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
|
||||
#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
|
||||
#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
|
||||
/* Interrupt Cause Rx Packet Timer Expire Count */
|
||||
#define E1000_ICRXPTC 0x04104
|
||||
/* Interrupt Cause Rx Absolute Timer Expire Count */
|
||||
#define E1000_ICRXATC 0x04108
|
||||
/* Interrupt Cause Tx Packet Timer Expire Count */
|
||||
#define E1000_ICTXPTC 0x0410C
|
||||
/* Interrupt Cause Tx Absolute Timer Expire Count */
|
||||
#define E1000_ICTXATC 0x04110
|
||||
/* Interrupt Cause Tx Queue Empty Count */
|
||||
#define E1000_ICTXQEC 0x04118
|
||||
/* Interrupt Cause Tx Queue Minimum Threshold Count */
|
||||
#define E1000_ICTXQMTC 0x0411C
|
||||
/* Interrupt Cause Rx Descriptor Minimum Threshold Count */
|
||||
#define E1000_ICRXDMTC 0x04120
|
||||
#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
|
||||
#define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */
|
||||
#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
|
||||
#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */
|
||||
#define E1000_CBTMPC 0x0402C /* Circuit Breaker TX Packet Count */
|
||||
#define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */
|
||||
#define E1000_CBRMPC 0x040FC /* Circuit Breaker RX Packet Count */
|
||||
#define E1000_RPTHC 0x04104 /* Rx Packets To Host */
|
||||
#define E1000_HGPTC 0x04118 /* Host Good Packets TX Count */
|
||||
#define E1000_HTCBDPC 0x04124 /* Host TX Circuit Breaker Dropped Count */
|
||||
#define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */
|
||||
#define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */
|
||||
#define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */
|
||||
#define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */
|
||||
#define E1000_LENERRS 0x04138 /* Length Errors Count */
|
||||
#define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */
|
||||
#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
|
||||
#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
|
||||
#define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */
|
||||
#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */
|
||||
#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
|
||||
#define E1000_RLPML 0x05004 /* RX Long Packet Max Length */
|
||||
#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
|
||||
#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
|
||||
#define E1000_RA 0x05400 /* Receive Address - RW Array */
|
||||
#define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */
|
||||
#define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))
|
||||
#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
|
||||
(0x054E0 + ((_i - 16) * 8)))
|
||||
#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
|
||||
(0x054E4 + ((_i - 16) * 8)))
|
||||
#define E1000_VLAPQF 0x055B0 /* VLAN Priority Queue Filter VLAPQF */
|
||||
#define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
|
||||
#define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
|
||||
#define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
|
||||
#define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
|
||||
#define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
|
||||
#define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
|
||||
#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
|
||||
#define E1000_VT_CTL 0x0581C /* VMDq Control - RW */
|
||||
#define E1000_WUC 0x05800 /* Wakeup Control - RW */
|
||||
#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
|
||||
#define E1000_WUS 0x05810 /* Wakeup Status - R/W1C */
|
||||
#define E1000_MANC 0x05820 /* Management Control - RW */
|
||||
#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
|
||||
#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
|
||||
|
||||
#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
|
||||
#define E1000_CCMCTL 0x05B48 /* CCM Control Register */
|
||||
#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
|
||||
#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */
|
||||
#define E1000_GCR 0x05B00 /* PCI-Ex Control */
|
||||
#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
|
||||
#define E1000_SWSM 0x05B50 /* SW Semaphore */
|
||||
#define E1000_FWSM 0x05B54 /* FW Semaphore */
|
||||
#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
|
||||
|
||||
/* RSS registers */
|
||||
#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
|
||||
#define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */
|
||||
#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/
|
||||
#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */
|
||||
/* MSI-X Allocation Register (_i) - RW */
|
||||
#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4))
|
||||
/* Redirection Table - RW Array */
|
||||
#define E1000_RETA(_i) (0x05C00 + ((_i) * 4))
|
||||
#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
|
||||
|
||||
/* VT Registers */
|
||||
#define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */
|
||||
#define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */
|
||||
#define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */
|
||||
#define E1000_VFRE 0x00C8C /* VF Receive Enables */
|
||||
#define E1000_VFTE 0x00C90 /* VF Transmit Enables */
|
||||
#define E1000_QDE 0x02408 /* Queue Drop Enable - RW */
|
||||
#define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */
|
||||
#define E1000_WVBR 0x03554 /* VM Wrong Behavior - RWS */
|
||||
#define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */
|
||||
#define E1000_UTA 0x0A000 /* Unicast Table Array - RW */
|
||||
#define E1000_IOVTCL 0x05BBC /* IOV Control Register */
|
||||
#define E1000_TXSWC 0x05ACC /* Tx Switch Control */
|
||||
#define E1000_LVMMC 0x03548 /* Last VM Misbehavior cause */
|
||||
/* These act per VF so an array friendly macro is used */
|
||||
#define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n)))
|
||||
#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))
|
||||
#define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n)))
|
||||
#define E1000_DVMOLR(_n) (0x0C038 + (64 * (_n)))
|
||||
#define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) /* VLAN VM Filter */
|
||||
#define E1000_VMVIR(_n) (0x03700 + (4 * (_n)))
|
||||
|
||||
struct e1000_hw;
|
||||
|
||||
u32 igb_rd32(struct e1000_hw *hw, u32 reg);
|
||||
|
||||
/* write operations, indexed using DWORDS */
|
||||
#define wr32(reg, val) \
|
||||
do { \
|
||||
u8 __iomem *hw_addr = READ_ONCE((hw)->hw_addr); \
|
||||
if (!E1000_REMOVED(hw_addr)) \
|
||||
writel((val), &hw_addr[(reg)]); \
|
||||
} while (0)
|
||||
|
||||
#define rd32(reg) (igb_rd32(hw, reg))
|
||||
|
||||
#define wrfl() ((void)rd32(E1000_STATUS))
|
||||
|
||||
#define array_wr32(reg, offset, value) \
|
||||
wr32((reg) + ((offset) << 2), (value))
|
||||
|
||||
#define array_rd32(reg, offset) (igb_rd32(hw, reg + ((offset) << 2)))
|
||||
|
||||
/* DMA Coalescing registers */
|
||||
#define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */
|
||||
|
||||
/* Energy Efficient Ethernet "EEE" register */
|
||||
#define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */
|
||||
#define E1000_EEER 0x0E30 /* Energy Efficient Ethernet */
|
||||
#define E1000_EEE_SU 0X0E34 /* EEE Setup */
|
||||
#define E1000_EMIADD 0x10 /* Extended Memory Indirect Address */
|
||||
#define E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */
|
||||
#define E1000_MMDAC 13 /* MMD Access Control */
|
||||
#define E1000_MMDAAD 14 /* MMD Access Address/Data */
|
||||
|
||||
/* Thermal Sensor Register */
|
||||
#define E1000_THSTAT 0x08110 /* Thermal Sensor Status */
|
||||
|
||||
/* OS2BMC Registers */
|
||||
#define E1000_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */
|
||||
#define E1000_B2OGPRC 0x04158 /* BMC2OS packets received by host */
|
||||
#define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */
|
||||
#define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */
|
||||
|
||||
#define E1000_SRWR 0x12018 /* Shadow Ram Write Register - RW */
|
||||
#define E1000_I210_FLMNGCTL 0x12038
|
||||
#define E1000_I210_FLMNGDATA 0x1203C
|
||||
#define E1000_I210_FLMNGCNT 0x12040
|
||||
|
||||
#define E1000_I210_FLSWCTL 0x12048
|
||||
#define E1000_I210_FLSWDATA 0x1204C
|
||||
#define E1000_I210_FLSWCNT 0x12050
|
||||
|
||||
#define E1000_I210_FLA 0x1201C
|
||||
|
||||
#define E1000_I210_DTXMXPKTSZ 0x355C
|
||||
|
||||
#define E1000_I210_TXDCTL(_n) (0x0E028 + ((_n) * 0x40))
|
||||
|
||||
#define E1000_I210_TQAVCTRL 0x3570
|
||||
#define E1000_I210_TQAVCC(_n) (0x3004 + ((_n) * 0x40))
|
||||
#define E1000_I210_TQAVHC(_n) (0x300C + ((_n) * 0x40))
|
||||
|
||||
#define E1000_I210_RR2DCDELAY 0x5BF4
|
||||
|
||||
#define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n))
|
||||
#define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */
|
||||
|
||||
#define E1000_REMOVED(h) unlikely(!(h))
|
||||
|
||||
#endif
|
||||
815
devices/igb/igb-5.14-ethercat.h
Normal file
815
devices/igb/igb-5.14-ethercat.h
Normal file
File diff suppressed because it is too large
Load Diff
3499
devices/igb/igb_ethtool-5.14-ethercat.c
Normal file
3499
devices/igb/igb_ethtool-5.14-ethercat.c
Normal file
File diff suppressed because it is too large
Load Diff
229
devices/igb/igb_hwmon-5.14-ethercat.c
Normal file
229
devices/igb/igb_hwmon-5.14-ethercat.c
Normal file
@@ -0,0 +1,229 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright(c) 2007 - 2018 Intel Corporation. */
|
||||
|
||||
#include "igb-5.14-ethercat.h"
|
||||
#include "e1000_82575-5.14-ethercat.h"
|
||||
#include "e1000_hw-5.14-ethercat.h"
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/sysfs.h>
|
||||
#include <linux/kobject.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/hwmon.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#ifdef CONFIG_IGB_HWMON
|
||||
static struct i2c_board_info i350_sensor_info = {
|
||||
I2C_BOARD_INFO("i350bb", (0Xf8 >> 1)),
|
||||
};
|
||||
|
||||
/* hwmon callback functions */
|
||||
static ssize_t igb_hwmon_show_location(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct hwmon_attr *igb_attr = container_of(attr, struct hwmon_attr,
|
||||
dev_attr);
|
||||
return sprintf(buf, "loc%u\n",
|
||||
igb_attr->sensor->location);
|
||||
}
|
||||
|
||||
static ssize_t igb_hwmon_show_temp(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct hwmon_attr *igb_attr = container_of(attr, struct hwmon_attr,
|
||||
dev_attr);
|
||||
unsigned int value;
|
||||
|
||||
/* reset the temp field */
|
||||
igb_attr->hw->mac.ops.get_thermal_sensor_data(igb_attr->hw);
|
||||
|
||||
value = igb_attr->sensor->temp;
|
||||
|
||||
/* display millidegree */
|
||||
value *= 1000;
|
||||
|
||||
return sprintf(buf, "%u\n", value);
|
||||
}
|
||||
|
||||
static ssize_t igb_hwmon_show_cautionthresh(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct hwmon_attr *igb_attr = container_of(attr, struct hwmon_attr,
|
||||
dev_attr);
|
||||
unsigned int value = igb_attr->sensor->caution_thresh;
|
||||
|
||||
/* display millidegree */
|
||||
value *= 1000;
|
||||
|
||||
return sprintf(buf, "%u\n", value);
|
||||
}
|
||||
|
||||
static ssize_t igb_hwmon_show_maxopthresh(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct hwmon_attr *igb_attr = container_of(attr, struct hwmon_attr,
|
||||
dev_attr);
|
||||
unsigned int value = igb_attr->sensor->max_op_thresh;
|
||||
|
||||
/* display millidegree */
|
||||
value *= 1000;
|
||||
|
||||
return sprintf(buf, "%u\n", value);
|
||||
}
|
||||
|
||||
/* igb_add_hwmon_attr - Create hwmon attr table for a hwmon sysfs file.
|
||||
* @ adapter: pointer to the adapter structure
|
||||
* @ offset: offset in the eeprom sensor data table
|
||||
* @ type: type of sensor data to display
|
||||
*
|
||||
* For each file we want in hwmon's sysfs interface we need a device_attribute
|
||||
* This is included in our hwmon_attr struct that contains the references to
|
||||
* the data structures we need to get the data to display.
|
||||
*/
|
||||
static int igb_add_hwmon_attr(struct igb_adapter *adapter,
|
||||
unsigned int offset, int type)
|
||||
{
|
||||
int rc;
|
||||
unsigned int n_attr;
|
||||
struct hwmon_attr *igb_attr;
|
||||
|
||||
n_attr = adapter->igb_hwmon_buff->n_hwmon;
|
||||
igb_attr = &adapter->igb_hwmon_buff->hwmon_list[n_attr];
|
||||
|
||||
switch (type) {
|
||||
case IGB_HWMON_TYPE_LOC:
|
||||
igb_attr->dev_attr.show = igb_hwmon_show_location;
|
||||
snprintf(igb_attr->name, sizeof(igb_attr->name),
|
||||
"temp%u_label", offset + 1);
|
||||
break;
|
||||
case IGB_HWMON_TYPE_TEMP:
|
||||
igb_attr->dev_attr.show = igb_hwmon_show_temp;
|
||||
snprintf(igb_attr->name, sizeof(igb_attr->name),
|
||||
"temp%u_input", offset + 1);
|
||||
break;
|
||||
case IGB_HWMON_TYPE_CAUTION:
|
||||
igb_attr->dev_attr.show = igb_hwmon_show_cautionthresh;
|
||||
snprintf(igb_attr->name, sizeof(igb_attr->name),
|
||||
"temp%u_max", offset + 1);
|
||||
break;
|
||||
case IGB_HWMON_TYPE_MAX:
|
||||
igb_attr->dev_attr.show = igb_hwmon_show_maxopthresh;
|
||||
snprintf(igb_attr->name, sizeof(igb_attr->name),
|
||||
"temp%u_crit", offset + 1);
|
||||
break;
|
||||
default:
|
||||
rc = -EPERM;
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* These always the same regardless of type */
|
||||
igb_attr->sensor =
|
||||
&adapter->hw.mac.thermal_sensor_data.sensor[offset];
|
||||
igb_attr->hw = &adapter->hw;
|
||||
igb_attr->dev_attr.store = NULL;
|
||||
igb_attr->dev_attr.attr.mode = 0444;
|
||||
igb_attr->dev_attr.attr.name = igb_attr->name;
|
||||
sysfs_attr_init(&igb_attr->dev_attr.attr);
|
||||
|
||||
adapter->igb_hwmon_buff->attrs[n_attr] = &igb_attr->dev_attr.attr;
|
||||
|
||||
++adapter->igb_hwmon_buff->n_hwmon;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void igb_sysfs_del_adapter(struct igb_adapter *adapter)
|
||||
{
|
||||
}
|
||||
|
||||
/* called from igb_main.c */
|
||||
void igb_sysfs_exit(struct igb_adapter *adapter)
|
||||
{
|
||||
igb_sysfs_del_adapter(adapter);
|
||||
}
|
||||
|
||||
/* called from igb_main.c */
|
||||
int igb_sysfs_init(struct igb_adapter *adapter)
|
||||
{
|
||||
struct hwmon_buff *igb_hwmon;
|
||||
struct i2c_client *client;
|
||||
struct device *hwmon_dev;
|
||||
unsigned int i;
|
||||
int rc = 0;
|
||||
|
||||
/* If this method isn't defined we don't support thermals */
|
||||
if (adapter->hw.mac.ops.init_thermal_sensor_thresh == NULL)
|
||||
goto exit;
|
||||
|
||||
/* Don't create thermal hwmon interface if no sensors present */
|
||||
rc = (adapter->hw.mac.ops.init_thermal_sensor_thresh(&adapter->hw));
|
||||
if (rc)
|
||||
goto exit;
|
||||
|
||||
igb_hwmon = devm_kzalloc(&adapter->pdev->dev, sizeof(*igb_hwmon),
|
||||
GFP_KERNEL);
|
||||
if (!igb_hwmon) {
|
||||
rc = -ENOMEM;
|
||||
goto exit;
|
||||
}
|
||||
adapter->igb_hwmon_buff = igb_hwmon;
|
||||
|
||||
for (i = 0; i < E1000_MAX_SENSORS; i++) {
|
||||
|
||||
/* Only create hwmon sysfs entries for sensors that have
|
||||
* meaningful data.
|
||||
*/
|
||||
if (adapter->hw.mac.thermal_sensor_data.sensor[i].location == 0)
|
||||
continue;
|
||||
|
||||
/* Bail if any hwmon attr struct fails to initialize */
|
||||
rc = igb_add_hwmon_attr(adapter, i, IGB_HWMON_TYPE_CAUTION);
|
||||
if (rc)
|
||||
goto exit;
|
||||
rc = igb_add_hwmon_attr(adapter, i, IGB_HWMON_TYPE_LOC);
|
||||
if (rc)
|
||||
goto exit;
|
||||
rc = igb_add_hwmon_attr(adapter, i, IGB_HWMON_TYPE_TEMP);
|
||||
if (rc)
|
||||
goto exit;
|
||||
rc = igb_add_hwmon_attr(adapter, i, IGB_HWMON_TYPE_MAX);
|
||||
if (rc)
|
||||
goto exit;
|
||||
}
|
||||
|
||||
/* init i2c_client */
|
||||
client = i2c_new_client_device(&adapter->i2c_adap, &i350_sensor_info);
|
||||
if (IS_ERR(client)) {
|
||||
dev_info(&adapter->pdev->dev,
|
||||
"Failed to create new i2c device.\n");
|
||||
rc = PTR_ERR(client);
|
||||
goto exit;
|
||||
}
|
||||
adapter->i2c_client = client;
|
||||
|
||||
igb_hwmon->groups[0] = &igb_hwmon->group;
|
||||
igb_hwmon->group.attrs = igb_hwmon->attrs;
|
||||
|
||||
hwmon_dev = devm_hwmon_device_register_with_groups(&adapter->pdev->dev,
|
||||
client->name,
|
||||
igb_hwmon,
|
||||
igb_hwmon->groups);
|
||||
if (IS_ERR(hwmon_dev)) {
|
||||
rc = PTR_ERR(hwmon_dev);
|
||||
goto err;
|
||||
}
|
||||
|
||||
goto exit;
|
||||
|
||||
err:
|
||||
igb_sysfs_del_adapter(adapter);
|
||||
exit:
|
||||
return rc;
|
||||
}
|
||||
#endif
|
||||
10125
devices/igb/igb_main-5.14-ethercat.c
Normal file
10125
devices/igb/igb_main-5.14-ethercat.c
Normal file
File diff suppressed because it is too large
Load Diff
1383
devices/igb/igb_ptp-5.14-ethercat.c
Normal file
1383
devices/igb/igb_ptp-5.14-ethercat.c
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user