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Renamed phy_ commands to reg_.

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This commit is contained in:
Florian Pose
2009-04-08 12:48:59 +00:00
parent 848ccb3bed
commit 7f97ba66a2
15 changed files with 109 additions and 110 deletions
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1
TODO
View File

@@ -24,7 +24,6 @@ Version 1.5.0:
* Test File access over EtherCAT (FoE) reading.
* Distributed clocks.
* Implement ecrt_master_slave() in kernel space.
* Rename phy-commands to register commands.
* Check for ioctl() interface version.
* Improve application-triggered SDO transfers by moving the statemachine into
the SDO handlers.

44
master/cdev.c
View File

@@ -1041,17 +1041,17 @@ int ec_cdev_ioctl_slave_sii_write(
/*****************************************************************************/
/** Read a slave's physical memory.
/** Read a slave's registers.
*/
int ec_cdev_ioctl_slave_phy_read(
int ec_cdev_ioctl_slave_reg_read(
ec_master_t *master, /**< EtherCAT master. */
unsigned long arg /**< ioctl() argument. */
)
{
ec_ioctl_slave_phy_t data;
ec_ioctl_slave_reg_t data;
ec_slave_t *slave;
uint8_t *contents;
ec_phy_request_t request;
ec_reg_request_t request;
if (copy_from_user(&data, (void __user *) arg, sizeof(data))) {
return -EFAULT;
@@ -1061,7 +1061,7 @@ int ec_cdev_ioctl_slave_phy_read(
return 0;
if (!(contents = kmalloc(data.length, GFP_KERNEL))) {
EC_ERR("Failed to allocate %u bytes for phy data.\n", data.length);
EC_ERR("Failed to allocate %u bytes for register data.\n", data.length);
return -ENOMEM;
}
@@ -1075,7 +1075,7 @@ int ec_cdev_ioctl_slave_phy_read(
return -EINVAL;
}
// init phy request
// init register request
INIT_LIST_HEAD(&request.list);
request.slave = slave;
request.dir = EC_DIR_INPUT;
@@ -1085,12 +1085,12 @@ int ec_cdev_ioctl_slave_phy_read(
request.state = EC_INT_REQUEST_QUEUED;
// schedule request.
list_add_tail(&request.list, &master->phy_requests);
list_add_tail(&request.list, &master->reg_requests);
up(&master->master_sem);
// wait for processing through FSM
if (wait_event_interruptible(master->phy_queue,
if (wait_event_interruptible(master->reg_queue,
request.state != EC_INT_REQUEST_QUEUED)) {
// interrupted by signal
down(&master->master_sem);
@@ -1105,7 +1105,7 @@ int ec_cdev_ioctl_slave_phy_read(
}
// wait until master FSM has finished processing
wait_event(master->phy_queue, request.state != EC_INT_REQUEST_BUSY);
wait_event(master->reg_queue, request.state != EC_INT_REQUEST_BUSY);
if (request.state == EC_INT_REQUEST_SUCCESS) {
if (copy_to_user((void __user *) data.data, contents, data.length))
@@ -1118,17 +1118,17 @@ int ec_cdev_ioctl_slave_phy_read(
/*****************************************************************************/
/** Write a slave's physical memory.
/** Write a slave's registers.
*/
int ec_cdev_ioctl_slave_phy_write(
int ec_cdev_ioctl_slave_reg_write(
ec_master_t *master, /**< EtherCAT master. */
unsigned long arg /**< ioctl() argument. */
)
{
ec_ioctl_slave_phy_t data;
ec_ioctl_slave_reg_t data;
ec_slave_t *slave;
uint8_t *contents;
ec_phy_request_t request;
ec_reg_request_t request;
if (copy_from_user(&data, (void __user *) arg, sizeof(data))) {
return -EFAULT;
@@ -1138,7 +1138,7 @@ int ec_cdev_ioctl_slave_phy_write(
return 0;
if (!(contents = kmalloc(data.length, GFP_KERNEL))) {
EC_ERR("Failed to allocate %u bytes for phy data.\n", data.length);
EC_ERR("Failed to allocate %u bytes for register data.\n", data.length);
return -ENOMEM;
}
@@ -1158,7 +1158,7 @@ int ec_cdev_ioctl_slave_phy_write(
return -EINVAL;
}
// init phy request
// init register request
INIT_LIST_HEAD(&request.list);
request.slave = slave;
request.dir = EC_DIR_OUTPUT;
@@ -1168,12 +1168,12 @@ int ec_cdev_ioctl_slave_phy_write(
request.state = EC_INT_REQUEST_QUEUED;
// schedule request.
list_add_tail(&request.list, &master->phy_requests);
list_add_tail(&request.list, &master->reg_requests);
up(&master->master_sem);
// wait for processing through FSM
if (wait_event_interruptible(master->phy_queue,
if (wait_event_interruptible(master->reg_queue,
request.state != EC_INT_REQUEST_QUEUED)) {
// interrupted by signal
down(&master->master_sem);
@@ -1188,7 +1188,7 @@ int ec_cdev_ioctl_slave_phy_write(
}
// wait until master FSM has finished processing
wait_event(master->phy_queue, request.state != EC_INT_REQUEST_BUSY);
wait_event(master->reg_queue, request.state != EC_INT_REQUEST_BUSY);
kfree(contents);
@@ -2981,12 +2981,12 @@ long eccdev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
if (!(filp->f_mode & FMODE_WRITE))
return -EPERM;
return ec_cdev_ioctl_slave_sii_write(master, arg);
case EC_IOCTL_SLAVE_PHY_READ:
return ec_cdev_ioctl_slave_phy_read(master, arg);
case EC_IOCTL_SLAVE_PHY_WRITE:
case EC_IOCTL_SLAVE_REG_READ:
return ec_cdev_ioctl_slave_reg_read(master, arg);
case EC_IOCTL_SLAVE_REG_WRITE:
if (!(filp->f_mode & FMODE_WRITE))
return -EPERM;
return ec_cdev_ioctl_slave_phy_write(master, arg);
return ec_cdev_ioctl_slave_reg_write(master, arg);
case EC_IOCTL_SLAVE_FOE_READ:
return ec_cdev_ioctl_slave_foe_read(master, arg);
case EC_IOCTL_SLAVE_FOE_WRITE:

52
master/fsm_master.c
View File

@@ -56,7 +56,7 @@ void ec_fsm_master_state_scan_slave(ec_fsm_master_t *);
void ec_fsm_master_state_write_sii(ec_fsm_master_t *);
void ec_fsm_master_state_sdo_dictionary(ec_fsm_master_t *);
void ec_fsm_master_state_sdo_request(ec_fsm_master_t *);
void ec_fsm_master_state_phy_request(ec_fsm_master_t *);
void ec_fsm_master_state_reg_request(ec_fsm_master_t *);
void ec_fsm_master_state_foe_request(ec_fsm_master_t *);
/*****************************************************************************/
@@ -327,29 +327,29 @@ int ec_fsm_master_action_process_sii(
/*****************************************************************************/
/** Check for pending phy requests and process one.
/** Check for pending register requests and process one.
*
* \return non-zero, if a phy request is processed.
* \return non-zero, if a register request is processed.
*/
int ec_fsm_master_action_process_phy(
int ec_fsm_master_action_process_register(
ec_fsm_master_t *fsm /**< Master state machine. */
)
{
ec_master_t *master = fsm->master;
ec_phy_request_t *request;
ec_reg_request_t *request;
// search the first request to be processed
while (!list_empty(&master->phy_requests)) {
while (!list_empty(&master->reg_requests)) {
// get first request
request = list_entry(master->phy_requests.next,
ec_phy_request_t, list);
request = list_entry(master->reg_requests.next,
ec_reg_request_t, list);
list_del_init(&request->list); // dequeue
request->state = EC_INT_REQUEST_BUSY;
// found pending request; process it!
if (master->debug_level)
EC_DBG("Processing phy request for slave %u, "
EC_DBG("Processing register request for slave %u, "
"offset 0x%04x, length %u...\n",
request->slave->ring_position,
request->offset, request->length);
@@ -359,11 +359,11 @@ int ec_fsm_master_action_process_phy(
"datagram size (%u)!\n", request->length,
fsm->datagram->mem_size);
request->state = EC_INT_REQUEST_FAILURE;
wake_up(&master->phy_queue);
wake_up(&master->reg_queue);
continue;
}
fsm->phy_request = request;
fsm->reg_request = request;
if (request->dir == EC_DIR_INPUT) {
ec_datagram_fprd(fsm->datagram, request->slave->station_address,
@@ -375,7 +375,7 @@ int ec_fsm_master_action_process_phy(
memcpy(fsm->datagram->data, request->data, request->length);
}
fsm->retries = EC_FSM_RETRIES;
fsm->state = ec_fsm_master_state_phy_request;
fsm->state = ec_fsm_master_state_reg_request;
return 1;
}
@@ -568,9 +568,9 @@ void ec_fsm_master_action_idle(
if (ec_fsm_master_action_process_sii(fsm))
return; // SII write request found
// check for pending phy requests.
if (ec_fsm_master_action_process_phy(fsm))
return; // phy request processing
// check for pending register requests.
if (ec_fsm_master_action_process_register(fsm))
return; // register request processing
ec_fsm_master_restart(fsm);
}
@@ -1014,21 +1014,21 @@ void ec_fsm_master_state_sdo_request(
/*****************************************************************************/
/** Master state: PHY.
/** Master state: REG REQUEST.
*/
void ec_fsm_master_state_phy_request(
void ec_fsm_master_state_reg_request(
ec_fsm_master_t *fsm /**< Master state machine. */
)
{
ec_master_t *master = fsm->master;
ec_datagram_t *datagram = fsm->datagram;
ec_phy_request_t *request = fsm->phy_request;
ec_reg_request_t *request = fsm->reg_request;
if (datagram->state != EC_DATAGRAM_RECEIVED) {
EC_ERR("Failed to receive phy request datagram (state %u).\n",
EC_ERR("Failed to receive register request datagram (state %u).\n",
datagram->state);
request->state = EC_INT_REQUEST_FAILURE;
wake_up(&master->phy_queue);
wake_up(&master->reg_queue);
ec_fsm_master_restart(fsm);
return;
}
@@ -1039,10 +1039,10 @@ void ec_fsm_master_state_phy_request(
kfree(request->data);
request->data = kmalloc(request->length, GFP_KERNEL);
if (!request->data) {
EC_ERR("Failed to allocate %u bytes of memory for phy request.\n",
request->length);
EC_ERR("Failed to allocate %u bytes of memory for"
" register data.\n", request->length);
request->state = EC_INT_REQUEST_FAILURE;
wake_up(&master->phy_queue);
wake_up(&master->reg_queue);
ec_fsm_master_restart(fsm);
return;
}
@@ -1054,10 +1054,10 @@ void ec_fsm_master_state_phy_request(
request->state = EC_INT_REQUEST_FAILURE;
}
wake_up(&master->phy_queue);
wake_up(&master->reg_queue);
// check for another PHY request
if (ec_fsm_master_action_process_phy(fsm))
// check for another register request
if (ec_fsm_master_action_process_register(fsm))
return; // processing another request
ec_fsm_master_restart(fsm);

8
master/fsm_master.h
View File

@@ -61,17 +61,17 @@ typedef struct {
/*****************************************************************************/
/** Physical memory request.
/** Register request.
*/
typedef struct {
struct list_head list; /**< List head. */
ec_slave_t *slave; /**< EtherCAT slave. */
ec_direction_t dir; /**< Direction. */
uint16_t offset; /**< Physical memory offset. */
uint16_t offset; /**< Register address. */
size_t length; /**< Number of bytes. */
uint8_t *data; /**< Data to write / memory for read data. */
ec_internal_request_state_t state; /**< State of the request. */
} ec_phy_request_t;
} ec_reg_request_t;
/*****************************************************************************/
@@ -114,7 +114,7 @@ struct ec_fsm_master {
ec_sii_write_request_t *sii_request; /**< SII write request */
off_t sii_index; /**< index to SII write request data */
ec_sdo_request_t *sdo_request; /**< SDO request to process. */
ec_phy_request_t *phy_request; /**< Physical memory request to process. */
ec_reg_request_t *reg_request; /**< Register request to process. */
ec_foe_request_t *foe_request; /**< FoE request to process. */
off_t foe_index; /**< index to FoE write request data */

6
master/ioctl.h
View File

@@ -69,8 +69,8 @@
#define EC_IOCTL_SLAVE_SDO_DOWNLOAD EC_IOWR(0x0d, ec_ioctl_slave_sdo_download_t)
#define EC_IOCTL_SLAVE_SII_READ EC_IOWR(0x0e, ec_ioctl_slave_sii_t)
#define EC_IOCTL_SLAVE_SII_WRITE EC_IOW(0x0f, ec_ioctl_slave_sii_t)
#define EC_IOCTL_SLAVE_PHY_READ EC_IOWR(0x10, ec_ioctl_slave_phy_t)
#define EC_IOCTL_SLAVE_PHY_WRITE EC_IOW(0x11, ec_ioctl_slave_phy_t)
#define EC_IOCTL_SLAVE_REG_READ EC_IOWR(0x10, ec_ioctl_slave_reg_t)
#define EC_IOCTL_SLAVE_REG_WRITE EC_IOW(0x11, ec_ioctl_slave_reg_t)
#define EC_IOCTL_SLAVE_FOE_READ EC_IOWR(0x12, ec_ioctl_slave_foe_t)
#define EC_IOCTL_SLAVE_FOE_WRITE EC_IOW(0x13, ec_ioctl_slave_foe_t)
#define EC_IOCTL_CONFIG EC_IOWR(0x14, ec_ioctl_config_t)
@@ -340,7 +340,7 @@ typedef struct {
uint16_t offset;
uint16_t length;
uint8_t *data;
} ec_ioctl_slave_phy_t;
} ec_ioctl_slave_reg_t;
/*****************************************************************************/

4
master/master.c
View File

@@ -170,8 +170,8 @@ int ec_master_init(ec_master_t *master, /**< EtherCAT master */
INIT_LIST_HEAD(&master->slave_sdo_requests);
init_waitqueue_head(&master->sdo_queue);
INIT_LIST_HEAD(&master->phy_requests);
init_waitqueue_head(&master->phy_queue);
INIT_LIST_HEAD(&master->reg_requests);
init_waitqueue_head(&master->reg_queue);
INIT_LIST_HEAD(&master->foe_requests);
init_waitqueue_head(&master->foe_queue);

4
master/master.h
View File

@@ -166,8 +166,8 @@ struct ec_master {
wait_queue_head_t sdo_queue; /**< Wait queue for SDO access requests
from user space. */
struct list_head phy_requests; /**< Physical memory requests. */
wait_queue_head_t phy_queue; /**< Wait queue for phy requests. */
struct list_head reg_requests; /**< Register requests. */
wait_queue_head_t reg_queue; /**< Wait queue for register requests. */
struct list_head foe_requests; /**< FoE write requests. */
wait_queue_head_t foe_queue; /**< Wait queue for FoE

20
tool/CommandPhyRead.cpp → tool/CommandRegRead.cpp
View File

@@ -31,18 +31,18 @@
#include <iomanip>
using namespace std;
#include "CommandPhyRead.h"
#include "CommandRegRead.h"
/*****************************************************************************/
CommandPhyRead::CommandPhyRead():
Command("phy_read", "Output a slave's physical memory contents.")
CommandRegRead::CommandRegRead():
Command("reg_read", "Output a slave's register contents.")
{
}
/*****************************************************************************/
string CommandPhyRead::helpString() const
string CommandRegRead::helpString() const
{
stringstream str;
@@ -53,7 +53,7 @@ string CommandPhyRead::helpString() const
<< "This command requires a single slave to be selected." << endl
<< endl
<< "Arguments:" << endl
<< " OFFSET is the physical memory address. Must" << endl
<< " OFFSET is the register address. Must" << endl
<< " be an unsigned 16 bit number." << endl
<< " LENGTH is the number of bytes to read and must also be" << endl
<< " an unsigned 16 bit number. OFFSET plus LENGTH" << endl
@@ -78,10 +78,10 @@ string CommandPhyRead::helpString() const
/****************************************************************************/
void CommandPhyRead::execute(MasterDevice &m, const StringVector &args)
void CommandRegRead::execute(MasterDevice &m, const StringVector &args)
{
SlaveList slaves;
ec_ioctl_slave_phy_t data;
ec_ioctl_slave_reg_t data;
stringstream strOffset, err;
const DataType *dataType = NULL;
@@ -152,7 +152,7 @@ void CommandPhyRead::execute(MasterDevice &m, const StringVector &args)
data.data = new uint8_t[data.length];
try {
m.readPhy(&data);
m.readReg(&data);
} catch (MasterDeviceException &e) {
delete [] data.data;
throw e;
@@ -208,7 +208,7 @@ void CommandPhyRead::execute(MasterDevice &m, const StringVector &args)
/****************************************************************************/
const CommandPhyRead::DataType *CommandPhyRead::findDataType(
const CommandRegRead::DataType *CommandRegRead::findDataType(
const string &str
)
{
@@ -223,7 +223,7 @@ const CommandPhyRead::DataType *CommandPhyRead::findDataType(
/****************************************************************************/
const CommandPhyRead::DataType CommandPhyRead::dataTypes[] = {
const CommandRegRead::DataType CommandRegRead::dataTypes[] = {
{"int8", 1},
{"int16", 2},
{"int32", 4},

8
tool/CommandPhyRead.h → tool/CommandRegRead.h
View File

@@ -27,18 +27,18 @@
*
****************************************************************************/
#ifndef __COMMANDPHYREAD_H__
#define __COMMANDPHYREAD_H__
#ifndef __COMMANDREGREAD_H__
#define __COMMANDREGREAD_H__
#include "Command.h"
/****************************************************************************/
class CommandPhyRead:
class CommandRegRead:
public Command
{
public:
CommandPhyRead();
CommandRegRead();
string helpString() const;
void execute(MasterDevice &, const StringVector &);

26
tool/CommandPhyWrite.cpp → tool/CommandRegWrite.cpp
View File

@@ -32,19 +32,19 @@
#include <fstream>
using namespace std;
#include "CommandPhyWrite.h"
#include "CommandRegWrite.h"
#include "sii_crc.h"
/*****************************************************************************/
CommandPhyWrite::CommandPhyWrite():
Command("phy_write", "Write data to a slave's physical memory.")
CommandRegWrite::CommandRegWrite():
Command("reg_write", "Write data to a slave's registers.")
{
}
/*****************************************************************************/
string CommandPhyWrite::helpString() const
string CommandRegWrite::helpString() const
{
stringstream str;
@@ -55,7 +55,7 @@ string CommandPhyWrite::helpString() const
<< "This command requires a single slave to be selected." << endl
<< endl
<< "Arguments:" << endl
<< " OFFSET must be the physical memory offset to start." << endl
<< " OFFSET must be the register address." << endl
<< " FILENAME must be a path to a file with data to write." << endl
<< " If it is '-', data are read from stdin." << endl
<< endl
@@ -71,10 +71,10 @@ string CommandPhyWrite::helpString() const
/****************************************************************************/
void CommandPhyWrite::execute(MasterDevice &m, const StringVector &args)
void CommandRegWrite::execute(MasterDevice &m, const StringVector &args)
{
stringstream strOffset, err;
ec_ioctl_slave_phy_t data;
ec_ioctl_slave_reg_t data;
ifstream file;
SlaveList slaves;
@@ -93,14 +93,14 @@ void CommandPhyWrite::execute(MasterDevice &m, const StringVector &args)
}
if (args[1] == "-") {
loadPhyData(&data, cin);
loadRegData(&data, cin);
} else {
file.open(args[1].c_str(), ifstream::in | ifstream::binary);
if (file.fail()) {
err << "Failed to open '" << args[0] << "'!";
throwCommandException(err);
}
loadPhyData(&data, file);
loadRegData(&data, file);
file.close();
}
@@ -126,14 +126,14 @@ void CommandPhyWrite::execute(MasterDevice &m, const StringVector &args)
// send data to master
try {
m.writePhy(&data);
m.writeReg(&data);
} catch (MasterDeviceException &e) {
delete [] data.data;
throw e;
}
if (getVerbosity() == Verbose) {
cerr << "Physical memory writing finished." << endl;
cerr << "Register writing finished." << endl;
}
delete [] data.data;
@@ -141,8 +141,8 @@ void CommandPhyWrite::execute(MasterDevice &m, const StringVector &args)
/*****************************************************************************/
void CommandPhyWrite::loadPhyData(
ec_ioctl_slave_phy_t *data,
void CommandRegWrite::loadRegData(
ec_ioctl_slave_reg_t *data,
const istream &in
)
{

10
tool/CommandPhyWrite.h → tool/CommandRegWrite.h
View File

@@ -27,24 +27,24 @@
*
****************************************************************************/
#ifndef __COMMANDPHYWRITE_H__
#define __COMMANDPHYWRITE_H__
#ifndef __COMMANDREGWRITE_H__
#define __COMMANDREGWRITE_H__
#include "Command.h"
/****************************************************************************/
class CommandPhyWrite:
class CommandRegWrite:
public Command
{
public:
CommandPhyWrite();
CommandRegWrite();
string helpString() const;
void execute(MasterDevice &, const StringVector &);
private:
void loadPhyData(ec_ioctl_slave_phy_t *, const istream &);
void loadRegData(ec_ioctl_slave_reg_t *, const istream &);
};
/****************************************************************************/

8
tool/Makefile.am
View File

@@ -45,8 +45,8 @@ ethercat_SOURCES = \
CommandFoeWrite.cpp \
CommandMaster.cpp \
CommandPdos.cpp \
CommandPhyRead.cpp \
CommandPhyWrite.cpp \
CommandRegRead.cpp \
CommandRegWrite.cpp \
CommandSdos.cpp \
CommandSiiRead.cpp \
CommandSiiWrite.cpp \
@@ -73,8 +73,8 @@ noinst_HEADERS = \
CommandFoeWrite.h \
CommandMaster.h \
CommandPdos.h \
CommandPhyRead.h \
CommandPhyWrite.h \
CommandRegRead.h \
CommandRegWrite.h \
CommandSdos.h \
CommandSiiRead.h \
CommandSiiWrite.h \

16
tool/MasterDevice.cpp
View File

@@ -369,26 +369,26 @@ void MasterDevice::writeSii(
/****************************************************************************/
void MasterDevice::readPhy(
ec_ioctl_slave_phy_t *data
void MasterDevice::readReg(
ec_ioctl_slave_reg_t *data
)
{
if (ioctl(fd, EC_IOCTL_SLAVE_PHY_READ, data) < 0) {
if (ioctl(fd, EC_IOCTL_SLAVE_REG_READ, data) < 0) {
stringstream err;
err << "Failed to read physical memory: " << strerror(errno);
err << "Failed to read register: " << strerror(errno);
throw MasterDeviceException(err);
}
}
/****************************************************************************/
void MasterDevice::writePhy(
ec_ioctl_slave_phy_t *data
void MasterDevice::writeReg(
ec_ioctl_slave_reg_t *data
)
{
if (ioctl(fd, EC_IOCTL_SLAVE_PHY_WRITE, data) < 0) {
if (ioctl(fd, EC_IOCTL_SLAVE_REG_WRITE, data) < 0) {
stringstream err;
err << "Failed to write physical memory: " << strerror(errno);
err << "Failed to write register: " << strerror(errno);
throw MasterDeviceException(err);
}
}

4
tool/MasterDevice.h
View File

@@ -109,8 +109,8 @@ class MasterDevice
void getSdoEntry(ec_ioctl_slave_sdo_entry_t *, uint16_t, int, uint8_t);
void readSii(ec_ioctl_slave_sii_t *);
void writeSii(ec_ioctl_slave_sii_t *);
void readPhy(ec_ioctl_slave_phy_t *);
void writePhy(ec_ioctl_slave_phy_t *);
void readReg(ec_ioctl_slave_reg_t *);
void writeReg(ec_ioctl_slave_reg_t *);
void setDebug(unsigned int);
void sdoDownload(ec_ioctl_slave_sdo_download_t *);
void sdoUpload(ec_ioctl_slave_sdo_upload_t *);

8
tool/main.cpp
View File

@@ -45,8 +45,8 @@ using namespace std;
#include "CommandFoeWrite.h"
#include "CommandMaster.h"
#include "CommandPdos.h"
#include "CommandPhyRead.h"
#include "CommandPhyWrite.h"
#include "CommandRegRead.h"
#include "CommandRegWrite.h"
#include "CommandSdos.h"
#include "CommandSiiRead.h"
#include "CommandSiiWrite.h"
@@ -299,8 +299,8 @@ int main(int argc, char **argv)
commandList.push_back(new CommandFoeWrite());
commandList.push_back(new CommandMaster());
commandList.push_back(new CommandPdos());
commandList.push_back(new CommandPhyRead());
commandList.push_back(new CommandPhyWrite());
commandList.push_back(new CommandRegRead());
commandList.push_back(new CommandRegWrite());
commandList.push_back(new CommandSdos());
commandList.push_back(new CommandSiiRead());
commandList.push_back(new CommandSiiWrite());