Intial Commit PX4 FMUV6RT

nxp/rt117x:Fix Pin IRQ nxp/rt117x:Support 4 i2c busses nxp/rt117x:Add px4io_serial support nxp/imxrt:Expand ToneAlarmInterface to GPT 3 & 4 px4_fmu-6xrt:Using imxrt_flexspi_nor_octal px4_fmu-6xrt:Entry is start px4_fmu-6xrt:Add Proper MTD px4_fmu-6xrt:Set I2C Buses px4_fmu-6xrt:Proper SPI usage px4_fmu-6xrt:Adjust memory Map to use the 2 MB px4_fmu-6xrt:Bring in ROMAPI px4_fmu-6xrt:Push FLASH to 200Mhz px4_fmu-6xrt:Use BOARD_I2C_LATEINIT px4_fmu-6xrt:Clock Config remove unused devices px4_fmu-6xrt:Remove EVK SDRAM IO px4_fmu-6xrt:Enable SE550 using HW_VER_REV_DRIVE px4_fmu-6xrt:Use MTD to mount FRAM on Flex SPI px4_fmu-6xrt:Manifest px4_fmu-6xrt:Restore board_peripheral_reset px4_fmu-6xrt:Set I2C buss Interna/Externa and startup nxp/rt117x:Set 6 I2C busses px4_fmu-6xrt:Correct Clock Sources and Freqency Settings px4_fmu-6xrt:Correct ADC Settings px4_fmu-6xrt:Tune FlexSPI config and sync header with debug variant Linker prep for rodata ahb partitioning px4_fmu-6xrt:FlexSPI prefetch partition split .text and .rodata Current config 1KB Prefetch .rodata 3KB Prefetch .text px4_fmu-6xrt:Run imxrt_flash_setup_prefetch_partition from ram with barriers px4_fmu-6xrt:Use All OCTL setting from FLASH g_flash_config SANS lookupTable px4_fmu-6xrt:Octal spi boot/debug problem bypass px4_fmu-6xrt:Add PWM test px4_fmu-6xrt:Fix clockconfig and USB vbus sense px4_fmu-6xrt: Use TCM px4_fmu-6xrt: Ethernet bringup imxrt: use unique_id register for board_identity px4_fmu-6xrt: update ITCM mapping, todo proper trap on pc hitting 0x0 px4_fmu-6xrt:correct rotation icm42688p onboard imu rt117x: Add SSARC HP RAM driver for memory dumps px4_fmu-6xrt: Enable hardfault_log px4_fmu-6xrt: Enable DMA pool px4_fmu-6xrt: fix uart mapping px4_fmu-6xrt: enable SocketCAN & DroneCAN px4_fmu-6xrt:Command line history TAB completion px4_fmu-6xrt:Fix pinning duplication px4_fmu-6xrt:Support conditional PHY address based on selected PHY px4_fmu-6xrt:Add Pull Downs on CTS, use GPIO for RTS px4_fmu-6xrt:Set TelemN TX Slew rate and Drive Strenth to max px4_fmu-6xrt::Set TELEM Buffers add HW HS px4_fmu-6xrt:Turn off DMA poll px4_fmu-6xrt:RC_SERIAL_PORT needed to be px4io to disable rc_input using TELEM2! px4_fmu-6xrt: bootloader (#22228) * imxrt:Add bootloader support * bootloader:imxrt clear BOOT_RTC_SIGNATURE * px4_fmu-6xrt:Add bootloader * px4_fmu-6xrt:bootloader removed ADC * px4_fmu-6xrt:bootloader base bootloader script off of script.ld * px4_fmu-6xrt:add _bootdelay_signature & change entry from 0x30000000 to 0x30040000 * px4_fmu-6xrt:hw_config Bootloader has to have 12 bytes px4_fmu-6xrt:Default to use LAN8742A PHY px4_fmu-v6xrt:VID Set to Drone Code board_reset:Enable ability to write RTC GP regs px4_fmu-6xrt:Fix CMP0079 error rt117x:micro_hal Add a PX4_MAKE_GPIO_PULLED_INPUT px4_fmu-v6xrt:Set CTS High before VDD_5V applided to ports to avoid radios fro entering bootloaders fmu-v6xrt: increase 5v down time fmu-v6xrt:Ready for Release DEBUGASSERTS off and Console 57600, Bootloder updated. imxrt:board_hw_rev_ver Rework for 3.893V Ref px4_fmu-v6xrt:Move ADC to Port3
2026-05-27 18:27:05 +08:00 · 2023-05-02 07:00:24 -07:00
parent e3f8d53718
commit e90e8ae0ea
69 changed files with 11080 additions and 308 deletions
@@ -111,6 +111,8 @@ pipeline {
                     "px4_fmu-v6c_default",
                     "px4_fmu-v6u_default",
                     "px4_fmu-v6x_default",
+                     "px4_fmu-v6xrt_bootloader",
+                     "px4_fmu-v6xrt_default",
                     "px4_io-v2_default",
                     "raspberrypi_pico_default",
                     "sky-drones_smartap-airlink_default",
@@ -57,7 +57,6 @@ jobs:
          mro_x21-777,
          nxp_fmuk66-e,
          nxp_fmuk66-v3,
-          nxp_fmurt1062-v1,
          nxp_mr-canhubk3,
          nxp_ucans32k146,
          omnibus_f4sd,
@@ -70,6 +69,7 @@ jobs:
          px4_fmu-v6c,
          px4_fmu-v6u,
          px4_fmu-v6x,
+          px4_fmu-v6xrt,
          raspberrypi_pico,
          sky-drones_smartap-airlink,
          spracing_h7extreme,
@@ -81,6 +81,16 @@ CONFIG:
      buildType: MinSizeRel
      settings:
        CONFIG: px4_fmu-v6x_bootloader
+    px4_fmu-v6xrt_default:
+      short: px4_fmu-v6xrt
+      buildType: MinSizeRel
+      settings:
+        CONFIG: px4_fmu-v6xrt_default
+    px4_fmu-v6xrt_bootloader:
+      short: px4_fmu-v6xrt_bootloader
+      buildType: MinSizeRel
+      settings:
+        CONFIG: px4_fmu-v6xrt_bootloader
    airmind_mindpx-v2_default:
      short: airmind_mindpx-v2
      buildType: MinSizeRel
@@ -170,7 +170,7 @@ else
 		param select-backup $PARAM_BACKUP_FILE
 	fi

-	if ver hwcmp PX4_FMU_V5X PX4_FMU_V6X ARK_FMU_V6X NXP_FMURT1062_V2
+	if ver hwcmp PX4_FMU_V5X PX4_FMU_V6X ARK_FMU_V6X PX4_FMU_V6XRT
 	then
 		netman update -i eth0
 	fi
@@ -0,0 +1,3 @@
+CONFIG_BOARD_TOOLCHAIN="arm-none-eabi"
+CONFIG_BOARD_ARCHITECTURE="cortex-m7"
+CONFIG_BOARD_ROMFSROOT=""
@@ -0,0 +1,87 @@
+CONFIG_BOARD_TOOLCHAIN="arm-none-eabi"
+CONFIG_BOARD_ARCHITECTURE="cortex-m7"
+CONFIG_BOARD_ETHERNET=y
+CONFIG_BOARD_SERIAL_GPS1="/dev/ttyS1"
+CONFIG_BOARD_SERIAL_GPS2="/dev/ttyS3"
+CONFIG_BOARD_SERIAL_TEL1="/dev/ttyS2"
+CONFIG_BOARD_SERIAL_TEL2="/dev/ttyS5"
+CONFIG_BOARD_SERIAL_TEL3="/dev/ttyS6"
+CONFIG_DRIVERS_ADC_BOARD_ADC=y
+CONFIG_DRIVERS_BAROMETER_BMP388=y
+CONFIG_DRIVERS_BAROMETER_MS5611=y
+CONFIG_DRIVERS_CAMERA_CAPTURE=y
+CONFIG_DRIVERS_CAMERA_TRIGGER=y
+CONFIG_DRIVERS_DISTANCE_SENSOR_LIGHTWARE_LASER_I2C=y
+CONFIG_DRIVERS_GPS=y
+CONFIG_DRIVERS_IMU_BOSCH_BMI088=y
+CONFIG_DRIVERS_IMU_INVENSENSE_ICM20602=y
+CONFIG_DRIVERS_IMU_INVENSENSE_ICM42688P=y
+CONFIG_COMMON_LIGHT=y
+CONFIG_DRIVERS_MAGNETOMETER_BOSCH_BMM150=y
+CONFIG_DRIVERS_MAGNETOMETER_HMC5883=y
+CONFIG_DRIVERS_MAGNETOMETER_ISENTEK_IST8310=y
+CONFIG_DRIVERS_POWER_MONITOR_INA226=y
+CONFIG_DRIVERS_POWER_MONITOR_INA228=y
+CONFIG_DRIVERS_POWER_MONITOR_INA238=y
+CONFIG_DRIVERS_PWM_OUT=y
+CONFIG_DRIVERS_PX4IO=y
+CONFIG_DRIVERS_RC_INPUT=y
+CONFIG_DRIVERS_SAFETY_BUTTON=y
+CONFIG_COMMON_TELEMETRY=y
+CONFIG_DRIVERS_TONE_ALARM=y
+CONFIG_DRIVERS_UAVCAN=y
+CONFIG_COMMON_UWB=y
+CONFIG_MODULES_BATTERY_STATUS=y
+CONFIG_MODULES_CAMERA_FEEDBACK=y
+CONFIG_MODULES_COMMANDER=y
+CONFIG_MODULES_CONTROL_ALLOCATOR=y
+CONFIG_MODULES_DATAMAN=y
+CONFIG_MODULES_EKF2=y
+CONFIG_MODULES_EVENTS=y
+CONFIG_MODULES_FLIGHT_MODE_MANAGER=y
+CONFIG_MODULES_GIMBAL=y
+CONFIG_MODULES_GYRO_CALIBRATION=y
+CONFIG_MODULES_GYRO_FFT=y
+CONFIG_MODULES_LAND_DETECTOR=y
+CONFIG_MODULES_LANDING_TARGET_ESTIMATOR=y
+CONFIG_MODULES_LOAD_MON=y
+CONFIG_MODULES_LOCAL_POSITION_ESTIMATOR=y
+CONFIG_MODULES_LOGGER=y
+CONFIG_MODULES_MAG_BIAS_ESTIMATOR=y
+CONFIG_MODULES_MANUAL_CONTROL=y
+CONFIG_MODULES_MAVLINK=y
+CONFIG_MODULES_MC_ATT_CONTROL=y
+CONFIG_MODULES_MC_AUTOTUNE_ATTITUDE_CONTROL=y
+CONFIG_MODULES_MC_HOVER_THRUST_ESTIMATOR=y
+CONFIG_MODULES_MC_POS_CONTROL=y
+CONFIG_MODULES_MC_RATE_CONTROL=y
+CONFIG_MODULES_NAVIGATOR=y
+CONFIG_MODULES_RC_UPDATE=y
+CONFIG_MODULES_ROVER_POS_CONTROL=y
+CONFIG_MODULES_SENSORS=y
+CONFIG_MODULES_TEMPERATURE_COMPENSATION=y
+CONFIG_SYSTEMCMDS_ACTUATOR_TEST=y
+CONFIG_SYSTEMCMDS_DMESG=y
+CONFIG_SYSTEMCMDS_DUMPFILE=y
+CONFIG_SYSTEMCMDS_HARDFAULT_LOG=y
+CONFIG_SYSTEMCMDS_I2CDETECT=y
+CONFIG_SYSTEMCMDS_IO_BYPASS_CONTROL=y
+CONFIG_SYSTEMCMDS_LED_CONTROL=y
+CONFIG_SYSTEMCMDS_MFT=y
+CONFIG_SYSTEMCMDS_MTD=y
+CONFIG_SYSTEMCMDS_NETMAN=y
+CONFIG_SYSTEMCMDS_NSHTERM=y
+CONFIG_SYSTEMCMDS_PARAM=y
+CONFIG_SYSTEMCMDS_PERF=y
+CONFIG_SYSTEMCMDS_REBOOT=y
+CONFIG_SYSTEMCMDS_SD_BENCH=y
+CONFIG_SYSTEMCMDS_SD_STRESS=y
+CONFIG_SYSTEMCMDS_SERIAL_TEST=y
+CONFIG_SYSTEMCMDS_SYSTEM_TIME=y
+CONFIG_SYSTEMCMDS_TOP=y
+CONFIG_SYSTEMCMDS_TOPIC_LISTENER=y
+CONFIG_SYSTEMCMDS_TUNE_CONTROL=y
+CONFIG_SYSTEMCMDS_UORB=y
+CONFIG_SYSTEMCMDS_USB_CONNECTED=y
+CONFIG_SYSTEMCMDS_VER=y
+CONFIG_SYSTEMCMDS_WORK_QUEUE=y
@@ -0,0 +1,13 @@
+{
+    "board_id": 35,
+    "magic": "PX4FWv1",
+    "description": "Firmware for the PX4FMUv6XRT board",
+    "image": "",
+    "build_time": 0,
+    "summary": "PX4FMUv6XRT",
+    "version": "0.1",
+    "image_size": 0,
+    "image_maxsize": 7340032,
+    "git_identity": "",
+    "board_revision": 0
+}
@@ -0,0 +1,28 @@
+#!/bin/sh
+#
+# board specific defaults
+#------------------------------------------------------------------------------
+
+# Mavlink ethernet (CFG 1000)
+param set-default MAV_2_CONFIG 1000
+param set-default MAV_2_BROADCAST 1
+param set-default MAV_2_MODE 0
+param set-default MAV_2_RADIO_CTL 0
+param set-default MAV_2_RATE 100000
+param set-default MAV_2_REMOTE_PRT 14550
+param set-default MAV_2_UDP_PRT 14550
+
+param set-default SENS_EN_INA238 0
+param set-default SENS_EN_INA228 0
+param set-default SENS_EN_INA226 1
+
+param set-default SYS_USE_IO 1
+
+safety_button start
+
+if param greater -s UAVCAN_ENABLE 0
+then
+	ifup can0
+	ifup can1
+	ifup can2
+fi
@@ -0,0 +1,7 @@
+#!/bin/sh
+#
+# board specific MAVLink startup script.
+#------------------------------------------------------------------------------
+
+# Start MAVLink on the UART connected to the mission computer
+mavlink start -d /dev/ttyS5 -b 3000000 -r 290000 -m onboard_low_bandwidth -x -z
@@ -0,0 +1,89 @@
+#!/bin/sh
+#
+# PX4 FMUv5 specific board sensors init
+#------------------------------------------------------------------------------
+#
+# UART mapping on PX4 FMU-V6XRT:
+#
+# LPUART1       /dev/ttyS0      CONSOLE
+# LPUART3       /dev/ttyS1      GPS
+# LPUART4       /dev/ttyS2      TELEM1
+# LPUART5       /dev/ttyS4      GPS2
+# LPUART6       /dev/ttyS5      PX4IO
+# LPUART8       /dev/ttyS6      TELEM2
+# LPUART10      /dev/ttyS7      TELEM3
+# LPUART11      /dev/ttyS8      EXT2
+#
+#------------------------------------------------------------------------------
+
+set HAVE_PM2 yes
+
+if ver hwtypecmp V5X005000 V5X005001 V5X005002
+then
+	set HAVE_PM2 no
+fi
+if param compare -s ADC_ADS1115_EN 1
+then
+	ads1115 start -X
+else
+	board_adc start
+fi
+
+
+if param compare SENS_EN_INA226 1
+then
+	# Start Digital power monitors
+	ina226 -X -b 1 -t 1 -k start
+
+	if [ $HAVE_PM2 = yes ]
+	then
+		ina226 -X -b 2 -t 2 -k start
+	fi
+fi
+
+if param compare SENS_EN_INA228 1
+then
+	# Start Digital power monitors
+	ina228 -X -b 1 -t 1 -k start
+	if [ $HAVE_PM2 = yes ]
+	then
+		ina228 -X -b 2 -t 2 -k start
+	fi
+fi
+
+if param compare SENS_EN_INA238 1
+then
+	# Start Digital power monitors
+	ina238 -X -b 1 -t 1 -k start
+	if [ $HAVE_PM2 = yes ]
+	then
+		ina238 -X -b 2 -t 2 -k start
+	fi
+fi
+
+# Internal SPI bus ICM42688p (hard-mounted)
+icm42688p -R 12 -b 1 -s start
+
+# Internal on IMU SPI BMI088
+bmi088 -A -R 4 -s start
+bmi088 -G -R 4 -s start
+
+# Internal on IMU SPI bus ICM42688p
+icm42688p -R 6 -b 2 -s start
+
+# Internal magnetometer on I2c
+bmm150 -I start
+
+
+# External compass on GPS1/I2C1 (the 3rd external bus): standard Holybro Pixhawk 4 or CUAV V5 GPS/compass puck (with lights, safety button, and buzzer)
+ist8310 -X -b 1 -R 10 start
+
+# Possible internal Baro
+
+# Disable startup of internal baros if param is set to false
+if param compare SENS_INT_BARO_EN 1
+then
+	bmp388 -I -b 3 -a 0x77 start
+	bmp388 -X -b 2 start
+fi
+unset HAVE_PM2
@@ -0,0 +1,59 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+choice
+	prompt "Boot Flash"
+	default PX4_FMU_V6XRT_V3_QSPI_FLASH
+
+config PX4_FMU_V6XRT_V3_HYPER_FLASH
+	bool "HYPER Flash"
+
+config PX4_FMU_V6XRT_V3_QSPI_FLASH
+	bool "QSPI Flash"
+
+endchoice # Boot Flash
+
+config BOARD_HAS_PROBES
+	bool "Board provides GPIO or other Hardware for signaling to timing analyze."
+	default y
+	---help---
+		This board provides GPIO FMU-CH1-8, as PROBE_1-8 to provide timing signals
+		from selected drivers.
+
+config BOARD_USE_PROBES
+	bool "Enable the use the board provided FMU-CH1-8 as PROBE_1-8"
+	default n
+	depends on BOARD_HAS_PROBES
+
+	---help---
+		Select to use GPIO FMU-CH1-8, as PROBE_1-8 to provide timing signals
+		from selected drivers.
+
+config BOARD_FORCE_ALIGNMENT
+	bool "Forces all acesses to be Aligned"
+	default n
+
+	---help---
+		Adds -mno-unaligned-access to build flags. to force alignment.
+		This can be needed if data is stored in a region of memory, that
+		is Strongly ordered and dcache is off.
+
+config BOARD_BOOTLOADER_INVALID_FCB
+	bool "Disables the FCB header"
+	default n
+
+	---help---
+		This can be used to keep the ROM bootloader in the serial Download mode.
+		Thus preventing bootlooping on `is_debug_pending` in the lame Rev B
+		silicon ROM bootloader. You can not cold boot (Power cycle) but can
+		Jtag from Load and be abel to reset it.
+
+config BOARD_BOOTLOADER_FIXUP
+	bool "Restores OCTAL Flash when No FCB"
+	default n
+	select ARCH_RAMFUNCS
+
+	---help---
+		Restores OCTAL Flash when FCB is invalid.
@@ -0,0 +1,111 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_DEV_CONSOLE is not set
+# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_SPI_EXCHANGE is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD_CUSTOM=y
+CONFIG_ARCH_BOARD_CUSTOM_DIR="../../../../boards/px4/fmu-v6xrt/nuttx-config"
+CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
+CONFIG_ARCH_BOARD_CUSTOM_NAME="px4"
+CONFIG_ARCH_CHIP="imxrt"
+CONFIG_ARCH_CHIP_IMXRT=y
+CONFIG_ARCH_CHIP_MIMXRT1176DVMAA=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_RAMVECTORS=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_ARMV7M_ITCM=y
+CONFIG_ARMV7M_MEMCPY=y
+CONFIG_ARMV7M_USEBASEPRI=y
+CONFIG_ARM_MPU=y
+CONFIG_BOARDCTL=y
+CONFIG_BOARDCTL_RESET=y
+CONFIG_BOARD_ASSERT_RESET_VALUE=0
+CONFIG_BOARD_BOOTLOADER_FIXUP=y
+CONFIG_BOARD_CRASHDUMP=y
+CONFIG_BOARD_FORCE_ALIGNMENT=y
+CONFIG_BOARD_INITTHREAD_PRIORITY=254
+CONFIG_BOARD_LATE_INITIALIZE=y
+CONFIG_BOARD_LOOPSPERMSEC=104926
+CONFIG_BOARD_RESET_ON_ASSERT=2
+CONFIG_CDCACM=y
+CONFIG_CDCACM_BULKIN_REQLEN=96
+CONFIG_CDCACM_IFLOWCONTROL=y
+CONFIG_CDCACM_PRODUCTID=0x001d
+CONFIG_CDCACM_PRODUCTSTR="PX4 BL FMU v6XRT.x"
+CONFIG_CDCACM_RXBUFSIZE=600
+CONFIG_CDCACM_TXBUFSIZE=12000
+CONFIG_CDCACM_VENDORID=0x3643
+CONFIG_CDCACM_VENDORSTR="Dronecode Project, Inc."
+CONFIG_DEBUG_ASSERTIONS=y
+CONFIG_DEBUG_ERROR=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_HARDFAULT_ALERT=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_TCBINFO=y
+CONFIG_DEBUG_USAGEFAULT=y
+CONFIG_DEFAULT_SMALL=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_FDCLONE_DISABLE=y
+CONFIG_FDCLONE_STDIO=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_IMXRT_EDMA=y
+CONFIG_IMXRT_EDMA_EDBG=y
+CONFIG_IMXRT_EDMA_ELINK=y
+CONFIG_IMXRT_EDMA_NTCD=64
+CONFIG_IMXRT_FLEXSPI2=y
+CONFIG_IMXRT_LPUART8=y
+CONFIG_IMXRT_SNVS_LPSRTC=y
+CONFIG_IMXRT_USBDEV=y
+CONFIG_INIT_ENTRYPOINT="bootloader_main"
+CONFIG_INIT_STACKSIZE=3194
+CONFIG_LIBC_FLOATINGPOINT=y
+CONFIG_LIBC_LONG_LONG=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_LPUART8_BAUD=57600
+CONFIG_LPUART8_IFLOWCONTROL=y
+CONFIG_LPUART8_OFLOWCONTROL=y
+CONFIG_LPUART8_RXBUFSIZE=600
+CONFIG_LPUART8_RXDMA=y
+CONFIG_LPUART8_TXBUFSIZE=1500
+CONFIG_LPUART8_TXDMA=y
+CONFIG_MEMSET_64BIT=y
+CONFIG_MEMSET_OPTSPEED=y
+CONFIG_PREALLOC_TIMERS=50
+CONFIG_PTHREAD_MUTEX_ROBUST=y
+CONFIG_PTHREAD_STACK_MIN=512
+CONFIG_RAM_SIZE=1835008
+CONFIG_RAM_START=0x20240000
+CONFIG_RAW_BINARY=y
+CONFIG_SERIAL_TERMIOS=y
+CONFIG_SIG_DEFAULT=y
+CONFIG_SIG_SIGALRM_ACTION=y
+CONFIG_SIG_SIGUSR1_ACTION=y
+CONFIG_SIG_SIGUSR2_ACTION=y
+CONFIG_SPI=y
+CONFIG_STACK_COLORATION=y
+CONFIG_START_DAY=30
+CONFIG_START_MONTH=11
+CONFIG_STDIO_BUFFER_SIZE=32
+CONFIG_SYSTEMTICK_HOOK=y
+CONFIG_SYSTEM_CDCACM=y
+CONFIG_TASK_NAME_SIZE=24
+CONFIG_USBDEV=y
+CONFIG_USBDEV_BUSPOWERED=y
+CONFIG_USBDEV_DMA=y
+CONFIG_USBDEV_DUALSPEED=y
+CONFIG_USBDEV_MAXPOWER=500
+CONFIG_USEC_PER_TICK=1000
@@ -0,0 +1,355 @@
+/************************************************************************************
+ * nuttx-configs/px4/fmu-v6xrt/include/board.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __NUTTX_CONFIG_PX4_FMU_V6XRT_INCLUDE_BOARD_H
+#define __NUTTX_CONFIG_PX4_FMU_V6XRT_INCLUDE_BOARD_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Clocking *************************************************************************/
+#define BOARD_CPU_FREQUENCY 996000000 //FIXME
+#define IMXRT_IPG_PODF_DIVIDER 5
+#define BOARD_GPT_FREQUENCY  24000000
+#define BOARD_XTAL_FREQUENCY 24000000
+
+/* SDIO *********************************************************************/
+
+/* Pin drive characteristics - drive strength in particular may need tuning
+ * for specific boards.
+ */
+
+#define PIN_USDHC1_D0     (GPIO_USDHC1_DATA0_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B1_02 */
+#define PIN_USDHC1_D1     (GPIO_USDHC1_DATA1_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B1_03 */
+#define PIN_USDHC1_D2     (GPIO_USDHC1_DATA2_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B1_04 */
+#define PIN_USDHC1_D3     (GPIO_USDHC1_DATA3_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B1_05 */
+#define PIN_USDHC1_DCLK   (GPIO_USDHC1_CLK_1   | IOMUX_USDHC1_CLK_DEFAULT)   /* GPIO_SD_B1_01 */
+#define PIN_USDHC1_CMD    (GPIO_USDHC1_CMD_1   | IOMUX_USDHC1_CMD_DEFAULT)   /* GPIO_SD_B1_00 */
+#define PIN_USDHC1_CD     (GPIO_USDHC1_CD_2    | IOMUX_USDHC1_CLK_DEFAULT)   /* GPIO_AD_32    */
+
+/* 386 KHz for initial inquiry stuff */
+
+#define BOARD_USDHC_IDMODE_PRESCALER    USDHC_SYSCTL_SDCLKFS_DIV256
+#define BOARD_USDHC_IDMODE_DIVISOR      USDHC_SYSCTL_DVS_DIV(2)
+
+/* 24.8MHz for other modes */
+
+#define BOARD_USDHC_MMCMODE_PRESCALER   USDHC_SYSCTL_SDCLKFS_DIV8
+#define BOARD_USDHC_MMCMODE_DIVISOR     USDHC_SYSCTL_DVS_DIV(1)
+
+#define BOARD_USDHC_SD1MODE_PRESCALER   USDHC_SYSCTL_SDCLKFS_DIV8
+#define BOARD_USDHC_SD1MODE_DIVISOR     USDHC_SYSCTL_DVS_DIV(1)
+
+#define BOARD_USDHC_SD4MODE_PRESCALER   USDHC_SYSCTL_SDCLKFS_DIV8
+#define BOARD_USDHC_SD4MODE_DIVISOR     USDHC_SYSCTL_DVS_DIV(1)
+
+/* LED definitions ******************************************************************/
+/* The px4 fmu-v6x board has numerous LEDs but only three, LED_GREEN a Green LED,
+ * LED_BLUE a Blue LED and LED_RED a Red LED, that can be controlled by software.
+ *
+ * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
+ * The following definitions are used to access individual LEDs.
+ */
+
+/* LED index values for use with board_userled() */
+
+#define BOARD_LED1        0
+#define BOARD_LED2        1
+#define BOARD_LED3        2
+#define BOARD_NLEDS       3
+
+#define BOARD_LED_RED     BOARD_LED1
+#define BOARD_LED_GREEN   BOARD_LED2
+#define BOARD_LED_BLUE    BOARD_LED3
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_LED1_BIT    (1 << BOARD_LED1)
+#define BOARD_LED2_BIT    (1 << BOARD_LED2)
+#define BOARD_LED3_BIT    (1 << BOARD_LED3)
+
+/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
+ * include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related
+ * events as follows:
+ *
+ *
+ *   SYMBOL                     Meaning                      LED state
+ *                                                        Red   Green Blue
+ *   ----------------------  --------------------------  ------ ------ ----*/
+
+#define LED_STARTED        0 /* NuttX has been started   OFF    OFF   OFF  */
+#define LED_HEAPALLOCATE   1 /* Heap has been allocated  OFF    OFF   ON   */
+#define LED_IRQSENABLED    2 /* Interrupts enabled       OFF    ON    OFF  */
+#define LED_STACKCREATED   3 /* Idle stack created       OFF    ON    ON   */
+#define LED_INIRQ          4 /* In an interrupt          N/C    N/C   GLOW */
+#define LED_SIGNAL         5 /* In a signal handler      N/C    GLOW  N/C  */
+#define LED_ASSERTION      6 /* An assertion failed      GLOW   N/C   GLOW */
+#define LED_PANIC          7 /* The system has crashed   Blink  OFF   N/C  */
+#define LED_IDLE           8 /* MCU is is sleep mode     ON     OFF   OFF  */
+
+/* Thus if the Green LED is statically on, NuttX has successfully booted and
+ * is, apparently, running normally.  If the Red LED is flashing at
+ * approximately 2Hz, then a fatal error has been detected and the system
+ * has halted.
+ */
+
+/* PIO Disambiguation ***************************************************************/
+/* LPUARTs
+ *
+ * We pull down CTS so that if nothing is connected, conde will not block.
+ */
+#define IOMUX_UART_CTS_DEFAULT              (IOMUX_PULL_DOWN | IOMUX_DRIVE_HIGHSTRENGTH | IOMUX_SLEW_SLOW)
+#define IOMUX_UART_BOARD_DEFAULT            (IOMUX_PULL_NONE | IOMUX_DRIVE_HIGHSTRENGTH | IOMUX_SLEW_FAST)
+
+/* Debug */
+
+#define GPIO_LPUART1_RX  (GPIO_LPUART1_RX_2|IOMUX_UART_DEFAULT|PADMUX_SION)       /* UART1_RX_DEBUG GPIO_DISP_B1_03 */
+#define GPIO_LPUART1_TX  (GPIO_LPUART1_TX_2|IOMUX_UART_BOARD_DEFAULT)            /* UART1_TX_DEBUG GPIO_DISP_B1_02 */
+
+/* GPS 1 */
+
+#define GPIO_LPUART3_RX  (GPIO_LPUART3_RX_1|IOMUX_UART_DEFAULT|PADMUX_SION)       /* UART3_RX_GPS1 GPIO_AD_31 */
+#define GPIO_LPUART3_TX  (GPIO_LPUART3_TX_1|IOMUX_UART_DEFAULT)                   /* UART3_TX_GPS1 GPIO_AD_30 */
+
+/* Telem 1 */
+
+#define GPIO_LPUART4_CTS (GPIO_LPUART4_CTS_1|IOMUX_UART_CTS_DEFAULT|PADMUX_SION) /* UART4_CTS_TELEM1 GPIO_DISP_B1_05 */
+#define GPIO_LPUART4_RTS (GPIO_PORT4 | GPIO_PIN28 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_UART_DEFAULT) /* UART4_RTS_TELEM1 GPIO_DISP_B1_07  GPIO4 Pin 28  */
+#define GPIO_LPUART4_RX  (GPIO_LPUART4_RX_1|IOMUX_UART_DEFAULT|PADMUX_SION)      /* UART4_RX_TELEM1 GPIO_DISP_B1_04 */
+#define GPIO_LPUART4_TX  (GPIO_LPUART4_TX_1|IOMUX_UART_BOARD_DEFAULT)           /* UART4_TX_TELEM1 GPIO_DISP_B1_06 */
+
+/* GPS 2 */
+
+#define GPIO_LPUART5_RX  (GPIO_LPUART5_RX_1|IOMUX_UART_DEFAULT|PADMUX_SION)     /* UART5_RX_GPS2 GPIO_AD_29 */
+#define GPIO_LPUART5_TX  (GPIO_LPUART5_TX_1|IOMUX_UART_DEFAULT)                 /* UART5_TX_GPS2 GPIO_AD_28 */
+
+/* PX4IO */
+
+#define GPIO_LPUART6_RX  (GPIO_LPUART6_RX_1|IOMUX_UART_DEFAULT|PADMUX_SION)     /* UART6_RX_FROM_IO__NC GPIO_EMC_B1_41 */
+#define GPIO_LPUART6_TX  (GPIO_LPUART6_TX_1|IOMUX_UART_DEFAULT)                 /* UART6_TX_TO_IO__RC_INPUT GPIO_EMC_B1_40 */
+
+/* Telem 2 */
+
+#define GPIO_LPUART8_CTS (GPIO_LPUART8_CTS_1|IOMUX_UART_CTS_DEFAULT|PADMUX_SION) /* UART8_CTS_TELEM2 GPIO_AD_04 */
+#define GPIO_LPUART8_RTS (GPIO_PORT3 | GPIO_PIN4 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_UART_DEFAULT) /* UART8_RTS_TELEM2 GPIO_AD_05 GPIO3 Pin 4 */
+#define GPIO_LPUART8_RX  (GPIO_LPUART8_RX_2|IOMUX_UART_DEFAULT|PADMUX_SION)      /* UART8_RX_TELEM2 GPIO_AD_03 */
+#define GPIO_LPUART8_TX  (GPIO_LPUART8_TX_2|IOMUX_UART_BOARD_DEFAULT)            /* UART8_TX_TELEM2 GPIO_AD_02 */
+
+/* Telem 3 */
+
+#define GPIO_LPUART10_CTS (GPIO_LPUART10_CTS_1|IOMUX_UART_CTS_DEFAULT|PADMUX_SION) /* UART10_CTS_TELEM3 GPIO_AD_34 */
+#define GPIO_LPUART10_RTS (GPIO_PORT4 | GPIO_PIN2 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_UART_DEFAULT) /* UART10_RTS_TELEM3 GPIO_AD_35 GPIO4 Pin 2 */
+#define GPIO_LPUART10_RX  (GPIO_LPUART10_RX_2|IOMUX_UART_DEFAULT|PADMUX_SION)      /* UART10_RX_TELEM3 GPIO_AD_33 */
+#define GPIO_LPUART10_TX  (GPIO_LPUART10_TX_1|IOMUX_UART_BOARD_DEFAULT)            /* UART10_TX_TELEM3 GPIO_AD_15 */
+
+/* Ext 2 */
+
+/* No DMA Support at this time for lack of DMA1, DMAMUX1 support */
+
+#define GPIO_LPUART11_RX  (GPIO_LPUART11_RX_2|IOMUX_UART_DEFAULT|PADMUX_SION) /* UART11_RX_EXTERNAL2 GPIO_LPSR_05 */
+#define GPIO_LPUART11_TX  (GPIO_LPUART11_TX_2|IOMUX_UART_DEFAULT)             /* UART11_TX_EXTERNAL2 GPIO_LPSR_04 */
+
+
+/* CAN
+ *
+ * CAN1 is routed to transceiver.
+ * CAN2 is routed to transceiver.
+ * CAN3 is routed to transceiver.
+ */
+
+#define FLEXCAN_IOMUX     (IOMUX_PULL_UP | IOMUX_SLEW_FAST)
+
+#define GPIO_FLEXCAN1_TX  (GPIO_FLEXCAN1_TX_1 | FLEXCAN_IOMUX) /* GPIO_AD_06 */
+#define GPIO_FLEXCAN1_RX  (GPIO_FLEXCAN1_RX_1 | FLEXCAN_IOMUX) /* GPIO_AD_07 */
+
+#define GPIO_FLEXCAN2_TX  (GPIO_FLEXCAN2_TX_1 | FLEXCAN_IOMUX) /* GPIO_AD_00 */
+#define GPIO_FLEXCAN2_RX  (GPIO_FLEXCAN2_RX_1 | FLEXCAN_IOMUX) /* GPIO_AD_01 */
+
+#define GPIO_FLEXCAN3_TX  (GPIO_FLEXCAN3_TX_1 | FLEXCAN_IOMUX) /* GPIO_LPSR_00 */
+#define GPIO_FLEXCAN3_RX  (GPIO_FLEXCAN3_RX_1 | FLEXCAN_IOMUX) /* GPIO_LPSR_01 */
+
+/* LPSPI */
+
+#define GPIO_LPSPI1_MISO  (GPIO_LPSPI1_SDI_2|IOMUX_LPSPI_DEFAULT) /* SPI1_MISO_SENSOR1 GPIO_EMC_B2_03 */
+#define GPIO_LPSPI1_MOSI  (GPIO_LPSPI1_SDO_2|IOMUX_LPSPI_DEFAULT) /* SPI1_MOSI_SENSOR1 GPIO_EMC_B2_02 */
+#define GPIO_LPSPI1_SCK   (GPIO_LPSPI1_SCK_2|IOMUX_LPSPI_DEFAULT) /* SPI1_SCK_SENSOR1 GPIO_EMC_B2_00 */
+
+#define GPIO_LPSPI2_MISO  (GPIO_LPSPI2_SDI_1|IOMUX_LPSPI_DEFAULT) /* SPI2_MISO_SENSOR2 GPIO_AD_27 */
+#define GPIO_LPSPI2_MOSI  (GPIO_LPSPI2_SDO_1|IOMUX_LPSPI_DEFAULT) /* SPI2_MOSI_SENSOR2 GPIO_AD_26 */
+#define GPIO_LPSPI2_SCK   (GPIO_LPSPI2_SCK_1|IOMUX_LPSPI_DEFAULT) /* SPI2_SCK_SENSOR2 GPIO_AD_24 */
+
+#define GPIO_LPSPI3_MISO  (GPIO_LPSPI3_SDI_1|IOMUX_LPSPI_DEFAULT) /* SPI3_MISO_SENSOR3 GPIO_EMC_B2_07 */
+#define GPIO_LPSPI3_MOSI  (GPIO_LPSPI3_SDO_1|IOMUX_LPSPI_DEFAULT) /* SPI3_MOSI_SENSOR3 GPIO_EMC_B2_06 */
+#define GPIO_LPSPI3_SCK   (GPIO_LPSPI3_SCK_1|IOMUX_LPSPI_DEFAULT) /* SPI3_SCK_SENSOR3 GPIO_EMC_B2_04 */
+
+/* SPI4 Not connected to anything */
+
+//#define GPIO_LPSPI4_MISO  (GPIO_LPSPI4_SDI_2|IOMUX_LPSPI_DEFAULT) /* SPI4_MISO_SENSOR4 GPIO_DISP_B2_13 */
+//#define GPIO_LPSPI4_MOSI  (GPIO_LPSPI4_SDO_2|IOMUX_LPSPI_DEFAULT) /* SPI4_MOSI_SENSOR4 GPIO_DISP_B2_14 */
+//#define GPIO_LPSPI4_SCK   (GPIO_LPSPI4_SCK_2|IOMUX_LPSPI_DEFAULT) /* SPI4_SCK_SENSOR4 GPIO_DISP_B2_12 */
+
+/* LPSPI6 No DMA Support at this time for lack of DMA1, DMAMUX1 support */
+
+
+#define GPIO_LPSPI6_MISO  (GPIO_LPSPI6_SDI_1|IOMUX_LPSPI_DEFAULT) /* SPI6_MISO_EXTERNAL1 GPIO_LPSR_12 */
+#define GPIO_LPSPI6_MOSI  (GPIO_LPSPI6_SDO_1|IOMUX_LPSPI_DEFAULT) /* SPI6_MOSI_EXTERNAL1 GPIO_LPSR_11 */
+#define GPIO_LPSPI6_SCK   (GPIO_LPSPI6_SCK_1|IOMUX_LPSPI_DEFAULT) /* SPI6_SCK_EXTERNAL1 GPIO_LPSR_10 */
+
+/* LPI2Cs */
+
+#define GPIO_LPI2C1_SCL_RESET  (GPIO_PORT3 | GPIO_PIN7 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) /* I2C1_SCL_GPS1 GPIO_AD_08 GPIO_GPIO3_IO07 */
+#define GPIO_LPI2C1_SDA_RESET  (GPIO_PORT3 | GPIO_PIN8 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) /* I2C1_SDA_GPS1 GPIO_AD_09 GPIO_GPIO3_IO08 */
+
+#define GPIO_LPI2C1_SCL        (GPIO_LPI2C1_SCL_2|IOMUX_LPI2C_DEFAULT) /* I2C1_SCL_GPS1 GPIO_AD_08 */
+#define GPIO_LPI2C1_SDA        (GPIO_LPI2C1_SDA_2|IOMUX_LPI2C_DEFAULT) /* I2C1_SDA_GPS1 GPIO_AD_09 */
+
+#define GPIO_LPI2C2_SCL_RESET  (GPIO_PORT3 | GPIO_PIN17 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) /* I2C2_SCL_GPS2 GPIO_AD_18 GPIO_GPIO3_IO17 */
+#define GPIO_LPI2C2_SDA_RESET  (GPIO_PORT3 | GPIO_PIN18 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) /* I2C2_SDA_GPS2 GPIO_AD_19 GPIO_GPIO3_IO18 */
+
+#define GPIO_LPI2C2_SCL        (GPIO_LPI2C2_SCL_2|IOMUX_LPI2C_DEFAULT) /* I2C2_SCL_GPS2 GPIO_AD_18 */
+#define GPIO_LPI2C2_SDA        (GPIO_LPI2C2_SDA_2|IOMUX_LPI2C_DEFAULT) /* I2C2_SDA_GPS2 GPIO_AD_19 */
+
+#define GPIO_LPI2C3_SCL_RESET  (GPIO_PORT5 | GPIO_PIN11 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) /* I2C3_SCL_FMU GPIO_DISP_B2_10 GPIO_GPIO5_IO11_1 */
+#define GPIO_LPI2C3_SDA_RESET  (GPIO_PORT5 | GPIO_PIN12 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) /* I2C3_SDA_FMU GPIO_DISP_B2_11 GPIO_GPIO5_IO12_1 */
+
+#define GPIO_LPI2C3_SCL        (GPIO_LPI2C3_SCL_2|IOMUX_LPI2C_DEFAULT) /* I2C3_SCL_FMU GPIO_DISP_B2_10 */
+#define GPIO_LPI2C3_SDA        (GPIO_LPI2C3_SDA_2|IOMUX_LPI2C_DEFAULT) /* I2C3_SDA_FMU GPIO_DISP_B2_11 */
+
+#define GPIO_LPI2C6_SCL_RESET  (GPIO_PORT6 | GPIO_PIN7 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) /* I2C6_SCL_EXTERNAL2 GPIO_LPSR_07 GPIO_GPIO6_IO07_1 */
+#define GPIO_LPI2C6_SDA_RESET  (GPIO_PORT6 | GPIO_PIN6 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) /* I2C6_SDA_EXTERNAL2 GPIO_LPSR_06 GPIO_GPIO6_IO06_1 */
+
+/* LPI2C6 No DMA Support at this time for lack of DMA1, DMAMUX1 support */
+
+#define GPIO_LPI2C6_SCL        (GPIO_LPI2C6_SCL_1|IOMUX_LPI2C_DEFAULT) /* I2C6_SCL_EXTERNAL2 GPIO_LPSR_07 */
+#define GPIO_LPI2C6_SDA        (GPIO_LPI2C6_SDA_1|IOMUX_LPI2C_DEFAULT) /* I2C6_SDA_EXTERNAL2 GPIO_LPSR_06 */
+
+/* ETH Disambiguation *******************************************************/
+
+// This is the ENET_1G interface.
+
+#if defined(CONFIG_ETH0_PHY_TJA1103)
+#  define BOARD_PHY_ADDR (18)
+#endif
+#if defined(CONFIG_ETH0_PHY_LAN8742A)
+#  define BOARD_PHY_ADDR (0)
+#endif
+
+#define GPIO_ENET2_TX_DATA00  (GPIO_ENET_1G_TX_DATA0_1|IOMUX_ENET_DATA_DEFAULT)  /* GPIO_DISP_B1_09 */
+#define GPIO_ENET2_TX_DATA01  (GPIO_ENET_1G_TX_DATA1_1|IOMUX_ENET_DATA_DEFAULT)  /* GPIO_DISP_B1_08 */
+#define GPIO_ENET2_RX_DATA00  (GPIO_ENET_1G_RX_DATA0_2|IOMUX_ENET_DATA_DEFAULT)  /* GPIO_EMC_B2_15  */
+#define GPIO_ENET2_RX_DATA01  (GPIO_ENET_1G_RX_DATA1_2|IOMUX_ENET_DATA_DEFAULT)  /* GPIO_EMC_B2_16  */
+#define GPIO_ENET2_MDIO       (GPIO_ENET_1G_MDIO_1|IOMUX_ENET_MDIO_DEFAULT)      /* GPIO_EMC_B2_20  */
+#define GPIO_ENET2_MDC        (GPIO_ENET_1G_MDC_1|IOMUX_ENET_MDC_DEFAULT)        /* GPIO_EMC_B2_19  */
+#define GPIO_ENET2_RX_EN      (GPIO_ENET_1G_RX_EN_1|IOMUX_ENET_EN_DEFAULT)       /* GPIO_DISP_B1_00 */
+#define GPIO_ENET2_RX_ER      (GPIO_ENET_RX_ER_1|IOMUX_ENET_RXERR_DEFAULT)       /* GPIO_DISP_B1_01 */
+#define GPIO_ENET2_TX_CLK     (GPIO_ENET_1G_REF_CLK_1|IOMUX_ENET_TX_CLK_DEFAULT) /* GPIO_DISP_B1_11 */
+#define GPIO_ENET2_TX_EN      (GPIO_ENET_1G_TX_EN_1|IOMUX_ENET_EN_DEFAULT)       /* GPIO_DISP_B1_10 */
+
+
+/* Board provides GPIO or other Hardware for signaling to timing analyzer */
+
+#if defined(CONFIG_BOARD_USE_PROBES)
+#include <imxrt_gpio.h>
+#include <imxrt_iomuxc.h>
+// add     -I<full path> build/px4_fmu-v6xrt_default/NuttX/nuttx/arch/arm/src/chip \ to NuttX Makedefs.in
+#define PROBE_IOMUX (IOMUX_SPEED_MAX | IOMUX_SLEW_FAST | IOMUX_DRIVE_33OHM  | IOMUX_CMOS_OUTPUT | IOMUX_PULL_NONE)
+# define PROBE_N(n) (1<<((n)-1))
+# define PROBE_1 /* GPIO_B0_06    */  (GPIO_PORT2 | GPIO_PIN6  | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX)
+# define PROBE_2 /* GPIO_EMC_08   */  (GPIO_PORT4 | GPIO_PIN8  | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX)
+# define PROBE_3 /* GPIO_EMC_10   */  (GPIO_PORT4 | GPIO_PIN10 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX)
+# define PROBE_4 /* GPIO_AD_B0_09 */  (GPIO_PORT1 | GPIO_PIN9  | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX)
+# define PROBE_5 /* GPIO_EMC_33   */  (GPIO_PORT3 | GPIO_PIN19 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX)
+# define PROBE_6 /* GPIO_EMC_30   */  (GPIO_PORT4 | GPIO_PIN30 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX)
+# define PROBE_7 /* GPIO_EMC_04   */  (GPIO_PORT4 | GPIO_PIN4  | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX)
+# define PROBE_8 /* GPIO_EMC_01   */  (GPIO_PORT4 | GPIO_PIN1  | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX)
+
+# define PROBE_INIT(mask) \
+	do { \
+		if ((mask)& PROBE_N(1)) { imxrt_config_gpio(PROBE_1); } \
+		if ((mask)& PROBE_N(2)) { imxrt_config_gpio(PROBE_2); } \
+		if ((mask)& PROBE_N(3)) { imxrt_config_gpio(PROBE_3); } \
+		if ((mask)& PROBE_N(4)) { imxrt_config_gpio(PROBE_4); } \
+		if ((mask)& PROBE_N(5)) { imxrt_config_gpio(PROBE_5); } \
+		if ((mask)& PROBE_N(6)) { imxrt_config_gpio(PROBE_6); } \
+		if ((mask)& PROBE_N(7)) { imxrt_config_gpio(PROBE_7); } \
+		if ((mask)& PROBE_N(8)) { imxrt_config_gpio(PROBE_8); } \
+	} while(0)
+
+# define PROBE(n,s)  do {imxrt_gpio_write(PROBE_##n,(s));}while(0)
+# define PROBE_MARK(n) PROBE(n,false);PROBE(n,true)
+#else
+# define PROBE_INIT(mask)
+# define PROBE(n,s)
+# define PROBE_MARK(n)
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __NUTTX_CONFIG_PX4_FMU_V6XRT_INCLUDE_BOARD_H */
@@ -0,0 +1,285 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NDEBUG is not set
+# CONFIG_NSH_DISABLE_MB is not set
+# CONFIG_NSH_DISABLE_MH is not set
+# CONFIG_NSH_DISABLE_MW is not set
+# CONFIG_SPI_CALLBACK is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD_CUSTOM=y
+CONFIG_ARCH_BOARD_CUSTOM_DIR="../../../../boards/px4/fmu-v6xrt/nuttx-config"
+CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
+CONFIG_ARCH_BOARD_CUSTOM_NAME="px4"
+CONFIG_ARCH_CHIP="imxrt"
+CONFIG_ARCH_CHIP_IMXRT=y
+CONFIG_ARCH_CHIP_MIMXRT1176DVMAA=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_RAMVECTORS=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_ARMV7M_ITCM=y
+CONFIG_ARMV7M_MEMCPY=y
+CONFIG_ARMV7M_USEBASEPRI=y
+CONFIG_ARM_MPU=y
+CONFIG_BOARDCTL_RESET=y
+CONFIG_BOARD_ASSERT_RESET_VALUE=0
+CONFIG_BOARD_BOOTLOADER_FIXUP=y
+CONFIG_BOARD_CRASHDUMP=y
+CONFIG_BOARD_CUSTOM_LEDS=y
+CONFIG_BOARD_FORCE_ALIGNMENT=y
+CONFIG_BOARD_LOOPSPERMSEC=104926
+CONFIG_BOARD_RESET_ON_ASSERT=2
+CONFIG_BUILTIN=y
+CONFIG_CDCACM=y
+CONFIG_CDCACM_BULKIN_REQLEN=96
+CONFIG_CDCACM_PRODUCTID=0x001d
+CONFIG_CDCACM_PRODUCTSTR="PX4 FMU v6XRT.x"
+CONFIG_CDCACM_RXBUFSIZE=600
+CONFIG_CDCACM_TXBUFSIZE=12000
+CONFIG_CDCACM_VENDORID=0x3643
+CONFIG_CDCACM_VENDORSTR="Dronecode Project, Inc."
+CONFIG_DEBUG_HARDFAULT_ALERT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_TCBINFO=y
+CONFIG_DEV_FIFO_SIZE=0
+CONFIG_DEV_PIPE_SIZE=70
+CONFIG_ETH0_PHY_LAN8742A=y
+CONFIG_FAT_DMAMEMORY=y
+CONFIG_FAT_LCNAMES=y
+CONFIG_FAT_LFN=y
+CONFIG_FAT_LFN_ALIAS_HASH=y
+CONFIG_FDCLONE_STDIO=y
+CONFIG_FSUTILS_IPCFG=y
+CONFIG_FS_BINFS=y
+CONFIG_FS_CROMFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FATTIME=y
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_MAX_TASKS=64
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_FS_ROMFS=y
+CONFIG_GRAN=y
+CONFIG_GRAN_INTR=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_I2C=y
+CONFIG_I2C_RESET=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_IMXRT_DTCM=0
+CONFIG_IMXRT_EDMA=y
+CONFIG_IMXRT_EDMA_EDBG=y
+CONFIG_IMXRT_EDMA_ELINK=y
+CONFIG_IMXRT_EDMA_NTCD=64
+CONFIG_IMXRT_ENET2=y
+CONFIG_IMXRT_ENET=y
+CONFIG_IMXRT_FLEXCAN1=y
+CONFIG_IMXRT_FLEXCAN2=y
+CONFIG_IMXRT_FLEXCAN3=y
+CONFIG_IMXRT_FLEXSPI2=y
+CONFIG_IMXRT_GPIO13_IRQ=y
+CONFIG_IMXRT_GPIO1_0_15_IRQ=y
+CONFIG_IMXRT_GPIO1_16_31_IRQ=y
+CONFIG_IMXRT_GPIO2_0_15_IRQ=y
+CONFIG_IMXRT_GPIO2_16_31_IRQ=y
+CONFIG_IMXRT_GPIO3_0_15_IRQ=y
+CONFIG_IMXRT_GPIO3_16_31_IRQ=y
+CONFIG_IMXRT_GPIO4_0_15_IRQ=y
+CONFIG_IMXRT_GPIO4_16_31_IRQ=y
+CONFIG_IMXRT_GPIO5_0_15_IRQ=y
+CONFIG_IMXRT_GPIO5_16_31_IRQ=y
+CONFIG_IMXRT_GPIO6_0_15_IRQ=y
+CONFIG_IMXRT_GPIO6_16_31_IRQ=y
+CONFIG_IMXRT_GPIO_IRQ=y
+CONFIG_IMXRT_INIT_FLEXRAM=y
+CONFIG_IMXRT_ITCM=0
+CONFIG_IMXRT_LPI2C1=y
+CONFIG_IMXRT_LPI2C2=y
+CONFIG_IMXRT_LPI2C3=y
+CONFIG_IMXRT_LPI2C6=y
+CONFIG_IMXRT_LPI2C_DMA=y
+CONFIG_IMXRT_LPI2C_DMA_MAXMSG=16
+CONFIG_IMXRT_LPI2C_DYNTIMEO=y
+CONFIG_IMXRT_LPI2C_DYNTIMEO_STARTSTOP=10
+CONFIG_IMXRT_LPSPI1=y
+CONFIG_IMXRT_LPSPI1_DMA=y
+CONFIG_IMXRT_LPSPI2=y
+CONFIG_IMXRT_LPSPI2_DMA=y
+CONFIG_IMXRT_LPSPI3=y
+CONFIG_IMXRT_LPSPI3_DMA=y
+CONFIG_IMXRT_LPSPI6=y
+CONFIG_IMXRT_LPSPI_DMA=y
+CONFIG_IMXRT_LPUART10=y
+CONFIG_IMXRT_LPUART11=y
+CONFIG_IMXRT_LPUART1=y
+CONFIG_IMXRT_LPUART3=y
+CONFIG_IMXRT_LPUART4=y
+CONFIG_IMXRT_LPUART5=y
+CONFIG_IMXRT_LPUART6=y
+CONFIG_IMXRT_LPUART8=y
+CONFIG_IMXRT_LPUART_INVERT=y
+CONFIG_IMXRT_LPUART_SINGLEWIRE=y
+CONFIG_IMXRT_PHY_POLLING=y
+CONFIG_IMXRT_PHY_PROVIDES_TXC=y
+CONFIG_IMXRT_SNVS_LPSRTC=y
+CONFIG_IMXRT_USBDEV=y
+CONFIG_IMXRT_USDHC1=y
+CONFIG_IMXRT_USDHC1_INVERT_CD=y
+CONFIG_IMXRT_USDHC1_WIDTH_D1_D4=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INIT_STACKSIZE=2944
+CONFIG_IOB_NBUFFERS=24
+CONFIG_IOB_THROTTLE=0
+CONFIG_IPCFG_BINARY=y
+CONFIG_IPCFG_CHARDEV=y
+CONFIG_IPCFG_PATH="/fs/mtd_net"
+CONFIG_LIBC_MAX_EXITFUNS=1
+CONFIG_LIBC_STRERROR=y
+CONFIG_LPI2C1_DMA=y
+CONFIG_LPI2C2_DMA=y
+CONFIG_LPI2C3_DMA=y
+CONFIG_LPUART10_IFLOWCONTROL=y
+CONFIG_LPUART10_OFLOWCONTROL=y
+CONFIG_LPUART10_RXBUFSIZE=600
+CONFIG_LPUART10_RXDMA=y
+CONFIG_LPUART10_TXBUFSIZE=3000
+CONFIG_LPUART10_TXDMA=y
+CONFIG_LPUART1_BAUD=57600
+CONFIG_LPUART1_SERIAL_CONSOLE=y
+CONFIG_LPUART3_BAUD=57600
+CONFIG_LPUART3_RXBUFSIZE=600
+CONFIG_LPUART3_RXDMA=y
+CONFIG_LPUART3_TXBUFSIZE=3000
+CONFIG_LPUART3_TXDMA=y
+CONFIG_LPUART4_BAUD=57600
+CONFIG_LPUART4_IFLOWCONTROL=y
+CONFIG_LPUART4_OFLOWCONTROL=y
+CONFIG_LPUART4_RXBUFSIZE=600
+CONFIG_LPUART4_RXDMA=y
+CONFIG_LPUART4_TXBUFSIZE=3000
+CONFIG_LPUART4_TXDMA=y
+CONFIG_LPUART5_BAUD=57600
+CONFIG_LPUART5_RXBUFSIZE=600
+CONFIG_LPUART5_RXDMA=y
+CONFIG_LPUART5_TXBUFSIZE=1500
+CONFIG_LPUART5_TXDMA=y
+CONFIG_LPUART6_BAUD=57600
+CONFIG_LPUART6_RXBUFSIZE=600
+CONFIG_LPUART6_RXDMA=y
+CONFIG_LPUART6_TXBUFSIZE=1500
+CONFIG_LPUART6_TXDMA=y
+CONFIG_LPUART8_BAUD=57600
+CONFIG_LPUART8_IFLOWCONTROL=y
+CONFIG_LPUART8_OFLOWCONTROL=y
+CONFIG_LPUART8_RXDMA=y
+CONFIG_LPUART8_TXBUFSIZE=10000
+CONFIG_LPUART8_TXDMA=y
+CONFIG_MEMSET_64BIT=y
+CONFIG_MEMSET_OPTSPEED=y
+CONFIG_MMCSD=y
+CONFIG_MMCSD_SDIO=y
+CONFIG_MTD=y
+CONFIG_MTD_BYTE_WRITE=y
+CONFIG_MTD_PARTITION=y
+CONFIG_MTD_RAMTRON=y
+CONFIG_NAME_MAX=40
+CONFIG_NET=y
+CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETDEV_CAN_BITRATE_IOCTL=y
+CONFIG_NETDEV_LATEINIT=y
+CONFIG_NETDEV_PHY_IOCTL=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETINIT_DNS=y
+CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
+CONFIG_NETINIT_DRIPADDR=0XC0A800FE
+CONFIG_NETINIT_MONITOR=y
+CONFIG_NETINIT_THREAD=y
+CONFIG_NETINIT_THREAD_PRIORITY=49
+CONFIG_NETUTILS_TELNETD=y
+CONFIG_NET_ARP_IPIN=y
+CONFIG_NET_ARP_SEND=y
+CONFIG_NET_BROADCAST=y
+CONFIG_NET_CAN=y
+CONFIG_NET_CAN_EXTID=y
+CONFIG_NET_CAN_NOTIFIER=y
+CONFIG_NET_CAN_RAW_TX_DEADLINE=y
+CONFIG_NET_CAN_SOCK_OPTS=y
+CONFIG_NET_ETH_PKTSIZE=1518
+CONFIG_NET_ICMP=y
+CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_SOLINGER=y
+CONFIG_NET_TCP=y
+CONFIG_NET_TCPBACKLOG=y
+CONFIG_NET_TCP_DELAYED_ACK=y
+CONFIG_NET_TCP_WRITE_BUFFERS=y
+CONFIG_NET_TIMESTAMP=y
+CONFIG_NET_UDP=y
+CONFIG_NET_UDP_CHECKSUMS=y
+CONFIG_NET_UDP_WRITE_BUFFERS=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_CROMFSETC=y
+CONFIG_NSH_LINELEN=128
+CONFIG_NSH_MAXARGUMENTS=15
+CONFIG_NSH_NESTDEPTH=8
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_ROMFSETC=y
+CONFIG_NSH_ROMFSSECTSIZE=128
+CONFIG_NSH_STRERROR=y
+CONFIG_NSH_TELNET_LOGIN=y
+CONFIG_NSH_VARS=y
+CONFIG_PIPES=y
+CONFIG_PREALLOC_TIMERS=50
+CONFIG_PRIORITY_INHERITANCE=y
+CONFIG_PTHREAD_STACK_MIN=512
+CONFIG_RAMTRON_SETSPEED=y
+CONFIG_RAM_SIZE=1835008
+CONFIG_RAM_START=0x20240000
+CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_RTC=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_HPWORKPRIORITY=249
+CONFIG_SCHED_HPWORKSTACKSIZE=1800
+CONFIG_SCHED_INSTRUMENTATION=y
+CONFIG_SCHED_INSTRUMENTATION_EXTERNAL=y
+CONFIG_SCHED_INSTRUMENTATION_SWITCH=y
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_LPWORKPRIORITY=50
+CONFIG_SCHED_LPWORKSTACKSIZE=1632
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDIO_BLOCKSETUP=y
+CONFIG_SEM_PREALLOCHOLDERS=32
+CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
+CONFIG_SERIAL_TERMIOS=y
+CONFIG_SIG_DEFAULT=y
+CONFIG_SIG_SIGALRM_ACTION=y
+CONFIG_SIG_SIGUSR1_ACTION=y
+CONFIG_SIG_SIGUSR2_ACTION=y
+CONFIG_SIG_SIGWORK=4
+CONFIG_STACK_COLORATION=y
+CONFIG_START_DAY=30
+CONFIG_START_MONTH=11
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_SYSTEM_CDCACM=y
+CONFIG_SYSTEM_CLE=y
+CONFIG_SYSTEM_DHCPC_RENEW=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_PING=y
+CONFIG_TASK_NAME_SIZE=24
+CONFIG_USBDEV=y
+CONFIG_USBDEV_BUSPOWERED=y
+CONFIG_USBDEV_DMA=y
+CONFIG_USBDEV_DUALSPEED=y
+CONFIG_USBDEV_MAXPOWER=500
+CONFIG_USEC_PER_TICK=1000
+CONFIG_WATCHDOG=y
@@ -0,0 +1,195 @@
+/****************************************************************************
+ * boards/px4/fmu-v6xrt/nuttx-config/scripts/bootloader_script.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Specify the memory areas */
+
+ /* Reallocate
+  * Final Configuration is
+  *    No DTCM
+  *    512k  OCRAM M7 (FlexRAM)          (2038:0000-203f:ffff)
+  *    128k  OCRAMM7 FlexRAM ECC         (2036:0000-2037:ffff)
+  *    64k   OCRAM2 ECC parity           (2035:0000-2035:ffff)
+  *    64k   OCRAM1 ECC parity           (2034:0000-2034:ffff)
+  *    512k  FlexRAM OCRAM2              (202C:0000-2033:ffff)
+  *    512k  FlexRAM OCRAM1              (2024:0000-202B:ffff)
+  *    256k  System  OCRAM M4            (2020:0000-2023:ffff)
+  */
+
+MEMORY
+{
+  flash (rx)  : ORIGIN = 0x30000000, LENGTH = 128K
+  sram  (rwx) : ORIGIN = 0x20240000, LENGTH = 2M-256k-512k
+  itcm  (rwx) : ORIGIN = 0x00000000, LENGTH = 256K   /* TODO FlexRAM partition */
+  dtcm  (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+EXTERN(g_flash_config)
+EXTERN(g_image_vector_table)
+EXTERN(g_boot_data)
+EXTERN(board_get_manifest)
+EXTERN(_bootdelay_signature)
+
+ENTRY(__start)
+
+SECTIONS
+{
+    /* Image Vector Table and Boot Data for booting from external flash */
+
+    .boot_hdr : ALIGN(4)
+    {
+        FILL(0xff)
+        . = 0x400 ;
+        __boot_hdr_start__ = ABSOLUTE(.) ;
+        KEEP(*(.boot_hdr.conf))
+        . = 0x1000 ;
+        KEEP(*(.boot_hdr.ivt))
+        . = 0x1020 ;
+        KEEP(*(.boot_hdr.boot_data))
+        . = 0x1030 ;
+        KEEP(*(.boot_hdr.dcd_data))
+        __boot_hdr_end__ = ABSOLUTE(.) ;
+        . = 0x2000 ;
+    } >flash
+
+    .vectors :
+    {
+        KEEP(*(.vectors))
+        *(.text .text.__start)
+    } >flash
+
+    .itcmfunc :
+    {
+        . = ALIGN(8);
+        _sitcmfuncs = ABSOLUTE(.);
+        FILL(0xFF)
+        . = 0x40 ;
+        . = ALIGN(8);
+        _eitcmfuncs = ABSOLUTE(.);
+    } > itcm AT > flash
+
+    _fitcmfuncs = LOADADDR(.itcmfunc);
+
+    /* The RAM vector table (if present) should lie at the beginning of SRAM */
+
+    .ram_vectors (COPY) : {
+        *(.ram_vectors)
+    } > dtcm
+
+    .text : ALIGN(4)
+    {
+        _stext = ABSOLUTE(.);
+        *(.vectors)
+		. = ALIGN(32);
+		/*
+		This signature provides the bootloader with a way to delay booting
+		*/
+		_bootdelay_signature = ABSOLUTE(.);
+		FILL(0xffecc2925d7d05c5)
+		. += 8;
+        *(.text .text.*)
+        *(.fixup)
+        *(.gnu.warning)
+        *(.gnu.linkonce.t.*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.got)
+        *(.gcc_except_table)
+        *(.gnu.linkonce.r.*)
+        . = ALIGN(4096);
+        _etext = ABSOLUTE(.);
+        _srodata = ABSOLUTE(.);
+        *(.rodata .rodata.*)
+        . = ALIGN(4096);
+        _erodata = ABSOLUTE(.);
+    } > flash
+
+    .init_section :
+    {
+        _sinit = ABSOLUTE(.);
+        KEEP(*(.init_array .init_array.*))
+        _einit = ABSOLUTE(.);
+    } > flash
+
+    .ARM.extab :
+    {
+        *(.ARM.extab*)
+    } > flash
+
+    .ARM.exidx :
+    {
+        __exidx_start = ABSOLUTE(.);
+        *(.ARM.exidx*)
+        __exidx_end = ABSOLUTE(.);
+    } > flash
+
+    _eronly = ABSOLUTE(.);
+
+    .data :
+    {
+        _sdata = ABSOLUTE(.);
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+        CONSTRUCTORS
+        . = ALIGN(4);
+        _edata = ABSOLUTE(.);
+    } > sram AT > flash
+
+    .ramfunc ALIGN(4):
+    {
+        _sramfuncs = ABSOLUTE(.);
+        *(.ramfunc  .ramfunc.*)
+        _eramfuncs = ABSOLUTE(.);
+    } > sram AT > flash
+
+    _framfuncs = LOADADDR(.ramfunc);
+
+    .bss :
+    {
+        _sbss = ABSOLUTE(.);
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = ABSOLUTE(.);
+    } > sram
+
+    /* Stabs debugging sections. */
+
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+    .debug_abbrev 0 : { *(.debug_abbrev) }
+    .debug_info 0 : { *(.debug_info) }
+    .debug_line 0 : { *(.debug_line) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    .debug_aranges 0 : { *(.debug_aranges) }
+
+    _boot_loadaddr = ORIGIN(flash);
+    _boot_size = LENGTH(flash);
+    _ram_size = LENGTH(sram);
+    _sdtcm = ORIGIN(dtcm);
+    _edtcm = ORIGIN(dtcm) + LENGTH(dtcm);
+}
@@ -0,0 +1,197 @@
+/****************************************************************************
+ * boards/px4/fmu-v6xrt/nuttx-config/scripts/script.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Specify the memory areas */
+
+ /* Reallocate
+  * Final Configuration is
+  *    No DTCM
+  *    512k  OCRAM M7 (FlexRAM)          (2038:0000-203f:ffff)
+  *    128k  OCRAMM7 FlexRAM ECC         (2036:0000-2037:ffff)
+  *    64k   OCRAM2 ECC parity           (2035:0000-2035:ffff)
+  *    64k   OCRAM1 ECC parity           (2034:0000-2034:ffff)
+  *    512k  FlexRAM OCRAM2              (202C:0000-2033:ffff)
+  *    512k  FlexRAM OCRAM1              (2024:0000-202B:ffff)
+  *    256k  System  OCRAM M4            (2020:0000-2023:ffff)
+  */
+
+MEMORY
+{
+  flash (rx)  : ORIGIN = 0x30020000, LENGTH = 4M-128K /* We have 64M but we do not want to wait to program it all */
+  sram  (rwx) : ORIGIN = 0x20240000, LENGTH = 2M-256k-512k
+  itcm  (rwx) : ORIGIN = 0x00000000, LENGTH = 256K   /* TODO FlexRAM partition */
+  dtcm  (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+EXTERN(g_flash_config)
+EXTERN(g_image_vector_table)
+EXTERN(g_boot_data)
+EXTERN(board_get_manifest)
+EXTERN(_bootdelay_signature)
+EXTERN(imxrt_flexspi_initialize)
+
+ENTRY(__start)
+
+SECTIONS
+{
+    /* Image Vector Table and Boot Data for booting from external flash */
+
+    .boot_hdr : ALIGN(4)
+    {
+        FILL(0xff)
+        . = 0x400 ;
+        __boot_hdr_start__ = ABSOLUTE(.) ;
+        KEEP(*(.boot_hdr.conf))
+        . = 0x1000 ;
+        KEEP(*(.boot_hdr.ivt))
+        . = 0x1020 ;
+        KEEP(*(.boot_hdr.boot_data))
+        . = 0x1030 ;
+        KEEP(*(.boot_hdr.dcd_data))
+        __boot_hdr_end__ = ABSOLUTE(.) ;
+        . = 0x2000 ;
+    } >flash
+
+    .vectors :
+    {
+        KEEP(*(.vectors))
+        *(.text .text.__start)
+    } >flash
+
+    .itcmfunc :
+    {
+        . = ALIGN(8);
+        _sitcmfuncs = ABSOLUTE(.);
+        FILL(0xFF)
+        . = 0x40 ;
+        INCLUDE "itcm_functions_includes.ld"
+        . = ALIGN(8);
+        _eitcmfuncs = ABSOLUTE(.);
+    } > itcm AT > flash
+
+    _fitcmfuncs = LOADADDR(.itcmfunc);
+
+    /* The RAM vector table (if present) should lie at the beginning of SRAM */
+
+    .ram_vectors (COPY) : {
+        *(.ram_vectors)
+    } > dtcm
+
+    .text : ALIGN(4)
+    {
+        _stext = ABSOLUTE(.);
+        *(.vectors)
+		. = ALIGN(32);
+		/*
+		This signature provides the bootloader with a way to delay booting
+		*/
+		_bootdelay_signature = ABSOLUTE(.);
+		FILL(0xffecc2925d7d05c5)
+		. += 8;
+        *(.text .text.*)
+        *(.fixup)
+        *(.gnu.warning)
+        *(.gnu.linkonce.t.*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.got)
+        *(.gcc_except_table)
+        *(.gnu.linkonce.r.*)
+        . = ALIGN(4096);
+        _etext = ABSOLUTE(.);
+        _srodata = ABSOLUTE(.);
+        *(.rodata .rodata.*)
+        . = ALIGN(4096);
+        _erodata = ABSOLUTE(.);
+    } > flash
+
+    .init_section :
+    {
+        _sinit = ABSOLUTE(.);
+        KEEP(*(.init_array .init_array.*))
+        _einit = ABSOLUTE(.);
+    } > flash
+
+    .ARM.extab :
+    {
+        *(.ARM.extab*)
+    } > flash
+
+    .ARM.exidx :
+    {
+        __exidx_start = ABSOLUTE(.);
+        *(.ARM.exidx*)
+        __exidx_end = ABSOLUTE(.);
+    } > flash
+
+    _eronly = ABSOLUTE(.);
+
+    .data :
+    {
+        _sdata = ABSOLUTE(.);
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+        CONSTRUCTORS
+        . = ALIGN(4);
+        _edata = ABSOLUTE(.);
+    } > sram AT > flash
+
+    .ramfunc ALIGN(4):
+    {
+        _sramfuncs = ABSOLUTE(.);
+        *(.ramfunc  .ramfunc.*)
+        _eramfuncs = ABSOLUTE(.);
+    } > sram AT > flash
+
+    _framfuncs = LOADADDR(.ramfunc);
+
+    .bss :
+    {
+        _sbss = ABSOLUTE(.);
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = ABSOLUTE(.);
+    } > sram
+
+    /* Stabs debugging sections. */
+
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+    .debug_abbrev 0 : { *(.debug_abbrev) }
+    .debug_info 0 : { *(.debug_info) }
+    .debug_line 0 : { *(.debug_line) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    .debug_aranges 0 : { *(.debug_aranges) }
+
+    _boot_loadaddr = ORIGIN(flash);
+    _boot_size = LENGTH(flash);
+    _ram_size = LENGTH(sram);
+    _sdtcm = ORIGIN(dtcm);
+    _edtcm = ORIGIN(dtcm) + LENGTH(dtcm);
+}
@@ -0,0 +1,92 @@
+############################################################################
+#
+#   Copyright (c) 2016, 2019, 2023 PX4 Development Team. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name PX4 nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+if("${PX4_BOARD_LABEL}" STREQUAL  "bootloader")
+	add_compile_definitions(BOOTLOADER)
+	add_library(drivers_board
+		bootloader_main.c
+		init.c
+		usb.c
+		imxrt_romapi.c
+		imxrt_flexspi_nor_boot.c
+		imxrt_flexspi_nor_flash.c
+		imxrt_clockconfig.c
+		timer_config.cpp
+	)
+	target_link_libraries(drivers_board
+		PRIVATE
+			nuttx_arch # sdio
+			nuttx_drivers # sdio
+			px4_layer #gpio
+			arch_io_pins # iotimer
+			bootloader
+	)
+	target_include_directories(drivers_board PRIVATE ${PX4_SOURCE_DIR}/platforms/nuttx/src/bootloader/common)
+
+else()
+	if(CONFIG_IMXRT1170_FLEXSPI_FRAM)
+	    list(APPEND SRCS
+			imxrt_flexspi_fram.c
+	    )
+	endif()
+
+	px4_add_library(drivers_board
+		autoleds.c
+		automount.c
+		#can.c
+		i2c.cpp
+		init.c
+		led.c
+		manifest.c
+		mtd.cpp
+		sdhc.c
+		spi.cpp
+		timer_config.cpp
+		usb.c
+		imxrt_romapi.c
+		imxrt_flexspi_fram.c
+		imxrt_flexspi_nor_boot.c
+		imxrt_flexspi_nor_flash.c
+		imxrt_clockconfig.c
+		${SRCS}
+	)
+
+	target_link_libraries(drivers_board
+		PRIVATE
+			arch_board_hw_info
+			arch_spi
+			drivers__led # drv_led_start
+			nuttx_arch # sdio
+			nuttx_drivers # sdio
+			px4_layer
+	)
+endif()
@@ -0,0 +1,191 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2016-2018 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/*
+ * This module shall be used during board bring up of Nuttx.
+ *
+ * The NXP FMUK66-V3 has a separate Red, Green and Blue LEDs driven by the K66
+ * as follows:
+ *
+ *   LED    K66
+ *   ------ -------------------------------------------------------
+ *   RED    FB_CS0_b/ UART2_CTS_b / ADC0_SE5b / SPI0_SCK / FTM3_CH1/ PTD1
+ *   GREEN  FTM2_FLT0/ CMP0_IN3/ FB_AD6 / I2S0_RX_BCLK/ FTM3_CH5/ ADC1_SE5b/ PTC9
+ *   BLUE   CMP0_IN2/ FB_AD7 / I2S0_MCLK/ FTM3_CH4/ ADC1_SE4b/ PTC8
+ *
+ * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
+ * the PX4 fmu-v6xrt.  The following definitions describe how NuttX controls
+ * the LEDs:
+ *
+ *   SYMBOL                Meaning                   LED state
+ *                                                   RED   GREEN  BLUE
+ *   -------------------  -----------------------    -----------------
+ *   LED_STARTED          NuttX has been started      OFF  OFF  OFF
+ *   LED_HEAPALLOCATE     Heap has been allocated     OFF  OFF  ON
+ *   LED_IRQSENABLED      Interrupts enabled          OFF  OFF  ON
+ *   LED_STACKCREATED     Idle stack created          OFF  ON   OFF
+ *   LED_INIRQ            In an interrupt            (no change)
+ *   LED_SIGNAL           In a signal handler        (no change)
+ *   LED_ASSERTION        An assertion failed        (no change)
+ *   LED_PANIC            The system has crashed      FLASH OFF OFF
+ *   LED_IDLE             fmu-v6xrt is in sleep mode (Optional, not used)
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <px4_platform_common/px4_config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "imxrt_gpio.h"
+#include "board_config.h"
+#ifdef CONFIG_ARCH_LEDS
+__BEGIN_DECLS
+extern void led_init(void);
+__END_DECLS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+bool nuttx_owns_leds = true;
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+	led_init();
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+void phy_set_led(int l, bool s)
+{
+
+}
+void board_autoled_on(int led)
+{
+	if (!nuttx_owns_leds) {
+		return;
+	}
+
+	switch (led) {
+	default:
+		break;
+
+	case LED_HEAPALLOCATE:
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_IRQSENABLED:
+		phy_set_led(BOARD_LED_BLUE, false);
+		phy_set_led(BOARD_LED_GREEN, true);
+		break;
+
+	case LED_STACKCREATED:
+		phy_set_led(BOARD_LED_GREEN, true);
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_INIRQ:
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_SIGNAL:
+		phy_set_led(BOARD_LED_GREEN, true);
+		break;
+
+	case LED_ASSERTION:
+		phy_set_led(BOARD_LED_RED, true);
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_PANIC:
+		phy_set_led(BOARD_LED_RED, true);
+		break;
+
+	case LED_IDLE : /* IDLE */
+		phy_set_led(BOARD_LED_RED, true);
+		break;
+	}
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+	if (!nuttx_owns_leds) {
+		return;
+	}
+
+	switch (led) {
+	default:
+		break;
+
+	case LED_SIGNAL:
+		phy_set_led(BOARD_LED_GREEN, false);
+		break;
+
+	case LED_INIRQ:
+		phy_set_led(BOARD_LED_BLUE, false);
+		break;
+
+	case LED_ASSERTION:
+		phy_set_led(BOARD_LED_RED, false);
+		phy_set_led(BOARD_LED_BLUE, false);
+		break;
+
+	case LED_PANIC:
+		phy_set_led(BOARD_LED_RED, false);
+		break;
+
+	case LED_IDLE : /* IDLE */
+		phy_set_led(BOARD_LED_RED, false);
+		break;
+	}
+}
+
+#endif /* CONFIG_ARCH_LEDS */
@@ -0,0 +1,304 @@
+/************************************************************************************
+ *
+ *   Copyright (C) 2016-2018 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <px4_platform_common/px4_config.h>
+
+#if defined(CONFIG_FS_AUTOMOUNTER_DEBUG) && !defined(CONFIG_DEBUG_FS)
+#  define CONFIG_DEBUG_FS 1
+#endif
+
+#include <debug.h>
+#include <stddef.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/clock.h>
+#include <nuttx/fs/automount.h>
+
+#include "board_config.h"
+#ifdef HAVE_AUTOMOUNTER
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+/* This structure represents the changeable state of the automounter */
+
+struct fmuk66_automount_state_s {
+	volatile automount_handler_t handler;    /* Upper half handler */
+	FAR void *arg;                           /* Handler argument */
+	bool enable;                             /* Fake interrupt enable */
+	bool pending;                            /* Set if there an event while disabled */
+};
+
+/* This structure represents the static configuration of an automounter */
+
+struct fmuk66_automount_config_s {
+	/* This must be first thing in structure so that we can simply cast from struct
+	 * automount_lower_s to struct fmuk66_automount_config_s
+	 */
+
+	struct automount_lower_s lower;          /* Publicly visible part */
+	FAR struct fmuk66_automount_state_s *state; /* Changeable state */
+};
+
+/************************************************************************************
+ * Private Function Prototypes
+ ************************************************************************************/
+
+static int  fmuk66_attach(FAR const struct automount_lower_s *lower, automount_handler_t isr, FAR void *arg);
+static void fmuk66_enable(FAR const struct automount_lower_s *lower, bool enable);
+static bool fmuk66_inserted(FAR const struct automount_lower_s *lower);
+
+/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+static struct fmuk66_automount_state_s g_sdhc_state;
+static const struct fmuk66_automount_config_s g_sdhc_config = {
+	.lower        =
+	{
+		.fstype     = CONFIG_FMUK66_SDHC_AUTOMOUNT_FSTYPE,
+		.blockdev   = CONFIG_FMUK66_SDHC_AUTOMOUNT_BLKDEV,
+		.mountpoint = CONFIG_FMUK66_SDHC_AUTOMOUNT_MOUNTPOINT,
+		.ddelay     = MSEC2TICK(CONFIG_FMUK66_SDHC_AUTOMOUNT_DDELAY),
+		.udelay     = MSEC2TICK(CONFIG_FMUK66_SDHC_AUTOMOUNT_UDELAY),
+		.attach     = fmuk66_attach,
+		.enable     = fmuk66_enable,
+		.inserted   = fmuk66_inserted
+	},
+	.state        = &g_sdhc_state
+};
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name:  fmuk66_attach
+ *
+ * Description:
+ *   Attach a new SDHC event handler
+ *
+ * Input Parameters:
+ *   lower - An instance of the auto-mounter lower half state structure
+ *   isr   - The new event handler to be attach
+ *   arg   - Client data to be provided when the event handler is invoked.
+ *
+ *  Returned Value:
+ *    Always returns OK
+ *
+ ************************************************************************************/
+
+static int fmuk66_attach(FAR const struct automount_lower_s *lower, automount_handler_t isr, FAR void *arg)
+{
+	FAR const struct fmuk66_automount_config_s *config;
+	FAR struct fmuk66_automount_state_s *state;
+
+	/* Recover references to our structure */
+
+	config = (FAR struct fmuk66_automount_config_s *)lower;
+	DEBUGASSERT(config != NULL && config->state != NULL);
+
+	state = config->state;
+
+	/* Save the new handler info (clearing the handler first to eliminate race
+	 * conditions).
+	 */
+
+	state->handler = NULL;
+	state->pending = false;
+	state->arg     = arg;
+	state->handler = isr;
+	return OK;
+}
+
+/************************************************************************************
+ * Name:  fmuk66_enable
+ *
+ * Description:
+ *   Enable card insertion/removal event detection
+ *
+ * Input Parameters:
+ *   lower - An instance of the auto-mounter lower half state structure
+ *   enable - True: enable event detection; False: disable
+ *
+ *  Returned Value:
+ *    None
+ *
+ ************************************************************************************/
+
+static void fmuk66_enable(FAR const struct automount_lower_s *lower, bool enable)
+{
+	FAR const struct fmuk66_automount_config_s *config;
+	FAR struct fmuk66_automount_state_s *state;
+	irqstate_t flags;
+
+	/* Recover references to our structure */
+
+	config = (FAR struct fmuk66_automount_config_s *)lower;
+	DEBUGASSERT(config != NULL && config->state != NULL);
+
+	state = config->state;
+
+	/* Save the fake enable setting */
+
+	flags = enter_critical_section();
+	state->enable = enable;
+
+	/* Did an interrupt occur while interrupts were disabled? */
+
+	if (enable && state->pending) {
+		/* Yes.. perform the fake interrupt if the interrutp is attached */
+
+		if (state->handler) {
+			bool inserted = fmuk66_cardinserted();
+			(void)state->handler(&config->lower, state->arg, inserted);
+		}
+
+		state->pending = false;
+	}
+
+	leave_critical_section(flags);
+}
+
+/************************************************************************************
+ * Name: fmuk66_inserted
+ *
+ * Description:
+ *   Check if a card is inserted into the slot.
+ *
+ * Input Parameters:
+ *   lower - An instance of the auto-mounter lower half state structure
+ *
+ *  Returned Value:
+ *    True if the card is inserted; False otherwise
+ *
+ ************************************************************************************/
+
+static bool fmuk66_inserted(FAR const struct automount_lower_s *lower)
+{
+	return fmuk66_cardinserted();
+}
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name:  fmuk66_automount_initialize
+ *
+ * Description:
+ *   Configure auto-mounters for each enable and so configured SDHC
+ *
+ * Input Parameters:
+ *   None
+ *
+ *  Returned Value:
+ *    None
+ *
+ ************************************************************************************/
+
+void fmuk66_automount_initialize(void)
+{
+	FAR void *handle;
+
+	finfo("Initializing automounter(s)\n");
+
+	/* Initialize the SDHC0 auto-mounter */
+
+	handle = automount_initialize(&g_sdhc_config.lower);
+
+	if (!handle) {
+		ferr("ERROR: Failed to initialize auto-mounter for SDHC0\n");
+	}
+}
+
+/************************************************************************************
+ * Name:  fmuk66_automount_event
+ *
+ * Description:
+ *   The SDHC card detection logic has detected an insertion or removal event.  It
+ *   has already scheduled the MMC/SD block driver operations.  Now we need to
+ *   schedule the auto-mount event which will occur with a substantial delay to make
+ *   sure that everything has settle down.
+ *
+ * Input Parameters:
+ *   slotno - Identifies the SDHC0 slot: SDHC0_SLOTNO or SDHC1_SLOTNO.  There is a
+ *      terminology problem here:  Each SDHC supports two slots, slot A and slot B.
+ *      Only slot A is used.  So this is not a really a slot, but an HSCMI peripheral
+ *      number.
+ *   inserted - True if the card is inserted in the slot.  False otherwise.
+ *
+ *  Returned Value:
+ *    None
+ *
+ *  Assumptions:
+ *    Interrupts are disabled.
+ *
+ ************************************************************************************/
+
+void fmuk66_automount_event(bool inserted)
+{
+	FAR const struct fmuk66_automount_config_s *config = &g_sdhc_config;
+	FAR struct fmuk66_automount_state_s *state = &g_sdhc_state;
+
+	/* Is the auto-mounter interrupt attached? */
+
+	if (state->handler) {
+		/* Yes.. Have we been asked to hold off interrupts? */
+
+		if (!state->enable) {
+			/* Yes.. just remember the there is a pending interrupt. We will
+			 * deliver the interrupt when interrupts are "re-enabled."
+			 */
+
+			state->pending = true;
+
+		} else {
+			/* No.. forward the event to the handler */
+
+			(void)state->handler(&config->lower, state->arg, inserted);
+		}
+	}
+}
+
+#endif /* HAVE_AUTOMOUNTER */
@@ -0,0 +1,61 @@
+/****************************************************************************
+ *
+ *   Copyright (c) 2023 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file bootloader_main.c
+ *
+ * FMU-specific early startup code for bootloader
+*/
+
+#include "board_config.h"
+#include "bl.h"
+
+#include <nuttx/config.h>
+#include <nuttx/board.h>
+#include <chip.h>
+#include <arch/board/board.h>
+#include "arm_internal.h"
+#include <px4_platform_common/init.h>
+
+extern int sercon_main(int c, char **argv);
+
+void board_late_initialize(void)
+{
+	sercon_main(0, NULL);
+}
+
+extern void sys_tick_handler(void);
+void board_timerhook(void)
+{
+	sys_tick_handler();
+}
@@ -0,0 +1,129 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2016, 2018 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file can.c
+ *
+ * Board-specific CAN functions.
+ */
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <px4_platform_common/px4_config.h>
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/can/can.h>
+#include <arch/board/board.h>
+
+#include <chip.h>
+#include "arm_internal.h"
+
+#include "board_config.h"
+
+#ifdef CONFIG_CAN
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+
+#if defined(CONFIG_IMXRT_FLEXCAN1) && defined(CONFIG_IMXRT_FLEXCAN2) \
+  && defined(CONFIG_IMXRT_FLEXCAN3)
+#  warning "CAN1 and CAN2 and CAN2 are enabled.  Assuming only CAN1."
+#endif
+
+#ifdef CONFIG_IMXRT_FLEXCAN1
+#  define CAN_PORT 1
+#else
+#  define CAN_PORT 2
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+int can_devinit(void);
+
+/************************************************************************************
+ * Name: can_devinit
+ *
+ * Description:
+ *   All architectures must provide the following interface to work with
+ *   examples/can.
+ *
+ ************************************************************************************/
+
+int can_devinit(void)
+{
+	static bool initialized = false;
+	struct can_dev_s *can;
+	int ret;
+
+	/* Check if we have already initialized */
+
+	if (!initialized) {
+
+		/* Call imxrt_caninitialize() to get an instance of the CAN interface */
+
+		can = imxrt_can_initialize(CAN_PORT);
+
+		if (can == NULL) {
+			canerr("ERROR:  Failed to get CAN interface\n");
+			return -ENODEV;
+		}
+
+		/* Register the CAN driver at "/dev/can0" */
+
+		ret = can_register("/dev/can0", can);
+
+		if (ret < 0) {
+			canerr("ERROR: can_register failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Now we are initialized */
+
+		initialized = true;
+	}
+
+	return OK;
+}
+
+#endif
@@ -0,0 +1,130 @@
+/*
+ * hw_config.h
+ *
+ *  Created on: May 17, 2015
+ *      Author: david_s5
+ */
+
+#ifndef HW_CONFIG_H_
+#define HW_CONFIG_H_
+
+/****************************************************************************
+ * 10-8--2016:
+ *  To simplify the ripple effect on the tools, we will be using
+ *  /dev/serial/by-id/<asterisk>PX4<asterisk> to locate PX4 devices. Therefore
+ *  moving forward all Bootloaders must contain the prefix "PX4 BL "
+ *  in the USBDEVICESTRING
+ *  This Change will be made in an upcoming BL release
+ ****************************************************************************/
+/*
+ * Define usage to configure a bootloader
+ *
+ *
+ * Constant                example          Usage
+ * APP_LOAD_ADDRESS     0x08004000            - The address in Linker Script, where the app fw is org-ed
+ * BOOTLOADER_DELAY     5000                  - Ms to wait while under USB pwr or bootloader request
+ * BOARD_FMUV2
+ * INTERFACE_USB        1                     - (Optional) Scan and use the USB interface for bootloading
+ * INTERFACE_USART      1                     - (Optional) Scan and use the Serial interface for bootloading
+ * USBDEVICESTRING      "PX4 BL FMU v2.x"     - USB id string
+ * USBPRODUCTID         0x0011                - PID Should match defconfig
+ * BOOT_DELAY_ADDRESS   0x000001a0            - (Optional) From the linker script from Linker Script to get a custom
+ *                                               delay provided by an APP FW
+ * BOARD_TYPE           9                     - Must match .prototype boad_id
+ * _FLASH_KBYTES        (*(uint16_t *)0x1fff7a22) - Run time flash size detection
+ * BOARD_FLASH_SECTORS  ((_FLASH_KBYTES == 0x400) ? 11 : 23) - Run time determine the physical last sector
+ * BOARD_FLASH_SECTORS   11                   - Hard coded zero based last sector
+ * BOARD_FLASH_SIZE     (_FLASH_KBYTES*1024)-   Total Flash size of device, determined at run time.
+ *                         (1024 * 1024)      - Hard coded Total Flash of device - The bootloader and app reserved will be deducted
+ *                                              programmatically
+ *
+ * BOARD_FIRST_FLASH_SECTOR_TO_ERASE  2        - Optional sectors index in the flash_sectors table  (F4 only), to begin erasing.
+ *                                               This is to allow sectors to be reserved for app fw usage. That will NOT be erased
+ *                                               during a FW upgrade.
+ *                                               The default is 0, and selects the first sector to be erased, as the 0th entry in the
+ *                                               flash_sectors table. Which is the second physical sector of FLASH in the device.
+ *                                               The first physical sector of FLASH is used by the bootloader, and is not defined
+ *                                               in the table.
+ *
+ * APP_RESERVATION_SIZE (BOARD_FIRST_FLASH_SECTOR_TO_ERASE * 16 * 1024) - Number of bytes reserved by the APP FW. This number plus
+ *                                                                        BOOTLOADER_RESERVATION_SIZE  will be deducted from
+ *                                                                        BOARD_FLASH_SIZE to determine the size of the App FW
+ *                                                                        and hence the address space of FLASH to erase and program.
+ * USBMFGSTRING            "PX4 AP"            - Optional USB MFG string (default is '3D Robotics' if not defined.)
+ * SERIAL_BREAK_DETECT_DISABLED                -  Optional prevent break selection on Serial port from entering or staying in BL
+ *
+ * * Other defines are somewhat self explanatory.
+ */
+
+/* Boot device selection list*/
+#define USB0_DEV       0x01
+#define SERIAL0_DEV    0x02
+#define SERIAL1_DEV    0x04
+
+#define APP_LOAD_ADDRESS               0x30020000
+#define APP_VECTOR_OFFSET              0x2000
+#define BOOTLOADER_DELAY               5000
+#define INTERFACE_USB                  1
+#define INTERFACE_USB_CONFIG           "/dev/ttyACM0"
+
+//#define USE_VBUS_PULL_DOWN
+#define INTERFACE_USART                1
+#define INTERFACE_USART_CONFIG         "/dev/ttyS0,1500000"
+#define BOOT_DELAY_ADDRESS             0x3003b540
+#define BOARD_TYPE                     35
+// The board has a 64 Mb part with 16384, 4K secors, but we artificialy limit it to 4 Mb
+// as 1024, 4K sectors
+#define BOARD_FLASH_SECTORS            1024 // Really (16384)
+#define BOARD_FIRST_FLASH_SECTOR_TO_ERASE 32 // We resreve 128K for the bootloader
+#define BOARD_FLASH_SIZE               (4 * 1024 * 1024)
+
+#define OSC_FREQ                       24
+
+#define BOARD_PIN_LED_ACTIVITY         GPIO_nLED_BLUE // BLUE
+#define BOARD_PIN_LED_BOOTLOADER       GPIO_nLED_GREEN // GREEN
+#define BOARD_LED_ON                   0
+#define BOARD_LED_OFF                  1
+
+#define SERIAL_BREAK_DETECT_DISABLED   1
+
+/*
+ * Uncommenting this allows to force the bootloader through
+ * a PWM output pin. As this can accidentally initialize
+ * an ESC prematurely, it is not recommended. This feature
+ * has not been used and hence defaults now to off.
+ *
+ * # define BOARD_FORCE_BL_PIN_OUT         (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN14)
+ * # define BOARD_FORCE_BL_PIN_IN          (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN11)
+ *
+ * # define BOARD_POWER_PIN_OUT           (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4)
+ * # define BOARD_POWER_ON                 1
+ * # define BOARD_POWER_OFF                0
+ * # undef  BOARD_POWER_PIN_RELEASE        // Leave pin enabling Power - un comment to release (disable power)
+ *
+*/
+
+#if !defined(ARCH_SN_MAX_LENGTH)
+# define ARCH_SN_MAX_LENGTH 12
+#endif
+
+#if !defined(APP_RESERVATION_SIZE)
+#  define APP_RESERVATION_SIZE 0
+#endif
+
+#if !defined(BOARD_FIRST_FLASH_SECTOR_TO_ERASE)
+#  define BOARD_FIRST_FLASH_SECTOR_TO_ERASE 1
+#endif
+
+#if !defined(USB_DATA_ALIGN)
+# define USB_DATA_ALIGN
+#endif
+
+#ifndef BOOT_DEVICES_SELECTION
+#  define BOOT_DEVICES_SELECTION USB0_DEV|SERIAL0_DEV|SERIAL1_DEV
+#endif
+
+#ifndef BOOT_DEVICES_FILTER_ONUSB
+#  define BOOT_DEVICES_FILTER_ONUSB USB0_DEV|SERIAL0_DEV|SERIAL1_DEV
+#endif
+
+#endif /* HW_CONFIG_H_ */
@@ -0,0 +1,43 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2020 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#include <px4_arch/i2c_hw_description.h>
+
+#if defined(CONFIG_I2C)
+constexpr px4_i2c_bus_t px4_i2c_buses[I2C_BUS_MAX_BUS_ITEMS] = {
+	initI2CBusExternal(1),
+	initI2CBusExternal(2),
+	initI2CBusInternal(3),
+	initI2CBusExternal(6),
+};
+#endif
@@ -0,0 +1,49 @@
+/****************************************************************************
+ * boards/px4/fmu-v6xrt/src/imxrt_flexspi_nor_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "imxrt_flexspi_nor_boot.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+locate_data(".boot_hdr.ivt")
+const struct ivt_s g_image_vector_table = {
+	IVT_HEADER,                         /* IVT Header */
+	IMAGE_ENTRY_ADDRESS,                /* Image  Entry Function */
+	IVT_RSVD,                           /* Reserved = 0 */
+	(uint32_t)DCD_ADDRESS,              /* Address where DCD information is stored */
+	(uint32_t)BOOT_DATA_ADDRESS,        /* Address where BOOT Data Structure is stored */
+	(uint32_t)IMAG_VECTOR_TABLE,        /* Pointer to IVT Self (absolute address */
+	(uint32_t)CSF_ADDRESS,              /* Address where CSF file is stored */
+	IVT_RSVD                            /* Reserved = 0 */
+};
+
+locate_data(".boot_hdr.boot_data")
+const struct boot_data_s g_boot_data = {
+	IMAGE_DEST,                         /* boot start location */
+	(IMAGE_DEST_END - IMAGE_DEST),      /* size */
+	PLUGIN_FLAG,                        /* Plugin flag */
+	0xffffffff                          /* empty - extra data word */
+};
@@ -0,0 +1,158 @@
+/****************************************************************************
+ * boards/px4/fmu-v6xrt/src/imxrt_flexspi_nor_boot.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_PX4_FMU_V6XRT_SRC_IMXRT_FLEXSPI_NOR_BOOT_H
+#define __BOARDS_PX4_FMU_V6XRT_SRC_IMXRT_FLEXSPI_NOR_BOOT_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IVT Data */
+
+#define IVT_MAJOR_VERSION           0x4
+#define IVT_MAJOR_VERSION_SHIFT     0x4
+#define IVT_MAJOR_VERSION_MASK      0xf
+#define IVT_MINOR_VERSION           0x1
+#define IVT_MINOR_VERSION_SHIFT     0x0
+#define IVT_MINOR_VERSION_MASK      0xf
+
+#define IVT_VERSION(major, minor)   \
+	((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) |  \
+	 (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
+
+#define IVT_TAG_HEADER              (0xd1)       /* Image Vector Table */
+#define IVT_SIZE                    0x2000
+#define IVT_PAR                     IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
+
+#define IVT_HEADER                  (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
+#define IVT_RSVD                    (uint32_t)(0x00000000)
+
+/* DCD Data */
+
+#define DCD_TAG_HEADER              (0xd2)
+#define DCD_TAG_HEADER_SHIFT        (24)
+#define DCD_VERSION                 (0x40)
+#define DCD_ARRAY_SIZE              1
+
+#define FLASH_BASE                  0x30000000
+#define FLASH_END                   FLASH_BASE + (3 * (1024*1024)) // We have 64M but we do not want to wait to program it all
+
+/* This needs to take into account  the memory configuration at boot bootloader */
+
+#define ROM_BOOTLOADER_OCRAM_RES    0x8000
+#define OCRAM_BASE                  (0x20200000 + ROM_BOOTLOADER_OCRAM_RES)
+#define OCRAM_END                   (OCRAM_BASE + (512 * 1024) + (256 * 1024) - ROM_BOOTLOADER_OCRAM_RES)
+
+
+#define SCLK 1
+#if defined(CONFIG_BOOT_RUNFROMFLASH)
+#  define IMAGE_DEST                FLASH_BASE
+#  define IMAGE_DEST_END            FLASH_END
+#  define IMAGE_DEST_OFFSET         0
+#else
+#  define IMAGE_DEST                OCRAM_BASE
+#  define IMAGE_DEST_END            OCRAM_END
+#  define IMAGE_DEST_OFFSET         IVT_SIZE
+#endif
+
+#define LOCATE_IN_DEST(x)           (((uint32_t)(x)) - FLASH_BASE + IMAGE_DEST)
+#define LOCATE_IN_SRC(x)            (((uint32_t)(x)) - IMAGE_DEST + FLASH_BASE)
+
+#define DCD_ADDRESS                 0
+#define BOOT_DATA_ADDRESS           LOCATE_IN_DEST(&g_boot_data)
+#define CSF_ADDRESS                 0
+#define PLUGIN_FLAG                 (uint32_t)0
+
+/* Located in Destination Memory */
+
+#define IMAGE_ENTRY_ADDRESS        ((uint32_t)&_vectors)
+#define IMAG_VECTOR_TABLE           LOCATE_IN_DEST(&g_image_vector_table)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* IVT Data */
+
+struct ivt_s {
+	/* Header with tag #HAB_TAG_IVT, length and HAB version fields
+	 * (see data)
+	 */
+
+	uint32_t hdr;
+
+	/* Absolute address of the first instruction to execute from the
+	 * image
+	 */
+
+	uint32_t entry;
+
+	/* Reserved in this version of HAB: should be NULL. */
+
+	uint32_t reserved1;
+
+	/* Absolute address of the image DCD: may be NULL. */
+
+	uint32_t dcd;
+
+	/* Absolute address of the Boot Data: may be NULL, but not interpreted
+	 * any further by HAB
+	 */
+
+	uint32_t boot_data;
+
+	/* Absolute address of the IVT. */
+
+	uint32_t self;
+
+	/* Absolute address of the image CSF. */
+
+	uint32_t csf;
+
+	/* Reserved in this version of HAB: should be zero. */
+
+	uint32_t reserved2;
+};
+
+/* Boot Data */
+
+struct boot_data_s {
+	uint32_t start;           /* boot start location */
+	uint32_t size;            /* size */
+	uint32_t plugin;          /* plugin flag - 1 if downloaded application is plugin */
+	uint32_t placeholder;     /* placeholder to make even 0x10 size */
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+extern const struct boot_data_s g_boot_data;
+extern const uint8_t g_dcd_data[];
+extern const uint32_t  _vectors[];
+
+#endif /* __BOARDS_PX4_FMU_V6XRT_SRC_IMXRT_FLEXSPI_NOR_BOOT_H */
@@ -0,0 +1,144 @@
+/****************************************************************************
+ * boards/px4/fmu-v6xrt/src/imxrt_flexspi_nor_flash.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "imxrt_flexspi_nor_flash.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+locate_data(".boot_hdr.conf")
+const struct flexspi_nor_config_s g_flash_config = {
+	.memConfig =
+	{
+#if !defined(CONFIG_BOARD_BOOTLOADER_INVALID_FCB)
+		.tag                 = FLEXSPI_CFG_BLK_TAG,
+#else
+		.tag                 = 0xffffffffL,
+#endif
+		.version             = FLEXSPI_CFG_BLK_VERSION,
+		.readSampleClkSrc    = kFlexSPIReadSampleClk_LoopbackInternally,
+		.csHoldTime          = 1,
+		.csSetupTime         = 1,
+		.deviceModeCfgEnable = 1,
+		.deviceModeType      = kDeviceConfigCmdType_Generic,
+		.waitTimeCfgCommands = 1,
+		.controllerMiscOption =
+		(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable),
+		.deviceType    = kFlexSpiDeviceType_SerialNOR,
+		.sflashPadType = kSerialFlash_1Pad,
+		.serialClkFreq = kFlexSpiSerialClk_30MHz,
+		.sflashA1Size  = 64ul * 1024u * 1024u,
+		.dataValidTime =
+		{
+			[0] = {.time_100ps = 0},
+		},
+		.busyOffset      = 0u,
+		.busyBitPolarity = 0u,
+		.lookupTable =
+		{
+			/* Read Dedicated 3Byte Address Read(0x03), 24bit address */
+			[0 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x03, RADDR_SDR, FLEXSPI_1PAD, 0x18),    //0x871187ee,
+			[0 + 1] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0),//0xb3048b20
+		},
+	},
+	.pageSize           = 256u,
+	.sectorSize         = 4u * 1024u,
+	.blockSize          = 64u * 1024u,
+	.isUniformBlockSize = false,
+	.ipcmdSerialClkFreq = 1,
+	.serialNorType = 2,
+	.reserve2[0] = 0x7008200,
+};
+
+const struct flexspi_nor_config_s g_flash_fast_config = {
+	.memConfig =
+	{
+		.tag                 = FLEXSPI_CFG_BLK_TAG,
+		.version             = FLEXSPI_CFG_BLK_VERSION,
+		.readSampleClkSrc    = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
+		.csHoldTime          = 1,
+		.csSetupTime         = 1,
+		.deviceModeCfgEnable = 1,
+		.deviceModeType      = kDeviceConfigCmdType_Spi2Xpi,
+		.waitTimeCfgCommands = 1,
+		.deviceModeSeq =
+		{
+			.seqNum   = 1,
+			.seqId    = 6, /* See Lookup table for more details */
+			.reserved = 0,
+		},
+		.deviceModeArg = 2, /* Enable OPI DDR mode */
+		.controllerMiscOption =
+		(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DdrModeEnable),
+		.deviceType    = kFlexSpiDeviceType_SerialNOR,
+		.sflashPadType = kSerialFlash_8Pads,
+		.serialClkFreq = kFlexSpiSerialClk_200MHz,
+		.sflashA1Size  = 64ul * 1024u * 1024u,
+		.dataValidTime =
+		{
+			[0] = {.time_100ps = 0},
+		},
+		.busyOffset      = 0u,
+		.busyBitPolarity = 0u,
+		.lookupTable =
+		{
+			/* Read */// EEH+11H+32bit addr+20dummy cycles+ 4Bytes read data    //200Mhz 18 dummy=10+8
+			[0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11),    //0x871187ee,
+			[0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04),//0xb3048b20,
+			[0 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00), //0xa704,
+
+			/* Read status */
+			[4 * 2 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x05, CMD_DDR, FLEXSPI_8PAD, 0xfa),
+			[4 * 2 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04),
+			[4 * 2 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00),
+
+			/* Write enable SPI *///06h
+			[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP_EXE, FLEXSPI_1PAD, 0x00),//0x00000406,
+
+			/* Write enable OPI SPI *///06h
+			[4 * 4 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x06, CMD_DDR, FLEXSPI_8PAD, 0xF9),
+
+			/* Erase sector */
+			[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x21, CMD_DDR, FLEXSPI_8PAD, 0xDE),
+			[4 * 5 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, STOP_EXE, FLEXSPI_1PAD, 0x00),
+
+			/*Write Configuration Register 2 =01, Enable OPI DDR mode*/ //72H +32bit address + CR20x00000000 = 0x01
+			[4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x72, CMD_SDR, FLEXSPI_1PAD, 0x00),//0x04000472,
+			[4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, CMD_SDR, FLEXSPI_1PAD, 0x00),//0x04000400,
+			[4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, WRITE_SDR, FLEXSPI_1PAD, 0x01),//0x20010400,
+
+			/*Page program*/
+			[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x12, CMD_DDR, FLEXSPI_8PAD, 0xED),//0x87ed8712,
+			[4 * 9 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, WRITE_DDR, FLEXSPI_8PAD, 0x04),//0xa3048b20,
+		},
+	},
+	.pageSize           = 256u,
+	.sectorSize         = 4u * 1024u,
+	.blockSize          = 64u * 1024u,
+	.isUniformBlockSize = false,
+	.ipcmdSerialClkFreq = 1,
+	.serialNorType = 2,
+	.reserve2[0] = 0x7008200,
+};
@@ -0,0 +1,352 @@
+/****************************************************************************
+ * boards/px4/fmu-v6xrt/src/imxrt_flexspi_nor_flash.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_PX4_FMU_V6XRT_SRC_IMXRT_FLEXSPI_NOR_FLASH_H
+#define __BOARDS_PX4_FMU_V6XRT_SRC_IMXRT_FLEXSPI_NOR_FLASH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/* FLEXSPI memory config block related defintions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related defintions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP_EXE 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+/*! @name LUT - LUT 0..LUT 63 */
+/*! @{ */
+
+#define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
+#define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
+/*! OPERAND0 - OPERAND0
+ */
+#define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
+
+#define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
+#define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
+/*! NUM_PADS0 - NUM_PADS0
+ */
+#define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
+
+#define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
+#define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
+/*! OPCODE0 - OPCODE
+ */
+#define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
+
+#define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
+#define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
+/*! OPERAND1 - OPERAND1
+  */
+#define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
+
+#define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
+#define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
+/*! NUM_PADS1 - NUM_PADS1
+ */
+#define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
+
+#define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
+#define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
+/*! OPCODE1 - OPCODE1
+ */
+#define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_LUT */
+#define FLEXSPI_LUT_COUNT                        (64U)
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+	(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+	 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq {
+	kFlexSpiSerialClk_30MHz  = 1,
+	kFlexSpiSerialClk_50MHz  = 2,
+	kFlexSpiSerialClk_60MHz  = 3,
+	kFlexSpiSerialClk_80MHz  = 4,
+	kFlexSpiSerialClk_100MHz  = 5,
+	kFlexSpiSerialClk_120MHz = 6,
+	kFlexSpiSerialClk_133MHz = 7,
+	kFlexSpiSerialClk_166MHz = 8,
+	kFlexSpiSerialClk_200MHz = 9,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum {
+	kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+	kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource {
+	kFlexSPIReadSampleClk_LoopbackInternally      = 0,
+	kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
+	kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
+	kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum {
+	kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
+	kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
+	kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
+	kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
+	kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
+	kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+	kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum {
+	kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
+	kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
+	kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
+	kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+	kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum {
+	kSerialFlash_1Pad  = 1,
+	kSerialFlash_2Pads = 2,
+	kSerialFlash_4Pads = 4,
+	kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence {
+	uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+	uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+	uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum {
+	kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
+	kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+	kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
+	kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
+	kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
+	kDeviceConfigCmdType_Reset,      //!< Reset device command
+};
+
+typedef struct {
+	uint8_t time_100ps;  /* Data valid time, in terms of 100ps */
+	uint8_t delay_cells; /* Data valid time, in terms of delay cells */
+} flexspi_dll_time_t;
+
+/*!
+ * @name Configuration Option
+ * @{
+ */
+/*! @brief Serial NOR Configuration Option. */
+typedef struct _serial_nor_config_option {
+	union {
+		struct {
+			uint32_t max_freq : 4;          /*!< Maximum supported Frequency */
+			uint32_t misc_mode : 4;         /*!< miscellaneous mode */
+			uint32_t quad_mode_setting : 4; /*!< Quad mode setting */
+			uint32_t cmd_pads : 4;          /*!< Command pads */
+			uint32_t query_pads : 4;        /*!< SFDP read pads */
+			uint32_t device_type : 4;       /*!< Device type */
+			uint32_t option_size : 4;       /*!< Option size, in terms of uint32_t, size = (option_size + 1) * 4 */
+			uint32_t tag : 4;               /*!< Tag, must be 0x0E */
+		} B;
+		uint32_t U;
+	} option0;
+
+	union {
+		struct {
+			uint32_t dummy_cycles : 8;     /*!< Dummy cycles before read */
+			uint32_t status_override : 8;  /*!< Override status register value during device mode configuration */
+			uint32_t pinmux_group : 4;     /*!< The pinmux group selection */
+			uint32_t dqs_pinmux_group : 4; /*!< The DQS Pinmux Group Selection */
+			uint32_t drive_strength : 4;   /*!< The Drive Strength of FlexSPI Pads */
+			uint32_t flash_connection : 4; /*!< Flash connection option: 0 - Single Flash connected to port A, 1 -
+                                                Parallel mode, 2 - Single Flash connected to Port B */
+		} B;
+		uint32_t U;
+	} option1;
+
+} serial_nor_config_option_t;
+
+//!@brief FlexSPI Memory Configuration Block
+struct mem_config_s {
+	uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+	uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+	uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+	uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+	uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
+	uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
+	uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet
+	uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+	uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.
+	uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for  DPI/QPI/OPI switch or reset command
+	flexspi_lut_seq_t
+	deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved
+	uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+	uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+	uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+	flexspi_lut_seq_t
+	configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+	uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+	uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+	uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+	uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details
+	uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+	uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+	uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot Chapter for more details
+	uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+	uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
+	uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
+	uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
+	uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
+	uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
+	uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+	uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+	uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+	uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+	uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
+	uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
+	flexspi_dll_time_t
+	dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+	uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+	uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 busy flag is 0 when flash device is busy
+	uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+	flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+	uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
+};
+
+/*  */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
+#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+	CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+	2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+	CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+	4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+	CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+	14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+	15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ *  Serial NOR configuration block
+ */
+struct flexspi_nor_config_s {
+	struct mem_config_s  memConfig; //!< Common memory configuration info via FlexSPI
+	uint32_t pageSize;              //!< Page size of Serial NOR
+	uint32_t sectorSize;            //!< Sector size of Serial NOR
+	uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+	uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+	uint8_t reserved0[2];           //!< Reserved for future use
+	uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+	uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+	uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+	uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+	uint32_t blockSize;             //!< Block size
+	uint32_t reserve2[11];          //!< Reserved for future use
+};
+
+extern const struct flexspi_nor_config_s g_flash_config;
+extern const struct flexspi_nor_config_s g_flash_fast_config;
+
+
+#endif /* __BOARDS_PX4_FMU_V6XRT_SRC_IMXRT_FLEXSPI_NOR_FLASH_H */
@@ -0,0 +1,271 @@
+/****************************************************************************
+ * boards/px4/fmu-v6xrt/src/imxrt_romapi.c
+ *
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+****************************************************************************/
+
+/****************************************************************************
+ *
+ * Included Files
+ ****************************************************************************/
+
+#include "board_config.h"
+
+#include <stdbool.h>
+#include <debug.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "arm_internal.h"
+
+#include "imxrt_flexspi_nor_flash.h"
+#include "imxrt_romapi.h"
+
+#include <hardware/rt117x/imxrt117x_anadig.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Structure of version property.
+ *
+ * @ingroup bl_core
+ */
+typedef union _standard_version {
+	struct {
+		uint8_t bugfix; /*!< bugfix version [7:0] */
+		uint8_t minor;  /*!< minor version [15:8] */
+		uint8_t major;  /*!< major version [23:16] */
+		char name;      /*!< name [31:24] */
+	};
+	uint32_t version; /*!< combined version numbers */
+
+#if defined(__cplusplus)
+	StandardVersion() : version(0) {
+	}
+	StandardVersion(uint32_t version) : version(version) {
+	}
+#endif
+} standard_version_t;
+
+/*!
+ * @brief Interface for the ROM FLEXSPI NOR flash driver.
+ */
+typedef struct {
+	uint32_t version;
+	status_t (*init)(uint32_t instance, flexspi_nor_config_t *config);
+	status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dst_addr, const uint32_t *src);
+	status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config);
+	status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
+	status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes);
+	void (*clear_cache)(uint32_t instance);
+	status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer);
+	status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq);
+	status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option);
+	status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
+	status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
+	const uint32_t reserved0; /*!< Reserved */
+	status_t (*wait_busy)(uint32_t instance, flexspi_nor_config_t *config, bool isParallelMode, uint32_t address);
+	const uint32_t reserved1[2]; /*!< Reserved */
+} flexspi_nor_driver_interface_t;
+
+/*!
+ * @brief Root of the bootloader api tree.
+ *
+ * An instance of this struct resides in read-only memory in the bootloader. It
+ * provides a user application access to APIs exported by the bootloader.
+ *
+ * @note The order of existing fields must not be changed.
+ */
+typedef struct {
+	void (*runBootloader)(void *arg);                       /*!< Function to start the bootloader executing.*/
+	standard_version_t version;                             /*!< Bootloader version number.*/
+	const char *copyright;                                  /*!< Copyright string.*/
+	const flexspi_nor_driver_interface_t *flexSpiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/
+	const uint32_t reserved[8];                             /*!< Reserved */
+} bootloader_api_entry_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+static bootloader_api_entry_t *g_bootloaderTree = NULL;
+
+/*******************************************************************************
+ * ROM FLEXSPI NOR driver
+ ******************************************************************************/
+/*!
+ * @brief ROM API init.
+ */
+locate_code(".ramfunc")
+void ROM_API_Init(void)
+{
+
+	if ((getreg32(IMXRT_ANADIG_MISC_MISC_DIFPROG) & ANADIG_MISC_MISC_DIFPROG_CHIPID(0x10U)) != 0U) {
+		g_bootloaderTree = ((bootloader_api_entry_t *) * (uint32_t *)0x0021001cU);
+
+	} else {
+		g_bootloaderTree = ((bootloader_api_entry_t *) * (uint32_t *)0x0020001cU);
+	}
+}
+
+/*!
+ * @brief Enter Bootloader.
+ *
+ * @param arg A pointer to the storage for the bootloader param.
+ *        refer to System Boot Chapter in device reference manual for details.
+ */
+locate_code(".ramfunc")
+void ROM_RunBootloader(void *arg)
+{
+	g_bootloaderTree->runBootloader(arg);
+}
+
+/*! @brief Get FLEXSPI NOR Configuration Block based on specified option. */
+locate_code(".ramfunc")
+status_t ROM_FLEXSPI_NorFlash_GetConfig(uint32_t instance,
+					flexspi_nor_config_t *config,
+					serial_nor_config_option_t *option)
+{
+	return g_bootloaderTree->flexSpiNorDriver->get_config(instance, config, option);
+}
+
+/*!
+ * @brief Initialize Serial NOR devices via FLEXSPI.
+ *
+ * @param instance storage the instance of FLEXSPI.
+ * @param config A pointer to the storage for the driver runtime state.
+ */
+locate_code(".ramfunc")
+status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config)
+{
+	return g_bootloaderTree->flexSpiNorDriver->init(instance, config);
+}
+
+/*!
+ * @brief Program data to Serial NOR via FLEXSPI.
+ *
+ * @param instance storage the instance of FLEXSPI.
+ * @param config  A pointer to the storage for the driver runtime state.
+ * @param dst_addr A pointer to the desired flash memory to be programmed.
+ * @param src A pointer to the source buffer of data that is to be programmed
+ *            into the NOR flash.
+ */
+locate_code(".ramfunc")
+status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance,
+		flexspi_nor_config_t *config,
+		uint32_t dst_addr,
+		const uint32_t *src)
+{
+	return g_bootloaderTree->flexSpiNorDriver->page_program(instance, config, dst_addr, src);
+}
+
+/*!
+ * @brief Read data from Serial NOR
+ *
+ * @param instance storage the instance of FLEXSPI.
+ * @param config  A pointer to the storage for the driver runtime state.
+ * @param dst     A pointer to the dest buffer of data that is to be read from the NOR flash.
+ * @param lengthInBytes The length, given in bytes to be read.
+ */
+locate_code(".ramfunc")
+status_t ROM_FLEXSPI_NorFlash_Read(
+	uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t lengthInBytes)
+{
+	return g_bootloaderTree->flexSpiNorDriver->read(instance, config, dst, start, lengthInBytes);
+}
+
+/*!
+ * @brief Erase Flash Region specified by address and length.
+ *
+ * @param instance storage the index of FLEXSPI.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired NOR flash memory to be erased.
+ * @param length The length, given in bytes to be erased.
+ */
+locate_code(".ramfunc")
+status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length)
+{
+	return g_bootloaderTree->flexSpiNorDriver->erase(instance, config, start, length);
+}
+
+/*!
+ * @brief Erase one sector specified by address.
+ *
+ * @param instance storage the index of FLEXSPI.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired NOR flash memory to be erased.
+ */
+locate_code(".ramfunc")
+status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)
+{
+	return g_bootloaderTree->flexSpiNorDriver->erase_sector(instance, config, start);
+}
+
+/*!
+ * @brief Erase one block specified by address.
+ *
+ * @param instance storage the index of FLEXSPI.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired NOR flash memory to be erased.
+ */
+locate_code(".ramfunc")
+status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)
+{
+	return g_bootloaderTree->flexSpiNorDriver->erase_block(instance, config, start);
+}
+
+/*! @brief Erase all the Serial NOR devices connected on FLEXSPI. */
+locate_code(".ramfunc")
+status_t ROM_FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config)
+{
+	return g_bootloaderTree->flexSpiNorDriver->erase_all(instance, config);
+}
+
+/*! @brief FLEXSPI command */
+locate_code(".ramfunc")
+status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer)
+{
+	return g_bootloaderTree->flexSpiNorDriver->xfer(instance, xfer);
+}
+/*! @brief Configure FLEXSPI Lookup table. */
+locate_code(".ramfunc")
+status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance,
+					uint32_t seqIndex,
+					const uint32_t *lutBase,
+					uint32_t seqNumber)
+{
+	return g_bootloaderTree->flexSpiNorDriver->update_lut(instance, seqIndex, lutBase, seqNumber);
+}
+
+/*! @brief Software reset for the FLEXSPI logic. */
+locate_code(".ramfunc")
+void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance)
+{
+	uint32_t clearCacheFunctionAddress;
+
+	if ((getreg32(IMXRT_ANADIG_MISC_MISC_DIFPROG) & ANADIG_MISC_MISC_DIFPROG_CHIPID(0x10U)) != 0U) {
+		clearCacheFunctionAddress = 0x0021a3b7U;
+
+	} else {
+		clearCacheFunctionAddress = 0x0020426bU;
+	}
+
+	clearCacheCommand_t clearCacheCommand;
+	MISRA_CAST(clearCacheCommand_t, clearCacheCommand, uint32_t, clearCacheFunctionAddress);
+	(void)clearCacheCommand(instance);
+}
+
+/*! @brief Wait until device is idle*/
+locate_code(".ramfunc")
+status_t ROM_FLEXSPI_NorFlash_WaitBusy(uint32_t instance,
+				       flexspi_nor_config_t *config,
+				       bool isParallelMode,
+				       uint32_t address)
+{
+	return g_bootloaderTree->flexSpiNorDriver->wait_busy(instance, config, isParallelMode, address);
+}
@@ -0,0 +1,373 @@
+/****************************************************************************
+ * boards/px4/fmu-v6xrt/src/imxrt_romapi.c
+ *
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+****************************************************************************/
+#ifndef __BOARDS_PX4_FMU_V6XRT_SRC_IMXRT_ROMAPI_H
+#define __BOARDS_PX4_FMU_V6XRT_SRC_IMXRT_ROMAPI_H
+
+/****************************************************************************
+ *
+ * Included Files
+ ****************************************************************************/
+
+#include "board_config.h"
+
+typedef int32_t status_t;
+typedef struct flexspi_nor_config_s flexspi_nor_config_t;
+typedef status_t (*clearCacheCommand_t)(uint32_t instance);
+
+/*! @brief FLEXSPI Operation Context */
+typedef enum _flexspi_operation {
+	kFLEXSPIOperation_Command,  /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */
+	kFLEXSPIOperation_Config,   /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */
+	kFLEXSPIOperation_Write,    /*!< FLEXSPI operation: Write, only TX buffer is effective */
+	kFLEXSPIOperation_Read,     /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */
+} flexspi_operation_t;
+
+#define kFLEXSPIOperation_End   kFLEXSPIOperation_Read
+
+/*! @brief FLEXSPI Transfer Context */
+typedef struct _flexspi_xfer {
+	flexspi_operation_t operation; /*!< FLEXSPI operation */
+	uint32_t baseAddress;          /*!< FLEXSPI operation base address */
+	uint32_t seqId;                /*!< Sequence Id */
+	uint32_t seqNum;               /*!< Sequence Number */
+	bool isParallelModeEnable;     /*!< Is a parallel transfer */
+	uint32_t *txBuffer;            /*!< Tx buffer */
+	uint32_t txSize;               /*!< Tx size in bytes */
+	uint32_t *rxBuffer;            /*!< Rx buffer */
+	uint32_t rxSize;               /*!< Rx size in bytes */
+} flexspi_xfer_t;
+
+/*! @brief convert the type for MISRA */
+#define MISRA_CAST(to_type, to_var, from_type, from_var)      \
+	do                                                        \
+	{                                                         \
+		union                                                 \
+		{                                                     \
+			to_type to_var_tmp;                               \
+			from_type from_var_tmp;                           \
+		} type_converter_var = {.from_var_tmp = (from_var)};  \
+		(to_var)             = type_converter_var.to_var_tmp; \
+	} while (false)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern struct flexspi_nor_config_s g_bootConfig;
+
+/*!
+ * @brief ROM API init
+ *
+ * Get the bootloader api entry address.
+ */
+void ROM_API_Init(void);
+
+/*!
+ * @name Enter Bootloader
+ * @{
+ */
+
+/*!
+ * @brief Enter Bootloader.
+ *
+ * @param arg A pointer to the storage for the bootloader param.
+ *        refer to System Boot Chapter in device reference manual for details.
+ */
+void ROM_RunBootloader(void *arg);
+
+/*@}*/
+
+/*!
+ * @name GetConfig
+ * @{
+ */
+/*!
+ * @brief Get FLEXSPI NOR Configuration Block based on specified option.
+ *
+ * @param instance storage the instance of FLEXSPI.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param option A pointer to the storage Serial NOR Configuration Option Context.
+ *
+ * @retval kStatus_Success Api was executed successfully.
+ * @retval kStatus_InvalidArgument A invalid argument is provided.
+ * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
+ * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
+ * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
+ */
+status_t ROM_FLEXSPI_NorFlash_GetConfig(uint32_t instance,
+					flexspi_nor_config_t *config,
+					serial_nor_config_option_t *option);
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initialize Serial NOR devices via FLEXSPI
+ *
+ * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs.
+ *
+ * @param instance storage the instance of FLEXSPI.
+ * @param config A pointer to the storage for the driver runtime state.
+ *
+ * @retval kStatus_Success Api was executed successfully.
+ * @retval kStatus_InvalidArgument A invalid argument is provided.
+ * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
+ * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
+ * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
+ */
+status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config);
+
+/*@}*/
+
+/*!
+ * @name Programming
+ * @{
+ */
+
+/*!
+ * @brief Program data to Serial NOR via FLEXSPI.
+ *
+ * This function programs the NOR flash memory with the dest address for a given
+ * flash area as determined by the dst address and the length.
+ *
+ * @param instance storage the instance of FLEXSPI.
+ * @param config  A pointer to the storage for the driver runtime state.
+ * @param dst_addr A pointer to the desired flash memory to be programmed.
+ *                @note It is recommended that use page aligned access;
+ *                If the dst_addr is not aligned to page, the driver automatically
+ *                aligns address down with the page address.
+ * @param src A pointer to the source buffer of data that is to be programmed
+ *            into the NOR flash.
+ *
+ * @retval kStatus_Success Api was executed successfully.
+ * @retval kStatus_InvalidArgument A invalid argument is provided.
+ * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
+ * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
+ * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
+ */
+status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance,
+		flexspi_nor_config_t *config,
+		uint32_t dst_addr,
+		const uint32_t *src);
+
+/*@}*/
+
+/*!
+ * @name Reading
+ * @{
+ */
+
+/*!
+ * @brief Read data from Serial NOR via FLEXSPI.
+ *
+ * This function read the NOR flash memory with the start address for a given
+ * flash area as determined by the dst address and the length.
+ *
+ * @param instance storage the instance of FLEXSPI.
+ * @param config  A pointer to the storage for the driver runtime state.
+ * @param dst     A pointer to the dest buffer of data that is to be read from the NOR flash.
+ *                @note It is recommended that use page aligned access;
+ *                If the dstAddr is not aligned to page, the driver automatically
+ *                aligns address down with the page address.
+ * @param start   The start address of the desired NOR flash memory to be read.
+ * @param lengthInBytes The length, given in bytes to be read.
+ *
+ * @retval kStatus_Success Api was executed successfully.
+ * @retval kStatus_InvalidArgument A invalid argument is provided.
+ * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
+ * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
+ * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
+ */
+status_t ROM_FLEXSPI_NorFlash_Read(
+	uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t lengthInBytes);
+
+/*@}*/
+
+/*!
+ * @name Erasing
+ * @{
+ */
+
+/*!
+ * @brief Erase Flash Region specified by address and length
+ *
+ * This function erases the appropriate number of flash sectors based on the
+ * desired start address and length.
+ *
+ * @param instance storage the index of FLEXSPI.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired NOR flash memory to be erased.
+ *              @note It is recommended that use sector-aligned access nor device;
+ *              If dstAddr is not aligned with the sector,the driver automatically
+ *              aligns address down with the sector address.
+ * @param length The length, given in bytes to be erased.
+ *              @note It is recommended that use sector-aligned access nor device;
+ *              If length is not aligned with the sector,the driver automatically
+ *              aligns up with the sector.
+ * @retval kStatus_Success Api was executed successfully.
+ * @retval kStatus_InvalidArgument A invalid argument is provided.
+ * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
+ * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
+ * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
+ */
+status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
+
+/*!
+ * @brief Erase one sector specified by address
+ *
+ * This function erases one of NOR flash sectors based on the desired address.
+ *
+ * @param instance storage the index of FLEXSPI.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired NOR flash memory to be erased.
+ *                @note It is recommended that use sector-aligned access nor device;
+ *                If dstAddr is not aligned with the sector, the driver automatically
+ *                aligns address down with the sector address.
+ *
+ * @retval kStatus_Success Api was executed successfully.
+ * @retval kStatus_InvalidArgument A invalid argument is provided.
+ * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
+ * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
+ * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
+ */
+status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t start);
+
+/*!
+ * @brief Erase one block specified by address
+ *
+ * This function erases one block of NOR flash based on the desired address.
+ *
+ * @param instance storage the index of FLEXSPI.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired NOR flash memory to be erased.
+ *              @note It is recommended that use block-aligned access nor device;
+ *              If dstAddr is not aligned with the block, the driver automatically
+ *              aligns address down with the block address.
+ *
+ * @retval kStatus_Success Api was executed successfully.
+ * @retval kStatus_InvalidArgument A invalid argument is provided.
+ * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
+ * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
+ * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
+ */
+status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start);
+
+/*!
+ * @brief Erase all the Serial NOR devices connected on FLEXSPI.
+ *
+ * @param instance storage the instance of FLEXSPI.
+ * @param config A pointer to the storage for the driver runtime state.
+ *
+ * @retval kStatus_Success Api was executed successfully.
+ * @retval kStatus_InvalidArgument A invalid argument is provided.
+ * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
+ * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
+ * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
+ */
+status_t ROM_FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config);
+
+/*@}*/
+
+/*!
+ * @name Command
+ * @{
+ */
+/*!
+ * @brief FLEXSPI command
+ *
+ * This function is used to perform the command write sequence to the NOR device.
+ *
+ * @param instance storage the index of FLEXSPI.
+ * @param xfer A pointer to the storage FLEXSPI Transfer Context.
+ *
+ * @retval kStatus_Success Api was executed successfully.
+ * @retval kStatus_InvalidArgument A invalid argument is provided.
+ * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
+ * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
+ */
+status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer);
+
+/*@}*/
+
+/*!
+ * @name UpdateLut
+ * @{
+ */
+
+/*!
+ * @brief Configure FLEXSPI Lookup table
+ *
+ * @param instance storage the index of FLEXSPI.
+ * @param seqIndex storage the sequence Id.
+ * @param lutBase A pointer to the look-up-table for command sequences.
+ * @param seqNumber storage sequence number.
+ *
+ * @retval kStatus_Success Api was executed successfully.
+ * @retval kStatus_InvalidArgument A invalid argument is provided.
+ * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
+ * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
+ */
+status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance,
+					uint32_t seqIndex,
+					const uint32_t *lutBase,
+					uint32_t seqNumber);
+
+
+/*@}*/
+
+/*!
+ * @name Device status
+ * @{
+ */
+/*!
+ * @brief Wait until device is idle.
+ *
+ * @param instance  Indicates the index of FLEXSPI.
+ * @param config    A pointer to the storage for the driver runtime state
+ * @param isParallelMode Indicates whether NOR flash is in parallel mode.
+ * @param address  Indicates the operation(erase/program/read) address for serial NOR flash.
+ *
+ * @retval kStatus_Success Api was executed successfully.
+ * @retval kStatus_InvalidArgument A invalid argument is provided.
+ * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
+ * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
+ * @retval kStatus_ROM_FLEXSPI_DeviceTimeout Device timeout.
+ */
+status_t ROM_FLEXSPI_NorFlash_WaitBusy(uint32_t instance,
+				       flexspi_nor_config_t *config,
+				       bool isParallelMode,
+				       uint32_t address);
+/*@}*/
+
+/*!
+ * @name ClearCache
+ * @{
+ */
+
+/*!
+ * @name ClearCache
+ * @{
+ */
+
+/*!
+ * @brief Software reset for the FLEXSPI logic.
+ *
+ * This function sets the software reset flags for both AHB and buffer domain and
+ * resets both AHB buffer and also IP FIFOs.
+ *
+ * @param instance storage the index of FLEXSPI.
+ */
+void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance);
+
+/*@}*/
+
+#endif /* __BOARDS_PX4_FMU_V6XRT_SRC_IMXRT_ROMAPI_H */
@@ -0,0 +1,115 @@
+/****************************************************************************
+ *
+ *   Copyright (c) 2016, 2018 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file led.c
+ *
+ * PX4 fmu-v6rt LED backend.
+ */
+
+#include <px4_platform_common/px4_config.h>
+
+#include <stdbool.h>
+
+#include "chip.h"
+#include <hardware/imxrt_gpio.h>
+#include "board_config.h"
+
+#include <arch/board/board.h>
+
+/*
+ * Ideally we'd be able to get these from arm_internal.h,
+ * but since we want to be able to disable the NuttX use
+ * of leds for system indication at will and there is no
+ * separate switch, we need to build independent of the
+ * CONFIG_ARCH_LEDS configuration switch.
+ */
+__BEGIN_DECLS
+extern void led_init(void);
+extern void led_on(int led);
+extern void led_off(int led);
+extern void led_toggle(int led);
+__END_DECLS
+
+
+static uint32_t g_ledmap[] = {
+	GPIO_nLED_BLUE,   // Indexed by LED_BLUE
+	GPIO_nLED_RED,    // Indexed by LED_RED, LED_AMBER
+	GPIO_LED_SAFETY,  // Indexed by LED_SAFETY
+	GPIO_nLED_GREEN,  // Indexed by LED_GREEN
+};
+
+__EXPORT void led_init(void)
+{
+	/* Configure LED GPIOs for output */
+	for (size_t l = 0; l < (sizeof(g_ledmap) / sizeof(g_ledmap[0])); l++) {
+		if (g_ledmap[l] != 0) {
+			imxrt_config_gpio(g_ledmap[l]);
+		}
+	}
+}
+
+static void phy_set_led(int led, bool state)
+{
+	/* Drive Low to switch on */
+
+	if (g_ledmap[led] != 0) {
+		imxrt_gpio_write(g_ledmap[led], !state);
+	}
+}
+
+static bool phy_get_led(int led)
+{
+
+	if (g_ledmap[led] != 0) {
+		return imxrt_gpio_read(!g_ledmap[led]);
+	}
+
+	return false;
+}
+
+__EXPORT void led_on(int led)
+{
+	phy_set_led(led, true);
+}
+
+__EXPORT void led_off(int led)
+{
+	phy_set_led(led, false);
+}
+
+__EXPORT void led_toggle(int led)
+{
+
+	phy_set_led(led, !phy_get_led(led));
+}
@@ -0,0 +1,148 @@
+/****************************************************************************
+ *
+ *   Copyright (c) 2018, 2021 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file manifest.c
+ *
+ * This module supplies the interface to the manifest of hardware that is
+ * optional and dependent on the HW REV and HW VER IDs
+ *
+ * The manifest allows the system to know whether a hardware option
+ * say for example the PX4IO is an no-pop option vs it is broken.
+ *
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <px4_platform_common/px4_config.h>
+#include <stdbool.h>
+#include <syslog.h>
+
+#include "systemlib/px4_macros.h"
+#include "px4_log.h"
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+
+typedef struct {
+	uint32_t                hw_ver_rev; /* the version and revision */
+	const px4_hw_mft_item_t *mft;       /* The first entry */
+	uint32_t                entries;    /* the lenght of the list */
+} px4_hw_mft_list_entry_t;
+
+typedef px4_hw_mft_list_entry_t *px4_hw_mft_list_entry;
+#define px4_hw_mft_list_uninitialized (px4_hw_mft_list_entry) -1
+
+static const px4_hw_mft_item_t device_unsupported = {0, 0, 0};
+
+// List of components on a specific board configuration
+// The index of those components is given by the enum (px4_hw_mft_item_id_t)
+// declared in board_common.h
+static const px4_hw_mft_item_t hw_mft_list_V00[] = {
+	{
+		//  PX4_MFT_PX4IO
+		.present     = 1,
+		.mandatory   = 1,
+		.connection  = px4_hw_con_onboard,
+	},
+	{
+		// PX4_MFT_USB
+		.present     = 1,
+		.mandatory   = 1,
+		.connection  = px4_hw_con_onboard,
+	},
+	{
+		// PX4_MFT_CAN2
+		.present     = 1,
+		.mandatory   = 1,
+		.connection  = px4_hw_con_onboard,
+	},
+	{
+		// PX4_MFT_CAN3
+		.present     = 1,
+		.mandatory   = 1,
+		.connection  = px4_hw_con_onboard,
+	},
+};
+
+static px4_hw_mft_list_entry_t mft_lists[] = {
+	{V6XRT_00, hw_mft_list_V00, arraySize(hw_mft_list_V00)},
+};
+
+/************************************************************************************
+ * Name: board_query_manifest
+ *
+ * Description:
+ *   Optional returns manifest item.
+ *
+ * Input Parameters:
+ *   manifest_id - the ID for the manifest item to retrieve
+ *
+ * Returned Value:
+ *   0 - item is not in manifest => assume legacy operations
+ *   pointer to a manifest item
+ *
+ ************************************************************************************/
+
+__EXPORT px4_hw_mft_item board_query_manifest(px4_hw_mft_item_id_t id)
+{
+	static px4_hw_mft_list_entry boards_manifest = px4_hw_mft_list_uninitialized;
+
+	if (boards_manifest == px4_hw_mft_list_uninitialized) {
+		uint32_t ver_rev = board_get_hw_version() << 8;
+		ver_rev |= board_get_hw_revision();
+
+		for (unsigned i = 0; i < arraySize(mft_lists); i++) {
+			if (mft_lists[i].hw_ver_rev == ver_rev) {
+				boards_manifest = &mft_lists[i];
+				break;
+			}
+		}
+
+		if (boards_manifest == px4_hw_mft_list_uninitialized) {
+			PX4_ERR("Board %4" PRIx32 " is not supported!", ver_rev);
+		}
+	}
+
+	px4_hw_mft_item rv = &device_unsupported;
+
+	if (boards_manifest != px4_hw_mft_list_uninitialized &&
+	    id < boards_manifest->entries) {
+		rv = &boards_manifest->mft[id];
+	}
+
+	return rv;
+}
@@ -0,0 +1,133 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2022 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#include <nuttx/spi/spi.h>
+#include <px4_platform_common/px4_manifest.h>
+
+static const px4_mft_device_t qspi_flash = {        // FM25V02A on FMUM 32K 512 X 64
+	.bus_type = px4_mft_device_t::FLEXSPI,             // Using Flex SPI
+};
+//                                                              KiB BS    nB
+static const px4_mft_device_t i2c3 = {             // 24LC64T on IMU  8K 32 X 256
+	.bus_type = px4_mft_device_t::I2C,
+	.devid    = PX4_MK_I2C_DEVID(3, 0x50)
+};
+static const px4_mft_device_t i2c6 = {             // 24LC64T on BASE  8K 32 X 256
+	.bus_type =  px4_mft_device_t::I2C,
+	.devid    =  PX4_MK_I2C_DEVID(6, 0x51)
+};
+
+
+static const px4_mtd_entry_t fmum_fram = {
+	.device = &qspi_flash,
+	.npart = 2,
+	.partd = {
+		{
+			.type = MTD_PARAMETERS,
+			.path = "/fs/mtd_params",
+			.nblocks = 32
+		},
+		{
+			.type = MTD_WAYPOINTS,
+			.path = "/fs/mtd_waypoints",
+			.nblocks = 32
+
+		}
+	},
+};
+
+static const px4_mtd_entry_t base_eeprom = {
+	.device = &i2c6,
+	.npart = 2,
+	.partd = {
+		{
+			.type = MTD_MFT_VER,
+			.path = "/fs/mtd_mft_ver",
+			.nblocks = 248
+		},
+		{
+			.type = MTD_NET,
+			.path = "/fs/mtd_net",
+			.nblocks = 8 // 256 = 32 * 8
+
+		}
+	},
+};
+
+static const px4_mtd_entry_t imu_eeprom = {
+	.device = &i2c3,
+	.npart = 3,
+	.partd = {
+		{
+			.type = MTD_CALDATA,
+			.path = "/fs/mtd_caldata",
+			.nblocks = 240
+		},
+		{
+			.type = MTD_MFT_REV,
+			.path = "/fs/mtd_mft_rev",
+			.nblocks = 8
+		},
+		{
+			.type = MTD_ID,
+			.path = "/fs/mtd_id",
+			.nblocks = 8 // 256 = 32 * 8
+		}
+	},
+};
+
+static const px4_mtd_manifest_t board_mtd_config = {
+	.nconfigs   = 3,
+	.entries = {
+		&fmum_fram,
+		&base_eeprom,
+		&imu_eeprom
+	}
+};
+
+static const px4_mft_entry_s mtd_mft = {
+	.type = MTD,
+	.pmft = (void *) &board_mtd_config,
+};
+
+static const px4_mft_s mft = {
+	.nmft = 1,
+	.mfts = {
+		&mtd_mft
+	}
+};
+
+const px4_mft_s *board_get_manifest(void)
+{
+	return &mft;
+}
@@ -0,0 +1,128 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2016-2018 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/* A micro Secure Digital (SD) card slot is available on the board connected to
+ * the SD Host Controller (USDHC1) signals of the MCU. This slot will accept
+ * micro format SD memory cards.
+ *
+ *   ------------ ------------- --------
+ *    SD Card Slot Board Signal  IMXRT Pin
+ *    ------------ ------------- --------
+ *    DAT0         USDHC1_DATA0  GPIO_SD_B0_02
+ *    DAT1         USDHC1_DATA1  GPIO_SD_B0_03
+ *    DAT2         USDHC1_DATA2  GPIO_SD_B0_04
+ *    CD/DAT3      USDHC1_DATA3  GPIO_SD_B0_05
+ *    CMD          USDHC1_CMD    GPIO_SD_B0_00
+ *    CLK          USDHC1_CLK    GPIO_SD_B0_01
+ *    CD           USDHC1_CD     GPIO_B1_12
+ *    ------------ ------------- --------
+ *
+ * There are no Write Protect available to the IMXRT.
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <px4_platform_common/px4_config.h>
+#include <px4_log.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <debug.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/sdio.h>
+#include <nuttx/mmcsd.h>
+
+#include "chip.h"
+#include "imxrt_usdhc.h"
+
+#include "board_config.h"
+
+#ifdef CONFIG_IMXRT_USDHC
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: fmuv6xrt_usdhc_initialize
+ *
+ * Description:
+ *   Inititialize the SDHC SD card slot
+ *
+ ****************************************************************************/
+
+int fmuv6xrt_usdhc_initialize(void)
+{
+	int ret;
+
+	/* Mount the SDHC-based MMC/SD block driver */
+	/* First, get an instance of the SDHC interface */
+
+	struct sdio_dev_s *sdhc = imxrt_usdhc_initialize(CONFIG_NSH_MMCSDSLOTNO);
+
+	if (!sdhc) {
+		PX4_ERR("ERROR: Failed to initialize SDHC slot %d\n", CONFIG_NSH_MMCSDSLOTNO);
+		return -ENODEV;
+	}
+
+	/* Now bind the SDHC interface to the MMC/SD driver */
+
+	ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdhc);
+
+	if (ret != OK) {
+		PX4_ERR("ERROR: Failed to bind SDHC to the MMC/SD driver: %d\n", ret);
+		return ret;
+	}
+
+	syslog(LOG_INFO, "Successfully bound SDHC to the MMC/SD driver\n");
+
+	return OK;
+}
+#endif /* CONFIG_IMXRT_USDHC */
@@ -0,0 +1,87 @@
+/************************************************************************************
+ *
+ *   Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <px4_arch/spi_hw_description.h>
+#include <drivers/drv_sensor.h>
+#include <nuttx/spi/spi.h>
+
+#include <px4_platform_common/px4_config.h>
+#include <px4_log.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/spi/spi.h>
+#include <arch/board/board.h>
+#include <systemlib/px4_macros.h>
+#include <px4_platform/gpio.h>
+
+#include <arm_internal.h>
+#include <chip.h>
+#include "imxrt_lpspi.h"
+#include "imxrt_gpio.h"
+#include "board_config.h"
+#include <systemlib/err.h>
+
+#ifdef CONFIG_IMXRT_LPSPI
+
+
+constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
+	initSPIBus(SPI::Bus::LPSPI1, {
+		initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::Port2, GPIO::Pin11}, SPI::DRDY{GPIO::Port3, GPIO::Pin19}), /* GPIO_EMC_B2_01 GPIO2_IO11, GPIO_AD_20, GPIO3_IO19 */
+	}, {GPIO::Port2, GPIO::Pin1}), // Power GPIO_EMC_B1_33  GPIO2_IO01
+
+	initSPIBus(SPI::Bus::LPSPI2, {
+		initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::Port3, GPIO::Pin24}, SPI::DRDY{GPIO::Port2, GPIO::Pin7}), /* GPIO_AD_25 GPIO3_IO24, GPIO_EMC_B1_39 GPIO2_IO07 */
+	}, {GPIO::Port1, GPIO::Pin22}), // Power GPIO_EMC_B1_22  GPIO1_IO22
+
+	initSPIBus(SPI::Bus::LPSPI3, {
+		initSPIDevice(DRV_GYR_DEVTYPE_BMI088, SPI::CS{GPIO::Port2, GPIO::Pin18}, SPI::DRDY{GPIO::Port2, GPIO::Pin28}), /* GPIO_EMC_B2_08 GPIO2_IO18, GPIO_EMC_B2_18 GPIO2_IO28 */
+		initSPIDevice(DRV_ACC_DEVTYPE_BMI088, SPI::CS{GPIO::Port2, GPIO::Pin15}),                                      /* GPIO_EMC_B2_05 GPIO2_IO15 */
+	}, {GPIO::Port1, GPIO::Pin14}), // Power GPIO_EMC_B1_14  GPIO1_IO14
+
+	initSPIBusExternal(SPI::Bus::LPSPI6, {
+		initSPIConfigExternal(SPI::CS{GPIO::Port6, GPIO::Pin9}, SPI::DRDY{GPIO::Port1, GPIO::Pin5}), /* GPIO_LPSR_09 GPIO6_IO09 GPIO_EMC_B1_05 GPIO1_IO05*/
+		initSPIConfigExternal(SPI::CS{GPIO::Port6, GPIO::Pin8}, SPI::DRDY{GPIO::Port1, GPIO::Pin7}), /* GPIO_LPSR_08 GPIO6_IO08  GPIO_EMC_B1_07  GPIO1_IO07*/
+	}),
+};
+
+#endif
+static constexpr bool unused = validateSPIConfig(px4_spi_buses);
@@ -0,0 +1,181 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2016, 2018-2019 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+// TODO:Stubbed out for now
+#include <stdint.h>
+
+#include <chip.h>
+#include "hardware/imxrt_tmr.h"
+#include "hardware/imxrt_flexpwm.h"
+#include "imxrt_gpio.h"
+#include "imxrt_iomuxc.h"
+#include "hardware/imxrt_pinmux.h"
+#include "imxrt_xbar.h"
+#include "imxrt_periphclks.h"
+
+#include <drivers/drv_pwm_output.h>
+#include <px4_arch/io_timer_hw_description.h>
+
+#include "board_config.h"
+
+/****************************************************************************************************
+ * Definitions
+ ****************************************************************************************************/
+
+/* Register accessors */
+
+#define _REG(_addr) (*(volatile uint16_t *)(_addr))
+
+/* QTimer3 register accessors */
+
+#define REG(_reg) _REG(IMXRT_TMR3_BASE + IMXRT_TMR_OFFSET(IMXRT_TMR_CH0,(_reg)))
+
+#define rCOMP1        REG(IMXRT_TMR_COMP1_OFFSET)
+#define rCOMP2        REG(IMXRT_TMR_COMP2_OFFSET)
+#define rCAPT         REG(IMXRT_TMR_CAPT_OFFSET)
+#define rLOAD         REG(IMXRT_TMR_LOAD_OFFSET)
+#define rHOLD         REG(IMXRT_TMR_HOLD_OFFSET)
+#define rCNTR         REG(IMXRT_TMR_CNTR_OFFSET)
+#define rCTRL         REG(IMXRT_TMR_CTRL_OFFSET)
+#define rSCTRL        REG(IMXRT_TMR_SCTRL_OFFSET)
+#define rCMPLD1       REG(IMXRT_TMR_CMPLD1_OFFSET)
+#define rCMPLD2       REG(IMXRT_TMR_CMPLD2_OFFSET)
+#define rCSCTRL       REG(IMXRT_TMR_CSCTRL_OFFSET)
+#define rFILT         REG(IMXRT_TMR_FILT_OFFSET)
+#define rDMA          REG(IMXRT_TMR_DMA_OFFSET)
+#define rENBL         REG(IMXRT_TMR_ENBL_OFFSET)
+
+
+// GPIO_EMC_B1_23  FMU_CH1  FLEXPWM1_PWM0_A
+// GPIO_EMC_B1_25  FMU_CH2  FLEXPWM1_PWM1_A + FLEXIO1_IO25
+// GPIO_EMC_B1_27  FMU_CH3  FLEXPWM1_PWM2_A + FLEXIO1_IO27
+// GPIO_EMC_B1_06  FMU_CH4  FLEXPWM2_PWM0_A + FLEXIO1_IO06
+// GPIO_EMC_B1_08  FMU_CH5  FLEXPWM2_PWM1_A + FLEXIO1_IO08
+// GPIO_EMC_B1_10  FMU_CH6  FLEXPWM2_PWM2_A + FLEXIO1_IO10
+// GPIO_EMC_B1_19  FMU_CH7  FLEXPWM2_PWM3_A + FLEXIO1_IO19
+// GPIO_EMC_B1_29  FMU_CH8  FLEXPWM3_PWM0_A + FLEXIO1_IO29
+// GPIO_EMC_B1_31  FMU_CH9  FLEXPWM3_PWM1_A + FLEXIO1_IO31
+// GPIO_EMC_B1_21  FMU_CH10 FLEXPWM3_PWM3_A + FLEXIO1_IO21
+// GPIO_EMC_B1_00  FMU_CH11 FLEXPWM4_PWM0_A + FLEXIO1_IO00
+// GPIO_EMC_B1_02  FMU_CH12 FLEXPWM4_PWM1_A + FLEXIO1_IO02
+
+
+constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
+	initIOPWM(PWM::FlexPWM1, PWM::Submodule0),
+	initIOPWM(PWM::FlexPWM1, PWM::Submodule1),
+	initIOPWM(PWM::FlexPWM1, PWM::Submodule2),
+	initIOPWM(PWM::FlexPWM2, PWM::Submodule0),
+	initIOPWM(PWM::FlexPWM2, PWM::Submodule1),
+	initIOPWM(PWM::FlexPWM2, PWM::Submodule2),
+	initIOPWM(PWM::FlexPWM2, PWM::Submodule3),
+	initIOPWM(PWM::FlexPWM3, PWM::Submodule0),
+	initIOPWM(PWM::FlexPWM3, PWM::Submodule1),
+	initIOPWM(PWM::FlexPWM3, PWM::Submodule3),
+	initIOPWM(PWM::FlexPWM4, PWM::Submodule0),
+	initIOPWM(PWM::FlexPWM4, PWM::Submodule1),
+};
+
+constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
+	/* FMU_CH1  */  initIOTimerChannel(io_timers, {PWM::PWM1_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_23),
+	/* FMU_CH2  */  initIOTimerChannel(io_timers, {PWM::PWM1_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_25),
+	/* FMU_CH3  */  initIOTimerChannel(io_timers, {PWM::PWM1_PWM_A, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_B1_27),
+	/* FMU_CH4  */  initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_06),
+	/* FMU_CH5  */  initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_08),
+	/* FMU_CH6  */  initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_B1_10),
+	/* FMU_CH7  */  initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule3}, IOMUX::Pad::GPIO_EMC_B1_19),
+	/* FMU_CH8  */  initIOTimerChannel(io_timers, {PWM::PWM3_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_29),
+	/* FMU_CH9  */  initIOTimerChannel(io_timers, {PWM::PWM3_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_31),
+	/* FMU_CH10 */  initIOTimerChannel(io_timers, {PWM::PWM3_PWM_A, PWM::Submodule3}, IOMUX::Pad::GPIO_EMC_B1_21),
+	/* FMU_CH11 */  initIOTimerChannel(io_timers, {PWM::PWM4_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_00),
+	/* FMU_CH12 */  initIOTimerChannel(io_timers, {PWM::PWM4_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_02),
+};
+
+
+constexpr io_timers_channel_mapping_t io_timers_channel_mapping =
+	initIOTimerChannelMapping(io_timers, timer_io_channels);
+
+constexpr io_timers_t led_pwm_timers[MAX_LED_TIMERS] = {
+};
+
+constexpr timer_io_channels_t led_pwm_channels[MAX_TIMER_LED_CHANNELS] = {
+};
+
+
+void fmuv6xrt_timer_initialize(void)
+{
+	/* We must configure Qtimer 3 as the bus_clk_root which is
+	 * BUS_CLK_ROOT_SYS_PLL3_CLK / 2 = 240 Mhz
+	 * devided by 15 by to yield 16 Mhz
+	 * and deliver that clock to the eFlexPWM1,2,34 via XBAR
+	 *
+	 * IPG    = 240 Mhz
+	 * 16Mhz  = 240 / 15
+	 * COMP 1 = 8, COMP2 = 7
+	 *
+	 * */
+	/* Enable Block Clocks for Qtimer and XBAR1 */
+
+	imxrt_clockall_timer3();
+	imxrt_clockall_xbar1();
+
+	/* Disable Timer */
+
+	rCTRL = 0;
+	rCOMP1 = 8 - 1; // N - 1
+	rCOMP2 = 7 - 1;
+
+	rCAPT = 0;
+	rLOAD = 0;
+	rCNTR = 0;
+
+	rSCTRL = TMR_SCTRL_OEN;
+
+	rCMPLD1 = 0;
+	rCMPLD2 = 0;
+	rCSCTRL = 0;
+	rFILT   = 0;
+	rDMA    = 0;
+
+	/* Count rising edges of primary source,
+	 * Prescaler is /1
+	 * Count UP until compare, then re-initialize. a successful compare occurs when the counter reaches a COMP1 value.
+	 * Toggle OFLAG output using alternating compare registers
+	 */
+	rCTRL   = (TMR_CTRL_CM_MODE1 | TMR_CTRL_PCS_DIV1 | TMR_CTRL_LENGTH | TMR_CTRL_OUTMODE_TOG_ALT);
+
+	/* QTIMER3_TIMER0  -> Flexpwm1,2,34ExtClk  */
+
+	imxrt_xbar_connect(IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET, IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT);
+	imxrt_xbar_connect(IMXRT_XBARA1_OUT_FLEXPWM2_EXT_CLK_SEL_OFFSET, IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT);
+	imxrt_xbar_connect(IMXRT_XBARA1_OUT_FLEXPWM34_EXT_CLK_SEL_OFFSET, IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT);
+}
@@ -0,0 +1,131 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2016, 2018 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file usb.c
+ *
+ * Board-specific USB functions.
+ */
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <px4_platform_common/px4_config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/usb/usbdev.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include <arm_internal.h>
+#include <chip.h>
+#include <hardware/imxrt_usb_analog.h>
+#include "board_config.h"
+#include "imxrt_periphclks.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+int imxrt_usb_initialize(void)
+{
+	imxrt_clockall_usboh3();
+	return 0;
+}
+/************************************************************************************
+ * Name:  imxrt_usbpullup
+ *
+ * Description:
+ *   If USB is supported and the board supports a pullup via GPIO (for USB software
+ *   connect and disconnect), then the board software must provide imxrt_usbpullup.
+ *   See include/nuttx/usb/usbdev.h for additional description of this method.
+ *   Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be
+ *   NULL.
+ *
+ ************************************************************************************/
+
+__EXPORT
+int imxrt_usbpullup(FAR struct usbdev_s *dev, bool enable)
+{
+	usbtrace(TRACE_DEVPULLUP, (uint16_t)enable);
+
+	return OK;
+}
+
+/************************************************************************************
+ * Name:  imxrt_usbsuspend
+ *
+ * Description:
+ *   Board logic must provide the imxrt_usbsuspend logic if the USBDEV driver is
+ *   used.  This function is called whenever the USB enters or leaves suspend mode.
+ *   This is an opportunity for the board logic to shutdown clocks, power, etc.
+ *   while the USB is suspended.
+ *
+ ************************************************************************************/
+
+__EXPORT
+void imxrt_usbsuspend(FAR struct usbdev_s *dev, bool resume)
+{
+	uinfo("resume: %d\n", resume);
+}
+
+/************************************************************************************
+ * Name: board_read_VBUS_state
+ *
+ * Description:
+ *   All boards must provide a way to read the state of VBUS, this my be simple
+ *   digital input on a GPIO. Or something more complicated like a Analong input
+ *   or reading a bit from a USB controller register.
+ *
+ * Returns -  0 if connected.
+ *
+ ************************************************************************************/
+#undef IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT
+#define USB1_VBUS_DET_STAT_OFFSET               0xd0
+#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT (IMXRT_USBPHY1_BASE + USB1_VBUS_DET_STAT_OFFSET)
+
+int board_read_VBUS_state(void)
+{
+	return (getreg32(IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT) & USB_ANALOG_USB_VBUS_DETECT_STAT_VBUS_3V_VALID) ? 0 : 1;
+}
@@ -266,6 +266,7 @@ else()
 		-fno-exceptions
 		-fno-rtti
 		-Wl,--script=${NUTTX_CONFIG_DIR_CYG}/scripts/${SCRIPT_PREFIX}script.ld
+		-L${NUTTX_CONFIG_DIR_CYG}/scripts/${SCRIPT_PREFIX}
 		-Wl,-Map=${PX4_CONFIG}.map
 		-Wl,--warn-common
 		-Wl,--gc-sections
@@ -383,6 +384,9 @@ if(NOT NUTTX_DIR MATCHES "external")
 	if(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A)
 		set(DEBUG_DEVICE "MIMXRT1062XXX6A")
 		set(DEBUG_SVD_FILE "MIMXRT1052.svd")
+	elseif(CONFIG_ARCH_CHIP_MIMXRT1176DVMAA)
+		set(DEBUG_DEVICE "MIMXRT1176DVMAA")
+		set(DEBUG_SVD_FILE "MIMXRT1176_cm7.xml")
 	elseif(CONFIG_ARCH_CHIP_MK66FN2M0VMD18)
 		set(DEBUG_DEVICE "MK66FN2M0xxx18")
 		set(DEBUG_SVD_FILE "MK66F18.svd")
@@ -294,13 +294,13 @@ void
 jump_to_app()
 {
 	const uint32_t *app_base = (const uint32_t *)APP_LOAD_ADDRESS;
-	const uint32_t *vec_base = (const uint32_t *)app_base;
+	const uint32_t *vec_base = (const uint32_t *)app_base + APP_VECTOR_OFFSET;

 	/*
 	 * We refuse to program the first word of the app until the upload is marked
 	 * complete by the host.  So if it's not 0xffffffff, we should try booting it.
 	 */
-	if (app_base[0] == 0xffffffff) {
+	if (app_base[APP_VECTOR_OFFSET_WORDS] == 0xffffffff) {
 		return;
 	}

@@ -382,11 +382,11 @@ jump_to_app()
 	 * The second word of the app is the entrypoint; it must point within the
 	 * flash area (or we have a bad flash).
 	 */
-	if (app_base[1] < APP_LOAD_ADDRESS) {
+	if (app_base[APP_VECTOR_OFFSET_WORDS + 1] < APP_LOAD_ADDRESS) {
 		return;
 	}

-	if (app_base[1] >= (APP_LOAD_ADDRESS + board_info.fw_size)) {
+	if (app_base[APP_VECTOR_OFFSET_WORDS + 1] >= (APP_LOAD_ADDRESS + board_info.fw_size)) {
 		return;
 	}

@@ -816,15 +816,17 @@ bootloader(unsigned timeout)
 				goto cmd_bad;
 			}

-			if (address == 0) {
+#if APP_VECTOR_OFFSET == 0

-#if defined(TARGET_HW_PX4_FMU_V4)
+			if (address == APP_VECTOR_OFFSET) {
+
+#  if defined(TARGET_HW_PX4_FMU_V4)

 				if (check_silicon()) {
 					goto bad_silicon;
 				}

-#endif
+# endif

 				// save the first word and don't program it until everything else is done
 				first_word = flash_buffer.w[0];
@@ -832,10 +834,20 @@ bootloader(unsigned timeout)
 				flash_buffer.w[0] = 0xffffffff;
 			}

+#endif
 			arg /= 4;

 			for (int i = 0; i < arg; i++) {
+#if APP_VECTOR_OFFSET != 0

+				if (address == APP_VECTOR_OFFSET) {
+					// save the first word from vector table and don't program it until everything else is done
+					first_word = flash_buffer.w[i];
+					// replace first word with bits we can overwrite later
+					flash_buffer.w[i] = 0xffffffff;
+				}
+
+#endif
 				// program the word
 				flash_func_write_word(address, flash_buffer.w[i]);

@@ -869,7 +881,7 @@ bootloader(unsigned timeout)
 			for (unsigned p = 0; p < board_info.fw_size; p += 4) {
 				uint32_t bytes;

-				if ((p == 0) && (first_word != 0xffffffff)) {
+				if ((p == APP_VECTOR_OFFSET) && (first_word != 0xffffffff)) {
 					bytes = first_word;

 				} else {
@@ -1032,9 +1044,9 @@ bootloader(unsigned timeout)

 			// program the deferred first word
 			if (first_word != 0xffffffff) {
-				flash_func_write_word(0, first_word);
+				flash_func_write_word(APP_VECTOR_OFFSET, first_word);

-				if (flash_func_read_word(0) != first_word) {
+				if (flash_func_read_word(APP_VECTOR_OFFSET) != first_word) {
 					goto cmd_fail;
 				}

@@ -129,3 +129,8 @@ extern void cinit(void *config, uint8_t interface);
 extern void cfini(void);
 extern int cin(uint32_t devices);
 extern void cout(uint8_t *buf, unsigned len);
+
+#if !defined(APP_VECTOR_OFFSET)
+#  define APP_VECTOR_OFFSET 0
+#endif
+#define APP_VECTOR_OFFSET_WORDS (APP_VECTOR_OFFSET/sizeof(uint32_t))
@@ -32,10 +32,13 @@
 ****************************************************************************/

 #include <string.h>
+
 #include "flash_cache.h"

 #include "hw_config.h"

+#include "bl.h"
+
 #include <nuttx/progmem.h>

 extern ssize_t arch_flash_write(uintptr_t address, const void *buffer, size_t buflen);
@@ -54,7 +57,7 @@ inline void fc_reset(void)
 		fcl_reset(&flash_cache[w]);
 	}

-	flash_cache[0].start_address = APP_LOAD_ADDRESS;
+	flash_cache[0].start_address = APP_LOAD_ADDRESS + APP_VECTOR_OFFSET;
 }

 static inline flash_cache_line_t *fc_line_select(uintptr_t address)
@@ -104,7 +107,7 @@ int fc_write(uintptr_t address, uint32_t word)

 		// Are we back writing the first word?

-		if (fc == &flash_cache[0] &&  index == 0 && fc->index == 7) {
+		if (fc == &flash_cache[0] &&  index == 0 && fc->index == FC_LAST_WORD) {

 			if (fc_is_dirty(fc1)) {

@@ -46,10 +46,15 @@
 * *writes to the first 8 words of flash at APP_LOAD_ADDRESS
 * are buffered until the "first word" is written with the real value (not 0xffffffff)
 *
+ * On a imxrt the ROM API supports 256 byte writes.
 */

-#define FC_NUMBER_LINES  2                                  // Number of cache lines.
+#if defined(CONFIG_ARCH_CHIP_IMXRT)
+#define FC_NUMBER_WORDS  64                                  // Number of words per page
+#else
 #define FC_NUMBER_WORDS  8                                  // Number of words per cache line.
+#endif
+#define FC_NUMBER_LINES  2                                  // Number of cache lines.
 #define FC_LAST_WORD     FC_NUMBER_WORDS-1                  // The index of the last word in cache line.
 #define FC_ADDRESS_MASK  ~(sizeof(flash_cache[0].words)-1)  // Cache tag from address
 #define FC_ADDR2INDX(a)   (((a) / sizeof(flash_cache[0].words[0])) % FC_NUMBER_WORDS) // index from address
@@ -0,0 +1,34 @@
+############################################################################
+#
+#   Copyright (c) 2023 PX4 Development Team. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name PX4 nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+add_subdirectory(${PX4_CHIP})
@@ -0,0 +1,43 @@
+############################################################################
+#
+#   Copyright (c) 2023 PX4 Development Team. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name PX4 nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+px4_add_library(arch_bootloader
+	main.c
+	systick.c
+)
+
+target_link_libraries(arch_bootloader
+	PRIVATE
+		bootloader_lib
+		nuttx_arch
+)
--- a/Show More
+++ b/Show More