mirror of
https://github.com/PX4/PX4-Autopilot.git
synced 2026-06-01 11:06:04 +08:00
Removed CMSIS.
This commit is contained in:
James Goppert
committed by
Lorenz Meier
Lorenz Meier
parent
425c5dea2a
commit
d02abf2cc0
@@ -599,8 +599,7 @@ RECURSIVE = YES
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# excluded from the INPUT source files. This way you can easily exclude a
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# excluded from the INPUT source files. This way you can easily exclude a
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# subdirectory from a directory tree whose root is specified with the INPUT tag.
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# subdirectory from a directory tree whose root is specified with the INPUT tag.
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EXCLUDE = ../src/lib/mathlib/CMSIS \
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EXCLUDE = ../src/modules/attitude_estimator_ekf/codegen
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../src/modules/attitude_estimator_ekf/codegen
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# The EXCLUDE_SYMLINKS tag can be used select whether or not files or
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# The EXCLUDE_SYMLINKS tag can be used select whether or not files or
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# directories that are symbolic links (a Unix filesystem feature) are excluded
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# directories that are symbolic links (a Unix filesystem feature) are excluded
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@@ -34,7 +34,6 @@ for fn in $(find src/examples \
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-path './mavlink' -prune -o \
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-path './mavlink' -prune -o \
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-path './NuttX' -prune -o \
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-path './NuttX' -prune -o \
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-path './src/lib/eigen' -prune -o \
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-path './src/lib/eigen' -prune -o \
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-path './src/lib/mathlib/CMSIS' -prune -o \
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-path './src/modules/uavcan/libuavcan' -prune -o \
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-path './src/modules/uavcan/libuavcan' -prune -o \
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-path './src/modules/attitude_estimator_ekf/codegen' -prune -o \
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-path './src/modules/attitude_estimator_ekf/codegen' -prune -o \
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-path './src/modules/ekf_att_pos_estimator' -prune -o \
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-path './src/modules/ekf_att_pos_estimator' -prune -o \
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@@ -103,7 +103,6 @@ set(config_module_list
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#
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#
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# Libraries
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# Libraries
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#
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#
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#lib/mathlib/CMSIS
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lib/mathlib
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lib/mathlib
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lib/mathlib/math/filter
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lib/mathlib/math/filter
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lib/ecl
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lib/ecl
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@@ -165,11 +164,9 @@ set(config_io_board
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)
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)
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set(config_extra_libs
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set(config_extra_libs
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${CMAKE_SOURCE_DIR}/src/lib/mathlib/CMSIS/libarm_cortexM4lf_math.a
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)
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)
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set(config_io_extra_libs
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set(config_io_extra_libs
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#${CMAKE_SOURCE_DIR}/src/lib/mathlib/CMSIS/libarm_cortexM3l_math.a
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)
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)
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add_custom_target(sercon)
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add_custom_target(sercon)
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@@ -112,7 +112,6 @@ set(config_module_list
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#
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#
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# Libraries
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# Libraries
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#
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#
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#lib/mathlib/CMSIS
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lib/mathlib
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lib/mathlib
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lib/mathlib/math/filter
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lib/mathlib/math/filter
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lib/ecl
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lib/ecl
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@@ -174,13 +173,11 @@ set(config_io_board
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)
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)
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set(config_extra_libs
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set(config_extra_libs
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${CMAKE_SOURCE_DIR}/src/lib/mathlib/CMSIS/libarm_cortexM4lf_math.a
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uavcan
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uavcan
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uavcan_stm32_driver
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uavcan_stm32_driver
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)
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)
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set(config_io_extra_libs
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set(config_io_extra_libs
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#${CMAKE_SOURCE_DIR}/src/lib/mathlib/CMSIS/libarm_cortexM3l_math.a
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)
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)
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add_custom_target(sercon)
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add_custom_target(sercon)
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@@ -112,7 +112,6 @@ set(config_module_list
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#
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#
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# Libraries
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# Libraries
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#
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#
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#lib/mathlib/CMSIS
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lib/mathlib
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lib/mathlib
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lib/mathlib/math/filter
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lib/mathlib/math/filter
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lib/ecl
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lib/ecl
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@@ -174,13 +173,11 @@ set(config_io_board
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)
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)
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set(config_extra_libs
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set(config_extra_libs
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${CMAKE_SOURCE_DIR}/src/lib/mathlib/CMSIS/libarm_cortexM4lf_math.a
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uavcan
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uavcan
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uavcan_stm32_driver
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uavcan_stm32_driver
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)
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)
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set(config_io_extra_libs
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set(config_io_extra_libs
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#${CMAKE_SOURCE_DIR}/src/lib/mathlib/CMSIS/libarm_cortexM3l_math.a
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)
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)
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add_custom_target(sercon)
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add_custom_target(sercon)
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@@ -111,7 +111,6 @@ set(config_module_list
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#
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#
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# Libraries
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# Libraries
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#
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#
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#lib/mathlib/CMSIS
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lib/mathlib
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lib/mathlib
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lib/mathlib/math/filter
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lib/mathlib/math/filter
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lib/rc
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lib/rc
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@@ -170,13 +169,11 @@ set(config_extra_builtin_cmds
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)
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)
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set(config_extra_libs
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set(config_extra_libs
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${CMAKE_SOURCE_DIR}/src/lib/mathlib/CMSIS/libarm_cortexM4lf_math.a
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uavcan
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uavcan
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uavcan_stm32_driver
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uavcan_stm32_driver
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)
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)
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set(config_io_extra_libs
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set(config_io_extra_libs
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#${CMAKE_SOURCE_DIR}/src/lib/mathlib/CMSIS/libarm_cortexM3l_math.a
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)
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)
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add_custom_target(sercon)
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add_custom_target(sercon)
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@@ -1,264 +0,0 @@
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/**************************************************************************//**
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* @file ARMCM3.h
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* @brief CMSIS Core Peripheral Access Layer Header File for
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* ARMCM3 Device Series
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* @version V1.07
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* @date 30. January 2012
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*
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* @note
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* Copyright (C) 2012 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef ARMCM3_H
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#define ARMCM3_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ------------------------- Interrupt Number Definition ------------------------ */
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typedef enum IRQn
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{
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/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
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/* ---------------------- ARMCM3 Specific Interrupt Numbers --------------------- */
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WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
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RTC_IRQn = 1, /*!< Real Time Clock Interrupt */
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TIM0_IRQn = 2, /*!< Timer0 / Timer1 Interrupt */
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TIM2_IRQn = 3, /*!< Timer2 / Timer3 Interrupt */
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MCIA_IRQn = 4, /*!< MCIa Interrupt */
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MCIB_IRQn = 5, /*!< MCIb Interrupt */
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UART0_IRQn = 6, /*!< UART0 Interrupt */
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UART1_IRQn = 7, /*!< UART1 Interrupt */
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UART2_IRQn = 8, /*!< UART2 Interrupt */
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UART4_IRQn = 9, /*!< UART4 Interrupt */
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AACI_IRQn = 10, /*!< AACI / AC97 Interrupt */
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CLCD_IRQn = 11, /*!< CLCD Combined Interrupt */
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ENET_IRQn = 12, /*!< Ethernet Interrupt */
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USBDC_IRQn = 13, /*!< USB Device Interrupt */
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USBHC_IRQn = 14, /*!< USB Host Controller Interrupt */
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CHLCD_IRQn = 15, /*!< Character LCD Interrupt */
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FLEXRAY_IRQn = 16, /*!< Flexray Interrupt */
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CAN_IRQn = 17, /*!< CAN Interrupt */
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LIN_IRQn = 18, /*!< LIN Interrupt */
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I2C_IRQn = 19, /*!< I2C ADC/DAC Interrupt */
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CPU_CLCD_IRQn = 28, /*!< CPU CLCD Combined Interrupt */
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UART3_IRQn = 30, /*!< UART3 Interrupt */
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SPI_IRQn = 31, /*!< SPI Touchscreen Interrupt */
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} IRQn_Type;
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
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#define __CM3_REV 0x0201 /*!< Core revision r2p1 */
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#define __MPU_PRESENT 1 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#include <core_cm3.h> /* Processor and core peripherals */
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/* NuttX */
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//#include "system_ARMCM3.h" /* System Header */
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/* ================================================================================ */
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/* ================ Device Specific Peripheral Section ================ */
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/* ================================================================================ */
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/* ------------------- Start of section using anonymous unions ------------------ */
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#if defined(__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined(__ICCARM__)
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#pragma language=extended
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined(__TASKING__)
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#pragma warning 586
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#else
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#warning Not supported compiler type
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#endif
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/* ================================================================================ */
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/* ================ CPU FPGA System (CPU_SYS) ================ */
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/* ================================================================================ */
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typedef struct
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{
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__I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
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__IO uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
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__I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
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__IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
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__I uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
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__IO uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
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uint32_t RESERVED0[2];
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__IO uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
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__IO uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
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__IO uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
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uint32_t RESERVED1[3];
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__IO uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
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__IO uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
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} ARM_CPU_SYS_TypeDef;
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/* ================================================================================ */
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/* ================ DUT FPGA System (DUT_SYS) ================ */
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/* ================================================================================ */
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typedef struct
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{
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__I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
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__IO uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
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__I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
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__IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
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__IO uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
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__I uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
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__I uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
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} ARM_DUT_SYS_TypeDef;
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/* ================================================================================ */
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/* ================ Timer (TIM) ================ */
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/* ================================================================================ */
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typedef struct
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{
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__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
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__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
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__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
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__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
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__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
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__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
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__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
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uint32_t RESERVED0[1];
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__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
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__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
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__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
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__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
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__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
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__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
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__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
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} ARM_TIM_TypeDef;
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/* ================================================================================ */
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/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
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/* ================================================================================ */
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typedef struct
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{
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__IO uint32_t DR; /* Offset: 0x000 (R/W) Data */
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union {
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__I uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
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__O uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
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};
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uint32_t RESERVED0[4];
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__IO uint32_t FR; /* Offset: 0x018 (R/W) Flags */
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uint32_t RESERVED1[1];
|
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__IO uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
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__IO uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
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__IO uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
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__IO uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
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__IO uint32_t CR; /* Offset: 0x030 (R/W) Control */
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__IO uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
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__IO uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
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__IO uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
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__IO uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
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__O uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
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__IO uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
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} ARM_UART_TypeDef;
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/* -------------------- End of section using anonymous unions ------------------- */
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#if defined(__CC_ARM)
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#pragma pop
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#elif defined(__ICCARM__)
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/* leave anonymous unions enabled */
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__TMS470__)
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||||||
/* anonymous unions are enabled by default */
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#elif defined(__TASKING__)
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#pragma warning restore
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#else
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#warning Not supported compiler type
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#endif
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/* ================================================================================ */
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|
||||||
/* ================ Peripheral memory map ================ */
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* -------------------------- CPU FPGA memory map ------------------------------- */
|
|
||||||
#define ARM_FLASH_BASE (0x00000000UL)
|
|
||||||
#define ARM_RAM_BASE (0x20000000UL)
|
|
||||||
#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
|
|
||||||
#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
|
|
||||||
|
|
||||||
#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000)
|
|
||||||
#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000)
|
|
||||||
|
|
||||||
/* -------------------------- DUT FPGA memory map ------------------------------- */
|
|
||||||
#define ARM_APB_BASE (0x40000000UL)
|
|
||||||
#define ARM_AHB_BASE (0x4FF00000UL)
|
|
||||||
#define ARM_DMC_BASE (0x60000000UL)
|
|
||||||
#define ARM_SMC_BASE (0xA0000000UL)
|
|
||||||
|
|
||||||
#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000)
|
|
||||||
#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000)
|
|
||||||
#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000)
|
|
||||||
#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000)
|
|
||||||
#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000)
|
|
||||||
#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000)
|
|
||||||
#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000)
|
|
||||||
|
|
||||||
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* ================ Peripheral declaration ================ */
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* -------------------------- CPU FPGA Peripherals ------------------------------ */
|
|
||||||
#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
|
|
||||||
#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
|
|
||||||
|
|
||||||
/* -------------------------- DUT FPGA Peripherals ------------------------------ */
|
|
||||||
#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
|
|
||||||
#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
|
|
||||||
#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
|
|
||||||
#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
|
|
||||||
#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
|
|
||||||
#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
|
|
||||||
#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* ARMCM3_H */
|
|
||||||
@@ -1,265 +0,0 @@
|
|||||||
/**************************************************************************//**
|
|
||||||
* @file ARMCM4.h
|
|
||||||
* @brief CMSIS Core Peripheral Access Layer Header File for
|
|
||||||
* ARMCM4 Device Series
|
|
||||||
* @version V1.07
|
|
||||||
* @date 30. January 2012
|
|
||||||
*
|
|
||||||
* @note
|
|
||||||
* Copyright (C) 2012 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* @par
|
|
||||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
|
||||||
* processor based microcontrollers. This file can be freely distributed
|
|
||||||
* within development tools that are supporting such ARM based processors.
|
|
||||||
*
|
|
||||||
* @par
|
|
||||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
|
||||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
|
||||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
|
||||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#ifndef ARMCM4_H
|
|
||||||
#define ARMCM4_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/* ------------------------- Interrupt Number Definition ------------------------ */
|
|
||||||
|
|
||||||
typedef enum IRQn
|
|
||||||
{
|
|
||||||
/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
|
|
||||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
|
||||||
HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */
|
|
||||||
MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
|
|
||||||
BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
|
|
||||||
UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
|
|
||||||
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
|
|
||||||
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
|
|
||||||
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
|
|
||||||
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
|
|
||||||
|
|
||||||
/* ---------------------- ARMCM4 Specific Interrupt Numbers --------------------- */
|
|
||||||
WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
|
|
||||||
RTC_IRQn = 1, /*!< Real Time Clock Interrupt */
|
|
||||||
TIM0_IRQn = 2, /*!< Timer0 / Timer1 Interrupt */
|
|
||||||
TIM2_IRQn = 3, /*!< Timer2 / Timer3 Interrupt */
|
|
||||||
MCIA_IRQn = 4, /*!< MCIa Interrupt */
|
|
||||||
MCIB_IRQn = 5, /*!< MCIb Interrupt */
|
|
||||||
UART0_IRQn = 6, /*!< UART0 Interrupt */
|
|
||||||
UART1_IRQn = 7, /*!< UART1 Interrupt */
|
|
||||||
UART2_IRQn = 8, /*!< UART2 Interrupt */
|
|
||||||
UART4_IRQn = 9, /*!< UART4 Interrupt */
|
|
||||||
AACI_IRQn = 10, /*!< AACI / AC97 Interrupt */
|
|
||||||
CLCD_IRQn = 11, /*!< CLCD Combined Interrupt */
|
|
||||||
ENET_IRQn = 12, /*!< Ethernet Interrupt */
|
|
||||||
USBDC_IRQn = 13, /*!< USB Device Interrupt */
|
|
||||||
USBHC_IRQn = 14, /*!< USB Host Controller Interrupt */
|
|
||||||
CHLCD_IRQn = 15, /*!< Character LCD Interrupt */
|
|
||||||
FLEXRAY_IRQn = 16, /*!< Flexray Interrupt */
|
|
||||||
CAN_IRQn = 17, /*!< CAN Interrupt */
|
|
||||||
LIN_IRQn = 18, /*!< LIN Interrupt */
|
|
||||||
I2C_IRQn = 19, /*!< I2C ADC/DAC Interrupt */
|
|
||||||
CPU_CLCD_IRQn = 28, /*!< CPU CLCD Combined Interrupt */
|
|
||||||
UART3_IRQn = 30, /*!< UART3 Interrupt */
|
|
||||||
SPI_IRQn = 31, /*!< SPI Touchscreen Interrupt */
|
|
||||||
} IRQn_Type;
|
|
||||||
|
|
||||||
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* ================ Processor and Core Peripheral Section ================ */
|
|
||||||
/* ================================================================================ */
|
|
||||||
|
|
||||||
/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
|
|
||||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
|
||||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
|
||||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
|
||||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
|
||||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
|
||||||
|
|
||||||
#include <core_cm4.h> /* Processor and core peripherals */
|
|
||||||
/* NuttX */
|
|
||||||
//#include "system_ARMCM4.h" /* System Header */
|
|
||||||
|
|
||||||
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* ================ Device Specific Peripheral Section ================ */
|
|
||||||
/* ================================================================================ */
|
|
||||||
|
|
||||||
/* ------------------- Start of section using anonymous unions ------------------ */
|
|
||||||
#if defined(__CC_ARM)
|
|
||||||
#pragma push
|
|
||||||
#pragma anon_unions
|
|
||||||
#elif defined(__ICCARM__)
|
|
||||||
#pragma language=extended
|
|
||||||
#elif defined(__GNUC__)
|
|
||||||
/* anonymous unions are enabled by default */
|
|
||||||
#elif defined(__TMS470__)
|
|
||||||
/* anonymous unions are enabled by default */
|
|
||||||
#elif defined(__TASKING__)
|
|
||||||
#pragma warning 586
|
|
||||||
#else
|
|
||||||
#warning Not supported compiler type
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* ================ CPU FPGA System (CPU_SYS) ================ */
|
|
||||||
/* ================================================================================ */
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
__I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
|
|
||||||
__IO uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
|
|
||||||
__I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
|
|
||||||
__IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
|
|
||||||
__I uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
|
|
||||||
__IO uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
|
|
||||||
uint32_t RESERVED0[2];
|
|
||||||
__IO uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
|
|
||||||
__IO uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
|
|
||||||
__IO uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
|
|
||||||
uint32_t RESERVED1[3];
|
|
||||||
__IO uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
|
|
||||||
__IO uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
|
|
||||||
} ARM_CPU_SYS_TypeDef;
|
|
||||||
|
|
||||||
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* ================ DUT FPGA System (DUT_SYS) ================ */
|
|
||||||
/* ================================================================================ */
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
__I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
|
|
||||||
__IO uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
|
|
||||||
__I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
|
|
||||||
__IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
|
|
||||||
__IO uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
|
|
||||||
__I uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
|
|
||||||
__I uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
|
|
||||||
} ARM_DUT_SYS_TypeDef;
|
|
||||||
|
|
||||||
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* ================ Timer (TIM) ================ */
|
|
||||||
/* ================================================================================ */
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
|
|
||||||
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
|
|
||||||
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
|
|
||||||
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
|
|
||||||
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
|
|
||||||
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
|
|
||||||
__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
|
|
||||||
uint32_t RESERVED0[1];
|
|
||||||
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
|
|
||||||
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
|
|
||||||
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
|
|
||||||
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
|
|
||||||
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
|
|
||||||
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
|
|
||||||
__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
|
|
||||||
} ARM_TIM_TypeDef;
|
|
||||||
|
|
||||||
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
|
|
||||||
/* ================================================================================ */
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
__IO uint32_t DR; /* Offset: 0x000 (R/W) Data */
|
|
||||||
union {
|
|
||||||
__I uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
|
|
||||||
__O uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
|
|
||||||
};
|
|
||||||
uint32_t RESERVED0[4];
|
|
||||||
__IO uint32_t FR; /* Offset: 0x018 (R/W) Flags */
|
|
||||||
uint32_t RESERVED1[1];
|
|
||||||
__IO uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
|
|
||||||
__IO uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
|
|
||||||
__IO uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
|
|
||||||
__IO uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
|
|
||||||
__IO uint32_t CR; /* Offset: 0x030 (R/W) Control */
|
|
||||||
__IO uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
|
|
||||||
__IO uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
|
|
||||||
__IO uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
|
|
||||||
__IO uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
|
|
||||||
__O uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
|
|
||||||
__IO uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
|
|
||||||
} ARM_UART_TypeDef;
|
|
||||||
|
|
||||||
|
|
||||||
/* -------------------- End of section using anonymous unions ------------------- */
|
|
||||||
#if defined(__CC_ARM)
|
|
||||||
#pragma pop
|
|
||||||
#elif defined(__ICCARM__)
|
|
||||||
/* leave anonymous unions enabled */
|
|
||||||
#elif defined(__GNUC__)
|
|
||||||
/* anonymous unions are enabled by default */
|
|
||||||
#elif defined(__TMS470__)
|
|
||||||
/* anonymous unions are enabled by default */
|
|
||||||
#elif defined(__TASKING__)
|
|
||||||
#pragma warning restore
|
|
||||||
#else
|
|
||||||
#warning Not supported compiler type
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* ================ Peripheral memory map ================ */
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* -------------------------- CPU FPGA memory map ------------------------------- */
|
|
||||||
#define ARM_FLASH_BASE (0x00000000UL)
|
|
||||||
#define ARM_RAM_BASE (0x20000000UL)
|
|
||||||
#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
|
|
||||||
#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
|
|
||||||
|
|
||||||
#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000)
|
|
||||||
#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000)
|
|
||||||
|
|
||||||
/* -------------------------- DUT FPGA memory map ------------------------------- */
|
|
||||||
#define ARM_APB_BASE (0x40000000UL)
|
|
||||||
#define ARM_AHB_BASE (0x4FF00000UL)
|
|
||||||
#define ARM_DMC_BASE (0x60000000UL)
|
|
||||||
#define ARM_SMC_BASE (0xA0000000UL)
|
|
||||||
|
|
||||||
#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000)
|
|
||||||
#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000)
|
|
||||||
#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000)
|
|
||||||
#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000)
|
|
||||||
#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000)
|
|
||||||
#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000)
|
|
||||||
#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000)
|
|
||||||
|
|
||||||
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* ================ Peripheral declaration ================ */
|
|
||||||
/* ================================================================================ */
|
|
||||||
/* -------------------------- CPU FPGA Peripherals ------------------------------ */
|
|
||||||
#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
|
|
||||||
#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
|
|
||||||
|
|
||||||
/* -------------------------- DUT FPGA Peripherals ------------------------------ */
|
|
||||||
#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
|
|
||||||
#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
|
|
||||||
#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
|
|
||||||
#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
|
|
||||||
#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
|
|
||||||
#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
|
|
||||||
#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* ARMCM4_H */
|
|
||||||
@@ -1,93 +0,0 @@
|
|||||||
/* ----------------------------------------------------------------------
|
|
||||||
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* $Date: 17. January 2013
|
|
||||||
* $Revision: V1.4.1
|
|
||||||
*
|
|
||||||
* Project: CMSIS DSP Library
|
|
||||||
* Title: arm_common_tables.h
|
|
||||||
*
|
|
||||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
|
|
||||||
*
|
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
* - Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* - Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this
|
|
||||||
* software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
#ifndef _ARM_COMMON_TABLES_H
|
|
||||||
#define _ARM_COMMON_TABLES_H
|
|
||||||
|
|
||||||
#include "arm_math.h"
|
|
||||||
|
|
||||||
extern const uint16_t armBitRevTable[1024];
|
|
||||||
extern const q15_t armRecipTableQ15[64];
|
|
||||||
extern const q31_t armRecipTableQ31[64];
|
|
||||||
extern const q31_t realCoefAQ31[1024];
|
|
||||||
extern const q31_t realCoefBQ31[1024];
|
|
||||||
extern const float32_t twiddleCoef_16[32];
|
|
||||||
extern const float32_t twiddleCoef_32[64];
|
|
||||||
extern const float32_t twiddleCoef_64[128];
|
|
||||||
extern const float32_t twiddleCoef_128[256];
|
|
||||||
extern const float32_t twiddleCoef_256[512];
|
|
||||||
extern const float32_t twiddleCoef_512[1024];
|
|
||||||
extern const float32_t twiddleCoef_1024[2048];
|
|
||||||
extern const float32_t twiddleCoef_2048[4096];
|
|
||||||
extern const float32_t twiddleCoef_4096[8192];
|
|
||||||
#define twiddleCoef twiddleCoef_4096
|
|
||||||
extern const q31_t twiddleCoefQ31[6144];
|
|
||||||
extern const q15_t twiddleCoefQ15[6144];
|
|
||||||
extern const float32_t twiddleCoef_rfft_32[32];
|
|
||||||
extern const float32_t twiddleCoef_rfft_64[64];
|
|
||||||
extern const float32_t twiddleCoef_rfft_128[128];
|
|
||||||
extern const float32_t twiddleCoef_rfft_256[256];
|
|
||||||
extern const float32_t twiddleCoef_rfft_512[512];
|
|
||||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
|
||||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
|
||||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
|
||||||
|
|
||||||
|
|
||||||
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
|
|
||||||
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
|
|
||||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
|
|
||||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
|
|
||||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
|
|
||||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
|
|
||||||
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
|
|
||||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
|
|
||||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
|
|
||||||
|
|
||||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
|
|
||||||
|
|
||||||
#endif /* ARM_COMMON_TABLES_H */
|
|
||||||
@@ -1,85 +0,0 @@
|
|||||||
/* ----------------------------------------------------------------------
|
|
||||||
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* $Date: 17. January 2013
|
|
||||||
* $Revision: V1.4.1
|
|
||||||
*
|
|
||||||
* Project: CMSIS DSP Library
|
|
||||||
* Title: arm_const_structs.h
|
|
||||||
*
|
|
||||||
* Description: This file has constant structs that are initialized for
|
|
||||||
* user convenience. For example, some can be given as
|
|
||||||
* arguments to the arm_cfft_f32() function.
|
|
||||||
*
|
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
* - Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* - Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this
|
|
||||||
* software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
#ifndef _ARM_CONST_STRUCTS_H
|
|
||||||
#define _ARM_CONST_STRUCTS_H
|
|
||||||
|
|
||||||
#include "arm_math.h"
|
|
||||||
#include "arm_common_tables.h"
|
|
||||||
|
|
||||||
const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
|
|
||||||
16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
|
|
||||||
};
|
|
||||||
|
|
||||||
const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
|
|
||||||
32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
|
|
||||||
};
|
|
||||||
|
|
||||||
const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
|
|
||||||
64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
|
|
||||||
};
|
|
||||||
|
|
||||||
const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
|
|
||||||
128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
|
|
||||||
};
|
|
||||||
|
|
||||||
const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
|
|
||||||
256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
|
|
||||||
};
|
|
||||||
|
|
||||||
const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
|
|
||||||
512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
|
|
||||||
};
|
|
||||||
|
|
||||||
const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
|
|
||||||
1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
|
|
||||||
};
|
|
||||||
|
|
||||||
const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
|
|
||||||
2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
|
|
||||||
};
|
|
||||||
|
|
||||||
const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
|
|
||||||
4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,46 +0,0 @@
|
|||||||
############################################################################
|
|
||||||
#
|
|
||||||
# Copyright (c) 2013 PX4 Development Team. All rights reserved.
|
|
||||||
#
|
|
||||||
# Redistribution and use in source and binary forms, with or without
|
|
||||||
# modification, are permitted provided that the following conditions
|
|
||||||
# are met:
|
|
||||||
#
|
|
||||||
# 1. Redistributions of source code must retain the above copyright
|
|
||||||
# notice, this list of conditions and the following disclaimer.
|
|
||||||
# 2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
# notice, this list of conditions and the following disclaimer in
|
|
||||||
# the documentation and/or other materials provided with the
|
|
||||||
# distribution.
|
|
||||||
# 3. Neither the name PX4 nor the names of its contributors may be
|
|
||||||
# used to endorse or promote products derived from this software
|
|
||||||
# without specific prior written permission.
|
|
||||||
#
|
|
||||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
|
||||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
|
||||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
# POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
#
|
|
||||||
############################################################################
|
|
||||||
|
|
||||||
#
|
|
||||||
# ARM CMSIS DSP library
|
|
||||||
#
|
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARCH),CORTEXM4F)
|
|
||||||
PREBUILT_LIB := libarm_cortexM4lf_math.a
|
|
||||||
else ifeq ($(CONFIG_ARCH),CORTEXM4)
|
|
||||||
PREBUILT_LIB := libarm_cortexM4l_math.a
|
|
||||||
else ifeq ($(CONFIG_ARCH),CORTEXM3)
|
|
||||||
PREBUILT_LIB := libarm_cortexM3l_math.a
|
|
||||||
else
|
|
||||||
$(error CONFIG_ARCH value '$(CONFIG_ARCH)' not supported by the DSP library)
|
|
||||||
endif
|
|
||||||
@@ -1,27 +0,0 @@
|
|||||||
All pre-built libraries are guided by the following license:
|
|
||||||
|
|
||||||
Copyright (C) 2009-2012 ARM Limited.
|
|
||||||
All rights reserved.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
- Redistributions of source code must retain the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer.
|
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
|
||||||
to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
@@ -46,11 +46,7 @@
|
|||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
#include <math.h>
|
#include <math.h>
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_ARM
|
|
||||||
#include "../CMSIS/Include/arm_math.h"
|
|
||||||
#else
|
|
||||||
#include "matrix/math.hpp"
|
#include "matrix/math.hpp"
|
||||||
#endif
|
|
||||||
#include <platforms/px4_defines.h>
|
#include <platforms/px4_defines.h>
|
||||||
|
|
||||||
namespace math
|
namespace math
|
||||||
@@ -72,11 +68,7 @@ public:
|
|||||||
/**
|
/**
|
||||||
* struct for using arm_math functions
|
* struct for using arm_math functions
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_ARCH_ARM
|
|
||||||
arm_matrix_instance_f32 arm_mat;
|
|
||||||
#else
|
|
||||||
eigen_matrix_instance arm_mat;
|
eigen_matrix_instance arm_mat;
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* trivial ctor
|
* trivial ctor
|
||||||
@@ -302,47 +294,29 @@ public:
|
|||||||
*/
|
*/
|
||||||
template <unsigned int P>
|
template <unsigned int P>
|
||||||
Matrix<M, P> operator *(const Matrix<N, P> &m) const {
|
Matrix<M, P> operator *(const Matrix<N, P> &m) const {
|
||||||
#ifdef CONFIG_ARCH_ARM
|
|
||||||
Matrix<M, P> res;
|
|
||||||
arm_mat_mult_f32(&arm_mat, &m.arm_mat, &res.arm_mat);
|
|
||||||
return res;
|
|
||||||
#else
|
|
||||||
matrix::Matrix<float, M, N> Me(this->arm_mat.pData);
|
matrix::Matrix<float, M, N> Me(this->arm_mat.pData);
|
||||||
matrix::Matrix<float, N, P> Him(m.arm_mat.pData);
|
matrix::Matrix<float, N, P> Him(m.arm_mat.pData);
|
||||||
matrix::Matrix<float, M, P> Product = Me * Him;
|
matrix::Matrix<float, M, P> Product = Me * Him;
|
||||||
Matrix<M, P> res(Product.data());
|
Matrix<M, P> res(Product.data());
|
||||||
return res;
|
return res;
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* transpose the matrix
|
* transpose the matrix
|
||||||
*/
|
*/
|
||||||
Matrix<N, M> transposed(void) const {
|
Matrix<N, M> transposed(void) const {
|
||||||
#ifdef CONFIG_ARCH_ARM
|
|
||||||
Matrix<N, M> res;
|
|
||||||
arm_mat_trans_f32(&this->arm_mat, &res.arm_mat);
|
|
||||||
return res;
|
|
||||||
#else
|
|
||||||
matrix::Matrix<float, N, M> Me(this->arm_mat.pData);
|
matrix::Matrix<float, N, M> Me(this->arm_mat.pData);
|
||||||
Matrix<N, M> res(Me.transpose().data());
|
Matrix<N, M> res(Me.transpose().data());
|
||||||
return res;
|
return res;
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* invert the matrix
|
* invert the matrix
|
||||||
*/
|
*/
|
||||||
Matrix<M, N> inversed(void) const {
|
Matrix<M, N> inversed(void) const {
|
||||||
#ifdef CONFIG_ARCH_ARM
|
|
||||||
Matrix<M, N> res;
|
|
||||||
arm_mat_inverse_f32(&this->arm_mat, &res.arm_mat);
|
|
||||||
return res;
|
|
||||||
#else
|
|
||||||
matrix::SquareMatrix<float, M> Me = matrix::Matrix<float, M, N>(this->arm_mat.pData);
|
matrix::SquareMatrix<float, M> Me = matrix::Matrix<float, M, N>(this->arm_mat.pData);
|
||||||
Matrix<M, N> res(Me.I().data());
|
Matrix<M, N> res(Me.I().data());
|
||||||
return res;
|
return res;
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
@@ -401,15 +375,10 @@ public:
|
|||||||
* multiplication by a vector
|
* multiplication by a vector
|
||||||
*/
|
*/
|
||||||
Vector<M> operator *(const Vector<N> &v) const {
|
Vector<M> operator *(const Vector<N> &v) const {
|
||||||
#ifdef CONFIG_ARCH_ARM
|
|
||||||
Vector<M> res;
|
|
||||||
arm_mat_mult_f32(&this->arm_mat, &v.arm_col, &res.arm_col);
|
|
||||||
#else
|
|
||||||
matrix::Matrix<float, M, N> Me(this->arm_mat.pData);
|
matrix::Matrix<float, M, N> Me(this->arm_mat.pData);
|
||||||
matrix::Matrix<float, N, 1> Vec(v.arm_col.pData);
|
matrix::Matrix<float, N, 1> Vec(v.arm_col.pData);
|
||||||
matrix::Matrix<float, M, 1> Product = Me * Vec;
|
matrix::Matrix<float, M, 1> Product = Me * Vec;
|
||||||
Vector<M> res(Product.data());
|
Vector<M> res(Product.data());
|
||||||
#endif
|
|
||||||
return res;
|
return res;
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|||||||
@@ -45,12 +45,9 @@
|
|||||||
|
|
||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
#include <math.h>
|
#include <math.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_ARM
|
|
||||||
#include "../CMSIS/Include/arm_math.h"
|
|
||||||
#else
|
|
||||||
#include <platforms/ros/eigen_math.h>
|
#include <platforms/ros/eigen_math.h>
|
||||||
#endif
|
|
||||||
|
|
||||||
#include <platforms/px4_defines.h>
|
#include <platforms/px4_defines.h>
|
||||||
|
|
||||||
@@ -72,11 +69,7 @@ public:
|
|||||||
/**
|
/**
|
||||||
* struct for using arm_math functions, represents column vector
|
* struct for using arm_math functions, represents column vector
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_ARCH_ARM
|
|
||||||
arm_matrix_instance_f32 arm_col;
|
|
||||||
#else
|
|
||||||
eigen_matrix_instance arm_col;
|
eigen_matrix_instance arm_col;
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|||||||
@@ -47,9 +47,3 @@
|
|||||||
#include "math/Limits.hpp"
|
#include "math/Limits.hpp"
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_ARM
|
|
||||||
|
|
||||||
#include "CMSIS/Include/arm_math.h"
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|||||||
Reference in New Issue
Block a user