mirror of
https://github.com/PX4/PX4-Autopilot.git
synced 2026-09-29 12:32:05 +08:00
Costmet clean, whitespace, carriage-return removal
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4274 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
@@ -356,7 +356,7 @@
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mtc0 k0, MIPS32_CP0_STATUS
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ehb
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mtc0 k1, MIPS32_CP0_EPC
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eret
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eret
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nop
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.endm
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@@ -132,7 +132,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
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*/
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irq = ((regval) & INT_INTSTAT_VEC_MASK) >> INT_INTSTAT_VEC_SHIFT;
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/* Deliver the IRQ */
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irq_dispatch(irq, regs);
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@@ -153,7 +153,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
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#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS
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/* I think there are some task switching issues here. You should not
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* enable nested interrupts unless you are ready to deal with the
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* enable nested interrupts unless you are ready to deal with the
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* complexities of nested context switching. The logic here is probably
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* insufficient.
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*/
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@@ -120,10 +120,10 @@ static inline unsigned int pic32mx_pinno(uint16_t pinset)
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* Description:
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* Configure a GPIO pin based on bit-encoded description of the pin (the
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* interrupt will be configured when pic32mx_attach() is called.
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*
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*
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* Returned Value:
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* OK on success; negated errno on failure.
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*
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*
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****************************************************************************/
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int pic32mx_configgpio(uint16_t cfgset)
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@@ -188,13 +188,13 @@ void pic32mx_gpioirqinitialize(void)
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* When an interrupt occurs, it is due to a change on the GPIO input pin.
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* In that case, all attached handlers will be called. Each handler must
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* maintain state and determine if the unlying GPIO input value changed.
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*
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*
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* Parameters:
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* - pinset: GPIO pin configuration
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* - cn: The change notification number associated with the pin.
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* - handler: Interrupt handler (may be NULL to detach)
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*
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* Returns:
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*
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* Returns:
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* The previous value of the interrupt handler function pointer. This
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* value may, for example, be used to restore the previous handler when
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* multiple handlers are used.
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@@ -228,7 +228,7 @@ xcpt_t pic32mx_gpioattach(uint32_t pinset, unsigned int cn, xcpt_t handler)
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pic32mx_configgpio(pinset);
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/* Pull-up requested? */
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if (pic32mx_pullup(pinset))
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{
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putreg32(1 << cn, PIC32MX_IOPORT_CNPUESET);
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@@ -158,7 +158,6 @@ __reset:
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nop
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.end __reset
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/****************************************************************************
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* Name: _gen_exception
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*
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@@ -218,7 +217,7 @@ _ebase_exception:
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*
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* Description:
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* Boot Exception Vector Handler. Jumps to _exception_handler. This
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* vector will be positioned at 0xbfc00380 by the linker script.
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* vector will be positioned at 0xbfc00380 by the linker script.
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*
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* Input Parameters:
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* None
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@@ -242,7 +241,7 @@ _bev_exception:
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*
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* Description:
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* Interrupt Exception Vector Handler. Jumps to _int_handler. This
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* vector will be positioned at 0xbfc00400 by the linker script.
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* vector will be positioned at 0xbfc00400 by the linker script.
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*
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* Input Parameters:
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* None
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@@ -379,7 +378,7 @@ __start:
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la t1, _sramfunc
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la t2, _eramfunc
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.Lramfuncloop:
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.Lramfuncloop:
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lw t3,(t0)
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sw t3,(t1)
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addu t0,4
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@@ -635,7 +634,7 @@ devconfig0:
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/* g_instackbase is a pointer to the final, aligned word of the interrupt
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* stack.
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*/
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.sdata
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.type g_intstackbase, object
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g_intstackbase:
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@@ -247,10 +247,10 @@ EXTERN uint32_t *pic32mx_exception(uint32_t *regs);
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* Description:
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* Configure a GPIO pin based on bit-encoded description of the pin (the interrupt
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* will be configured when pic32mx_attach() is called).
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*
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*
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* Returned Value:
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* OK on success; negated errno on failure.
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*
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*
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************************************************************************************/
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EXTERN int pic32mx_configgpio(uint16_t cfgset);
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@@ -303,13 +303,13 @@ EXTERN void pic32mx_gpioirqinitialize(void);
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* When an interrupt occurs, it is due to a change on the GPIO input pin. In that
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* case, all attached handlers will be called. Each handler must maintain state
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* and determine if the unlying GPIO input value changed.
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*
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*
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* Parameters:
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* - pinset: GPIO pin configuration
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* - cn: The change notification number associated with the pin
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* - handler: Interrupt handler (may be NULL to detach)
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*
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* Returns:
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*
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* Returns:
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* The previous value of the interrupt handler function pointer. This value may,
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* for example, be used to restore the previous handler when multiple handlers are
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* used.
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@@ -370,7 +370,7 @@ EXTERN void pic32mx_dumpgpio(uint32_t pinset, const char *msg);
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* Description:
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* These external functions must be provided by board-specific logic. They are
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* implementations of the select, status, and cmddata methods of the SPI interface
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* defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods
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* defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods
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* including up_spiinitialize()) are provided by common PIC32MX logic. To use
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* this common SPI logic on your board:
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*
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@@ -386,7 +386,7 @@ EXTERN void pic32mx_dumpgpio(uint32_t pinset, const char *msg);
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* 3. Add a call to up_spiinitialize() in your low level application
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* initialization logic
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* 4. The handle returned by up_spiinitialize() may then be used to bind the
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* SPI driver to higher level logic (e.g., calling
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* SPI driver to higher level logic (e.g., calling
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* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
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* the SPI MMC/SD driver).
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*
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@@ -127,7 +127,7 @@ void up_irqinitialize(void)
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/* Set the IV bit in the CAUSE register */
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regval = cp0_getcause();
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regval |= CP0_CAUSE_IV;
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regval |= CP0_CAUSE_IV;
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cp0_putcause(regval);
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/* Clear the EXL and BEV bits in the STATUS register */
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@@ -145,7 +145,7 @@ void up_irqinitialize(void)
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#endif
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/* Initialize GPIO change notification handling */
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#ifdef CONFIG_GPIO_IRQ
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pic32mx_gpioirqinitialize();
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#endif
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@@ -175,7 +175,7 @@ static void pic32mx_uartsetbaud(uintptr_t uart_base, uint32_t baudrate)
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/* We want the largest value of BRG divisor possible (for the best accuracy).
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* Subject to BRG <= 65536.
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*/
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tmp = BOARD_PBCLOCK / baudrate;
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/* Try BRGH=1 first. This will select the 4x divisor and will produce the
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@@ -115,9 +115,9 @@ static inline void pic32mx_waitstates(void)
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/* Disable DRM wait states */
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putreg32(BMX_CON_BMXWSDRM, PIC32MX_BMX_CONCLR);
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/* Configure pre-fetch cache FLASH wait states */
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residual = BOARD_CPU_CLOCK;
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nwaits = 0;
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@@ -153,7 +153,7 @@ static inline void pic32mx_cache(void)
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regval = getreg32(PIC32MX_CHE_CON);
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regval |= CHE_CON_PREFEN_ALL;
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putreg32(regval, PIC32MX_CHE_CON);
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/* Enable cache on KSEG 0 in the CP0 CONFIG register*/
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asm("\tmfc0 %0,$16,0\n" : "=r"(regval));
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File diff suppressed because it is too large
Load Diff
@@ -419,7 +419,7 @@ static int up_attach(struct uart_dev_s *dev)
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static void up_detach(struct uart_dev_s *dev)
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{
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struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
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/* Disable interrupts */
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up_disableuartint(dev, NULL);
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@@ -478,8 +478,8 @@ static int up_interrupt(int irq, void *context)
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handled = false;
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/* Handle error interrupts. This interrupt occurs when any of the
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* following error conditions take place:
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* - Parity error PERR (UxSTA bit 3) is detected
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* following error conditions take place:
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* - Parity error PERR (UxSTA bit 3) is detected
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* - Framing Error FERR (UxSTA bit 2) is detected
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* - Overflow condition for the receive buffer OERR (UxSTA bit 1) occurs
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*/
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@@ -544,7 +544,7 @@ static int up_interrupt(int irq, void *context)
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uart_xmitchars(dev);
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handled = true;
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/* Clear the pending TX interrupt if the TX FIFO is empty.
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/* Clear the pending TX interrupt if the TX FIFO is empty.
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* Note that interrupts can be lost if the interrupt condition is
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* still true when the interrupt is cleared. Keeping the TX
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* interrupt pending too long is not a problem: Upper level logic
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@@ -104,7 +104,7 @@
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* TIMER1_PRESCALE = 64
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* TIMER1_MATCH = 9375 -> 100.0 ticks/sec
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*/
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#define OPTIMAL_PRESCALE (TIMER1_SRC_FREQ / CLOCKS_PER_SEC / 65535)
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#if OPTIMAL_PRESCALE <= 1
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# define TIMER1_CON_TCKPS TIMER1_CON_TCKPS_1
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@@ -148,7 +148,7 @@
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int up_timerisr(int irq, uint32_t *regs)
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{
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/* Clear the pending timer interrupt */
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putreg32(INT_T1, PIC32MX_INT_IFS0CLR);
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/* Process timer interrupt */
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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