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WIP nxphlite-v3

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Configure Clocking, USB and Console on LPUART
This commit is contained in:
David Sidrane
2017-02-27 15:45:20 -10:00
committed by Daniel Agar
parent 6dfae5bfac
commit 7cde985e27
1 changed files with 54 additions and 0 deletions
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nuttx-configs/nxphlite-v3/include/board.h
+54
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@@ -48,6 +48,8 @@
# include <stdint.h> # include <stdint.h>
#endif #endif
#include <arch/chip/chip.h>
/************************************************************************************ /************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
@@ -105,6 +107,46 @@
#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3) #define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3)
#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4) #define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4)
/* Use BOARD_MCG_FREQ as the output SIM_SOPT2 MUX selected by
* SIM_SOPT2[PLLFLLSEL]
*/
#define BOARD_SOPT2_PLLFLLSEL SIM_SOPT2_PLLFLLSEL_MCGPLLCLK
#define BOARD_SOPT2_FREQ BOARD_MCG_FREQ
/* Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
* SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ × [ (USBFRAC+1) / (USBDIV+1) ]
* 48Mhz = 168Mhz X [(1 + 1) / (6 + 1)]
* 48Mhz = 168Mhz / (6 + 1) * (1 + 1)
*/
#define BOARD_SIM_CLKDIV2_USBFRAC 2
#define BOARD_SIM_CLKDIV2_USBDIV 7
#define BOARD_SIM_CLKDIV2_FREQ (BOARD_SOPT2_FREQ / \
BOARD_SIM_CLKDIV2_USBDIV * \
BOARD_SIM_CLKDIV2_USBFRAC)
#define BOARD_USB_CLKSRC SIM_SOPT2_USBSRC
#define BOARD_USB_FREQ BOARD_SIM_CLKDIV2_FREQ
/* Divider output clock = Divider input clock * ((PLLFLLFRAC+1)/(PLLFLLDIV+1))
* SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ × [ (PLLFLLFRAC+1) / (PLLFLLDIV+1)]
* 84 Mhz = 168 Mhz X [(0 + 1) / (1 + 1)]
* 84 Mhz = 168 Mhz / (1 + 1) * (0 + 1)
*/
#define BOARD_SIM_CLKDIV3_PLLFLLFRAC 1
#define BOARD_SIM_CLKDIV3_PLLFLLDIV 2
#define BOARD_SIM_CLKDIV3_FREQ (BOARD_SOPT2_FREQ / \
BOARD_SIM_CLKDIV3_PLLFLLDIV * \
BOARD_SIM_CLKDIV3_PLLFLLFRAC)
#define BOARD_LPUART0_CLKSRC SIM_SOPT2_LPUARTSRC_MCGCLK
#define BOARD_LPUART0_FREQ BOARD_SIM_CLKDIV3_FREQ
#define BOARD_TPM_CLKSRC SIM_SOPT2_TPMSRC_MCGCLK
#define BOARD_TPM_FREQ BOARD_SIM_CLKDIV3_FREQ
/* SDHC clocking ********************************************************************/ /* SDHC clocking ********************************************************************/
/* SDCLK configurations corresponding to various modes of operation. Formula is: /* SDCLK configurations corresponding to various modes of operation. Formula is:
@@ -306,6 +348,18 @@
#define PIN_UART4_RX PIN_UART4_RX_1 /* PTC14 UART P10-3 */ #define PIN_UART4_RX PIN_UART4_RX_1 /* PTC14 UART P10-3 */
#define PIN_UART4_TX PIN_UART4_TX_1 /* PTC15 UART P10-2 */ #define PIN_UART4_TX PIN_UART4_TX_1 /* PTC15 UART P10-2 */
/* LPUART
*
* P16 Pin Name K66 Name
* -------- ------------ ------ ---------
* 2 UART_TX PTD9 LPUART0_TX
* 3 UART_RX PTD8 LPUART0_RX
* -------- ----- ------ ---------
*/
#define PIN_LPUART0_RX PIN_LPUART0_RX_3
#define PIN_LPUART0_TX PIN_LPUART0_TX_3
/* UART5 is not connected on V1 /* UART5 is not connected on V1
*/ */