mirror of
https://github.com/PX4/PX4-Autopilot.git
synced 2026-06-01 02:55:07 +08:00
px4_fmu-v2/v3: add board_dma_map.h and enable SPI1/SPI4 DMA
This commit is contained in:
Daniel Agar
@@ -40,6 +40,7 @@
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include "board_dma_map.h"
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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@@ -195,17 +196,6 @@
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# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA Channl/Stream Selections *****************************************************/
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/* Stream selections are arbitrary for now but might become important in the future
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* is we set aside more DMA channels/streams.
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*
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* SDIO DMA
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* DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA
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* DMAMAP_SDIO_2 = Channel 4, Stream 6
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*/
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#define DMAMAP_SDIO DMAMAP_SDIO_1
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/* Alternate function pin selections ************************************************/
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/* UARTs */
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@@ -234,10 +224,6 @@
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/* UART8 has no alternate pin config */
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/* UART RX DMA configurations */
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#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
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/* CAN
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*
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* CAN1 is routed to the onboard transceiver.
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@@ -0,0 +1,56 @@
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/****************************************************************************
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*
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* Copyright (c) 2020 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#pragma once
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// DMA1 Channel/Stream Selections
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//--------------------------------------------//---------------------------//----------------
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// DMAMAP_USART3_RX // DMA1, Stream 1, Channel 4
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// DMAMAP_UART4_RX // DMA1, Stream 2, Channel 4
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// DMAMAP_UART7_RX // DMA1, Stream 3, Channel 5
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// AVAILABLE // DMA1, Stream 4
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// DMAMAP_USART2_RX // DMA1, Stream 5, Channel 4
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// DMAMAP_TIM4_UP // DMA1, Stream 6, Channel 2 (DSHOT)
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// DMA2 Channel/Stream Selections
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//--------------------------------------------//---------------------------//----------------
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#define DMACHAN_SPI4_RX DMAMAP_SPI4_RX_1 // DMA2, Stream 0, Channel 4 (SPI4 sensors RX)
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#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 // DMA2, Stream 1, Channel 4 (PX4IO RX)
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#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2 // DMA2, Stream 2, Channel 3 (SPI1 sensors RX)
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#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3 (SPI1 sensors TX)
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#define DMACHAN_SPI4_TX DMAMAP_SPI4_TX_2 // DMA2, Stream 4, Channel 5 (SPI4 sensors TX)
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// DMAMAP_TIM1_UP // DMA2, Stream 5, Channel 6 (DSHOT)
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#define DMAMAP_SDIO DMAMAP_SDIO_2 // DMA2, Stream 6, Channel 4
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#define DMAMAP_USART6_TX DMAMAP_USART6_TX_2 // DMA2, Stream 7, Channel 5 (PX4IO TX)
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@@ -188,8 +188,11 @@ CONFIG_STM32_SDIO_CARD=y
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CONFIG_STM32_SERIALBRK_BSDCOMPAT=y
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CONFIG_STM32_SERIAL_DISABLE_REORDERING=y
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CONFIG_STM32_SPI1=y
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CONFIG_STM32_SPI1_DMA=y
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CONFIG_STM32_SPI2=y
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CONFIG_STM32_SPI4=y
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CONFIG_STM32_SPI4_DMA=y
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CONFIG_STM32_SPI_DMA=y
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CONFIG_STM32_TIM10=y
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CONFIG_STM32_TIM11=y
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CONFIG_STM32_TIM3=y
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@@ -74,8 +74,8 @@
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#define PX4IO_SERIAL_RX_GPIO GPIO_USART6_RX
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#define PX4IO_SERIAL_BASE STM32_USART6_BASE /* hardwired on the board */
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#define PX4IO_SERIAL_VECTOR STM32_IRQ_USART6
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#define PX4IO_SERIAL_TX_DMAMAP DMAMAP_USART6_TX_2
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#define PX4IO_SERIAL_RX_DMAMAP DMAMAP_USART6_RX_2
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#define PX4IO_SERIAL_TX_DMAMAP DMAMAP_USART6_TX
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#define PX4IO_SERIAL_RX_DMAMAP DMAMAP_USART6_RX
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#define PX4IO_SERIAL_RCC_REG STM32_RCC_APB2ENR
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#define PX4IO_SERIAL_RCC_EN RCC_APB2ENR_USART6EN
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#define PX4IO_SERIAL_CLOCK STM32_PCLK2_FREQUENCY
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@@ -421,7 +421,7 @@
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#define BOARD_HAS_PWM DIRECT_PWM_OUTPUT_CHANNELS
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/* This board provides a DMA pool and APIs */
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#define BOARD_DMA_ALLOC_POOL_SIZE 5120
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#define BOARD_DMA_ALLOC_POOL_SIZE (5120 + 512 + 512) // 5120 fat + 512 + 512 spi
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#define BOARD_HAS_ON_RESET 1
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@@ -40,6 +40,7 @@
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include "board_dma_map.h"
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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@@ -195,17 +196,6 @@
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# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA Channl/Stream Selections *****************************************************/
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/* Stream selections are arbitrary for now but might become important in the future
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* is we set aside more DMA channels/streams.
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*
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* SDIO DMA
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* DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA
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* DMAMAP_SDIO_2 = Channel 4, Stream 6
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*/
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#define DMAMAP_SDIO DMAMAP_SDIO_1
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/* Alternate function pin selections ************************************************/
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/* UARTs */
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@@ -234,10 +224,6 @@
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/* UART8 has no alternate pin config */
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/* UART RX DMA configurations */
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#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
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/* CAN
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*
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* CAN1 is routed to the onboard transceiver.
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@@ -0,0 +1,56 @@
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/****************************************************************************
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*
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* Copyright (c) 2020 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#pragma once
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// DMA1 Channel/Stream Selections
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//--------------------------------------------//---------------------------//----------------
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// DMAMAP_USART3_RX // DMA1, Stream 1, Channel 4
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// DMAMAP_UART4_RX // DMA1, Stream 2, Channel 4
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// DMAMAP_UART7_RX // DMA1, Stream 3, Channel 5
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// AVAILABLE // DMA1, Stream 4
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// DMAMAP_USART2_RX // DMA1, Stream 5, Channel 4
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// DMAMAP_TIM4_UP // DMA1, Stream 6, Channel 2 (DSHOT)
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// DMA2 Channel/Stream Selections
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//--------------------------------------------//---------------------------//----------------
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#define DMACHAN_SPI4_RX DMAMAP_SPI4_RX_1 // DMA2, Stream 0, Channel 4 (SPI4 sensors RX)
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#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 // DMA2, Stream 1, Channel 4 (PX4IO RX)
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#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2 // DMA2, Stream 2, Channel 3 (SPI1 sensors RX)
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#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3 (SPI1 sensors TX)
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#define DMACHAN_SPI4_TX DMAMAP_SPI4_TX_2 // DMA2, Stream 4, Channel 5 (SPI4 sensors TX)
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// DMAMAP_TIM1_UP // DMA2, Stream 5, Channel 6 (DSHOT)
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#define DMAMAP_SDIO DMAMAP_SDIO_2 // DMA2, Stream 6, Channel 4
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#define DMAMAP_USART6_TX DMAMAP_USART6_TX_2 // DMA2, Stream 7, Channel 5 (PX4IO TX)
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@@ -187,8 +187,11 @@ CONFIG_STM32_SDIO_CARD=y
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CONFIG_STM32_SERIALBRK_BSDCOMPAT=y
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CONFIG_STM32_SERIAL_DISABLE_REORDERING=y
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CONFIG_STM32_SPI1=y
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CONFIG_STM32_SPI1_DMA=y
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CONFIG_STM32_SPI2=y
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CONFIG_STM32_SPI4=y
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CONFIG_STM32_SPI4_DMA=y
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CONFIG_STM32_SPI_DMA=y
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CONFIG_STM32_TIM10=y
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CONFIG_STM32_TIM11=y
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CONFIG_STM32_TIM3=y
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@@ -74,8 +74,8 @@
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#define PX4IO_SERIAL_RX_GPIO GPIO_USART6_RX
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#define PX4IO_SERIAL_BASE STM32_USART6_BASE /* hardwired on the board */
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#define PX4IO_SERIAL_VECTOR STM32_IRQ_USART6
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#define PX4IO_SERIAL_TX_DMAMAP DMAMAP_USART6_TX_2
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#define PX4IO_SERIAL_RX_DMAMAP DMAMAP_USART6_RX_2
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#define PX4IO_SERIAL_TX_DMAMAP DMAMAP_USART6_TX
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#define PX4IO_SERIAL_RX_DMAMAP DMAMAP_USART6_RX
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#define PX4IO_SERIAL_RCC_REG STM32_RCC_APB2ENR
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#define PX4IO_SERIAL_RCC_EN RCC_APB2ENR_USART6EN
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#define PX4IO_SERIAL_CLOCK STM32_PCLK2_FREQUENCY
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@@ -421,7 +421,7 @@
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#define BOARD_HAS_PWM DIRECT_PWM_OUTPUT_CHANNELS
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/* This board provides a DMA pool and APIs */
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#define BOARD_DMA_ALLOC_POOL_SIZE 5120
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#define BOARD_DMA_ALLOC_POOL_SIZE (5120 + 512 + 512) // 5120 fat + 512 + 512 spi
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#define BOARD_HAS_ON_RESET 1
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