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io timer: remove some fields from io_timers_t and split out channel indexes

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- reduces amount of board configuration required
- removes the cyclic dependency between io_timers_t and timer_io_channels_t

Fixes a bug in the fmuk66-v3 config: the 2. timer has 3 channels associated
not 2.
Fixes a bug in the modelai config: the 2. timer has 4 channels associated.
This commit is contained in:
Beat Küng
2020-01-03 10:02:47 +01:00
committed by David Sidrane
parent 8020e82c1c
commit 62b4f3487a
28 changed files with 581 additions and 301 deletions
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boards/av/x-v1/src/timer_config.c
+25 -18
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@@ -56,9 +56,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
},
{
@@ -66,9 +63,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM2EN,
.clock_freq = STM32_APB1_TIM2_CLKIN,
.first_channel_index = 4,
.last_channel_index = 4,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM2,
},
{
@@ -76,9 +70,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM8EN,
.clock_freq = STM32_APB2_TIM8_CLKIN,
.first_channel_index = 5,
.last_channel_index = 5,
.handler = io_timer_handler2,
.vectorno = STM32_IRQ_TIM8CC,
},
{
@@ -86,9 +77,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM11EN,
.clock_freq = STM32_APB2_TIM11_CLKIN,
.first_channel_index = 6,
.last_channel_index = 6,
.handler = io_timer_handler3,
.vectorno = STM32_IRQ_TIM11,
},
{
@@ -96,9 +84,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM10EN,
.clock_freq = STM32_APB2_TIM10_CLKIN,
.first_channel_index = 7,
.last_channel_index = 7,
.handler = io_timer_handler4,
.vectorno = STM32_IRQ_TIM10,
},
// {
@@ -106,13 +91,35 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
// .clock_register = STM32_RCC_APB1ENR,
// .clock_bit = RCC_APB1ENR_TIM4EN,
// .clock_freq = STM32_APB1_TIM4_CLKIN,
// .first_channel_index = 8,
// .last_channel_index = 8,
// .handler = io_timer_handler5,
// .vectorno = STM32_IRQ_TIM4,
// }
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 1,
},
{
.first_channel_index = 5,
.channel_count = 1,
},
{
.first_channel_index = 6,
.channel_count = 1,
},
{
.first_channel_index = 7,
.channel_count = 1,
},
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH1OUT,