mirror of
https://github.com/PX4/PX4-Autopilot.git
synced 2026-06-01 02:55:07 +08:00
fmurt1062-v1:Remove EVK build options
This commit is contained in:
committed by
Daniel Agar
parent
a8e0c29161
commit
51f0bc9788
@@ -46,7 +46,6 @@
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/************************************************************************************
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/************************************************************************************
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* Pre-processor Definitions
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* Pre-processor Definitions
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************************************************************************************/
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************************************************************************************/
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//#define ON_EVK // For Board Bring up before BIG Board on IMXRT1060-EVK
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/* Clocking *************************************************************************/
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/* Clocking *************************************************************************/
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@@ -226,14 +225,6 @@
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#define GPIO_LPUART2_RX (GPIO_LPUART2_RX_1 | LPUART_IOMUX) /* EVK J22-8 */ /* GPIO_AD_B1_03 */
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#define GPIO_LPUART2_RX (GPIO_LPUART2_RX_1 | LPUART_IOMUX) /* EVK J22-8 */ /* GPIO_AD_B1_03 */
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#define GPIO_LPUART2_TX (GPIO_LPUART2_TX_1 | LPUART_IOMUX) /* EVK J22-7 */ /* GPIO_AD_B1_02 */
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#define GPIO_LPUART2_TX (GPIO_LPUART2_TX_1 | LPUART_IOMUX) /* EVK J22-7 */ /* GPIO_AD_B1_02 */
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#if defined(ON_EVK)
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#define GPIO_LPUART1_RX (GPIO_LPUART1_RX_1 | LPUART_IOMUX) /* GPIO_AD_B0_13 EVK J46-2 */
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#define GPIO_LPUART1_TX (GPIO_LPUART1_TX_1 | LPUART_IOMUX) /* GPIO_AD_B0_12 EVK J46-2 */
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#define GPIO_LPUART3_RX (GPIO_LPUART3_RX_1 | LPUART_IOMUX) /* GPIO_AD_B1_07 EVK J22-1 */
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#define GPIO_LPUART3_TX (GPIO_LPUART3_TX_1 | LPUART_IOMUX) /* GPIO_AD_B1_06 EVK J22-2 */
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#else
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/* Telem 2 */
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/* Telem 2 */
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#define HS_INPUT_IOMUX (IOMUX_CMOS_INPUT | IOMUX_SLEW_SLOW | IOMUX_DRIVE_HIZ | IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_47K)
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#define HS_INPUT_IOMUX (IOMUX_CMOS_INPUT | IOMUX_SLEW_SLOW | IOMUX_DRIVE_HIZ | IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_47K)
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@@ -243,7 +234,6 @@
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#define GPIO_LPUART3_TX (GPIO_LPUART3_TX_3 | LPUART_IOMUX) /* GPIO_B0_08 */
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#define GPIO_LPUART3_TX (GPIO_LPUART3_TX_3 | LPUART_IOMUX) /* GPIO_B0_08 */
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#define GPIO_LPUART3_CTS (GPIO_PORT1 | GPIO_PIN8 | GPIO_INPUT | HS_INPUT_IOMUX) /* GPIO_AD_B0_08 GPIO1 Pin 8 (GPIO only, no HW Flow control) */
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#define GPIO_LPUART3_CTS (GPIO_PORT1 | GPIO_PIN8 | GPIO_INPUT | HS_INPUT_IOMUX) /* GPIO_AD_B0_08 GPIO1 Pin 8 (GPIO only, no HW Flow control) */
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#define GPIO_LPUART3_RTS (GPIO_PORT4 | GPIO_PIN24 | GPIO_OUTPUT | HS_OUTPUT_IOMUX) /* GPIO_EMC_24 GPIO4 Pin 24 (GPIO only, no HW Flow control) */
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#define GPIO_LPUART3_RTS (GPIO_PORT4 | GPIO_PIN24 | GPIO_OUTPUT | HS_OUTPUT_IOMUX) /* GPIO_EMC_24 GPIO4 Pin 24 (GPIO only, no HW Flow control) */
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#endif
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/* Telem 1 */
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/* Telem 1 */
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@@ -290,15 +280,9 @@
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#define GPIO_LPSPI1_MISO (GPIO_LPSPI1_SDI_1 | LPSPI_IOMUX) /* GPIO_EMC_29 */
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#define GPIO_LPSPI1_MISO (GPIO_LPSPI1_SDI_1 | LPSPI_IOMUX) /* GPIO_EMC_29 */
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#define GPIO_LPSPI1_MOSI (GPIO_LPSPI1_SDO_1 | LPSPI_IOMUX) /* GPIO_EMC_28 */
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#define GPIO_LPSPI1_MOSI (GPIO_LPSPI1_SDO_1 | LPSPI_IOMUX) /* GPIO_EMC_28 */
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#if defined(ON_EVK)
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#define GPIO_LPSPI2_SCK (GPIO_LPSPI2_SCK_2 | LPSPI_IOMUX) /* EVK J24-6 POP R280 GPIO_SD_B0_00 */
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#define GPIO_LPSPI2_MISO (GPIO_LPSPI1_SDI_2 | LPSPI_IOMUX) /* EVK J24-5 POP R278 GPIO_SD_B0_03 */
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#define GPIO_LPSPI2_MOSI (GPIO_LPSPI1_SDO_2 | LPSPI_IOMUX) /* EVK J24-4 POP R279 GPIO_SD_B0_02 */
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#else
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#define GPIO_LPSPI2_SCK (GPIO_LPSPI2_SCK_1 | LPSPI_IOMUX) /* GPIO_EMC_00 */
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#define GPIO_LPSPI2_SCK (GPIO_LPSPI2_SCK_1 | LPSPI_IOMUX) /* GPIO_EMC_00 */
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#define GPIO_LPSPI2_MISO (GPIO_LPSPI2_SDI_1 | LPSPI_IOMUX) /* GPIO_EMC_03 */
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#define GPIO_LPSPI2_MISO (GPIO_LPSPI2_SDI_1 | LPSPI_IOMUX) /* GPIO_EMC_03 */
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#define GPIO_LPSPI2_MOSI (GPIO_LPSPI2_SDO_1 | LPSPI_IOMUX) /* GPIO_EMC_02 */
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#define GPIO_LPSPI2_MOSI (GPIO_LPSPI2_SDO_1 | LPSPI_IOMUX) /* GPIO_EMC_02 */
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#endif
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#define GPIO_LPSPI3_SCK (GPIO_LPSPI3_SCK_1 | LPSPI_IOMUX) /* GPIO_AD_B1_15 */
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#define GPIO_LPSPI3_SCK (GPIO_LPSPI3_SCK_1 | LPSPI_IOMUX) /* GPIO_AD_B1_15 */
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#define GPIO_LPSPI3_MISO (GPIO_LPSPI3_SDI_1 | LPSPI_IOMUX) /* GPIO_AD_B1_13 */
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#define GPIO_LPSPI3_MISO (GPIO_LPSPI3_SDI_1 | LPSPI_IOMUX) /* GPIO_AD_B1_13 */
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@@ -1,181 +0,0 @@
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_DISABLE_OS_API is not set
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# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
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# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set
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# CONFIG_MMCSD_SPI is not set
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# CONFIG_NSH_DISABLEBG is not set
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# CONFIG_NSH_DISABLESCRIPT is not set
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# CONFIG_NSH_DISABLE_DF is not set
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# CONFIG_NSH_DISABLE_EXEC is not set
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# CONFIG_NSH_DISABLE_EXIT is not set
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# CONFIG_NSH_DISABLE_GET is not set
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# CONFIG_NSH_DISABLE_ITEF is not set
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# CONFIG_NSH_DISABLE_LOOPS is not set
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# CONFIG_NSH_DISABLE_SEMICOLON is not set
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# CONFIG_NSH_DISABLE_TIME is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD_CUSTOM=y
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CONFIG_ARCH_BOARD_CUSTOM_DIR="../nuttx-config"
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CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
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CONFIG_ARCH_BOARD_CUSTOM_NAME="px4"
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CONFIG_ARCH_CHIP="imxrt"
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CONFIG_ARCH_CHIP_IMXRT=y
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CONFIG_ARCH_CHIP_MIMXRT1062DVL6A=y
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CONFIG_ARCH_INTERRUPTSTACK=750
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_BASEPRI_WAR=y
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CONFIG_ARMV7M_DCACHE=y
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CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
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CONFIG_ARMV7M_ICACHE=y
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CONFIG_ARMV7M_MEMCPY=y
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CONFIG_ARMV7M_USEBASEPRI=y
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CONFIG_BOARDCTL_RESET=y
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CONFIG_BOARD_CRASHDUMP=y
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CONFIG_BOARD_CUSTOM_LEDS=y
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CONFIG_BOARD_LOOPSPERMSEC=104926
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CONFIG_BOARD_RESET_ON_ASSERT=2
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CONFIG_BUILTIN=y
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CONFIG_C99_BOOL8=y
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CONFIG_CDCACM=y
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CONFIG_CDCACM_PRODUCTID=0x001d
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CONFIG_CDCACM_PRODUCTSTR="PX4 FMURT1062 v1.x"
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CONFIG_CDCACM_RXBUFSIZE=600
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CONFIG_CDCACM_TXBUFSIZE=12000
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CONFIG_CDCACM_VENDORID=0x1FC9
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CONFIG_CDCACM_VENDORSTR="NXP SEMICONDUCTORS"
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CONFIG_CLOCK_MONOTONIC=y
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CONFIG_DEBUG_FULLOPT=y
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CONFIG_DEBUG_HARDFAULT_ALERT=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DEFAULT_SMALL=y
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CONFIG_DEV_FIFO_SIZE=0
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CONFIG_DEV_PIPE_MAXSIZE=1024
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CONFIG_DEV_PIPE_SIZE=70
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CONFIG_FAT_DMAMEMORY=y
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CONFIG_FAT_LCNAMES=y
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CONFIG_FAT_LFN=y
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CONFIG_FAT_LFN_ALIAS_HASH=y
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CONFIG_FDCLONE_STDIO=y
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CONFIG_FS_BINFS=y
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CONFIG_FS_CROMFS=y
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CONFIG_FS_FAT=y
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CONFIG_FS_FATTIME=y
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CONFIG_FS_PROCFS=y
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CONFIG_FS_PROCFS_EXCLUDE_BLOCKS=y
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CONFIG_FS_PROCFS_EXCLUDE_MOUNT=y
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CONFIG_FS_PROCFS_EXCLUDE_MOUNTS=y
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CONFIG_FS_PROCFS_EXCLUDE_USAGE=y
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CONFIG_FS_PROCFS_REGISTER=y
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CONFIG_FS_ROMFS=y
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CONFIG_GRAN=y
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CONFIG_GRAN_INTR=y
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CONFIG_HAVE_CXX=y
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CONFIG_HAVE_CXXINITIALIZE=y
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CONFIG_I2C=y
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CONFIG_I2C_RESET=y
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CONFIG_IDLETHREAD_STACKSIZE=750
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CONFIG_IMXRT_EDMA=y
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CONFIG_IMXRT_LPSPI3=y
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CONFIG_IMXRT_LPUART1=y
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CONFIG_IMXRT_LPUART2=y
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CONFIG_IMXRT_LPUART3=y
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CONFIG_IMXRT_LPUART_INVERT=y
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CONFIG_IMXRT_RTC_MAGIC_REG=1
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CONFIG_IMXRT_SNVS_LPSRTC=y
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CONFIG_IMXRT_USDHC1=y
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CONFIG_LIBC_FLOATINGPOINT=y
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CONFIG_LIBC_LONG_LONG=y
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CONFIG_LIBC_STRERROR=y
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CONFIG_LPUART2_RXBUFSIZE=600
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CONFIG_LPUART2_TXBUFSIZE=1500
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CONFIG_LPUART3_BAUD=57600
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CONFIG_LPUART3_RXBUFSIZE=600
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CONFIG_LPUART3_SERIAL_CONSOLE=y
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CONFIG_LPUART3_TXBUFSIZE=3000
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CONFIG_MAX_WDOGPARMS=2
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CONFIG_MEMSET_64BIT=y
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CONFIG_MEMSET_OPTSPEED=y
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CONFIG_MMCSD=y
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CONFIG_MMCSD_SDIO=y
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CONFIG_NFILE_DESCRIPTORS=54
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CONFIG_NFILE_STREAMS=8
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CONFIG_NSH_ARCHINIT=y
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CONFIG_NSH_ARCHROMFS=y
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CONFIG_NSH_ARGCAT=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_CMDPARMS=y
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CONFIG_NSH_CROMFSETC=y
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CONFIG_NSH_DISABLE_IFCONFIG=y
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CONFIG_NSH_DISABLE_IFUPDOWN=y
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CONFIG_NSH_DISABLE_MB=y
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CONFIG_NSH_DISABLE_MH=y
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CONFIG_NSH_DISABLE_PSSTACKUSAGE=y
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CONFIG_NSH_DISABLE_TELNETD=y
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CONFIG_NSH_LINELEN=128
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CONFIG_NSH_MAXARGUMENTS=12
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CONFIG_NSH_NESTDEPTH=8
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CONFIG_NSH_QUOTE=y
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CONFIG_NSH_ROMFSETC=y
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CONFIG_NSH_ROMFSSECTSIZE=128
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CONFIG_NSH_STRERROR=y
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CONFIG_NSH_VARS=y
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CONFIG_NXFONTS_DISABLE_16BPP=y
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CONFIG_NXFONTS_DISABLE_1BPP=y
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CONFIG_NXFONTS_DISABLE_24BPP=y
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CONFIG_NXFONTS_DISABLE_2BPP=y
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CONFIG_NXFONTS_DISABLE_32BPP=y
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CONFIG_NXFONTS_DISABLE_4BPP=y
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CONFIG_NXFONTS_DISABLE_8BPP=y
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CONFIG_PIPES=y
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CONFIG_PREALLOC_MQ_MSGS=4
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CONFIG_PREALLOC_TIMERS=50
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CONFIG_PREALLOC_WDOGS=50
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CONFIG_PRIORITY_INHERITANCE=y
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CONFIG_PTHREAD_MUTEX_ROBUST=y
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CONFIG_PTHREAD_STACK_MIN=512
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CONFIG_RAM_SIZE=1048576
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CONFIG_RAM_START=0x20200000
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CONFIG_RAW_BINARY=y
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CONFIG_RTC=y
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CONFIG_SCHED_ATEXIT=y
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CONFIG_SCHED_HPWORK=y
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CONFIG_SCHED_HPWORKPRIORITY=249
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CONFIG_SCHED_HPWORKSTACKSIZE=1800
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CONFIG_SCHED_INSTRUMENTATION=y
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CONFIG_SCHED_LPWORK=y
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CONFIG_SCHED_LPWORKPRIORITY=50
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CONFIG_SCHED_LPWORKSTACKSIZE=1800
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CONFIG_SCHED_WAITPID=y
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CONFIG_SDCLONE_DISABLE=y
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CONFIG_SDIO_BLOCKSETUP=y
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CONFIG_SEM_NNESTPRIO=8
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CONFIG_SEM_PREALLOCHOLDERS=0
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CONFIG_SERIAL_TERMIOS=y
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CONFIG_SIG_DEFAULT=y
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CONFIG_SIG_SIGALRM_ACTION=y
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CONFIG_SIG_SIGUSR1_ACTION=y
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CONFIG_SIG_SIGUSR2_ACTION=y
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CONFIG_SIG_SIGWORK=4
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CONFIG_SPI=y
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CONFIG_STACK_COLORATION=y
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CONFIG_START_DAY=30
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CONFIG_START_MONTH=11
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CONFIG_STDIO_BUFFER_SIZE=32
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CONFIG_SYSTEM_CDCACM=y
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CONFIG_SYSTEM_NSH=y
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CONFIG_SYSTEM_SPITOOL=y
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CONFIG_TASK_NAME_SIZE=24
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CONFIG_TIME_EXTENDED=y
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CONFIG_USBDEV=y
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CONFIG_USBDEV_BUSPOWERED=y
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CONFIG_USBDEV_MAXPOWER=500
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CONFIG_USEC_PER_TICK=1000
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CONFIG_USERMAIN_STACKSIZE=2500
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CONFIG_USER_ENTRYPOINT="nsh_main"
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CONFIG_WATCHDOG=y
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@@ -56,11 +56,6 @@
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/****************************************************************************************************
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/****************************************************************************************************
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* Definitions
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* Definitions
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****************************************************************************************************/
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****************************************************************************************************/
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#if defined(ON_EVK)
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//#define ON_EVK_SPI // Uses SDHC pins and requires R278-R281
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#define ON_EVK_SDIO // SPI2 is mapped on Pins and requires
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//#define ON_EVK_I2C // I2C2 is mapped on Pins and requires R278-R281
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#endif
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/* PX4IO connection configuration */
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/* PX4IO connection configuration */
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@@ -118,14 +113,10 @@
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#define OUT_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_PULL_UP_100K | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MEDIUM | IOMUX_SLEW_FAST)
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#define OUT_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_PULL_UP_100K | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MEDIUM | IOMUX_SLEW_FAST)
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/* SPI 1 CS */
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/* SPI 1 CS */
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#if defined(ON_EVK) && defined(ON_EVK_SPI)
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#define GPIO_SPI1_CS1_ICM20689 /* J24-3 POP R280 GPIO_SD_B0_01 */ (GPIO_PORT3 | GPIO_PIN13 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
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#else
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#define GPIO_SPI1_CS1_ICM20689 /* GPIO_EMC_40 GPIO3_IO26 */ (GPIO_PORT3 | GPIO_PIN26 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
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#define GPIO_SPI1_CS1_ICM20689 /* GPIO_EMC_40 GPIO3_IO26 */ (GPIO_PORT3 | GPIO_PIN26 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
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// GPIO_SPI1_CS2_ICM20602 is not wired from CPU
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// GPIO_SPI1_CS2_ICM20602 is not wired from CPU
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#define GPIO_SPI1_CS3_BMI055_GYRO /* GPIO_B1_10 GPIO2_IO26 */ (GPIO_PORT2 | GPIO_PIN26 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
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#define GPIO_SPI1_CS3_BMI055_GYRO /* GPIO_B1_10 GPIO2_IO26 */ (GPIO_PORT2 | GPIO_PIN26 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
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#define GPIO_SPI1_CS4_BMI055_ACCEL /* GPIO_B1_15 GPIO2_IO31 */ (GPIO_PORT2 | GPIO_PIN31 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
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#define GPIO_SPI1_CS4_BMI055_ACCEL /* GPIO_B1_15 GPIO2_IO31 */ (GPIO_PORT2 | GPIO_PIN31 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
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#endif
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#define SPI1_CS5_AUX_MEM /* GPIO_SD_B1_00 GPIO3_IO00 */ (GPIO_PORT3 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
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#define SPI1_CS5_AUX_MEM /* GPIO_SD_B1_00 GPIO3_IO00 */ (GPIO_PORT3 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
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@@ -240,14 +231,6 @@
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/* Define GPIO pins used as ADC N.B. Channel numbers are for reference, */
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/* Define GPIO pins used as ADC N.B. Channel numbers are for reference, */
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#if defined(ON_EVK)
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#define PX4_ADC_GPIO \
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/* J23-2 BATTERY1_VOLTAGE GPIO_AD_B1_11 GPIO1 Pin 27 */ ADC1_GPIO(0, 27), \
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|
||||||
/* J23-3 HW_VER_SENSE GPIO_AD_B1_04 GPIO1 Pin 20 */ ADC1_GPIO(9, 20), \
|
|
||||||
/* J23-4 SCALED_V5 GPIO_AD_B1_05 GPIO1 Pin 21 */ ADC1_GPIO(10, 21), \
|
|
||||||
/* J22-4 HW_REV_SENSE GPIO_AD_B1_08 GPIO1 Pin 24 */ ADC1_GPIO(13, 24), \
|
|
||||||
/* J23-1 RSSI_IN GPIO_AD_B1_10 GPIO1 Pin 26 */ ADC1_GPIO(15, 26)
|
|
||||||
#else
|
|
||||||
#define PX4_ADC_GPIO \
|
#define PX4_ADC_GPIO \
|
||||||
/* BATTERY1_VOLTAGE GPIO_AD_B1_11 GPIO1 Pin 27 */ ADC1_GPIO(0, 27), \
|
/* BATTERY1_VOLTAGE GPIO_AD_B1_11 GPIO1 Pin 27 */ ADC1_GPIO(0, 27), \
|
||||||
/* BATTERY1_CURRENT GPIO_AD_B0_12 GPIO1 Pin 12 */ ADC1_GPIO(1, 12), \
|
/* BATTERY1_CURRENT GPIO_AD_B0_12 GPIO1 Pin 12 */ ADC1_GPIO(1, 12), \
|
||||||
@@ -260,7 +243,6 @@
|
|||||||
/* HW_REV_SENSE GPIO_AD_B1_08 GPIO1 Pin 24 */ ADC1_GPIO(13, 24), \
|
/* HW_REV_SENSE GPIO_AD_B1_08 GPIO1 Pin 24 */ ADC1_GPIO(13, 24), \
|
||||||
/* SPARE_1 GPIO_AD_B1_09 GPIO1 Pin 25 */ ADC1_GPIO(14, 25), \
|
/* SPARE_1 GPIO_AD_B1_09 GPIO1 Pin 25 */ ADC1_GPIO(14, 25), \
|
||||||
/* RSSI_IN GPIO_AD_B1_10 GPIO1 Pin 26 */ ADC1_GPIO(15, 26)
|
/* RSSI_IN GPIO_AD_B1_10 GPIO1 Pin 26 */ ADC1_GPIO(15, 26)
|
||||||
#endif // defined(ON_EVK)
|
|
||||||
|
|
||||||
/* Define Channel numbers must match above GPIO pin IN(n)*/
|
/* Define Channel numbers must match above GPIO pin IN(n)*/
|
||||||
|
|
||||||
@@ -276,14 +258,6 @@
|
|||||||
#define ADC1_SPARE_1_CHANNEL /* GPIO_AD_B1_09 GPIO1 Pin 25 */ ADC1_CH(14)
|
#define ADC1_SPARE_1_CHANNEL /* GPIO_AD_B1_09 GPIO1 Pin 25 */ ADC1_CH(14)
|
||||||
#define ADC_RSSI_IN_CHANNEL /* GPIO_AD_B1_10 GPIO1 Pin 26 */ ADC1_CH(15)
|
#define ADC_RSSI_IN_CHANNEL /* GPIO_AD_B1_10 GPIO1 Pin 26 */ ADC1_CH(15)
|
||||||
|
|
||||||
#if defined(ON_EVK)
|
|
||||||
#define ADC_CHANNELS \
|
|
||||||
((1 << ADC_BATTERY1_VOLTAGE_CHANNEL) | \
|
|
||||||
(1 << ADC_RSSI_IN_CHANNEL) | \
|
|
||||||
(1 << ADC_SCALED_V5_CHANNEL) | \
|
|
||||||
(1 << ADC_HW_VER_SENSE_CHANNEL) | \
|
|
||||||
(1 << ADC_HW_REV_SENSE_CHANNEL))
|
|
||||||
#else
|
|
||||||
#define ADC_CHANNELS \
|
#define ADC_CHANNELS \
|
||||||
((1 << ADC_BATTERY1_VOLTAGE_CHANNEL) | \
|
((1 << ADC_BATTERY1_VOLTAGE_CHANNEL) | \
|
||||||
(1 << ADC_BATTERY1_CURRENT_CHANNEL) | \
|
(1 << ADC_BATTERY1_CURRENT_CHANNEL) | \
|
||||||
@@ -454,7 +428,7 @@
|
|||||||
#define VDD_3V3_SD_CARD_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_3V3_SD_CARD_EN, (on_true))
|
#define VDD_3V3_SD_CARD_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_3V3_SD_CARD_EN, (on_true))
|
||||||
|
|
||||||
/* Tone alarm output */
|
/* Tone alarm output */
|
||||||
#if !defined(ON_EVK)
|
|
||||||
#define TONE_ALARM_TIMER 2 /* GPT 2 */
|
#define TONE_ALARM_TIMER 2 /* GPT 2 */
|
||||||
#define TONE_ALARM_CHANNEL 3 /* GPIO_AD_B1_07 GPT2_COMPARE3 */
|
#define TONE_ALARM_CHANNEL 3 /* GPIO_AD_B1_07 GPT2_COMPARE3 */
|
||||||
|
|
||||||
@@ -462,7 +436,7 @@
|
|||||||
|
|
||||||
#define GPIO_TONE_ALARM_IDLE GPIO_BUZZER_1
|
#define GPIO_TONE_ALARM_IDLE GPIO_BUZZER_1
|
||||||
#define GPIO_TONE_ALARM GPIO_GPT2_COMPARE3_1
|
#define GPIO_TONE_ALARM GPIO_GPT2_COMPARE3_1
|
||||||
#endif
|
|
||||||
/* USB OTG FS
|
/* USB OTG FS
|
||||||
*
|
*
|
||||||
* VBUS_VALID is detected in USB_ANALOG_USB1_VBUS_DETECT_STAT
|
* VBUS_VALID is detected in USB_ANALOG_USB1_VBUS_DETECT_STAT
|
||||||
@@ -574,12 +548,6 @@
|
|||||||
GPIO_GPIO0_INPUT, \
|
GPIO_GPIO0_INPUT, \
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(ON_EVK)
|
|
||||||
#define PX4_GPIO_INIT_LIST { \
|
|
||||||
PX4_ADC_GPIO, \
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
#define PX4_GPIO_INIT_LIST { \
|
#define PX4_GPIO_INIT_LIST { \
|
||||||
PX4_ADC_GPIO, \
|
PX4_ADC_GPIO, \
|
||||||
GPIO_HW_VER_REV_DRIVE, \
|
GPIO_HW_VER_REV_DRIVE, \
|
||||||
@@ -610,7 +578,6 @@
|
|||||||
GPIO_nSAFETY_SWITCH_LED_OUT_INIT, \
|
GPIO_nSAFETY_SWITCH_LED_OUT_INIT, \
|
||||||
GPIO_SAFETY_SWITCH_IN \
|
GPIO_SAFETY_SWITCH_IN \
|
||||||
}
|
}
|
||||||
#endif //defined(ON_EVK)
|
|
||||||
|
|
||||||
#define BOARD_ENABLE_CONSOLE_BUFFER
|
#define BOARD_ENABLE_CONSOLE_BUFFER
|
||||||
__BEGIN_DECLS
|
__BEGIN_DECLS
|
||||||
|
|||||||
@@ -260,7 +260,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
|||||||
led_off(LED_GREEN);
|
led_off(LED_GREEN);
|
||||||
led_off(LED_BLUE);
|
led_off(LED_BLUE);
|
||||||
|
|
||||||
#if defined(ON_EVK_SDIO) && defined(CONFIG_IMXRT_USDHC)
|
#if defined(CONFIG_IMXRT_USDHC)
|
||||||
int ret = fmurt1062_usdhc_initialize();
|
int ret = fmurt1062_usdhc_initialize();
|
||||||
|
|
||||||
if (ret != OK) {
|
if (ret != OK) {
|
||||||
@@ -269,7 +269,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
#if defined(ON_EVK_SPI)
|
|
||||||
/* Configure SPI-based devices */
|
/* Configure SPI-based devices */
|
||||||
|
|
||||||
ret = imxrt1062_spi_bus_initialize();
|
ret = imxrt1062_spi_bus_initialize();
|
||||||
@@ -279,7 +279,6 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return OK;
|
return OK;
|
||||||
}
|
}
|
||||||
@@ -298,16 +297,3 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
|
|||||||
{
|
{
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(ON_EVK)
|
|
||||||
# if !defined(CONFIG_IMXRT_LPI2C)
|
|
||||||
FAR struct i2c_master_s *imxrt_i2cbus_initialize(int port)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
int imxrt_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
# endif
|
|
||||||
#endif
|
|
||||||
|
|||||||
@@ -88,12 +88,6 @@ static const px4_hw_mft_item_t hw_mft_list_v0540[] = {
|
|||||||
static px4_hw_mft_list_entry_t mft_lists[] = {
|
static px4_hw_mft_list_entry_t mft_lists[] = {
|
||||||
{0x0000, hw_mft_list_v0500, arraySize(hw_mft_list_v0500)},
|
{0x0000, hw_mft_list_v0500, arraySize(hw_mft_list_v0500)},
|
||||||
{0x0400, hw_mft_list_v0540, arraySize(hw_mft_list_v0540)},
|
{0x0400, hw_mft_list_v0540, arraySize(hw_mft_list_v0540)},
|
||||||
#if defined(ON_EVK)
|
|
||||||
{0x0804, hw_mft_list_v0540, arraySize(hw_mft_list_v0540)},
|
|
||||||
{0x0807, hw_mft_list_v0540, arraySize(hw_mft_list_v0540)},
|
|
||||||
{0x0404, hw_mft_list_v0540, arraySize(hw_mft_list_v0540)},
|
|
||||||
#endif
|
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
|
|||||||
@@ -60,10 +60,6 @@
|
|||||||
* Definitions
|
* Definitions
|
||||||
****************************************************************************************************/
|
****************************************************************************************************/
|
||||||
|
|
||||||
#if defined(ON_EVK)
|
|
||||||
//# define DEBUG_CLOCK_EVK 1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Register accessors */
|
/* Register accessors */
|
||||||
|
|
||||||
#define _REG(_addr) (*(volatile uint16_t *)(_addr))
|
#define _REG(_addr) (*(volatile uint16_t *)(_addr))
|
||||||
@@ -233,18 +229,4 @@ __EXPORT void fmurt1062_timer_initialize(void)
|
|||||||
/* QTIMER3_TIMER0 -> Flexpwm234ExtClk */
|
/* QTIMER3_TIMER0 -> Flexpwm234ExtClk */
|
||||||
|
|
||||||
imxrt_xbar_connect(IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET, IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT);
|
imxrt_xbar_connect(IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET, IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT);
|
||||||
|
|
||||||
|
|
||||||
#if defined(DEBUG_CLOCK_EVK)
|
|
||||||
|
|
||||||
/* Make it Scope-able on J24-1 */
|
|
||||||
|
|
||||||
imxrt_xbar_connect(IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET, IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT);
|
|
||||||
|
|
||||||
imxrt_config_gpio(GPIO_XBAR1_INOUT17_1 | (IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_60OHM | IOMUX_SPEED_MAX |
|
|
||||||
IOMUX_SLEW_FAST));
|
|
||||||
modifyreg32(IMXRT_IOMUXC_GPR_GPR6, 0, GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK);
|
|
||||||
#endif /* DEBUG_CLOCK_EVK */
|
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -193,12 +193,8 @@ static int read_id_dn(int *id, uint32_t gpio_drive, uint32_t gpio_sense, int adc
|
|||||||
|
|
||||||
uint32_t dn_sum = 0;
|
uint32_t dn_sum = 0;
|
||||||
uint16_t dn = 0;
|
uint16_t dn = 0;
|
||||||
#if defined(ON_EVK)
|
|
||||||
|
|
||||||
if (1 || high || low) { // no if
|
|
||||||
#else
|
|
||||||
if ((high ^ low) && low == 0) {
|
if ((high ^ low) && low == 0) {
|
||||||
#endif
|
|
||||||
/* Yes - Fire up the ADC (it has once control) */
|
/* Yes - Fire up the ADC (it has once control) */
|
||||||
|
|
||||||
if (px4_arch_adc_init(HW_REV_VER_ADC_BASE) == OK) {
|
if (px4_arch_adc_init(HW_REV_VER_ADC_BASE) == OK) {
|
||||||
|
|||||||
Reference in New Issue
Block a user