adds_synergy_logic

This commit is contained in:
Michael Scott
2025-02-26 14:32:35 -05:00
parent 6f41f757e7
commit 8a2d76dbb4
7 changed files with 2013 additions and 1 deletions
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+1 -1
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@@ -1892,7 +1892,7 @@ __end:
#if defined(SL_RP4)
#include "SL-RP4.h"
#endif
#include "synergy.h"
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@@ -45,6 +45,7 @@
{#include "sema.txt" }
{#include "communication_blocks.txt" }
{#include "sm_cards.txt" }
{#include "synergy.txt" }
{#include "SL-RP4.txt" }
{enable code generation}
+290
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@@ -0,0 +1,290 @@
(*
* This file is part of OpenPLC - an open source Programmable
* Logic Controller compliant with IEC 61131-3
*
* Copyright (C) 2021 Thiago Alves
*
* See COPYING and COPYING.LESSER files for copyright details.
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 3 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
* USA
*
* This code is made available on the understanding that it will not be
* used in safety-critical situations without a full and competent review.
*)
(*
* An IEC 61131-3 compiler.
*
* Based on the
* FINAL DRAFT - IEC 61131-3, 2nd Ed. (2001-12-10)
*
*)
(*
* This is a dummy implementation of those block since
* its code is actually written in C, not ST
*)
(*
* SLM_INIT
* -------------
*)
FUNCTION_BLOCK SLM_INIT
VAR_INPUT
INIT : BOOL;
END_VAR
VAR_OUTPUT
SUCCESS : BOOL;
END_VAR
SUCCESS := 0;
END_FUNCTION_BLOCK
(*
* SLM_DISCRETE_OUT_8
* -------------
*)
FUNCTION_BLOCK SLM_DISCRETE_OUT_8
VAR_INPUT
SLOT : SINT;
O1 : BOOL;
O2 : BOOL;
O3 : BOOL;
O4 : BOOL;
O5 : BOOL;
O6 : BOOL;
O7 : BOOL;
O8 : BOOL;
END_VAR
VAR
DUMMY : SINT;
END_VAR
DUMMY := SLOT;
END_FUNCTION_BLOCK
(*
* SLM_DISCRETE_OUT_15
* -------------
*)
FUNCTION_BLOCK SLM_DISCRETE_OUT_15
VAR_INPUT
SLOT : SINT;
O1 : BOOL;
O2 : BOOL;
O3 : BOOL;
O4 : BOOL;
O5 : BOOL;
O6 : BOOL;
O7 : BOOL;
O8 : BOOL;
O9 : BOOL;
O10 : BOOL;
O11 : BOOL;
O12 : BOOL;
O13 : BOOL;
O14 : BOOL;
O15 : BOOL;
END_VAR
VAR
DUMMY : SINT;
END_VAR
DUMMY := SLOT;
END_FUNCTION_BLOCK
(*
* SLM_DISCRETE_OUT_16
* -------------
*)
FUNCTION_BLOCK SLM_DISCRETE_OUT_16
VAR_INPUT
SLOT : SINT;
O1 : BOOL;
O2 : BOOL;
O3 : BOOL;
O4 : BOOL;
O5 : BOOL;
O6 : BOOL;
O7 : BOOL;
O8 : BOOL;
O9 : BOOL;
O10 : BOOL;
O11 : BOOL;
O12 : BOOL;
O13 : BOOL;
O14 : BOOL;
O15 : BOOL;
O16 : BOOL;
END_VAR
VAR
DUMMY : SINT;
END_VAR
DUMMY := SLOT;
END_FUNCTION_BLOCK
(*
* SL_DISCRETE_IN_8
* -------------
*)
FUNCTION_BLOCK SLM_DISCRETE_IN_8
VAR_INPUT
SLOT : SINT;
END_VAR
VAR_OUTPUT
I1 : BOOL;
I2 : BOOL;
I3 : BOOL;
I4 : BOOL;
I5 : BOOL;
I6 : BOOL;
I7 : BOOL;
I8 : BOOL;
END_VAR
I1 := 0;
END_FUNCTION_BLOCK
(*
* SLM_DISCRETE_IN_16
* -------------
*)
FUNCTION_BLOCK SLM_DISCRETE_IN_16
VAR_INPUT
SLOT : SINT;
END_VAR
VAR_OUTPUT
I1 : BOOL;
I2 : BOOL;
I3 : BOOL;
I4 : BOOL;
I5 : BOOL;
I6 : BOOL;
I7 : BOOL;
I8 : BOOL;
I9 : BOOL;
I10 : BOOL;
I11 : BOOL;
I12 : BOOL;
I13 : BOOL;
I14 : BOOL;
I15 : BOOL;
I16 : BOOL;
END_VAR
I1 := 0;
END_FUNCTION_BLOCK
(*
* SLM_ANALOG_IN_4
* -------------
*)
FUNCTION_BLOCK SLM_ANALOG_IN_4
VAR_INPUT
SLOT : SINT;
END_VAR
VAR_OUTPUT
I1 : UINT;
I2 : UINT;
I3 : UINT;
I4 : UINT;
END_VAR
VAR
DUMMY : SINT;
END_VAR
DUMMY := 0;
END_FUNCTION_BLOCK
(*
* SLM_ANALOG_IN_8
* -------------
*)
FUNCTION_BLOCK SLM_ANALOG_IN_8
VAR_INPUT
SLOT : SINT;
END_VAR
VAR_OUTPUT
I1 : UINT;
I2 : UINT;
I3 : UINT;
I4 : UINT;
I5 : UINT;
I6 : UINT;
I7 : UINT;
I8 : UINT;
END_VAR
VAR
DUMMY : SINT;
END_VAR
DUMMY := 0;
END_FUNCTION_BLOCK
(*
* SLM_ANALOG_OUT_4
* -------------
*)
FUNCTION_BLOCK SLM_ANALOG_OUT_4
VAR_INPUT
SLOT : SINT;
O1 : UINT;
O2 : UINT;
O3 : UINT;
O4 : UINT;
END_VAR
VAR
DUMMY : SINT;
END_VAR
DUMMY := 0;
END_FUNCTION_BLOCK
(*
* SLM_ANALOG_OUT_8
* -------------
*)
FUNCTION_BLOCK SLM_ANALOG_OUT_8
VAR_INPUT
SLOT : SINT;
O1 : UINT;
O2 : UINT;
O3 : UINT;
O4 : UINT;
O5 : UINT;
O6 : UINT;
O7 : UINT;
O8 : UINT;
END_VAR
VAR
DUMMY : SINT;
END_VAR
DUMMY := 0;
END_FUNCTION_BLOCK
(*
* SLM_TEMPERATURE_4
* -------------
*)
FUNCTION_BLOCK SLM_TEMPERATURE_4
VAR_INPUT
SLOT : SINT;
END_VAR
VAR_OUTPUT
I1 : REAL;
I2 : REAL;
I3 : REAL;
I4 : REAL;
END_VAR
VAR
DUMMY : SINT;
END_VAR
DUMMY := 0;
END_FUNCTION_BLOCK
@@ -136,6 +136,13 @@ elif [ "$1" == "piplc" ]; then
echo rpi > ../scripts/openplc_platform
echo piplc > ../scripts/openplc_driver
elif [ "$1" == "synergy_logic" ]; then
echo "Activating Synergy Logic driver"
cp ./hardware_layers/synergy.cpp ./hardware_layer.cpp
echo "Setting Platform"
echo linux > ../scripts/openplc_platform
echo synergy_logic > ../scripts/openplc_driver
else
echo "Error: Invalid hardware layer"
fi
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@@ -1778,6 +1778,8 @@ def hardware():
else: return_str += "<option value='sl_rp4'>SL-RP4</option>"
if (current_driver == "piplc"): return_str += "<option selected='selected' value='piplc'>Binary-6 PiPLC</option>"
else: return_str += "<option value='piplc'>Binary-6 PiPLC</option>"
if (current_driver == "synergy_logic"): return_str += "<option selected='selected' value='synergy_logic'>Synergy Logic</option>"
else: return_str += "<option value='synergy_logic'>Synergy Logic</option>"
return_str += """
</select>
<br>