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Upgrade to CubeMX v4.20.0 and FreeRTOS v9.0.0

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sirus
2017-03-12 18:53:22 -07:00
parent dbb9424a24
commit 367fcc0342
83 changed files with 10059 additions and 5185 deletions
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Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h
+196 -73
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Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
+5 -5
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@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.6.0
* @date 04-November-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -124,11 +124,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS version number V2.6.0
* @brief CMSIS version number V2.6.1
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h
+3 -3
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@@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V2.6.0
* @date 04-November-2016
* @version V2.6.1
* @date 14-February-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
+763
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Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+127 -75
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@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -138,6 +138,7 @@
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
@@ -150,6 +151,9 @@
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
@@ -160,8 +164,16 @@
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
#if defined(STM32L0)
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
/* to the second dedicated IO (only for COMP2). */
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
#else
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
#endif
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
@@ -229,9 +241,9 @@
#define DAC1_CHANNEL_1 DAC_CHANNEL_1
#define DAC1_CHANNEL_2 DAC_CHANNEL_2
#define DAC2_CHANNEL_1 DAC_CHANNEL_1
#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
#define DAC_WAVE_NONE 0x00000000U
#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
@@ -344,6 +356,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
/**
* @}
*/
@@ -369,7 +382,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
#if defined(STM32L4) || defined(STM32F7)
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@@ -841,6 +854,8 @@
#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
#define __DIV_LPUART UART_DIV_LPUART
#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
@@ -902,48 +917,45 @@
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
#define ETH_MMCCR ((uint32_t)0x00000100U)
#define ETH_MMCRIR ((uint32_t)0x00000104U)
#define ETH_MMCTIR ((uint32_t)0x00000108U)
#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
#define ETH_MMCTIMR ((uint32_t)0x00000110U)
#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
#define ETH_MMCCR 0x00000100U
#define ETH_MMCRIR 0x00000104U
#define ETH_MMCTIR 0x00000108U
#define ETH_MMCRIMR 0x0000010CU
#define ETH_MMCTIMR 0x00000110U
#define ETH_MMCTGFSCCR 0x0000014CU
#define ETH_MMCTGFMSCCR 0x00000150U
#define ETH_MMCTGFCR 0x00000168U
#define ETH_MMCRFCECR 0x00000194U
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
/**
* @}
@@ -965,7 +977,7 @@
* @}
*/
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
@@ -990,7 +1002,7 @@
/**
* @}
*/
#endif /* STM32L4xx || STM32F7*/
#endif /* STM32L4 || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@@ -1175,6 +1187,9 @@
* @{
*/
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
#define HAL_LTDC_Relaod HAL_LTDC_Reload
#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
/**
* @}
*/
@@ -1610,7 +1625,11 @@
#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
#if defined(STM32F1)
#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
#else
#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
#endif /* STM32F1 */
#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
@@ -2216,26 +2235,26 @@
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
@@ -2637,10 +2656,22 @@
#define RCC_IT_HSI14 RCC_IT_HSI14RDY
#if defined(STM32L0)
#define RCC_IT_LSECSS RCC_IT_CSSLSE
#define RCC_IT_CSS RCC_IT_CSSHSE
#endif
#define RCC_IT_CSSLSE RCC_IT_LSECSS
#define RCC_IT_CSSHSE RCC_IT_CSS
#define RCC_PLLMUL_3 RCC_PLL_MUL3
#define RCC_PLLMUL_4 RCC_PLL_MUL4
#define RCC_PLLMUL_6 RCC_PLL_MUL6
#define RCC_PLLMUL_8 RCC_PLL_MUL8
#define RCC_PLLMUL_12 RCC_PLL_MUL12
#define RCC_PLLMUL_16 RCC_PLL_MUL16
#define RCC_PLLMUL_24 RCC_PLL_MUL24
#define RCC_PLLMUL_32 RCC_PLL_MUL32
#define RCC_PLLMUL_48 RCC_PLL_MUL48
#define RCC_PLLDIV_2 RCC_PLL_DIV2
#define RCC_PLLDIV_3 RCC_PLL_DIV3
#define RCC_PLLDIV_4 RCC_PLL_DIV4
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
@@ -2757,10 +2788,22 @@
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
/**
* @}
@@ -2891,6 +2934,14 @@
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
/**
* @}
*/
@@ -3079,6 +3130,7 @@
* @{
*/
#define __HAL_LTDC_LAYER LTDC_LAYER
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
/**
* @}
*/
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
+5 -4
View File
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_hal.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -164,7 +164,7 @@
/**
* @}
*/
/** @defgroup PVD_Lock_Enable PVD Lock
* @{
*/
@@ -220,6 +220,7 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
void HAL_GetUID(uint32_t *UID);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
void HAL_EnableMemorySwappingBank(void);
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h
+51 -51
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_adc.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -172,34 +172,34 @@ typedef struct
* @brief HAL ADC state machine: ADC states definition (bitfields)
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */
#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
/**
@@ -233,11 +233,11 @@ typedef struct
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
/**
* @}
*/
@@ -246,7 +246,7 @@ typedef struct
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
#define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
@@ -257,7 +257,7 @@ typedef struct
/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
* @{
*/
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
#define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
@@ -280,7 +280,7 @@ typedef struct
/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
#define ADC_RESOLUTION_12B 0x00000000U
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
@@ -291,7 +291,7 @@ typedef struct
/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
@@ -304,7 +304,7 @@ typedef struct
*/
/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
/* compatibility with other STM32 devices. */
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
@@ -328,7 +328,7 @@ typedef struct
/** @defgroup ADC_Data_align ADC Data Align
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define ADC_DATAALIGN_RIGHT 0x00000000U
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
/**
* @}
@@ -337,7 +337,7 @@ typedef struct
/** @defgroup ADC_channels ADC Common Channels
* @{
*/
#define ADC_CHANNEL_0 ((uint32_t)0x00000000U)
#define ADC_CHANNEL_0 0x00000000U
#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
@@ -366,7 +366,7 @@ typedef struct
/** @defgroup ADC_sampling_times ADC Sampling Times
* @{
*/
#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
#define ADC_SAMPLETIME_3CYCLES 0x00000000U
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
@@ -381,9 +381,9 @@ typedef struct
/** @defgroup ADC_EOCSelection ADC EOC Selection
* @{
*/
#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */
#define ADC_EOC_SEQ_CONV 0x00000000U
#define ADC_EOC_SINGLE_CONV 0x00000001U
#define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */
/**
* @}
*/
@@ -406,7 +406,7 @@ typedef struct
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)
#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
/**
* @}
*/
@@ -438,9 +438,9 @@ typedef struct
/** @defgroup ADC_channels_type ADC Channels Type
* @{
*/
#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */
#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
#define ADC_ALL_CHANNELS 0x00000001U
#define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */
#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */
/**
* @}
*/
@@ -597,11 +597,11 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/* Delay for ADC stabilization time. */
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
/* Unit: us */
#define ADC_STAB_DELAY_US ((uint32_t) 3U)
#define ADC_STAB_DELAY_US 3U
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
#define ADC_TEMPSENSOR_DELAY_US 10U
/**
* @}
*/
@@ -729,16 +729,16 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFFU))
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)16U)))
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1U)) && ((NUMBER) <= ((uint32_t)8U)))
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U)))
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU)))
/**
* @brief Set ADC Regular channel sequence length.
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h
+25 -14
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -152,7 +152,7 @@ typedef struct
/** @defgroup ADCEx_Common_mode ADC Common Mode
* @{
*/
#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U)
#define ADC_MODE_INDEPENDENT 0x00000000U
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
@@ -172,7 +172,7 @@ typedef struct
/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
* @{
*/
#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U) /*!< DMA mode disabled */
#define ADC_DMAACCESSMODE_DISABLED 0x00000000U /*!< DMA mode disabled */
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
@@ -183,7 +183,7 @@ typedef struct
/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
* @{
*/
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE 0x00000000U
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
@@ -194,7 +194,7 @@ typedef struct
/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
* @{
*/
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 0x00000000U
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
@@ -218,10 +218,10 @@ typedef struct
/** @defgroup ADCEx_injected_rank ADC Injected Rank
* @{
*/
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U)
#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U)
#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U)
#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U)
#define ADC_INJECTED_RANK_1 0x00000001U
#define ADC_INJECTED_RANK_2 0x00000002U
#define ADC_INJECTED_RANK_3 0x00000003U
#define ADC_INJECTED_RANK_4 0x00000004U
/**
* @}
*/
@@ -239,7 +239,7 @@ typedef struct
#if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT ((uint32_t)0x10000000U) /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
#endif /* STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
@@ -372,8 +372,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)4U)))
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)4U)))
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= 4U))
/**
* @brief Set the selected injected Channel rank.
@@ -384,6 +384,17 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
*/
#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
/**
* @brief Defines if the selected ADC is within ADC common register ADC123 or ADC1
* if available (ADC2, ADC3 availability depends on STM32 product)
* @param __HANDLE__: ADC handle
* @retval Common control register ADC123 or ADC1
*/
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define ADC_COMMON_REGISTER(__HANDLE__) ADC123_COMMON
#else
#define ADC_COMMON_REGISTER(__HANDLE__) ADC1_COMMON
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx || STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h
+60 -60
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_can.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -128,21 +128,21 @@ typedef struct
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
@@ -173,7 +173,7 @@ typedef struct
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFFU */
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
This parameter can be a value of @ref CAN_Identifier_Type */
@@ -198,7 +198,7 @@ typedef struct
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFFU */
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
This parameter can be a value of @ref CAN_Identifier_Type */
@@ -270,8 +270,8 @@ typedef struct
/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
#define CAN_INITSTATUS_FAILED ((uint8_t)0x00U) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01U) /*!< CAN initialization OK */
#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
/**
* @}
*/
@@ -279,7 +279,7 @@ typedef struct
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
#define CAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
@@ -290,7 +290,7 @@ typedef struct
/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
* @{
*/
#define CAN_SJW_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
@@ -301,7 +301,7 @@ typedef struct
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
* @{
*/
#define CAN_BS1_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
@@ -324,7 +324,7 @@ typedef struct
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
* @{
*/
#define CAN_BS2_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
@@ -339,8 +339,8 @@ typedef struct
/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
/**
* @}
*/
@@ -348,8 +348,8 @@ typedef struct
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
/**
* @}
*/
@@ -357,8 +357,8 @@ typedef struct
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
@@ -366,8 +366,8 @@ typedef struct
/** @defgroup CAN_Identifier_Type CAN Identifier Type
* @{
*/
#define CAN_ID_STD ((uint32_t)0x00000000U) /*!< Standard Id */
#define CAN_ID_EXT ((uint32_t)0x00000004U) /*!< Extended Id */
#define CAN_ID_STD 0x00000000U /*!< Standard Id */
#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
/**
* @}
*/
@@ -375,8 +375,8 @@ typedef struct
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
#define CAN_RTR_DATA ((uint32_t)0x00000000U) /*!< Data frame */
#define CAN_RTR_REMOTE ((uint32_t)0x00000002U) /*!< Remote frame */
#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
/**
* @}
*/
@@ -384,8 +384,8 @@ typedef struct
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
/**
* @}
*/
@@ -399,37 +399,37 @@ typedef struct
CAN_GetFlagStatus() function. */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500U) /*!< Request MailBox0 flag */
#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508U) /*!< Request MailBox1 flag */
#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510U) /*!< Request MailBox2 flag */
#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501U) /*!< Transmission OK MailBox0 flag */
#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509U) /*!< Transmission OK MailBox1 flag */
#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511U) /*!< Transmission OK MailBox2 flag */
#define CAN_FLAG_TME0 ((uint32_t)0x0000051AU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 ((uint32_t)0x0000051BU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME2 ((uint32_t)0x0000051CU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */
#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */
#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */
#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */
#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */
#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */
#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */
/* Receive Flags */
#define CAN_FLAG_FF0 ((uint32_t)0x00000203U) /*!< FIFO 0 Full flag */
#define CAN_FLAG_FOV0 ((uint32_t)0x00000204U) /*!< FIFO 0 Overrun flag */
#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */
#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */
#define CAN_FLAG_FF1 ((uint32_t)0x00000403U) /*!< FIFO 1 Full flag */
#define CAN_FLAG_FOV1 ((uint32_t)0x00000404U) /*!< FIFO 1 Overrun flag */
#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */
#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */
/* Operating Mode Flags */
#define CAN_FLAG_INAK ((uint32_t)0x00000100U) /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK ((uint32_t)0x00000101U) /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI ((uint32_t)0x00000102U) /*!< Error flag */
#define CAN_FLAG_WKU ((uint32_t)0x00000103U) /*!< Wake up flag */
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104U) /*!< Sleep acknowledge flag */
#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */
#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */
#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x00000300U) /*!< Error warning flag */
#define CAN_FLAG_EPV ((uint32_t)0x00000301U) /*!< Error passive flag */
#define CAN_FLAG_BOF ((uint32_t)0x00000302U) /*!< Bus-Off flag */
#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */
#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */
#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */
/**
* @}
*/
@@ -464,9 +464,9 @@ typedef struct
/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
* @{
*/
#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
/**
* @}
*/
@@ -509,7 +509,7 @@ typedef struct
* @retval The number of pending message.
*/
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & (uint32_t)0x03U)))
((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
/** @brief Check whether the specified CAN flag is set or not.
* @param __HANDLE__: CAN Handle
@@ -570,9 +570,9 @@ typedef struct
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))))
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
@@ -705,8 +705,8 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
#define CAN_FLAG_MASK ((uint32_t)0x000000FFU)
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
#define CAN_FLAG_MASK 0x000000FFU
/**
* @}
*/
@@ -733,10 +733,10 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
((FIFO) == CAN_FILTER_FIFO1))
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFFU))
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h
+88 -127
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_cortex.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -58,7 +58,7 @@
* @{
*/
#if (__MPU_PRESENT == 1)
#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
@@ -105,16 +105,16 @@ typedef struct
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
0 bits for subpriority */
/**
* @}
*/
@@ -122,8 +122,8 @@ typedef struct
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/**
* @}
@@ -133,10 +133,11 @@ typedef struct
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/**
* @}
*/
@@ -144,8 +145,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01U)
#define MPU_REGION_DISABLE ((uint8_t)0x00U)
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
* @}
*/
@@ -153,8 +154,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/**
* @}
*/
@@ -162,8 +163,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/**
* @}
*/
@@ -171,8 +172,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/**
* @}
*/
@@ -180,8 +181,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/**
* @}
*/
@@ -189,9 +190,9 @@ typedef struct
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
/**
* @}
*/
@@ -199,34 +200,34 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/**
* @}
*/
@@ -234,12 +235,12 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
*/
@@ -247,14 +248,14 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/**
* @}
*/
@@ -273,8 +274,8 @@ typedef struct
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @{
*/
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
@@ -287,12 +288,9 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @{
*/
* @{
*/
/* Peripheral Control functions ***********************************************/
#if (__MPU_PRESENT == 1)
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
@@ -302,6 +300,12 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1U)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
/**
* @}
*/
@@ -397,57 +401,14 @@ void HAL_SYSTICK_Callback(void);
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
* @brief CORTEX private functions
* @{
*/
#if (__MPU_PRESENT == 1)
/**
* @brief Disables the MPU
* @retval None
*/
__STATIC_INLINE void HAL_MPU_Disable(void)
{
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU */
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/**
* @brief Enables the MPU
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
}
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
+7 -7
View File
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_hal_def.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,7 +102,7 @@ typedef enum
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
#if (USE_RTOS == 1)
#if (USE_RTOS == 1U)
/* Reserved for future use */
#error "USE_RTOS should be 0 in the current HAL release"
#else
@@ -116,12 +116,12 @@ typedef enum
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0)
}while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
}while (0U)
#endif /* USE_RTOS */
#if defined ( __GNUC__ )
@@ -148,7 +148,7 @@ typedef enum
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h
+105 -105
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dma.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -133,8 +133,8 @@ typedef enum
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
/**
@@ -142,13 +142,13 @@ typedef enum
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
}HAL_DMA_CallbackIDTypeDef;
/**
@@ -156,33 +156,33 @@ typedef enum
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Stream_TypeDef *Instance; /*!< Register base address */
DMA_Stream_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
HAL_LockTypeDef Lock; /*!< DMA locking object */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
__IO uint32_t ErrorCode; /*!< DMA Error code */
uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
uint32_t StreamIndex; /*!< DMA Stream Index */
uint32_t StreamIndex; /*!< DMA Stream Index */
}DMA_HandleTypeDef;
@@ -201,14 +201,14 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */
#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */
#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
/**
* @}
*/
@@ -217,23 +217,23 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA channel selection
* @{
*/
#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */
#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */
#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */
#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */
#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */
#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
#if defined (DMA_SxCR_CHSEL_3)
#define DMA_CHANNEL_8 ((uint32_t)0x10000000U) /*!< DMA Channel 8 */
#define DMA_CHANNEL_9 ((uint32_t)0x12000000U) /*!< DMA Channel 9 */
#define DMA_CHANNEL_10 ((uint32_t)0x14000000U) /*!< DMA Channel 10 */
#define DMA_CHANNEL_11 ((uint32_t)0x16000000U) /*!< DMA Channel 11 */
#define DMA_CHANNEL_12 ((uint32_t)0x18000000U) /*!< DMA Channel 12 */
#define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) /*!< DMA Channel 13 */
#define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) /*!< DMA Channel 14 */
#define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) /*!< DMA Channel 15 */
#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */
#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */
#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */
#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */
#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */
#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */
#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */
#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */
#endif /* DMA_SxCR_CHSEL_3 */
/**
* @}
@@ -243,9 +243,9 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
/**
* @}
*/
@@ -254,8 +254,8 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
/**
* @}
*/
@@ -264,8 +264,8 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
/**
* @}
*/
@@ -274,9 +274,9 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
/**
* @}
*/
@@ -285,9 +285,9 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
/**
* @}
*/
@@ -296,9 +296,9 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA mode
* @{
*/
#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
/**
* @}
*/
@@ -307,10 +307,10 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA priority levels
* @{
*/
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
/**
* @}
*/
@@ -319,8 +319,8 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA FIFO direct mode
* @{
*/
#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
/**
* @}
*/
@@ -329,7 +329,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA FIFO level
* @{
*/
#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
@@ -341,10 +341,10 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA memory burst
* @{
*/
#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
#define DMA_MBURST_SINGLE 0x00000000U
#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
/**
* @}
*/
@@ -353,10 +353,10 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA peripheral burst
* @{
*/
#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
#define DMA_PBURST_SINGLE 0x00000000U
#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
/**
* @}
*/
@@ -365,11 +365,11 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA interrupts definition
* @{
*/
#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
#define DMA_IT_FE ((uint32_t)0x00000080U)
#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
#define DMA_IT_FE 0x00000080U
/**
* @}
*/
@@ -378,26 +378,26 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA flag definitions
* @{
*/
#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
#define DMA_FLAG_FEIF0_4 0x00800001U
#define DMA_FLAG_DMEIF0_4 0x00800004U
#define DMA_FLAG_TEIF0_4 0x00000008U
#define DMA_FLAG_HTIF0_4 0x00000010U
#define DMA_FLAG_TCIF0_4 0x00000020U
#define DMA_FLAG_FEIF1_5 0x00000040U
#define DMA_FLAG_DMEIF1_5 0x00000100U
#define DMA_FLAG_TEIF1_5 0x00000200U
#define DMA_FLAG_HTIF1_5 0x00000400U
#define DMA_FLAG_TCIF1_5 0x00000800U
#define DMA_FLAG_FEIF2_6 0x00010000U
#define DMA_FLAG_DMEIF2_6 0x00040000U
#define DMA_FLAG_TEIF2_6 0x00080000U
#define DMA_FLAG_HTIF2_6 0x00100000U
#define DMA_FLAG_TCIF2_6 0x00200000U
#define DMA_FLAG_FEIF3_7 0x00400000U
#define DMA_FLAG_DMEIF3_7 0x01000000U
#define DMA_FLAG_TEIF3_7 0x02000000U
#define DMA_FLAG_HTIF3_7 0x04000000U
#define DMA_FLAG_TCIF3_7 0x08000000U
/**
* @}
*/
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h
+3 -3
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h
+42 -38
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_flash.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -105,13 +105,13 @@ typedef struct
* @brief FLASH Error Code
* @{
*/
#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000001U) /*!< Read Protection error */
#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000002U) /*!< Programming Sequence error */
#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */
#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */
#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */
#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */
#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_FLASH_ERROR_RD 0x00000001U /*!< Read Protection error */
#define HAL_FLASH_ERROR_PGS 0x00000002U /*!< Programming Sequence error */
#define HAL_FLASH_ERROR_PGP 0x00000004U /*!< Programming Parallelism error */
#define HAL_FLASH_ERROR_PGA 0x00000008U /*!< Programming Alignment error */
#define HAL_FLASH_ERROR_WRP 0x00000010U /*!< Write protection error */
#define HAL_FLASH_ERROR_OPERATION 0x00000020U /*!< Operation Error */
/**
* @}
*/
@@ -119,10 +119,10 @@ typedef struct
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */
#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */
#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */
#define FLASH_TYPEPROGRAM_BYTE 0x00000000U /*!< Program byte (8-bit) at a specified address */
#define FLASH_TYPEPROGRAM_HALFWORD 0x00000001U /*!< Program a half-word (16-bit) at a specified address */
#define FLASH_TYPEPROGRAM_WORD 0x00000002U /*!< Program a word (32-bit) at a specified address */
#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00000003U /*!< Program a double word (64-bit) at a specified address */
/**
* @}
*/
@@ -137,7 +137,9 @@ typedef struct
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */
#define FLASH_FLAG_RDERR ((uint32_t)0x00000100U) /*!< Read Protection error flag (PCROP) */
#if defined(FLASH_SR_RDERR)
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read Protection error flag (PCROP) */
#endif /* FLASH_SR_RDERR */
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
/**
* @}
@@ -148,7 +150,7 @@ typedef struct
* @{
*/
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */
#define FLASH_IT_ERR 0x02000000U /*!< Error Interrupt source */
/**
* @}
*/
@@ -156,11 +158,11 @@ typedef struct
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
* @{
*/
#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)
#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100U)
#define FLASH_PSIZE_WORD ((uint32_t)0x00000200U)
#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300U)
#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU)
#define FLASH_PSIZE_BYTE 0x00000000U
#define FLASH_PSIZE_HALF_WORD 0x00000100U
#define FLASH_PSIZE_WORD 0x00000200U
#define FLASH_PSIZE_DOUBLE_WORD 0x00000300U
#define CR_PSIZE_MASK 0xFFFFFCFFU
/**
* @}
*/
@@ -168,11 +170,11 @@ typedef struct
/** @defgroup FLASH_Keys FLASH Keys
* @{
*/
#define RDP_KEY ((uint16_t)0x00A5U)
#define FLASH_KEY1 ((uint32_t)0x45670123U)
#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)
#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)
#define RDP_KEY ((uint16_t)0x00A5)
#define FLASH_KEY1 0x45670123U
#define FLASH_KEY2 0xCDEF89ABU
#define FLASH_OPT_KEY1 0x08192A3BU
#define FLASH_OPT_KEY2 0x4C5D6E7FU
/**
* @}
*/
@@ -243,7 +245,7 @@ typedef struct
*/
#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \
FLASH->ACR &= ~FLASH_ACR_ICRST; \
}while(0)
}while(0U)
/**
* @brief Resets the FLASH data Cache.
@@ -252,7 +254,7 @@ typedef struct
*/
#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \
FLASH->ACR &= ~FLASH_ACR_DCRST; \
}while(0)
}while(0U)
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ : FLASH interrupt
@@ -275,22 +277,23 @@ typedef struct
/**
* @brief Get the specified FLASH flag status.
* @param __FLAG__: specifies the FLASH flag to check.
* This parameter can be one of the following values:
* @param __FLAG__: specifies the FLASH flags to check.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
* @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)
* @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
* @arg FLASH_FLAG_BSY : FLASH Busy flag
* (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
/**
* @brief Clear the specified FLASH flag.
* @brief Clear the specified FLASH flags.
* @param __FLAG__: specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
@@ -299,7 +302,8 @@ typedef struct
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
* @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)
* @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
* (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices
* @retval none
*/
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
@@ -374,23 +378,23 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @brief ACR register byte 0 (Bits[7:0]) base address
*/
#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00U)
#define ACR_BYTE0_ADDRESS 0x40023C00U
/**
* @brief OPTCR register byte 0 (Bits[7:0]) base address
*/
#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14U)
#define OPTCR_BYTE0_ADDRESS 0x40023C14U
/**
* @brief OPTCR register byte 1 (Bits[15:8]) base address
*/
#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15U)
#define OPTCR_BYTE1_ADDRESS 0x40023C15U
/**
* @brief OPTCR register byte 2 (Bits[23:16]) base address
*/
#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16U)
#define OPTCR_BYTE2_ADDRESS 0x40023C16U
/**
* @brief OPTCR register byte 3 (Bits[31:24]) base address
*/
#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17U)
#define OPTCR_BYTE3_ADDRESS 0x40023C17U
/**
* @}
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h
+267 -265
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File diff suppressed because it is too large Load Diff
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h
+3 -3
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ramfunc.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
+41 -41
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_gpio.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -101,25 +101,25 @@ typedef enum
/** @defgroup GPIO_pins_define GPIO pins define
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
/**
* @}
*/
@@ -134,21 +134,21 @@ typedef enum
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
*/
#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */
#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@@ -157,10 +157,10 @@ typedef enum
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< IO works at 2 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
/**
* @}
*/
@@ -169,9 +169,9 @@ typedef enum
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */
#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */
#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
/**
* @}
*/
@@ -280,7 +280,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00U)
#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
+513 -512
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File diff suppressed because it is too large Load Diff
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h
+23 -23
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pcd.h
* @author MCD Application Team
* @version V1.5.2
* @date 22-September-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,7 +46,7 @@
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_usb.h"
@@ -82,7 +82,7 @@ typedef enum
LPM_L0 = 0x00U, /* on */
LPM_L1 = 0x01U, /* LPM L1 sleep */
LPM_L2 = 0x02U, /* suspend */
LPM_L3 = 0x03U /* off */
LPM_L3 = 0x03U /* off */
}PCD_LPM_StateTypeDef;
#endif /* USB_OTG_GLPMCFG_LPMEN */
@@ -97,11 +97,11 @@ typedef struct
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
PCD_EPTypeDef IN_ep[16U]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[16U]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
uint32_t Setup[12]; /*!< Setup packet buffer */
uint32_t Setup[12U]; /*!< Setup packet buffer */
#ifdef USB_OTG_GLPMCFG_LPMEN
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
@@ -182,16 +182,16 @@ typedef struct
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10U)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000U) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000U) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
#define USB_OTG_HS_WAKEUP_EXTI_LINE 0x00100000U /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
#define USB_OTG_FS_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
@@ -200,17 +200,17 @@ typedef struct
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
}while(0)
}while(0U)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
}while(0)
}while(0U)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
}while(0)
}while(0U)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
@@ -221,17 +221,17 @@ typedef struct
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
}while(0)
}while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
}while(0)
}while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
}while(0)
}while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
/**
@@ -332,7 +332,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
STM32F412Vx || STM32F412Cx */
STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
#ifdef __cplusplus
}
#endif
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h
+13 -13
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.5.2
* @date 22-September-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,7 +46,7 @@
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -59,15 +59,15 @@
*/
/* Exported types ------------------------------------------------------------*/
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
typedef enum
{
PCD_LPM_L0_ACTIVE = 0x00U, /* on */
PCD_LPM_L1_ACTIVE = 0x01U /* LPM L1 sleep */
}PCD_LPM_MsgTypeDef;
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx*/
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
typedef enum
{
PCD_BCD_ERROR = 0xFFU,
@@ -77,7 +77,7 @@ typedef enum
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFBU,
PCD_BCD_DISCOVERY_COMPLETED = 0x00U
}PCD_BCD_MsgTypeDef;
#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
@@ -91,19 +91,19 @@ typedef enum
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
void HAL_PCDEx_ADP_Sensing_Start(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_ADP_Sensing_Callback(PCD_HandleTypeDef *hpcd);
#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx*/
/**
* @}
@@ -122,7 +122,7 @@ void HAL_PCDEx_ADP_Sensing_Callback(PCD_HandleTypeDef *hpcd);
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
STM32F412Vx || STM32F412Cx */
STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
#ifdef __cplusplus
}
#endif
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h
+18 -18
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pwr.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -84,7 +84,7 @@ typedef struct
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
* @{
*/
#define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100U)
#define PWR_WAKEUP_PIN1 0x00000100U
/**
* @}
*/
@@ -108,13 +108,13 @@ typedef struct
/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@@ -123,7 +123,7 @@ typedef struct
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
#define PWR_MAINREGULATOR_ON 0x00000000U
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
/**
* @}
@@ -132,8 +132,8 @@ typedef struct
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
/**
* @}
*/
@@ -141,8 +141,8 @@ typedef struct
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
/**
* @}
*/
@@ -255,7 +255,7 @@ typedef struct
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
}while(0)
}while(0U)
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
@@ -264,7 +264,7 @@ typedef struct
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
}while(0)
}while(0U)
/**
* @brief checks whether the specified PVD Exti interrupt flag is set or not.
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h
+8 -8
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -87,7 +87,7 @@
*/
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
#define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00000000U) /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
#define PWR_REGULATOR_VOLTAGE_SCALE2 0x00000000U /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
#else
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
180 MHz by activating the over-drive mode. */
@@ -103,10 +103,10 @@
/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
* @{
*/
#define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080U)
#define PWR_WAKEUP_PIN2 0x00000080U
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
#define PWR_WAKEUP_PIN3 ((uint32_t)0x00000040U)
#define PWR_WAKEUP_PIN3 0x00000040U
#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \
STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
/**
@@ -140,7 +140,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
UNUSED(tmpreg); \
} while(0)
} while(0U)
#else
/** @brief macros configure the main internal regulator output voltage.
* @param __REGULATOR__: specifies the regulator output voltage to achieve
@@ -158,7 +158,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
UNUSED(tmpreg); \
} while(0)
} while(0U)
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
+112 -112
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rcc.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -123,11 +123,11 @@ typedef struct
/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
#define RCC_OSCILLATORTYPE_NONE 0x00000000U
#define RCC_OSCILLATORTYPE_HSE 0x00000001U
#define RCC_OSCILLATORTYPE_HSI 0x00000002U
#define RCC_OSCILLATORTYPE_LSE 0x00000004U
#define RCC_OSCILLATORTYPE_LSI 0x00000008U
/**
* @}
*/
@@ -135,7 +135,7 @@ typedef struct
/** @defgroup RCC_HSE_Config HSE Config
* @{
*/
#define RCC_HSE_OFF ((uint32_t)0x00000000U)
#define RCC_HSE_OFF 0x00000000U
#define RCC_HSE_ON RCC_CR_HSEON
#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
/**
@@ -145,7 +145,7 @@ typedef struct
/** @defgroup RCC_LSE_Config LSE Config
* @{
*/
#define RCC_LSE_OFF ((uint32_t)0x00000000U)
#define RCC_LSE_OFF 0x00000000U
#define RCC_LSE_ON RCC_BDCR_LSEON
#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
/**
@@ -155,10 +155,10 @@ typedef struct
/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
#define RCC_HSI_OFF ((uint8_t)0x00U)
#define RCC_HSI_ON ((uint8_t)0x01U)
#define RCC_HSI_OFF ((uint8_t)0x00)
#define RCC_HSI_ON ((uint8_t)0x01)
#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
/**
* @}
*/
@@ -166,8 +166,8 @@ typedef struct
/** @defgroup RCC_LSI_Config LSI Config
* @{
*/
#define RCC_LSI_OFF ((uint8_t)0x00U)
#define RCC_LSI_ON ((uint8_t)0x01U)
#define RCC_LSI_OFF ((uint8_t)0x00)
#define RCC_LSI_ON ((uint8_t)0x01)
/**
* @}
*/
@@ -175,9 +175,9 @@ typedef struct
/** @defgroup RCC_PLL_Config PLL Config
* @{
*/
#define RCC_PLL_NONE ((uint8_t)0x00U)
#define RCC_PLL_OFF ((uint8_t)0x01U)
#define RCC_PLL_ON ((uint8_t)0x02U)
#define RCC_PLL_NONE ((uint8_t)0x00)
#define RCC_PLL_OFF ((uint8_t)0x01)
#define RCC_PLL_ON ((uint8_t)0x02)
/**
* @}
*/
@@ -185,10 +185,10 @@ typedef struct
/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
* @{
*/
#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
#define RCC_PLLP_DIV2 0x00000002U
#define RCC_PLLP_DIV4 0x00000004U
#define RCC_PLLP_DIV6 0x00000006U
#define RCC_PLLP_DIV8 0x00000008U
/**
* @}
*/
@@ -205,10 +205,10 @@ typedef struct
/** @defgroup RCC_System_Clock_Type System Clock Type
* @{
*/
#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
#define RCC_CLOCKTYPE_SYSCLK 0x00000001U
#define RCC_CLOCKTYPE_HCLK 0x00000002U
#define RCC_CLOCKTYPE_PCLK1 0x00000004U
#define RCC_CLOCKTYPE_PCLK2 0x00000008U
/**
* @}
*/
@@ -270,38 +270,38 @@ typedef struct
/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
* @{
*/
#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
#define RCC_RTCCLKSOURCE_LSE 0x00000100U
#define RCC_RTCCLKSOURCE_LSI 0x00000200U
#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
/**
* @}
*/
@@ -309,8 +309,8 @@ typedef struct
/** @defgroup RCC_MCO_Index MCO Index
* @{
*/
#define RCC_MCO1 ((uint32_t)0x00000000U)
#define RCC_MCO2 ((uint32_t)0x00000001U)
#define RCC_MCO1 0x00000000U
#define RCC_MCO2 0x00000001U
/**
* @}
*/
@@ -318,7 +318,7 @@ typedef struct
/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
* @{
*/
#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
#define RCC_MCO1SOURCE_HSI 0x00000000U
#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
@@ -329,7 +329,7 @@ typedef struct
/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
* @{
*/
#define RCC_MCODIV_1 ((uint32_t)0x00000000U)
#define RCC_MCODIV_1 0x00000000U
#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
@@ -341,13 +341,13 @@ typedef struct
/** @defgroup RCC_Interrupt Interrupts
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01U)
#define RCC_IT_LSERDY ((uint8_t)0x02U)
#define RCC_IT_HSIRDY ((uint8_t)0x04U)
#define RCC_IT_HSERDY ((uint8_t)0x08U)
#define RCC_IT_PLLRDY ((uint8_t)0x10U)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
#define RCC_IT_CSS ((uint8_t)0x80U)
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define RCC_IT_CSS ((uint8_t)0x80)
/**
* @}
*/
@@ -362,23 +362,23 @@ typedef struct
* @{
*/
/* Flags in the CR register */
#define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
#define RCC_FLAG_HSERDY ((uint8_t)0x31U)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
/* Flags in the BDCR register */
#define RCC_FLAG_LSERDY ((uint8_t)0x41U)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
/* Flags in the CSR register */
#define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
#define RCC_FLAG_BORRST ((uint8_t)0x79U)
#define RCC_FLAG_PINRST ((uint8_t)0x7AU)
#define RCC_FLAG_PORRST ((uint8_t)0x7BU)
#define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_BORRST ((uint8_t)0x79)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
/**
* @}
*/
@@ -405,42 +405,42 @@ typedef struct
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
@@ -489,49 +489,49 @@ typedef struct
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_USART2_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
@@ -583,56 +583,56 @@ typedef struct
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_USART6_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
} while(0)
} while(0U)
#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
@@ -924,7 +924,7 @@ typedef struct
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \
} while(0)
} while(0U)
/**
* @}
*/
@@ -967,7 +967,7 @@ typedef struct
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0)
} while(0U)
/**
* @}
*/
@@ -1008,7 +1008,7 @@ typedef struct
#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
} while (0)
} while(0U)
/** @brief Macros to force or release the Backup domain reset.
* @note This function resets the RTC peripheral (including the backup registers)
@@ -1225,7 +1225,7 @@ typedef struct
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define RCC_FLAG_MASK ((uint8_t)0x1FU)
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
/**
* @}
@@ -1319,7 +1319,7 @@ void HAL_RCC_CSSCallback(void);
#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
/* CR register byte 3 (Bits[23:16]) base address */
#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)
#define RCC_CR_BYTE2_ADDRESS 0x40023802U
/* CIR register byte 2 (Bits[15:8]) base address */
#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
@@ -1330,12 +1330,12 @@ void HAL_RCC_CSSCallback(void);
/* BDCR register base address */
#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U)
#define RCC_DBP_TIMEOUT_VALUE 2U
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
#define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
#define HSI_TIMEOUT_VALUE 2U /* 2 ms */
#define LSI_TIMEOUT_VALUE 2U /* 2 ms */
/**
* @}
@@ -1412,7 +1412,7 @@ void HAL_RCC_CSSCallback(void);
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
#define IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U))
#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
+455 -465
View File
File diff suppressed because it is too large Load Diff
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h
+36 -32
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_spi.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -165,13 +165,13 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Error_Code SPI Error Code
* @{
*/
#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) /*!< MODF error */
#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) /*!< CRC error */
#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) /*!< OVR error */
#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) /*!< FRE error */
#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) /*!< Flag: RXNE,TXE, BSY */
#define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */
#define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */
#define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */
#define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */
#define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */
#define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */
/**
* @}
*/
@@ -179,7 +179,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Mode SPI Mode
* @{
*/
#define SPI_MODE_SLAVE ((uint32_t)0x00000000U)
#define SPI_MODE_SLAVE 0x00000000U
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
/**
* @}
@@ -188,7 +188,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Direction SPI Direction Mode
* @{
*/
#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U)
#define SPI_DIRECTION_2LINES 0x00000000U
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
/**
@@ -198,7 +198,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000U)
#define SPI_DATASIZE_8BIT 0x00000000U
#define SPI_DATASIZE_16BIT SPI_CR1_DFF
/**
* @}
@@ -207,7 +207,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
#define SPI_POLARITY_LOW ((uint32_t)0x00000000U)
#define SPI_POLARITY_LOW 0x00000000U
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
/**
* @}
@@ -216,7 +216,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
#define SPI_PHASE_1EDGE ((uint32_t)0x00000000U)
#define SPI_PHASE_1EDGE 0x00000000U
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
/**
* @}
@@ -226,8 +226,8 @@ typedef struct __SPI_HandleTypeDef
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U)
#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U)
#define SPI_NSS_HARD_INPUT 0x00000000U
#define SPI_NSS_HARD_OUTPUT 0x00040000U
/**
* @}
*/
@@ -235,14 +235,14 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U)
#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U)
#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U)
#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U)
#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U)
#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U)
#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U)
#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U)
#define SPI_BAUDRATEPRESCALER_2 0x00000000U
#define SPI_BAUDRATEPRESCALER_4 0x00000008U
#define SPI_BAUDRATEPRESCALER_8 0x00000010U
#define SPI_BAUDRATEPRESCALER_16 0x00000018U
#define SPI_BAUDRATEPRESCALER_32 0x00000020U
#define SPI_BAUDRATEPRESCALER_64 0x00000028U
#define SPI_BAUDRATEPRESCALER_128 0x00000030U
#define SPI_BAUDRATEPRESCALER_256 0x00000038U
/**
* @}
*/
@@ -250,7 +250,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
* @{
*/
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
#define SPI_FIRSTBIT_MSB 0x00000000U
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
/**
* @}
@@ -259,7 +259,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U)
#define SPI_TIMODE_DISABLE 0x00000000U
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
/**
* @}
@@ -268,7 +268,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U)
#define SPI_CRCCALCULATION_DISABLE 0x00000000U
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
/**
* @}
@@ -373,7 +373,7 @@ typedef struct __SPI_HandleTypeDef
tmpreg_modf = (__HANDLE__)->Instance->SR; \
(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
UNUSED(tmpreg_modf); \
} while(0)
} while(0U)
/** @brief Clear the SPI OVR pending flag.
* @param __HANDLE__: specifies the SPI Handle.
@@ -386,7 +386,7 @@ typedef struct __SPI_HandleTypeDef
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_ovr); \
} while(0)
} while(0U)
/** @brief Clear the SPI FRE pending flag.
* @param __HANDLE__: specifies the SPI Handle.
@@ -398,7 +398,7 @@ typedef struct __SPI_HandleTypeDef
__IO uint32_t tmpreg_fre = 0x00U; \
tmpreg_fre = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_fre); \
}while(0)
}while(0U)
/** @brief Enable the SPI peripheral.
* @param __HANDLE__: specifies the SPI Handle.
@@ -450,6 +450,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
@@ -459,6 +462,7 @@ void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
/**
* @}
*/
@@ -506,7 +510,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
* @retval None
*/
#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
(__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
(__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
((MODE) == SPI_MODE_MASTER))
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h
+286 -122
View File
File diff suppressed because it is too large Load Diff
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h
+23 -23
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_tim_ex.h
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -122,28 +122,28 @@ typedef struct
/** @defgroup TIMEx_Remap TIM Remap
* @{
*/
#define TIM_TIM2_TIM8_TRGO (0x00000000U)
#define TIM_TIM2_ETH_PTP (0x00000400U)
#define TIM_TIM2_USBFS_SOF (0x00000800U)
#define TIM_TIM2_USBHS_SOF (0x00000C00U)
#define TIM_TIM5_GPIO (0x00000000U)
#define TIM_TIM5_LSI (0x00000040U)
#define TIM_TIM5_LSE (0x00000080U)
#define TIM_TIM5_RTC (0x000000C0U)
#define TIM_TIM11_GPIO (0x00000000U)
#define TIM_TIM11_HSE (0x00000002U)
#define TIM_TIM2_TIM8_TRGO 0x00000000U
#define TIM_TIM2_ETH_PTP 0x00000400U
#define TIM_TIM2_USBFS_SOF 0x00000800U
#define TIM_TIM2_USBHS_SOF 0x00000C00U
#define TIM_TIM5_GPIO 0x00000000U
#define TIM_TIM5_LSI 0x00000040U
#define TIM_TIM5_LSE 0x00000080U
#define TIM_TIM5_RTC 0x000000C0U
#define TIM_TIM11_GPIO 0x00000000U
#define TIM_TIM11_HSE 0x00000002U
#if defined(STM32F413xx) || defined(STM32F423xx)
#define TIM_TIM9_TIM3_TRGO (0x10000000U)
#define TIM_TIM9_LPTIM (0x10000010U)
#define TIM_TIM5_TIM3_TRGO (0x10000000U)
#define TIM_TIM5_LPTIM (0x10000008U)
#define TIM_TIM1_TIM3_TRGO (0x10000000U)
#define TIM_TIM1_LPTIM (0x10000004U)
#define TIM_TIM9_TIM3_TRGO 0x10000000U
#define TIM_TIM9_LPTIM 0x10000010U
#define TIM_TIM5_TIM3_TRGO 0x10000000U
#define TIM_TIM5_LPTIM 0x10000008U
#define TIM_TIM1_TIM3_TRGO 0x10000000U
#define TIM_TIM1_LPTIM 0x10000004U
#endif /* STM32F413xx | STM32F423xx */
#if defined (STM32F446xx)
#define TIM_TIM11_SPDIFRX (0x00000001U)
#define TIM_TIM11_SPDIFRX 0x00000001U
#endif /* STM32F446xx */
/**
* @}
@@ -153,9 +153,9 @@ typedef struct
/** @defgroup TIMEx_SystemBreakInput TIM System Break Input
* @{
*/
#define TIM_SYSTEMBREAKINPUT_HARDFAULT ((uint32_t)0x00000001U) /* Core Lockup lock output(Hardfault) is connected to Break Input of TIM1 and TIM8 */
#define TIM_SYSTEMBREAKINPUT_PVD ((uint32_t)0x00000004U) /* PVD Interrupt is connected to Break Input of TIM1 and TIM8 */
#define TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD ((uint32_t)0x00000005U) /* Core Lockup lock output(Hardfault) and PVD Interrupt are connected to Break Input of TIM1 and TIM8 */
#define TIM_SYSTEMBREAKINPUT_HARDFAULT 0x00000001U /* Core Lockup lock output(Hardfault) is connected to Break Input of TIM1 and TIM8 */
#define TIM_SYSTEMBREAKINPUT_PVD 0x00000004U /* PVD Interrupt is connected to Break Input of TIM1 and TIM8 */
#define TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD 0x00000005U /* Core Lockup lock output(Hardfault) and PVD Interrupt are connected to Break Input of TIM1 and TIM8 */
/**
* @}
*/
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h
+9 -9
View File
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_usb.h
* @author MCD Application Team
* @version V1.5.2
* @date 22-September-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Header file of USB Core HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,7 +46,7 @@
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -379,10 +379,10 @@ typedef struct
#define HC_PID_DATA1 2U
#define HC_PID_SETUP 3U
#define GRXSTS_PKTSTS_IN 2
#define GRXSTS_PKTSTS_IN_XFER_COMP 3
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5
#define GRXSTS_PKTSTS_CH_HALTED 7
#define GRXSTS_PKTSTS_IN 2U
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
@@ -466,7 +466,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
STM32F412Vx || STM32F412Cx */
STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
#ifdef __cplusplus
}
#endif
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c
+32 -13
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -68,18 +68,18 @@
* @{
*/
/**
* @brief STM32F4xx HAL Driver version number V1.6.0
* @brief STM32F4xx HAL Driver version number V1.5.0
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
|(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\
|(__STM32F4xx_HAL_VERSION_RC))
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFFU)
#define IDCODE_DEVID_MASK 0x00000FFFU
/* ------------ RCC registers bit address in the alias region ----------- */
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
@@ -331,7 +331,7 @@ __weak uint32_t HAL_GetTick(void)
}
/**
* @brief This function provides accurate delay (in milliseconds) based
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
@@ -343,9 +343,16 @@ __weak uint32_t HAL_GetTick(void)
*/
__weak void HAL_Delay(__IO uint32_t Delay)
{
uint32_t tickstart = 0U;
tickstart = HAL_GetTick();
while((HAL_GetTick() - tickstart) < Delay)
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a period to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait++;
}
while((HAL_GetTick() - tickstart) < wait)
{
}
}
@@ -485,6 +492,18 @@ void HAL_DisableCompensationCell(void)
*(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
}
/**
* @brief Return the unique device identifier (UID based on 96 bits)
* @param UID: pointer to 3 words array.
* @retval Device identifier
*/
void HAL_GetUID(uint32_t *UID)
{
UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
/**
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c
+48 -17
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
@@ -164,7 +164,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -437,6 +437,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -489,19 +490,24 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
@@ -728,6 +734,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -781,12 +788,17 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
@@ -795,7 +807,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
@@ -1013,6 +1025,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -1066,12 +1079,17 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
@@ -1099,7 +1117,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
@@ -1279,6 +1297,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
@@ -1333,19 +1352,24 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
}
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
{
/* Enable the VBAT channel*/
ADC->CCR |= ADC_CCR_VBATE;
tmpADC_Common->CCR |= ADC_CCR_VBATE;
}
/* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
{
@@ -1498,10 +1522,17 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
ADC_Common_TypeDef *tmpADC_Common;
/* Set ADC parameters */
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Set the ADC clock prescaler */
ADC->CCR &= ~(ADC_CCR_ADCPRE);
ADC->CCR |= hadc->Init.ClockPrescaler;
tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);
tmpADC_Common->CCR |= hadc->Init.ClockPrescaler;
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c
+72 -25
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
@@ -86,7 +86,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -178,6 +178,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0U;
uint32_t tmp1 = 0U, tmp2 = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Process locked */
__HAL_LOCK(hadc);
@@ -228,9 +229,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
/* Clear injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
@@ -267,6 +273,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0U;
uint32_t tmp1 = 0U, tmp2 = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Process locked */
__HAL_LOCK(hadc);
@@ -320,9 +327,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
/* Enable end of conversion interrupt for injected channels */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
@@ -597,6 +609,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -674,20 +687,25 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
if (hadc->Init.DMAContinuousRequests != DISABLE)
{
/* Enable the selected ADC DMA request after last transfer */
ADC->CCR |= ADC_CCR_DDS;
tmpADC_Common->CCR |= ADC_CCR_DDS;
}
else
{
/* Disable the selected ADC EOC rising on each regular channel conversion */
ADC->CCR &= ~ADC_CCR_DDS;
tmpADC_Common->CCR &= ~ADC_CCR_DDS;
}
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
@@ -710,6 +728,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -720,12 +739,17 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Check if ADC is effectively disabled */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Disable the selected ADC DMA mode for multimode */
ADC->CCR &= ~ADC_CCR_DDS;
tmpADC_Common->CCR &= ~ADC_CCR_DDS;
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* DMA transfer is on going) */
@@ -756,8 +780,15 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
*/
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
{
ADC_Common_TypeDef *tmpADC_Common;
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Return the multi mode conversion value */
return ADC->CDR;
return tmpADC_Common->CDR;
}
/**
@@ -788,8 +819,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
#ifdef USE_FULL_ASSERT
uint32_t tmp = 0U;
#endif /* USE_FULL_ASSERT */
#endif /* USE_FULL_ASSERT */
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
@@ -804,7 +838,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
#endif /* USE_FULL_ASSERT */
if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
}
@@ -909,19 +943,24 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
break;
}
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
{
/* Enable the VBAT channel*/
ADC->CCR |= ADC_CCR_VBATE;
tmpADC_Common->CCR |= ADC_CCR_VBATE;
}
/* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
}
/* Process unlocked */
@@ -941,6 +980,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
{
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_ADC_MODE(multimode->Mode));
assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
@@ -948,18 +990,23 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
/* Process locked */
__HAL_LOCK(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Set ADC mode */
ADC->CCR &= ~(ADC_CCR_MULTI);
ADC->CCR |= multimode->Mode;
tmpADC_Common->CCR &= ~(ADC_CCR_MULTI);
tmpADC_Common->CCR |= multimode->Mode;
/* Set the ADC DMA access mode */
ADC->CCR &= ~(ADC_CCR_DMA);
ADC->CCR |= multimode->DMAAccessMode;
tmpADC_Common->CCR &= ~(ADC_CCR_DMA);
tmpADC_Common->CCR |= multimode->DMAAccessMode;
/* Set delay between two sampling phases */
ADC->CCR &= ~(ADC_CCR_DELAY);
ADC->CCR |= multimode->TwoSamplingDelay;
tmpADC_Common->CCR &= ~(ADC_CCR_DELAY);
tmpADC_Common->CCR |= multimode->TwoSamplingDelay;
/* Process unlocked */
__HAL_UNLOCK(hadc);
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c
+40 -48
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_can.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
* + Initialization and de-initialization functions
@@ -77,7 +77,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -360,6 +360,9 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy
uint32_t filternbrbitpos = 0U;
CAN_TypeDef *can_ip;
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* Check the parameters */
assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
@@ -368,7 +371,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy
assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
filternbrbitpos = ((uint32_t)1U) << sFilterConfig->FilterNumber;
filternbrbitpos = 1U << sFilterConfig->FilterNumber;
#if defined (CAN3)
/* Check the CAN instance */
if(hcan->Instance == CAN3)
@@ -561,7 +564,7 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
{
uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
@@ -617,7 +620,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
}
/* Set up the DLC */
hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
@@ -647,6 +650,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
hcan->State = HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hcan);
__HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
return HAL_TIMEOUT;
}
}
@@ -697,9 +701,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
{
/* Process Locked */
__HAL_LOCK(hcan);
/* Select one empty transmit mailbox */
if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
{
@@ -731,7 +733,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
}
/* Set up the DLC */
hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
@@ -758,10 +760,6 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hcan);
/* Enable Error warning, Error passive, Bus-off,
Last error and Error Interrupts */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
@@ -835,32 +833,32 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
}
/* Get the Id */
hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
if (hcan->pRxMsg->IDE == CAN_ID_STD)
{
hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
}
else
{
hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
}
hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
/* Get the FMI */
hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
/* Get the FIFONumber */
hcan->pRxMsg->FIFONumber = FIFONumber;
/* Get the data field */
hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
hcan->pRxMsg->Data[0U] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
hcan->pRxMsg->Data[1U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
hcan->pRxMsg->Data[2U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
hcan->pRxMsg->Data[3U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
hcan->pRxMsg->Data[4U] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
hcan->pRxMsg->Data[5U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
hcan->pRxMsg->Data[6U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
hcan->pRxMsg->Data[7U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
/* Release the FIFO */
if(FIFONumber == CAN_FIFO0)
@@ -909,9 +907,6 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber
tmp = hcan->State;
if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
{
/* Process locked */
__HAL_LOCK(hcan);
if(hcan->State == HAL_CAN_STATE_BUSY_TX)
{
/* Change CAN state */
@@ -934,9 +929,6 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber
CAN_IT_LEC |
CAN_IT_ERR);
/* Process unlocked */
__HAL_UNLOCK(hcan);
if(FIFONumber == CAN_FIFO0)
{
/* Enable FIFO 0 message pending Interrupt */
@@ -1330,32 +1322,32 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
/* Get the Id */
hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
if (hcan->pRxMsg->IDE == CAN_ID_STD)
{
hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
}
else
{
hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
}
hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
/* Get the FIFONumber */
hcan->pRxMsg->FIFONumber = FIFONumber;
/* Get the FMI */
hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
/* Get the data field */
hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
hcan->pRxMsg->Data[0U] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
hcan->pRxMsg->Data[1U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
hcan->pRxMsg->Data[2U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
hcan->pRxMsg->Data[3U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
hcan->pRxMsg->Data[4U] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
hcan->pRxMsg->Data[5U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
hcan->pRxMsg->Data[6U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
hcan->pRxMsg->Data[7U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
/* Release the FIFO */
/* Release FIFO0 */
if (FIFONumber == CAN_FIFO0)
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c
+45 -5
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cortex.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@@ -26,7 +26,7 @@
function according to the following table.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
(#) please refer to programing manual for details in how to configure priority.
(#) please refer to programming manual for details in how to configure priority.
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
@@ -45,7 +45,7 @@
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
(++) Configures the SysTick IRQ priority to the lowest value 0x0F.
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
@@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -269,6 +269,46 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
*/
#if (__MPU_PRESENT == 1U)
/**
* @brief Disables the MPU
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU and clear the control register*/
MPU->CTRL = 0U;
}
/**
* @brief Enable the MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c
+72 -74
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -85,7 +85,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -139,7 +139,7 @@ typedef struct
/** @addtogroup DMA_Private_Constants
* @{
*/
#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */
#define HAL_TIMEOUT_DMA_ABORT 5U /* 5 ms */
/**
* @}
*/
@@ -155,8 +155,8 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions
* @{
*/
@@ -180,7 +180,7 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
*/
/**
* @brief Initializes the DMA according to the specified
* @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and create the associated handle.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
@@ -277,21 +277,26 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* Prepare the DMA Stream FIFO configuration */
tmp |= hdma->Init.FIFOMode;
/* the FIFO threshold is not used when the FIFO mode is disabled */
/* The FIFO threshold is not used when the FIFO mode is disabled */
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
{
/* Get the FIFO threshold */
tmp |= hdma->Init.FIFOThreshold;
if(DMA_CheckFifoParam(hdma) != HAL_OK)
/* Check compatibility between FIFO threshold level and size of the memory burst */
/* for INCR4, INCR8, INCR16 bursts */
if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
return HAL_ERROR;
if (DMA_CheckFifoParam(hdma) != HAL_OK)
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
return HAL_ERROR;
}
}
}
@@ -359,7 +364,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
hdma->Instance->M1AR = 0U;
/* Reset DMA Streamx FIFO control register */
hdma->Instance->FCR = (uint32_t)0x00000021U;
hdma->Instance->FCR = 0x00000021U;
/* Get DMA steam Base Address */
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
@@ -446,7 +451,7 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
}
/**
* @brief Starts the DMA Transfer with interrupt enabled.
* @brief Start the DMA Transfer with interrupt enabled.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
@@ -659,7 +664,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
/* Check for the Timeout (Not applicable in circular mode)*/
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
@@ -753,8 +758,8 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
uint32_t tmpisr;
__IO uint32_t count = 0;
uint32_t timeout = SystemCoreClock / 9600;
__IO uint32_t count = 0U;
uint32_t timeout = SystemCoreClock / 9600U;
/* calculate DMA base and stream number */
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
@@ -1210,7 +1215,7 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
}
/**
* @brief Checks compatibility between FIFO threshold level and size of the memory burst
* @brief Check compatibility between FIFO threshold level and size of the memory burst
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
@@ -1225,28 +1230,23 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{
switch (tmp)
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
}
break;
case DMA_FIFO_THRESHOLD_HALFFULL:
if(hdma->Init.MemBurst == DMA_MBURST_INC16)
{
status = HAL_ERROR;
}
break;
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
}
break;
case DMA_FIFO_THRESHOLD_FULL:
break;
default:
break;
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
}
break;
case DMA_FIFO_THRESHOLD_HALFFULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
{
status = HAL_ERROR;
}
break;
case DMA_FIFO_THRESHOLD_FULL:
break;
default:
break;
}
}
@@ -1255,26 +1255,24 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{
switch (tmp)
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
status = HAL_ERROR;
break;
case DMA_FIFO_THRESHOLD_HALFFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
break;
case DMA_FIFO_THRESHOLD_HALFFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
}
break;
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
}
break;
case DMA_FIFO_THRESHOLD_FULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
{
status = HAL_ERROR;
break;
case DMA_FIFO_THRESHOLD_FULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
{
status = HAL_ERROR;
}
break;
default:
break;
}
break;
default:
break;
}
}
@@ -1283,19 +1281,19 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{
switch (tmp)
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_HALFFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_HALFFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
status = HAL_ERROR;
break;
case DMA_FIFO_THRESHOLD_FULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
break;
case DMA_FIFO_THRESHOLD_FULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
}
break;
default:
break;
}
break;
default:
break;
}
}
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c
+3 -3
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma_ex.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
@@ -27,7 +27,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c
+19 -8
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -65,7 +65,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -111,7 +111,7 @@
/** @addtogroup FLASH_Private_Constants
* @{
*/
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
/**
* @}
*/
@@ -281,8 +281,13 @@ void HAL_FLASH_IRQHandler(void)
uint32_t addresstmp = 0U;
/* Check FLASH operation error flags */
#if defined(FLASH_SR_RDERR)
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
#else
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
#endif /* FLASH_SR_RDERR */
{
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
{
@@ -588,9 +593,13 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
#if defined(FLASH_SR_RDERR)
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
#else
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
#endif /* FLASH_SR_RDERR */
{
/*Save the error code*/
FLASH_SetErrorCode();
@@ -624,7 +633,9 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
FLASH->CR |= FLASH_CR_PG;
*(__IO uint64_t*)Address = Data;
/* Program the double-word */
*(__IO uint32_t*)Address = (uint32_t)Data;
*(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
}
@@ -740,7 +751,7 @@ static void FLASH_SetErrorCode(void)
/* Clear FLASH Programming sequence error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);
}
#if defined(FLASH_SR_RDERR)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
@@ -748,7 +759,7 @@ static void FLASH_SetErrorCode(void)
/* Clear FLASH Proprietary readout protection error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR);
}
#endif /* FLASH_SR_RDERR */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c
+18 -18
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ex.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@@ -51,7 +51,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -97,7 +97,7 @@
/** @addtogroup FLASHEx_Private_Constants
* @{
*/
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
/**
* @}
*/
@@ -479,10 +479,10 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
{
uint8_t optiontmp = 0xFFU;
uint8_t optiontmp = 0xFF;
/* Mask SPRMOD bit */
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7FU);
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
/* Update Option Byte */
*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp);
@@ -504,10 +504,10 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
{
uint8_t optiontmp = 0xFFU;
uint8_t optiontmp = 0xFF;
/* Mask SPRMOD bit */
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7FU);
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
/* Update Option Byte */
*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp);
@@ -680,7 +680,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
if(WRPSector == OB_WRP_SECTOR_All)
{
/*Write protection on all sector of BANK1*/
*(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~(WRPSector>>12U));
*(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~(WRPSector>>12));
}
else
{
@@ -691,7 +691,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
else
{
/*Write protection done on sectors of BANK2*/
*(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12U));
*(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12));
}
/*Write protection on all sector of BANK2*/
@@ -702,7 +702,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
if(status == HAL_OK)
{
*(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12U));
*(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12));
}
}
@@ -751,7 +751,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
if(WRPSector == OB_WRP_SECTOR_All)
{
/*Write protection on all sector of BANK1*/
*(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12U);
*(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12);
}
else
{
@@ -762,7 +762,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
else
{
/*Write protection done on sectors of BANK2*/
*(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12U);
*(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12);
}
/*Write protection on all sector of BANK2*/
@@ -773,7 +773,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
if(status == HAL_OK)
{
*(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12U);
*(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12);
}
}
@@ -1213,7 +1213,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
*/
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
{
uint8_t optiontmp = 0xFFU;
uint8_t optiontmp = 0xFF;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
@@ -1227,7 +1227,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t
if(status == HAL_OK)
{
/* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1FU);
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
/* Update User Option Byte */
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp)));
@@ -1267,7 +1267,7 @@ static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
static uint8_t FLASH_OB_GetUser(void)
{
/* Return the User Option Byte */
return ((uint8_t)(FLASH->OPTCR & 0xE0U));
return ((uint8_t)(FLASH->OPTCR & 0xE0));
}
/**
@@ -1319,7 +1319,7 @@ static uint8_t FLASH_OB_GetRDP(void)
static uint8_t FLASH_OB_GetBOR(void)
{
/* Return the FLASH BOR level */
return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0CU);
return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
}
/**
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c
+3 -3
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ramfunc.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief FLASH RAMFUNC module driver.
* This file provides a FLASH firmware functions which should be
* executed from internal SRAM
@@ -36,7 +36,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c
+19 -19
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_gpio.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -95,7 +95,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -141,15 +141,15 @@
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE ((uint32_t)0x00000003U)
#define EXTI_MODE ((uint32_t)0x10000000U)
#define GPIO_MODE_IT ((uint32_t)0x00010000U)
#define GPIO_MODE_EVT ((uint32_t)0x00020000U)
#define RISING_EDGE ((uint32_t)0x00100000U)
#define FALLING_EDGE ((uint32_t)0x00200000U)
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)
#define GPIO_MODE 0x00000003U
#define EXTI_MODE 0x10000000U
#define GPIO_MODE_IT 0x00010000U
#define GPIO_MODE_EVT 0x00020000U
#define RISING_EDGE 0x00100000U
#define FALLING_EDGE 0x00200000U
#define GPIO_OUTPUT_TYPE 0x00000010U
#define GPIO_NUMBER ((uint32_t)16U)
#define GPIO_NUMBER 16U
/**
* @}
*/
@@ -203,7 +203,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
for(position = 0U; position < GPIO_NUMBER; position++)
{
/* Get the IO position */
ioposition = ((uint32_t)0x01U) << position;
ioposition = 0x01U << position;
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
@@ -217,8 +217,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
@@ -261,7 +261,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2U];
temp &= ~(((uint32_t)0x0FU) << (4U * (position & 0x03U)));
temp &= ~(0x0FU << (4U * (position & 0x03U)));
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
SYSCFG->EXTICR[position >> 2U] = temp;
@@ -325,7 +325,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
for(position = 0U; position < GPIO_NUMBER; position++)
{
/* Get the IO position */
ioposition = ((uint32_t)0x01U) << position;
ioposition = 0x01U << position;
/* Get the current IO position */
iocurrent = (GPIO_Pin) & ioposition;
@@ -336,7 +336,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
@@ -349,11 +349,11 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/*------------------------- EXTI Mode Configuration --------------------*/
tmp = SYSCFG->EXTICR[position >> 2U];
tmp &= (((uint32_t)0x0FU) << (4U * (position & 0x03U)));
tmp &= (0x0FU << (4U * (position & 0x03U)));
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
{
/* Configure the External Interrupt or event for the current IO */
tmp = ((uint32_t)0x0FU) << (4U * (position & 0x03U));
tmp = 0x0FU << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
/* Clear EXTI line configuration */
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c
+59 -66
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pcd.c
* @author MCD Application Team
* @version V1.5.2
* @date 22-September-2016
* @version V1.7.0
* @date 17-February-2017
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -45,7 +45,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -89,7 +89,7 @@
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
@@ -329,7 +329,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
uint32_t i = 0U, ep_intr = 0U, epint = 0U, epnum = 0U;
uint32_t fifoemptymsk = 0U, temp = 0U;
USB_OTG_EPTypeDef *ep;
uint32_t hclk = 180000000;
uint32_t hclk = 180000000U;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
@@ -508,7 +508,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if( hpcd->LPM_State == LPM_L0)
{
hpcd->LPM_State = LPM_L1;
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
}
else
@@ -522,7 +522,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
USB_FlushTxFifo(hpcd->Instance , 0U);
USB_FlushTxFifo(hpcd->Instance , 0x10U);
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
{
@@ -580,65 +580,65 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
if((hclk >= 14200000)&&(hclk < 15000000))
if((hclk >= 14200000U)&&(hclk < 15000000U))
{
/* hclk Clock Range between 14.2-15 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT);
hpcd->Instance->GUSBCFG |= (uint32_t)((0xFU << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 15000000)&&(hclk < 16000000))
else if((hclk >= 15000000U)&&(hclk < 16000000U))
{
/* hclk Clock Range between 15-16 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT);
hpcd->Instance->GUSBCFG |= (uint32_t)((0xEU << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 16000000)&&(hclk < 17200000))
else if((hclk >= 16000000U)&&(hclk < 17200000U))
{
/* hclk Clock Range between 16-17.2 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT);
hpcd->Instance->GUSBCFG |= (uint32_t)((0xDU << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 17200000)&&(hclk < 18500000))
else if((hclk >= 17200000U)&&(hclk < 18500000U))
{
/* hclk Clock Range between 17.2-18.5 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT);
hpcd->Instance->GUSBCFG |= (uint32_t)((0xCU << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 18500000)&&(hclk < 20000000))
else if((hclk >= 18500000U)&&(hclk < 20000000U))
{
/* hclk Clock Range between 18.5-20 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT);
hpcd->Instance->GUSBCFG |= (uint32_t)((0xBU << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 20000000)&&(hclk < 21800000))
else if((hclk >= 20000000U)&&(hclk < 21800000U))
{
/* hclk Clock Range between 20-21.8 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT);
hpcd->Instance->GUSBCFG |= (uint32_t)((0xAU << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 21800000)&&(hclk < 24000000))
else if((hclk >= 21800000U)&&(hclk < 24000000U))
{
/* hclk Clock Range between 21.8-24 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT);
hpcd->Instance->GUSBCFG |= (uint32_t)((0x9U << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 24000000)&&(hclk < 27700000))
else if((hclk >= 24000000U)&&(hclk < 27700000U))
{
/* hclk Clock Range between 24-27.7 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT);
hpcd->Instance->GUSBCFG |= (uint32_t)((0x8U << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 27700000)&&(hclk < 32000000))
else if((hclk >= 27700000U)&&(hclk < 32000000U))
{
/* hclk Clock Range between 27.7-32 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT);
hpcd->Instance->GUSBCFG |= (uint32_t)((0x7U << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else /* if(hclk >= 32000000) */
{
/* hclk Clock Range between 32-180 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT);
hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10U) & USB_OTG_GUSBCFG_TRDT);
}
}
@@ -947,17 +947,17 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
HAL_StatusTypeDef ret = HAL_OK;
USB_OTG_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
if ((ep_addr & 0x80) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
}
ep->num = ep_addr & 0x7FU;
ep->num = ep_addr & 0x7F;
ep->is_in = (0x80U & ep_addr) != 0U;
ep->is_in = (0x80 & ep_addr) != 0;
ep->maxpacket = ep_mps;
ep->type = ep_type;
if (ep->is_in)
@@ -988,17 +988,17 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
USB_OTG_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
if ((ep_addr & 0x80) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
}
ep->num = ep_addr & 0x7FU;
ep->num = ep_addr & 0x7F;
ep->is_in = (0x80U & ep_addr) != 0U;
ep->is_in = (0x80 & ep_addr) != 0;
__HAL_LOCK(hpcd);
USB_DeactivateEndpoint(hpcd->Instance , ep);
@@ -1019,23 +1019,21 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
{
USB_OTG_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 0U;
ep->num = ep_addr & 0x7FU;
ep->num = ep_addr & 0x7F;
if (hpcd->Init.dma_enable == 1U)
{
ep->dma_addr = (uint32_t)pBuf;
}
__HAL_LOCK(hpcd);
if ((ep_addr & 0x7FU) == 0U)
if ((ep_addr & 0x7F) == 0)
{
USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
@@ -1043,7 +1041,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
{
USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@@ -1056,7 +1053,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
*/
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count;
return hpcd->OUT_ep[ep_addr & 0xF].xfer_count;
}
/**
* @brief Send an amount of data.
@@ -1070,23 +1067,21 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
{
USB_OTG_EPTypeDef *ep;
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
ep = &hpcd->IN_ep[ep_addr & 0x7F];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 1U;
ep->num = ep_addr & 0x7FU;
ep->num = ep_addr & 0x7F;
if (hpcd->Init.dma_enable == 1U)
{
ep->dma_addr = (uint32_t)pBuf;
}
__HAL_LOCK(hpcd);
if ((ep_addr & 0x7FU) == 0U)
if ((ep_addr & 0x7F) == 0)
{
USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
@@ -1095,8 +1090,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@@ -1110,9 +1103,9 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
USB_OTG_EPTypeDef *ep;
if ((0x80U & ep_addr) == 0x80U)
if ((0x80 & ep_addr) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
@@ -1120,13 +1113,13 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
ep->is_stall = 1U;
ep->num = ep_addr & 0x7FU;
ep->is_in = ((ep_addr & 0x80U) == 0x80U);
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80);
__HAL_LOCK(hpcd);
USB_EPSetStall(hpcd->Instance , ep);
if((ep_addr & 0x7FU) == 0U)
if((ep_addr & 0x7F) == 0)
{
USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
}
@@ -1145,9 +1138,9 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
USB_OTG_EPTypeDef *ep;
if ((0x80U & ep_addr) == 0x80U)
if ((0x80 & ep_addr) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
@@ -1155,8 +1148,8 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
ep->is_stall = 0U;
ep->num = ep_addr & 0x7FU;
ep->is_in = ((ep_addr & 0x80U) == 0x80U);
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80);
__HAL_LOCK(hpcd);
USB_EPClearStall(hpcd->Instance , ep);
@@ -1175,9 +1168,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
__HAL_LOCK(hpcd);
if ((ep_addr & 0x80U) == 0x80U)
if ((ep_addr & 0x80) == 0x80)
{
USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7FU);
USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
}
else
{
@@ -1285,9 +1278,9 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
len32b = (len + 3U) / 4U;
while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
ep->xfer_count < ep->xfer_len &&
ep->xfer_len != 0U)
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) &&
(ep->xfer_count < ep->xfer_len) &&
(ep->xfer_len != 0U))
{
/* Write the FIFO */
len = ep->xfer_len - ep->xfer_count;
@@ -1319,7 +1312,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
STM32F412Vx || STM32F412Cx */
STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c
+13 -13
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.5.2
* @date 22-September-2016
* @version V1.7.0
* @date 17-February-2017
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,7 @@
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
@@ -90,7 +90,7 @@
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
uint8_t i = 0U;
uint8_t i = 0;
uint32_t Tx_Offset = 0U;
/* TXn min size = 16 words. (n : Transmit FIFO index)
@@ -105,20 +105,20 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
Tx_Offset = hpcd->Instance->GRXFSIZ;
if(fifo == 0U)
if(fifo == 0)
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
}
else
{
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
for (i = 0U; i < (fifo - 1U); i++)
for (i = 0; i < (fifo - 1); i++)
{
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16U);
}
/* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1U] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
}
return HAL_OK;
@@ -138,7 +138,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
}
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief Activate LPM feature
* @param hpcd: PCD handle
@@ -184,9 +184,9 @@ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef m
UNUSED(hpcd);
UNUSED(msg);
}
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief HAL_PCDEx_BCD_VBUSDetect : handle BatteryCharging Process
* @param hpcd: PCD handle
@@ -299,7 +299,7 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m
UNUSED(msg);
}
#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
/**
* @}
@@ -311,7 +311,7 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
STM32F412Vx || STM32F412Cx */
STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
+7 -7
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,10 +63,10 @@
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_MODE_IT ((uint32_t)0x00010000U)
#define PVD_MODE_EVT ((uint32_t)0x00020000U)
#define PVD_RISING_EDGE ((uint32_t)0x00000001U)
#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
#define PVD_MODE_IT 0x00010000U
#define PVD_MODE_EVT 0x00020000U
#define PVD_RISING_EDGE 0x00000001U
#define PVD_FALLING_EDGE 0x00000002U
/**
* @}
*/
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c
+3 -3
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr_ex.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
+7 -9
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rcc.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -56,7 +56,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,7 +102,7 @@
/** @addtogroup RCC_Private_Constants
* @{
*/
#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
/* Private macro -------------------------------------------------------------*/
#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
@@ -120,11 +120,9 @@
/** @defgroup RCC_Private_Variables RCC Private Variables
* @{
*/
const uint8_t APBAHBPrescTable[16] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
@@ -701,7 +699,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
@@ -937,7 +935,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
}
/**
@@ -949,7 +947,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
}
/**
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c
+1000 -328
View File
File diff suppressed because it is too large Load Diff
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c
+509 -81
View File
File diff suppressed because it is too large Load Diff
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c
+22 -10
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -98,7 +98,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -404,7 +404,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if((pData == 0U) && (Length > 0U))
if((pData == 0U) && (Length > 0))
{
return HAL_ERROR;
}
@@ -803,7 +803,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U) && (Length > 0U))
if(((uint32_t)pData == 0U) && (Length > 0))
{
return HAL_ERROR;
}
@@ -1163,7 +1163,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
* @brief Starts the PWM signal generation in interrupt mode.
* @param htim: pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1318,7 +1318,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U) && (Length > 0U))
if(((uint32_t)pData == 0U) && (Length > 0))
{
return HAL_ERROR;
}
@@ -1806,7 +1806,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if((pData == 0U) && (Length > 0U))
if((pData == 0U) && (Length > 0))
{
return HAL_ERROR;
}
@@ -2106,6 +2106,9 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2140,6 +2143,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
/* Disable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2182,7 +2188,10 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@@ -2214,6 +2223,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
@@ -2626,7 +2638,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0))
{
return HAL_ERROR;
}
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c
+28 -25
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim_ex.c
* @author MCD Application Team
* @version V1.6.0
* @date 04-November-2016
* @version V1.7.0
* @date 17-February-2017
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer extension peripheral:
@@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -394,7 +394,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U) && (Length > 0U))
if(((uint32_t)pData == 0U) && (Length > 0))
{
return HAL_ERROR;
}
@@ -701,7 +701,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U) && (Length > 0U))
if(((uint32_t)pData == 0U) && (Length > 0))
{
return HAL_ERROR;
}
@@ -1119,7 +1119,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U) && (Length > 0U))
if(((uint32_t)pData == 0U) && (Length > 0))
{
return HAL_ERROR;
}
@@ -1655,39 +1655,42 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
* contains the BDTR Register configuration information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
{
uint32_t tmpbdtr = 0U;
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
/* Process Locked */
/* Check input state */
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
sBreakDeadTimeConfig->OffStateIDLEMode |
sBreakDeadTimeConfig->LockLevel |
sBreakDeadTimeConfig->DeadTime |
sBreakDeadTimeConfig->BreakState |
sBreakDeadTimeConfig->BreakPolarity |
sBreakDeadTimeConfig->AutomaticOutput;
the OSSI State, the dead time value and the Automatic Output Enable Bit */
htim->State = HAL_TIM_STATE_READY;
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
__HAL_UNLOCK(htim);
return HAL_OK;
}
@@ -1730,7 +1733,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
{
__HAL_RCC_LPTIM1_CLK_ENABLE();
LPTIM1->OR = (Remap& 0xEFFFFFFF);
LPTIM1->OR = (Remap& 0xEFFFFFFFU);
}
else
{
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c
+158 -56
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_usb.c
* @author MCD Application Team
* @version V1.5.2
* @date 22-September-2016
* @version V1.7.0
* @date 17-February-2017
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -28,7 +28,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -67,7 +67,7 @@
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -135,6 +135,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
if(cfg.dma_enable == ENABLE)
{
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
}
@@ -207,7 +208,7 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
/*Activate VBUS Sensing B */
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
if (cfg.vbus_sensing_enable == 0U)
@@ -220,17 +221,20 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
}
#else
USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
if (cfg.vbus_sensing_enable == 0U)
{
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
}
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
else
{
/* Enable VBUS */
USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
/* Restart the Phy Clock */
USBx_PCGCCTL = 0U;
/* Device mode configuration */
USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
@@ -346,13 +350,13 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
*/
HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
{
uint32_t count = 0U;
uint32_t count = 0;
USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
do
{
if (++count > 200000U)
if (++count > 200000)
{
return HAL_TIMEOUT;
}
@@ -370,13 +374,13 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t count = 0U;
uint32_t count = 0;
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
do
{
if (++count > 200000U)
if (++count > 200000)
{
return HAL_TIMEOUT;
}
@@ -515,18 +519,65 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
/* Read DEPCTLn register */
uint32_t count = 0U;
/* Disable the IN endpoint */
if (ep->is_in == 1U)
{
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_USBAEP;
/* sets the NAK bit for the IN endpoint */
USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
/* Disable IN endpoint */
USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS;
do
{
if (++count > 200000U)
{
return HAL_TIMEOUT;
}
}
/*Wait for EPDISD endpoint disabled interrupt*/
while ((USBx_INEP(ep->num)->DIEPINT & USB_OTG_DIEPCTL_EPDIS) == USB_OTG_DIEPCTL_EPDIS);
/* Flush any data remaining in the TxFIFO */
USB_FlushTxFifo(USBx , 0x10U);
/* Disable endpoint interrupts */
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
}
else
else /* Disable the OUT endpoint */
{
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
/* sets the NAK bit for the OUT endpoint */
USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
/* Disable OUT endpoint */
USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS;
do
{
if (++count > 200000U)
{
return HAL_TIMEOUT;
}
}
/*Wait for EPDISD endpoint disabled interrupt*/
while ((USBx_OUTEP(ep->num)->DOEPINT & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS);
/* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
/* Disable endpoint interrupts */
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
}
return HAL_OK;
}
@@ -539,18 +590,68 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
*/
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
/* Read DEPCTLn register */
uint32_t count = 0U;
/* Disable the IN endpoint */
if (ep->is_in == 1U)
{
USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_USBAEP;
/* sets the NAK bit for the IN endpoint */
USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
/* Disable IN endpoint */
USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS;
do
{
if (++count > 200000U)
{
return HAL_TIMEOUT;
}
}
/*Wait for EPDISD endpoint disabled interrupt*/
while ((USBx_INEP(ep->num)->DIEPINT & USB_OTG_DIEPCTL_EPDIS) == USB_OTG_DIEPCTL_EPDIS);
/* Flush any data remaining in the TxFIFO */
USB_FlushTxFifo(USBx , 0x10U);
/* Disable endpoint interrupts */
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
}
else
else /* Disable the OUT endpoint */
{
USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
/* sets the NAK bit for the OUT endpoint */
USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
/* Disable OUT endpoint */
USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS;
do
{
if (++count > 200000U)
{
return HAL_TIMEOUT;
}
}
/*Wait for EPDISD endpoint disabled interrupt*/
while ((USBx_OUTEP(ep->num)->DOEPINT & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS);
/* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
/* Disable endpoint interrupts */
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
}
return HAL_OK;
}
/**
@@ -716,6 +817,9 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
}
/* EP enable, IN data in FIFO */
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
if (dma == 1)
{
USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
@@ -728,10 +832,8 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num);
}
}
/* EP enable, IN data in FIFO */
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
else /* OUT endpoint */
{
/* Program the transfer size and packet count as follows:
@@ -1139,13 +1241,13 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
/* Activate VBUS Sensing B */
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
/* Disable the FS/LS support mode only */
if((cfg.speed == USB_OTG_SPEED_FULL)&&
@@ -1183,14 +1285,14 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
if(USBx == USB_OTG_FS)
{
/* set Rx FIFO size */
USBx->GRXFSIZ = (uint32_t )0x80U;
USBx->GRXFSIZ = 0x80U;
USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60U << 16U)& USB_OTG_NPTXFD) | 0x80U);
USBx->HPTXFSIZ = (uint32_t )(((0x40U << 16U)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
}
else
{
/* set Rx FIFO size */
USBx->GRXFSIZ = (uint32_t )0x200U;
USBx->GRXFSIZ = 0x200U;
USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100U << 16U)& USB_OTG_NPTXFD) | 0x200U);
USBx->HPTXFSIZ = (uint32_t )(((0xE0U << 16U)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
}
@@ -1226,11 +1328,11 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq
if (freq == HCFG_48_MHZ)
{
USBx_HOST->HFIR = (uint32_t)48000U;
USBx_HOST->HFIR = 48000U;
}
else if (freq == HCFG_6_MHZ)
{
USBx_HOST->HFIR = (uint32_t)6000U;
USBx_HOST->HFIR = 6000U;
}
return HAL_OK;
}
@@ -1442,20 +1544,20 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
#endif /* __CC_ARM */
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
{
uint8_t is_oddframe = 0U;
uint16_t len_words = 0U;
uint16_t num_packets = 0U;
uint16_t max_hc_pkt_count = 256U;
uint8_t is_oddframe = 0;
uint16_t len_words = 0;
uint16_t num_packets = 0;
uint16_t max_hc_pkt_count = 256;
uint32_t tmpreg = 0U;
if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
{
if((dma == 0U) && (hc->do_ping == 1U))
if((dma == 0) && (hc->do_ping == 1U))
{
USB_DoPing(USBx, hc->ch_num);
return HAL_OK;
}
else if(dma == 1U)
else if(dma == 1)
{
USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
hc->do_ping = 0U;
@@ -1475,7 +1577,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
}
else
{
num_packets = 1U;
num_packets = 1;
}
if (hc->ep_is_in)
{
@@ -1493,9 +1595,9 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
}
is_oddframe = (USBx_HOST->HFNUM & 0x01U) ? 0U : 1U;
is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29U);
USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
/* Set host channel enable */
tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
@@ -1503,7 +1605,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
if (dma == 0U) /* Slave mode */
if (dma == 0) /* Slave mode */
{
if((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
{
@@ -1513,10 +1615,10 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
case EP_TYPE_CTRL:
case EP_TYPE_BULK:
len_words = (hc->xfer_len + 3U) / 4U;
len_words = (hc->xfer_len + 3) / 4;
/* check if there is enough space in FIFO space */
if(len_words > (USBx->HNPTXSTS & 0xFFFFU))
if(len_words > (USBx->HNPTXSTS & 0xFFFF))
{
/* need to process data in nptxfempty interrupt */
USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
@@ -1525,9 +1627,9 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
/* Periodic transfer */
case EP_TYPE_INTR:
case EP_TYPE_ISOC:
len_words = (hc->xfer_len + 3U) / 4U;
len_words = (hc->xfer_len + 3) / 4;
/* check if there is enough space in FIFO space */
if(len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
{
/* need to process data in ptxfempty interrupt */
USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
@@ -1659,7 +1761,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
USB_FlushRxFifo(USBx);
/* Flush out any leftover queued requests. */
for (i = 0U; i <= 15U; i++)
for (i = 0; i <= 15; i++)
{
value = USBx_HC(i)->HCCHAR ;
@@ -1670,7 +1772,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
}
/* Halt all channels to put them into a known state. */
for (i = 0U; i <= 15U; i++)
for (i = 0; i <= 15; i++)
{
value = USBx_HC(i)->HCCHAR ;
@@ -1700,7 +1802,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
STM32F412Vx || STM32F412Cx */
STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
#endif /* defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) */
/**
Inc/FreeRTOSConfig.h
+3 -1
View File
@@ -1,5 +1,5 @@
/*
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
@@ -94,6 +94,8 @@
#endif
#define configUSE_PREEMPTION 1
#define configSUPPORT_STATIC_ALLOCATION 0
#define configSUPPORT_DYNAMIC_ALLOCATION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( SystemCoreClock )

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