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Update MSP432 projects to use updated driver library files.

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Remove references to INCLUDE_pcTaskGetTaskName and INCLUDE_xTimerGetTimerDaemonTaskHandle, which are no longer required.
This commit is contained in:
Richard Barry
2016-03-30 11:12:06 +00:00
parent b9b64c0889
commit f9c02d09c3
111 changed files with 16550 additions and 23297 deletions
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FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/RTOSDemo.cproj
+221 -255
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File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/FreeRTOSConfig.h
+1 -2
View File
@@ -173,7 +173,7 @@ extern "C" {
#define configCPU_CLOCK_HZ (( unsigned long ) 14000000)
#define configMAX_PRIORITIES ( 6 )
#define configMINIMAL_STACK_SIZE (( unsigned short ) 130)
#define configTOTAL_HEAP_SIZE (( size_t )(25000))
#define configTOTAL_HEAP_SIZE (( size_t )(24000))
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY ( 0 )
#define configUSE_16_BIT_TICKS ( 0 )
@@ -237,7 +237,6 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define INCLUDE_uxTaskGetStackHighWaterMark ( 0 )
#define INCLUDE_xTaskGetIdleTaskHandle ( 0 )
#define INCLUDE_xTimerGetTimerDaemonTaskHandle ( 0 )
#define INCLUDE_pcTaskGetTaskName ( 0 )
#define INCLUDE_eTaskGetState ( 1 )
#define INCLUDE_xTimerPendFunctionCall ( 1 )
FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/FreeRTOSConfig.h
+2 -3
View File
@@ -98,7 +98,7 @@ extern "C" {
* See the comments at the top of main.c, main_full.c and main_low_power.c for
* more information.
*/
#define configCREATE_LOW_POWER_DEMO 0
#define configCREATE_LOW_POWER_DEMO 1
/* Some configuration is dependent on the demo being built. */
#if( configCREATE_LOW_POWER_DEMO == 0 )
@@ -150,7 +150,7 @@ extern "C" {
#define configCPU_CLOCK_HZ ( CMU_ClockFreqGet( cmuClock_CORE ) )
#define configMAX_PRIORITIES ( 6 )
#define configMINIMAL_STACK_SIZE (( unsigned short ) 130)
#define configTOTAL_HEAP_SIZE (( size_t )(25000))
#define configTOTAL_HEAP_SIZE (( size_t )(24000))
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY ( 0 )
#define configUSE_16_BIT_TICKS ( 0 )
@@ -214,7 +214,6 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define INCLUDE_uxTaskGetStackHighWaterMark ( 0 )
#define INCLUDE_xTaskGetIdleTaskHandle ( 0 )
#define INCLUDE_xTimerGetTimerDaemonTaskHandle ( 0 )
#define INCLUDE_pcTaskGetTaskName ( 0 )
#define INCLUDE_eTaskGetState ( 1 )
#define INCLUDE_xTimerPendFunctionCall ( 1 )
FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h
-1
View File
@@ -124,7 +124,6 @@ to exclude the API function. */
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1
#define INCLUDE_xTaskGetIdleTaskHandle 1
#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_xSemaphoreGetMutexHolder 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTimerPendFunctionCall 1
FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.cproj
+5 -3
View File
@@ -2,7 +2,7 @@
<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003" DefaultTargets="Build">
<PropertyGroup>
<SchemaVersion>2.0</SchemaVersion>
<ProjectVersion>6.2</ProjectVersion>
<ProjectVersion>7.0</ProjectVersion>
<ProjectGuid>{257fe152-8d54-41ca-afe7-777de72fe329}</ProjectGuid>
<Name>$(MSBuildProjectName)</Name>
<AssemblyName>$(MSBuildProjectName)</AssemblyName>
@@ -180,7 +180,7 @@
<documentation help="http://asf.atmel.com/docs/3.11.0/common.applications.user_application.sam4e_ek/html/index.html" />
<offline-documentation help="" />
<dependencies>
<content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.11.0" />
<content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.20.1" />
</dependencies>
<project id="common.applications.user_application.sam4e_ek" value="Add" config="" content-id="Atmel.ASF" />
<board id="board.sam4e_ek" value="Add" config="" content-id="Atmel.ASF" />
@@ -219,6 +219,7 @@
<ToolName>J-Link</ToolName>
</com_atmel_avrdbg_tool_samice>
<avrtoolinterface>SWD</avrtoolinterface>
<preserveEEPROM>true</preserveEEPROM>
</PropertyGroup>
<PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
<ToolchainSettings>
@@ -380,12 +381,13 @@
<Value>../src/ASF/sam/drivers/tc</Value>
</ListValues>
</armgcc.compiler.directories.IncludePaths>
<armgcc.compiler.optimization.level>Optimize (-O1)</armgcc.compiler.optimization.level>
<armgcc.compiler.optimization.OtherFlags>-fdata-sections</armgcc.compiler.optimization.OtherFlags>
<armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
<armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
<armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
<armgcc.compiler.warnings.ExtraWarnings>True</armgcc.compiler.warnings.ExtraWarnings>
<armgcc.compiler.miscellaneous.OtherFlags>-pipe -fno-strict-aliasing -Wall -Wextra -ffunction-sections -fdata-sections --param max-inline-insns-single=500 -mfloat-abi=softfp -mfpu=vfpv4</armgcc.compiler.miscellaneous.OtherFlags>
<armgcc.compiler.miscellaneous.OtherFlags>-pipe -fno-strict-aliasing -ffunction-sections -fdata-sections --param max-inline-insns-single=500 -mfloat-abi=softfp -mfpu=vfpv4 -Wno-attributes -Wno-unused-function</armgcc.compiler.miscellaneous.OtherFlags>
<armgcc.linker.libraries.Libraries>
<ListValues>
<Value>m</Value>
FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/compiler.h
+8 -6
View File
@@ -153,12 +153,14 @@
* heuristics and inline the function no matter how big it thinks it
* becomes.
*/
#if defined(__CC_ARM)
# define __always_inline __forceinline
#elif (defined __GNUC__)
# define __always_inline inline __attribute__((__always_inline__))
#elif (defined __ICCARM__)
# define __always_inline _Pragma("inline=forced")
#ifndef __always_inline
#if defined(__CC_ARM)
# define __always_inline __forceinline
#elif (defined __GNUC__)
# define __always_inline inline __attribute__((__always_inline__))
#elif (defined __ICCARM__)
# define __always_inline _Pragma("inline=forced")
#endif
#endif
/*! \brief This macro is used to test fatal errors.
FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_low_power/low_power_tick_config.c
+6 -6
View File
@@ -109,15 +109,15 @@ resolution and low resolution respectively. */
/* When lpINCLUDE_TEST_TIMER is set to 1 a basic timer is used to generate
interrupts at a low frequency. The purpose being to bring the CPU out of its
sleep mode by an interrupt other than the tick interrupt, and therefore
allowing an additional past through the code to be tested. */
allowing an additional paths through the code to be tested. */
#define lpINCLUDE_TEST_TIMER 0
/* Some registers are accessed directly as the library is not compatible with
all the compilers used. */
#define lpHTIMER_PRELOAD_REGISTER ( * ( uint16_t * ) 0x40009800 )
#define lpHTIMER_CONTROL_REGISTER ( * ( uint16_t * ) 0x40009804 )
#define lpHTIMER_COUNT_REGISTER ( * ( uint16_t * ) 0x40009808 )
#define lpEC_GIRQ17_ENABLE_SET ( * ( uint32_t * ) 0x4000C0B8 )
#define lpHTIMER_PRELOAD_REGISTER ( * ( volatile uint16_t * ) 0x40009800 )
#define lpHTIMER_CONTROL_REGISTER ( * ( volatile uint16_t * ) 0x40009804 )
#define lpHTIMER_COUNT_REGISTER ( * ( volatile uint16_t * ) 0x40009808 )
#define lpEC_GIRQ17_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C0B8 )
#define lpHTIMER_INTERRUPT_CONTROL_BIT ( 1UL << 20UL )
/*
@@ -378,7 +378,7 @@ TickType_t xModifiableIdleTime;
/* Undo the adjustment that was made to the reload value to account
for the fact that a time slice was part way through when this
function was called before working out how many complete tick
periods this represents. (could have used [ulExpectedIdleTime *
periods this represents. (could have used [ulExpectedIdleTime *
ulReloadValueForOneHighResolutionTick] instead of ulReloadValue on
the previous line, but this way avoids the multiplication). */
ulCompletedTimerDecrements += ( ulReloadValueForOneHighResolutionTick - ulCountBeforeSleep );
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.project
+18 -9
View File
@@ -166,7 +166,7 @@
</matcher>
</filter>
<filter>
<id>1424443780710</id>
<id>1458999824885</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -175,7 +175,7 @@
</matcher>
</filter>
<filter>
<id>1424443780715</id>
<id>1458999824885</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -184,7 +184,7 @@
</matcher>
</filter>
<filter>
<id>1424443780721</id>
<id>1458999824885</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -193,7 +193,7 @@
</matcher>
</filter>
<filter>
<id>1424443780726</id>
<id>1458999824895</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -202,7 +202,7 @@
</matcher>
</filter>
<filter>
<id>1424443780730</id>
<id>1458999824895</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -211,7 +211,7 @@
</matcher>
</filter>
<filter>
<id>1424443780734</id>
<id>1458999824905</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -220,7 +220,7 @@
</matcher>
</filter>
<filter>
<id>1424443780739</id>
<id>1458999824905</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -229,7 +229,7 @@
</matcher>
</filter>
<filter>
<id>1424443780744</id>
<id>1458999824915</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -238,7 +238,7 @@
</matcher>
</filter>
<filter>
<id>1424443780748</id>
<id>1458999824915</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -246,6 +246,15 @@
<arguments>1.0-name-matches-false-false-timer32.c</arguments>
</matcher>
</filter>
<filter>
<id>1458999824925</id>
<name>driverlib</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-sysctl.c</arguments>
</matcher>
</filter>
<filter>
<id>1423578948112</id>
<name>system</name>
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h
-1
View File
@@ -124,7 +124,6 @@ referenced anyway. */
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 0
#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTaskResumeFromISR 0
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c
+10 -10
View File
@@ -104,17 +104,17 @@ void vT32_1_Handler( void );
void vInitialiseTimerForIntQueueTest( void )
{
/* Configure the timer channels. */
MAP_Timer32_initModule( TIMER32_0_MODULE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
MAP_Timer32_setCount( TIMER32_0_MODULE, CS_getMCLK() / tmrTIMER_0_FREQUENCY );
MAP_Timer32_enableInterrupt( TIMER32_0_MODULE );
MAP_Timer32_startTimer( TIMER32_0_MODULE, false );
MAP_Timer32_initModule( (uint32_t)TIMER32_0_BASE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
MAP_Timer32_setCount( (uint32_t)TIMER32_0_BASE, CS_getMCLK() / tmrTIMER_0_FREQUENCY );
MAP_Timer32_enableInterrupt( (uint32_t)TIMER32_0_BASE );
MAP_Timer32_startTimer( (uint32_t)TIMER32_0_BASE, false );
MAP_Interrupt_setPriority( INT_T32_INT1, tmrLOWER_PRIORITY );
MAP_Interrupt_enableInterrupt( INT_T32_INT1 );
MAP_Timer32_initModule( TIMER32_1_MODULE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
MAP_Timer32_setCount( TIMER32_1_MODULE, CS_getMCLK() / tmrTIMER_1_FREQUENCY );
MAP_Timer32_enableInterrupt( TIMER32_1_MODULE );
MAP_Timer32_startTimer( TIMER32_1_MODULE, false );
MAP_Timer32_initModule( (uint32_t)TIMER32_1_BASE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
MAP_Timer32_setCount( (uint32_t)TIMER32_1_BASE, CS_getMCLK() / tmrTIMER_1_FREQUENCY );
MAP_Timer32_enableInterrupt( (uint32_t)TIMER32_1_BASE );
MAP_Timer32_startTimer( (uint32_t)TIMER32_1_BASE, false );
MAP_Interrupt_setPriority( INT_T32_INT2, tmrHIGHER_PRIORITY );
MAP_Interrupt_enableInterrupt( INT_T32_INT2 );
}
@@ -122,14 +122,14 @@ void vInitialiseTimerForIntQueueTest( void )
void vT32_0_Handler( void )
{
MAP_Timer32_clearInterruptFlag( TIMER32_0_MODULE );
MAP_Timer32_clearInterruptFlag( (uint32_t)TIMER32_0_BASE );
portYIELD_FROM_ISR( xFirstTimerHandler() );
}
/*-----------------------------------------------------------*/
void vT32_1_Handler( void )
{
MAP_Timer32_clearInterruptFlag( TIMER32_1_MODULE );
MAP_Timer32_clearInterruptFlag( (uint32_t)TIMER32_1_BASE );
portYIELD_FROM_ISR( xSecondTimerHandler() );
}
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c
+4 -4
View File
@@ -68,7 +68,7 @@
*/
__asm vRegTest1Implementation( void )
__asm void vRegTest1Implementation( void )
{
PRESERVE8
IMPORT ulRegTest1LoopCounter
@@ -251,7 +251,7 @@ reg1_error_loop
}
/*-----------------------------------------------------------*/
__asm vRegTest2Implementation( void )
__asm void vRegTest2Implementation( void )
{
PRESERVE8
IMPORT ulRegTest2LoopCounter
@@ -443,7 +443,7 @@ reg2_error_loop
}
/*-----------------------------------------------------------*/
__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )
__asm void vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )
{
PRESERVE8
@@ -460,7 +460,7 @@ __asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )
}
/*-----------------------------------------------------------*/
__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )
__asm void ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )
{
PRESERVE8
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c
+13 -13
View File
@@ -107,7 +107,7 @@ static QueueHandle_t xRxQueue = NULL;
static volatile const signed char *pcStringStart = NULL, *pcStringEnd = NULL;
static volatile TaskHandle_t xTransmittingTask = NULL;
static EUSCI_A0_Type * const pxUARTA0 = ( EUSCI_A0_Type * ) EUSCI_A0_MODULE;
static EUSCI_A_Type * const pxUARTA0 = ( EUSCI_A_Type * ) EUSCI_A0_BASE;
/* UART Configuration for 19200 baud. Value generated using the tool provided
on the following page:
@@ -137,10 +137,10 @@ xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned long
configASSERT( xRxQueue );
/* Use the library functions to initialise and enable the UART. */
MAP_UART_initModule( EUSCI_A0_MODULE, &xUARTConfig );
MAP_UART_enableModule( EUSCI_A0_MODULE );
MAP_UART_clearInterruptFlag( EUSCI_A0_MODULE, EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT );
MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_RECEIVE_INTERRUPT );
MAP_UART_initModule( EUSCI_A0_BASE, &xUARTConfig );
MAP_UART_enableModule( EUSCI_A0_BASE );
MAP_UART_clearInterruptFlag( EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT );
MAP_UART_enableInterrupt( EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT );
/* The interrupt handler uses the FreeRTOS API function so its priority must
be at or below the configured maximum system call interrupt priority.
@@ -191,11 +191,11 @@ const TickType_t xMaxWaitTime = pdMS_TO_TICKS( 20UL * ( uint32_t ) usStringLengt
pcStringEnd = pcStringStart + usStringLength;
/* Start to send the first byte. */
pxUARTA0->rTXBUF.r = ( uint_fast8_t ) *pcString;
pxUARTA0->TXBUF = ( uint_fast8_t ) *pcString;
/* Enable the interrupt then wait for the byte to be sent. The interrupt
will be disabled again in the ISR. */
MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
MAP_UART_enableInterrupt( EUSCI_A0_BASE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
ulTaskNotifyTake( pdTRUE, xMaxWaitTime );
}
/*-----------------------------------------------------------*/
@@ -223,11 +223,11 @@ const TickType_t xMaxWaitTime = pdMS_TO_TICKS( 20UL );
pcStringEnd = pcStringStart + sizeof( cOutChar );
/* Start to send the byte. */
pxUARTA0->rTXBUF.r = ( uint_fast8_t ) cOutChar;
pxUARTA0->TXBUF = ( uint_fast8_t ) cOutChar;
/* Enable the interrupt then wait for the byte to be sent. The interrupt
will be disabled again in the ISR. */
MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
MAP_UART_enableInterrupt( EUSCI_A0_BASE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
ulTaskNotifyTake( pdTRUE, xMaxWaitTime );
return pdPASS;
@@ -247,12 +247,12 @@ uint8_t ucChar;
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
uint_fast8_t xInterruptStatus;
xInterruptStatus = MAP_UART_getEnabledInterruptStatus( EUSCI_A0_MODULE );
xInterruptStatus = MAP_UART_getEnabledInterruptStatus( EUSCI_A0_BASE );
if( ( xInterruptStatus & EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG ) != 0x00 )
{
/* Obtain the character. */
ucChar = MAP_UART_receiveData( EUSCI_A0_MODULE );
ucChar = MAP_UART_receiveData( EUSCI_A0_BASE );
/* Send the character to the queue. Note the comments at the top of this
file with regards to the inefficiency of this method for anything other than
@@ -277,13 +277,13 @@ uint_fast8_t xInterruptStatus;
/* This is probably quite a heavy wait function just for writing to
the Tx register. An optimised design would probably replace this
with a simple register write. */
pxUARTA0->rTXBUF.r = ( uint_fast8_t ) *pcStringStart;
pxUARTA0->TXBUF = ( uint_fast8_t ) *pcStringStart;
}
else
{
/* No more characters to send. Disable the interrupt and notify the
task, if the task is waiting. */
MAP_UART_disableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
MAP_UART_disableInterrupt( EUSCI_A0_BASE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
if( xTransmittingTask != NULL )
{
vTaskNotifyGiveFromISR( xTransmittingTask, &xHigherPriorityTaskWoken );
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewd
+403 -107
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewp
+82 -42
View File
@@ -12,7 +12,7 @@
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>22</version>
<version>24</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -27,11 +27,6 @@
<name>ListPath</name>
<state>IAR_Debug\List</state>
</option>
<option>
<name>Variant</name>
<version>21</version>
<state>40</state>
</option>
<option>
<name>GEndianMode</name>
<state>0</state>
@@ -58,11 +53,6 @@
<name>GOutputBinary</name>
<state>0</state>
</option>
<option>
<name>FPU</name>
<version>3</version>
<state>5</state>
</option>
<option>
<name>OGCoreOrChip</name>
<state>1</state>
@@ -87,7 +77,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>7.30.4.8186</state>
<state>7.50.3.10745</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@@ -135,14 +125,9 @@
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
</option>
<option>
<name>GFPUCoreSlave</name>
<version>21</version>
<state>40</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>21</version>
<version>22</version>
<state>40</state>
</option>
<option>
@@ -157,6 +142,34 @@
<name>GRuntimeLibThreads</name>
<state>0</state>
</option>
<option>
<name>CoreVariant</name>
<version>22</version>
<state>39</state>
</option>
<option>
<name>GFPUDeviceSlave</name>
<state>MSP432P401R TexasInstruments MSP432P401R</state>
</option>
<option>
<name>FPU2</name>
<version>0</version>
<state>4</state>
</option>
<option>
<name>NrRegs</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>NEON</name>
<state>0</state>
</option>
<option>
<name>GFPUCoreSlave2</name>
<version>22</version>
<state>39</state>
</option>
</data>
</settings>
<settings>
@@ -594,7 +607,7 @@
<debug>1</debug>
<option>
<name>OOCOutputFormat</name>
<version>2</version>
<version>3</version>
<state>0</state>
</option>
<option>
@@ -641,7 +654,7 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>16</version>
<version>17</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -722,7 +735,7 @@
</option>
<option>
<name>IlinkIcfFile</name>
<state>$TOOLKIT_DIR$\config\linker\TexasInstruments\MSP432P401R.icf</state>
<state>$TOOLKIT_DIR$\config\linker\TexasInstruments\msp432p401r.icf</state>
</option>
<option>
<name>IlinkIcfFileSlave</name>
@@ -925,6 +938,10 @@
<name>IlinkThreadsSlave</name>
<state>1</state>
</option>
<option>
<name>IlinkLogCallGraph</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@@ -964,7 +981,7 @@
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>22</version>
<version>24</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@@ -979,11 +996,6 @@
<name>ListPath</name>
<state>Release\List</state>
</option>
<option>
<name>Variant</name>
<version>21</version>
<state>0</state>
</option>
<option>
<name>GEndianMode</name>
<state>0</state>
@@ -1010,11 +1022,6 @@
<name>GOutputBinary</name>
<state>0</state>
</option>
<option>
<name>FPU</name>
<version>3</version>
<state>0</state>
</option>
<option>
<name>OGCoreOrChip</name>
<state>1</state>
@@ -1039,7 +1046,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>6.30.1.53141</state>
<state>7.50.3.10745</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@@ -1051,7 +1058,7 @@
</option>
<option>
<name>OGChipSelectEditMenu</name>
<state>TM4L2001H8PZI TexasInstruments TM4L2001H8PZI</state>
<state>Default None</state>
</option>
<option>
<name>GenLowLevelInterface</name>
@@ -1087,14 +1094,9 @@
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
</option>
<option>
<name>GFPUCoreSlave</name>
<version>21</version>
<state>0</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>21</version>
<version>22</version>
<state>0</state>
</option>
<option>
@@ -1109,6 +1111,34 @@
<name>GRuntimeLibThreads</name>
<state>0</state>
</option>
<option>
<name>CoreVariant</name>
<version>22</version>
<state>0</state>
</option>
<option>
<name>GFPUDeviceSlave</name>
<state>Default None</state>
</option>
<option>
<name>FPU2</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>NrRegs</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>NEON</name>
<state>0</state>
</option>
<option>
<name>GFPUCoreSlave2</name>
<version>22</version>
<state>0</state>
</option>
</data>
</settings>
<settings>
@@ -1538,7 +1568,7 @@
<debug>0</debug>
<option>
<name>OOCOutputFormat</name>
<version>2</version>
<version>3</version>
<state>0</state>
</option>
<option>
@@ -1585,7 +1615,7 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>16</version>
<version>17</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@@ -1869,6 +1899,10 @@
<name>IlinkThreadsSlave</name>
<state>1</state>
</option>
<option>
<name>IlinkLogCallGraph</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@@ -1918,6 +1952,9 @@
<file>
<name>$PROJ_DIR$\driverlib\pcm.c</name>
</file>
<file>
<name>$PROJ_DIR$\driverlib\sysctl.c</name>
</file>
<file>
<name>$PROJ_DIR$\driverlib\timer32.c</name>
</file>
@@ -2074,6 +2111,9 @@
<file>
<name>$PROJ_DIR$\system\IAR\msp432_startup_ewarm.c</name>
</file>
<file>
<name>$PROJ_DIR$\system\IAR\system_msp432p401r.c</name>
</file>
</group>
<file>
<name>$PROJ_DIR$\FreeRTOSConfig.h</name>
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewt
+1931 -1
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvoptx
+45 -48
View File
@@ -73,11 +73,33 @@
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>4</CpuCode>
<Books>
<Book>
<Number>0</Number>
<Title>MSP432 Hardware Tools User's Guide (MSP-TS432PZ100)</Title>
<Path>http://www.ti.com/lit/pdf/slau571</Path>
</Book>
<Book>
<Number>1</Number>
<Title>MSP432 Quick Start Guide (MSP-EXP432P401R)</Title>
<Path>http://www.ti.com/lit/pdf/slau596</Path>
</Book>
<Book>
<Number>2</Number>
<Title>LaunchPad Development Kit User's Guide (MSP-EXP432P401R)</Title>
<Path>http://www.ti.com/lit/pdf/slau597</Path>
</Book>
<Book>
<Number>3</Number>
<Title>MSP432P401R LaunchPad Web page (MSP-EXP432P401R)</Title>
<Path>http://www.ti.com/tool/msp-exp432p401r</Path>
</Book>
</Books>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
@@ -147,7 +169,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>-UM0149MEE -O175 -S8 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB.FLM -FS00 -FL040000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FF1MSP432P4xx_InfoFlash.FLM -FS1200000 -FL14000 -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM)</Name>
<Name>-UM0356BUE -O175 -S8 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB.FLM -FS00 -FL040000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FF1MSP432P4xx_InfoFlash.FLM -FS1200000 -FL14000 -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
@@ -174,7 +196,7 @@
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
@@ -199,6 +221,10 @@
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<Lin2Executable></Lin2Executable>
<Lin2ConfigFile></Lin2ConfigFile>
<bLin2Auto>0</bLin2Auto>
<DebugDescription>
<Enable>1</Enable>
<EnableLog>0</EnableLog>
@@ -219,7 +245,6 @@
<FileNumber>1</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\system\Keil\startup_MSP432P4.s</PathWithFileName>
@@ -231,12 +256,11 @@
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>1</tvExp>
<Focus>0</Focus>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\system\Keil\system_MSP432P4.c</PathWithFileName>
<FilenameWithoutPath>system_MSP432P4.c</FilenameWithoutPath>
<PathWithFileName>.\system\Keil\system_msp432p401r.c</PathWithFileName>
<FilenameWithoutPath>system_msp432p401r.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
@@ -244,7 +268,7 @@
<Group>
<GroupName>main</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@@ -253,7 +277,6 @@
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\main.c</PathWithFileName>
@@ -266,7 +289,6 @@
<FileNumber>4</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\FreeRTOSConfig.h</PathWithFileName>
@@ -287,7 +309,6 @@
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\SimplyBlinkyDemo\main_blinky.c</PathWithFileName>
@@ -308,7 +329,6 @@
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\event_groups.c</PathWithFileName>
@@ -321,7 +341,6 @@
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\list.c</PathWithFileName>
@@ -334,7 +353,6 @@
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\queue.c</PathWithFileName>
@@ -347,7 +365,6 @@
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\tasks.c</PathWithFileName>
@@ -360,7 +377,6 @@
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\timers.c</PathWithFileName>
@@ -373,7 +389,6 @@
<FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\portable\MemMang\heap_4.c</PathWithFileName>
@@ -386,7 +401,6 @@
<FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\portable\RVDS\ARM_CM4F\port.c</PathWithFileName>
@@ -407,7 +421,6 @@
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\main_full.c</PathWithFileName>
@@ -420,7 +433,6 @@
<FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\RunTimeStatsTimer.c</PathWithFileName>
@@ -433,7 +445,6 @@
<FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\serial.c</PathWithFileName>
@@ -446,7 +457,6 @@
<FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\BlockQ.c</PathWithFileName>
@@ -459,7 +469,6 @@
<FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\countsem.c</PathWithFileName>
@@ -472,7 +481,6 @@
<FileNumber>18</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\EventGroupsDemo.c</PathWithFileName>
@@ -485,7 +493,6 @@
<FileNumber>19</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\GenQTest.c</PathWithFileName>
@@ -498,7 +505,6 @@
<FileNumber>20</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\IntSemTest.c</PathWithFileName>
@@ -511,7 +517,6 @@
<FileNumber>21</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\recmutex.c</PathWithFileName>
@@ -524,7 +529,6 @@
<FileNumber>22</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\semtest.c</PathWithFileName>
@@ -537,7 +541,6 @@
<FileNumber>23</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\sp_flop.c</PathWithFileName>
@@ -550,7 +553,6 @@
<FileNumber>24</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\TaskNotify.c</PathWithFileName>
@@ -563,7 +565,6 @@
<FileNumber>25</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\TimerDemo.c</PathWithFileName>
@@ -576,7 +577,6 @@
<FileNumber>26</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c</PathWithFileName>
@@ -589,7 +589,6 @@
<FileNumber>27</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\Sample-CLI-commands.c</PathWithFileName>
@@ -602,7 +601,6 @@
<FileNumber>28</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\UARTCommandConsole.c</PathWithFileName>
@@ -615,7 +613,6 @@
<FileNumber>29</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\RegTest.c</PathWithFileName>
@@ -628,7 +625,6 @@
<FileNumber>30</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\IntQueueTimer.c</PathWithFileName>
@@ -641,7 +637,6 @@
<FileNumber>31</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\IntQueue.c</PathWithFileName>
@@ -662,7 +657,6 @@
<FileNumber>32</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\cpu.c</PathWithFileName>
@@ -675,7 +669,6 @@
<FileNumber>33</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\cs.c</PathWithFileName>
@@ -688,7 +681,6 @@
<FileNumber>34</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\gpio.c</PathWithFileName>
@@ -701,7 +693,6 @@
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\interrupt.c</PathWithFileName>
@@ -714,7 +705,6 @@
<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\pcm.c</PathWithFileName>
@@ -727,7 +717,6 @@
<FileNumber>37</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\uart.c</PathWithFileName>
@@ -740,7 +729,6 @@
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<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\wdt_a.c</PathWithFileName>
@@ -753,7 +741,6 @@
<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\sysctl.c</PathWithFileName>
@@ -766,7 +753,6 @@
<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\fpu.c</PathWithFileName>
@@ -779,7 +765,6 @@
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<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\timer32.c</PathWithFileName>
@@ -787,6 +772,18 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>42</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\rtc_c.c</PathWithFileName>
<FilenameWithoutPath>rtc_c.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvprojx
+20 -47
View File
@@ -10,11 +10,13 @@
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060061::V5.06 update 1 (build 61)::ARMCC</pCCUsed>
<TargetOption>
<TargetCommonOption>
<Device>MSP432P401R</Device>
<Vendor>Texas Instruments</Vendor>
<PackID>TI.MSP432.1.0.0</PackID>
<PackID>TexasInstruments.MSP432.1.0.3</PackID>
<PackURL>http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/mspkeil/latest/exports</PackURL>
<Cpu>IROM(0x00000000,0x00040000) IROM2(0x00200000,0x00004000) IRAM(0x20000000,0x00010000) IRAM2(0x01000000,0x00010000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@@ -83,6 +85,8 @@
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
@@ -121,47 +125,6 @@
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
<RestoreSysVw>1</RestoreSysVw>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>1</RestoreTracepoints>
<RestoreSysVw>1</RestoreSysVw>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>1</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>BIN\UL2CM3.DLL</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
@@ -226,6 +189,7 @@
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
@@ -358,13 +322,17 @@
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uC99>1</uC99>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<VariousControls>
<MiscControls></MiscControls>
<Define>keil __MSP432P401R__</Define>
<Define>keil __MSP432P401R__ NO_MSP_CLASSIC_DEFINES</Define>
<Undefine></Undefine>
<IncludePath>.\driverlib;..\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil;.\Full_Demo;..\Common\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F</IncludePath>
<IncludePath>.\driverlib;..\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil;.\Full_Demo;..\Common\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F;.\driverlib\inc</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -413,9 +381,9 @@
<FilePath>.\system\Keil\startup_MSP432P4.s</FilePath>
</File>
<File>
<FileName>system_MSP432P4.c</FileName>
<FileName>system_msp432p401r.c</FileName>
<FileType>1</FileType>
<FilePath>.\system\Keil\system_MSP432P4.c</FilePath>
<FilePath>.\system\Keil\system_msp432p401r.c</FilePath>
</File>
</Files>
</Group>
@@ -637,6 +605,11 @@
<FileType>1</FileType>
<FilePath>.\driverlib\timer32.c</FilePath>
</File>
<File>
<FileName>rtc_c.c</FileName>
<FileType>1</FileType>
<FilePath>.\driverlib\rtc_c.c</FilePath>
</File>
</Files>
</Group>
<Group>
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.c
+94 -87
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,16 +45,16 @@
/* Statics */
static volatile uint32_t* const _ctlRegs[32] =
{ &ADC14->rMCTL0.r, &ADC14->rMCTL1.r, &ADC14->rMCTL2.r, &ADC14->rMCTL3.r,
&ADC14->rMCTL4.r, &ADC14->rMCTL5.r, &ADC14->rMCTL6.r, &ADC14->rMCTL7.r,
&ADC14->rMCTL8.r, &ADC14->rMCTL9.r, &ADC14->rMCTL10.r,
&ADC14->rMCTL11.r, &ADC14->rMCTL12.r, &ADC14->rMCTL13.r,
&ADC14->rMCTL14.r, &ADC14->rMCTL15.r, &ADC14->rMCTL16.r,
&ADC14->rMCTL17.r, &ADC14->rMCTL18.r, &ADC14->rMCTL19.r,
&ADC14->rMCTL20.r, &ADC14->rMCTL21.r, &ADC14->rMCTL22.r,
&ADC14->rMCTL23.r, &ADC14->rMCTL24.r, &ADC14->rMCTL25.r,
&ADC14->rMCTL26.r, &ADC14->rMCTL27.r, &ADC14->rMCTL28.r,
&ADC14->rMCTL29.r, &ADC14->rMCTL30.r, &ADC14->rMCTL31.r };
{ &ADC14->MCTL[0], &ADC14->MCTL[1], &ADC14->MCTL[2], &ADC14->MCTL[3],
&ADC14->MCTL[4], &ADC14->MCTL[5], &ADC14->MCTL[6], &ADC14->MCTL[7],
&ADC14->MCTL[8], &ADC14->MCTL[9], &ADC14->MCTL[10],
&ADC14->MCTL[11], &ADC14->MCTL[12], &ADC14->MCTL[13],
&ADC14->MCTL[14], &ADC14->MCTL[15], &ADC14->MCTL[16],
&ADC14->MCTL[17], &ADC14->MCTL[18], &ADC14->MCTL[19],
&ADC14->MCTL[20], &ADC14->MCTL[21], &ADC14->MCTL[22],
&ADC14->MCTL[23], &ADC14->MCTL[24], &ADC14->MCTL[25],
&ADC14->MCTL[26], &ADC14->MCTL[27], &ADC14->MCTL[28],
&ADC14->MCTL[29], &ADC14->MCTL[30], &ADC14->MCTL[31] };
static uint_fast8_t _getIndexForMemRegister(uint32_t reg)
{
@@ -145,12 +145,12 @@ static uint_fast8_t _getIndexForMemRegister(uint32_t reg)
//*****************************************************************************
static bool ADCIsConversionRunning(void)
{
return BITBAND_PERI(ADC14->rCTL0.r, ADC14BUSY_OFS);
return BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_BUSY_OFS);
}
void ADC14_enableModule(void)
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS) = 1;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS) = 1;
}
bool ADC14_disableModule(void)
@@ -158,7 +158,7 @@ bool ADC14_disableModule(void)
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS) = 0;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS) = 0;
return true;
}
@@ -168,14 +168,14 @@ bool ADC14_enableSampleTimer(uint32_t multiSampleConvert)
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL0.r, ADC14SHP_OFS) = 1;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SHP_OFS) = 1;
if (multiSampleConvert == ADC_MANUAL_ITERATION)
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14MSC_OFS) = 0;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_MSC_OFS) = 0;
} else
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14MSC_OFS) = 1;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_MSC_OFS) = 1;
}
return true;
@@ -186,7 +186,7 @@ bool ADC14_disableSampleTimer(void)
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL0.r, ADC14SHP_OFS) = 0;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SHP_OFS) = 0;
return true;
}
@@ -225,11 +225,11 @@ bool ADC14_initModule(uint32_t clockSource, uint32_t clockPredivider,
if (ADCIsConversionRunning())
return false;
ADC14->rCTL0.r = (ADC14->rCTL0.r
& ~(ADC14PDIV_M | ADC14DIV_M | ADC14SSEL_M))
ADC14->CTL0 = (ADC14->CTL0
& ~(ADC14_CTL0_PDIV_MASK | ADC14_CTL0_DIV_MASK | ADC14_CTL0_SSEL_MASK))
| clockDivider | clockPredivider | clockSource;
ADC14->rCTL1.r = (ADC14->rCTL1.r
ADC14->CTL1 = (ADC14->CTL1
& ~(ADC_MAPINTCH3 | ADC_MAPINTCH2 | ADC_MAPINTCH1 | ADC_MAPINTCH0
| ADC_TEMPSENSEMAP | ADC_BATTMAP)) | internalChannelMask;
@@ -242,12 +242,12 @@ void ADC14_setResolution(uint32_t resolution)
resolution == ADC_8BIT || resolution == ADC_10BIT
|| resolution == ADC_12BIT || resolution == ADC_14BIT);
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~ADC14RES_M) | resolution;
ADC14->CTL1 = (ADC14->CTL1 & ~ADC14_CTL1_RES_MASK) | resolution;
}
uint_fast32_t ADC14_getResolution(void)
{
return ADC14->rCTL1.r & ADC14RES_M;
return ADC14->CTL1 & ADC14_CTL1_RES_MASK;
}
bool ADC14_setSampleHoldTrigger(uint32_t source, bool invertSignal)
@@ -267,13 +267,13 @@ bool ADC14_setSampleHoldTrigger(uint32_t source, bool invertSignal)
if (invertSignal)
{
ADC14->rCTL0.r = (ADC14->rCTL0.r
& ~(ADC14ISSH | ADC14SHS_M)) | source
| ADC14ISSH;
ADC14->CTL0 = (ADC14->CTL0
& ~(ADC14_CTL0_ISSH | ADC14_CTL0_SHS_MASK)) | source
| ADC14_CTL0_ISSH;
} else
{
ADC14->rCTL0.r = (ADC14->rCTL0.r
& ~(ADC14ISSH | ADC14SHS_M)) | source;
ADC14->CTL0 = (ADC14->CTL0
& ~(ADC14_CTL0_ISSH | ADC14_CTL0_SHS_MASK)) | source;
}
return true;
@@ -305,8 +305,8 @@ bool ADC14_setSampleHoldTime(uint32_t firstPulseWidth,
if (ADCIsConversionRunning())
return false;
ADC14->rCTL0.r = (ADC14->rCTL0.r
& ~(ADC14SHT0_M | ADC14SHT1_M)) | secondPulseWidth
ADC14->CTL0 = (ADC14->CTL0
& ~(ADC14_CTL0_SHT0_MASK | ADC14_CTL0_SHT1_MASK)) | secondPulseWidth
| (firstPulseWidth >> 4);
return true;
@@ -327,26 +327,26 @@ bool repeatMode)
/* Clearing out any lingering EOS */
for (ii = 0; ii < 32; ii++)
{
BITBAND_PERI(*(_ctlRegs[ii]), ADC14EOS_OFS) = 0;
BITBAND_PERI(*(_ctlRegs[ii]), ADC14_MCTLN_EOS_OFS) = 0;
}
/* Setting Start/Stop locations */
BITBAND_PERI(
(*(_ctlRegs[_getIndexForMemRegister(memoryEnd)])),
ADC14EOS_OFS) = 1;
ADC14_MCTLN_EOS_OFS) = 1;
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14CSTARTADD_M))
ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_CSTARTADD_MASK))
| (_getIndexForMemRegister(memoryStart) << 16);
/* Setting multiple sample mode */
if (!repeatMode)
{
ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
| (ADC14CONSEQ_1);
ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
| (ADC14_CTL0_CONSEQ_1);
} else
{
ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
| (ADC14CONSEQ_3);
ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
| (ADC14_CTL0_CONSEQ_3);
}
return true;
@@ -361,18 +361,18 @@ bool repeatMode)
return false;
/* Setting the destination register */
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14CSTARTADD_M))
ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_CSTARTADD_MASK))
| (_getIndexForMemRegister(memoryDestination) << 16);
/* Setting single sample mode */
if (!repeatMode)
{
ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
| (ADC14CONSEQ_0);
ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
| (ADC14_CTL0_CONSEQ_0);
} else
{
ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
| (ADC14CONSEQ_2);
ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
| (ADC14_CTL0_CONSEQ_2);
}
return true;
@@ -380,25 +380,25 @@ bool repeatMode)
bool ADC14_enableConversion(void)
{
if (ADCIsConversionRunning() || !BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS))
if (ADCIsConversionRunning() || !BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS))
return false;
ADC14->rCTL0.r |= (ADC14ENC);
ADC14->CTL0 |= (ADC14_CTL0_ENC);
return true;
}
bool ADC14_toggleConversionTrigger(void)
{
if (!BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS))
if (!BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS))
return false;
if (BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS))
if (BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS))
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS) = 0;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS) = 0;
} else
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS) = 1;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS) = 1;
}
return true;
@@ -406,12 +406,12 @@ bool ADC14_toggleConversionTrigger(void)
void ADC14_disableConversion(void)
{
ADC14->rCTL0.r &= ~(ADC14SC | ADC14ENC);
ADC14->CTL0 &= ~(ADC14_CTL0_SC | ADC14_CTL0_ENC);
}
bool ADC14_isBusy(void)
{
return BITBAND_PERI(ADC14->rCTL0.r, ADC14BUSY_OFS);
return BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_BUSY_OFS);
}
bool ADC14_configureConversionMemory(uint32_t memorySelect, uint32_t refSelect,
@@ -444,14 +444,14 @@ bool ADC14_configureConversionMemory(uint32_t memorySelect, uint32_t refSelect,
if (differntialMode)
{
(*curReg) = ((*curReg)
& ~(ADC14VRSEL_M | ADC14INCH_M
| ADC14DIF))
| (channelSelect | refSelect | ADC14DIF);
& ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK
| ADC14_MCTLN_DIF))
| (channelSelect | refSelect | ADC14_MCTLN_DIF);
} else
{
(*curReg) = ((*curReg)
& ~(ADC14VRSEL_M | ADC14INCH_M
| ADC14DIF)) | (channelSelect | refSelect);
& ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK
| ADC14_MCTLN_DIF)) | (channelSelect | refSelect);
}
}
@@ -489,11 +489,11 @@ bool ADC14_enableComparatorWindow(uint32_t memorySelect, uint32_t windowSelect)
if (windowSelect == ADC_COMP_WINDOW0)
{
(*curRegPoint) = ((*curRegPoint)
& ~(ADC14WINC | ADC14WINCTH))
| (ADC14WINC);
& ~(ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH))
| (ADC14_MCTLN_WINC);
} else if (windowSelect == ADC_COMP_WINDOW1)
{
(*curRegPoint) |= ADC14WINC | ADC14WINCTH;
(*curRegPoint) |= ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH;
}
}
@@ -525,7 +525,7 @@ bool ADC14_disableComparatorWindow(uint32_t memorySelect)
ii = ii << 1;
(*(_ctlRegs[_getIndexForMemRegister(currentReg)])) &=
~ADC14WINC;
~ADC14_MCTLN_WINC;
}
@@ -536,20 +536,27 @@ bool ADC14_setComparatorWindowValue(uint32_t window, int16_t low, int16_t high)
{
if (ADCIsConversionRunning())
return false;
if(BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS))
{
low = ((low << 2) | (0x8000 & low)) & 0xFFFC;
high = ((high << 2) | (0x8000 & high)) & 0xFFFC;
}
if (window == ADC_COMP_WINDOW0)
{
ADC14->rHI0.r = (high);
ADC14->rLO0.r = (low);
ADC14->HI0 = (high);
ADC14->LO0 = (low);
} else if (window == ADC_COMP_WINDOW1)
{
ADC14->rHI1.r = (high);
ADC14->rLO1.r = (low);
ADC14->HI1 = (high);
ADC14->LO1 = (low);
} else
{
ASSERT(false);
return false;
}
return true;
@@ -562,10 +569,10 @@ bool ADC14_setResultFormat(uint32_t resultFormat)
if (resultFormat == ADC_UNSIGNED_BINARY)
{
BITBAND_PERI(ADC14->rCTL1.r, ADC14DF_OFS) = 0;
BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS) = 0;
} else if (resultFormat == ADC_SIGNED_BINARY)
{
BITBAND_PERI(ADC14->rCTL1.r, ADC14DF_OFS) = 1;
BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS) = 1;
} else
{
ASSERT(false);
@@ -577,7 +584,7 @@ bool ADC14_setResultFormat(uint32_t resultFormat)
uint_fast16_t ADC14_getResult(uint32_t memorySelect)
{
return *((uint16_t*) (_ctlRegs[_getIndexForMemRegister(memorySelect)]
+ 0x80));
+ 0x20));
}
void ADC14_getMultiSequenceResult(uint16_t* res)
@@ -585,16 +592,16 @@ void ADC14_getMultiSequenceResult(uint16_t* res)
uint32_t *startAddr, *curAddr;
uint32_t ii;
startAddr = (uint32_t*) _ctlRegs[(ADC14->rCTL1.r & ADC14CSTARTADD_M)
startAddr = (uint32_t*) _ctlRegs[(ADC14->CTL1 & ADC14_CTL1_CSTARTADD_MASK)
>> 16];
curAddr = startAddr;
for (ii = 0; ii < 32; ii++)
{
res[ii] = *(((uint16_t*) curAddr) + 0x80);
res[ii] = *(((uint16_t*) curAddr) + 0x40);
if (BITBAND_PERI((*curAddr), ADC14EOS_OFS))
if (BITBAND_PERI((*curAddr), ADC14_MCTLN_EOS_OFS))
break;
if (curAddr == _ctlRegs[31])
@@ -627,7 +634,7 @@ void ADC14_getResultArray(uint32_t memoryStart, uint32_t memoryEnd,
foundEnd = true;
}
res[ii] = *(((uint16_t*) firstPoint) + 0x80);
res[ii] = *(((uint16_t*) firstPoint) + 0x40);
if (firstPoint == _ctlRegs[31])
firstPoint = (uint32_t*) _ctlRegs[0];
@@ -641,7 +648,7 @@ bool ADC14_enableReferenceBurst(void)
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL1.r, ADC14REFBURST_OFS) = 1;
BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_REFBURST_OFS) = 1;
return true;
}
@@ -651,7 +658,7 @@ bool ADC14_disableReferenceBurst(void)
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL1.r, ADC14REFBURST_OFS) = 0;
BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_REFBURST_OFS) = 0;
return true;
}
@@ -664,12 +671,12 @@ bool ADC14_setPowerMode(uint32_t adcPowerMode)
switch (adcPowerMode)
{
case ADC_UNRESTRICTED_POWER_MODE:
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14PWRMD_M))
| (ADC14PWRMD_0);
ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_PWRMD_MASK))
| (ADC14_CTL1_PWRMD_0);
break;
case ADC_ULTRA_LOW_POWER_MODE:
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14PWRMD_M))
| (ADC14PWRMD_2);
ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_PWRMD_MASK))
| (ADC14_CTL1_PWRMD_2);
break;
default:
ASSERT(false);
@@ -683,31 +690,31 @@ void ADC14_enableInterrupt(uint_fast64_t mask)
{
uint32_t stat = mask & 0xFFFFFFFF;
ADC14->rIER0.r |= stat;
ADC14->IER0 |= stat;
stat = (mask >> 32);
ADC14->rIER1.r |= (stat);
ADC14->IER1 |= (stat);
}
void ADC14_disableInterrupt(uint_fast64_t mask)
{
uint32_t stat = mask & 0xFFFFFFFF;
ADC14->rIER0.r &= ~stat;
ADC14->IER0 &= ~stat;
stat = (mask >> 32);
ADC14->rIER1.r &= ~(stat);
ADC14->IER1 &= ~(stat);
}
uint_fast64_t ADC14_getInterruptStatus(void)
{
uint_fast64_t status = ADC14->rIFGR1.r;
return ((status << 32) | ADC14->rIFGR0.r);
uint_fast64_t status = ADC14->IFGR1;
return ((status << 32) | ADC14->IFGR0);
}
uint_fast64_t ADC14_getEnabledInterruptStatus(void)
{
uint_fast64_t stat = ADC14->rIER1.r;
uint_fast64_t stat = ADC14->IER1;
return ADC14_getInterruptStatus() & ((stat << 32) | ADC14->rIER0.r);
return ADC14_getInterruptStatus() & ((stat << 32) | ADC14->IER0);
}
@@ -715,9 +722,9 @@ void ADC14_clearInterruptFlag(uint_fast64_t mask)
{
uint32_t stat = mask & 0xFFFFFFFF;
ADC14->rCLRIFGR0.r |= stat;
ADC14->CLRIFGR0 |= stat;
stat = (mask >> 32);
ADC14->rCLRIFGR1.r |= (stat);
ADC14->CLRIFGR1 |= (stat);
}
void ADC14_registerInterrupt(void (*intHandler)(void))
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.h
+120 -123
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -71,57 +71,57 @@ extern "C"
//The following are values that can be passed to ADC14_initModule
//
//*****************************************************************************
#define ADC_CLOCKSOURCE_ADCOSC (ADC14SSEL_0)
#define ADC_CLOCKSOURCE_SYSOSC (ADC14SSEL_1)
#define ADC_CLOCKSOURCE_ACLK (ADC14SSEL_2)
#define ADC_CLOCKSOURCE_MCLK (ADC14SSEL_3)
#define ADC_CLOCKSOURCE_SMCLK (ADC14SSEL_4)
#define ADC_CLOCKSOURCE_HSMCLK (ADC14SSEL_5)
#define ADC_CLOCKSOURCE_ADCOSC (ADC14_CTL0_SSEL_0)
#define ADC_CLOCKSOURCE_SYSOSC (ADC14_CTL0_SSEL_1)
#define ADC_CLOCKSOURCE_ACLK (ADC14_CTL0_SSEL_2)
#define ADC_CLOCKSOURCE_MCLK (ADC14_CTL0_SSEL_3)
#define ADC_CLOCKSOURCE_SMCLK (ADC14_CTL0_SSEL_4)
#define ADC_CLOCKSOURCE_HSMCLK (ADC14_CTL0_SSEL_5)
#define ADC_PREDIVIDER_1 (ADC14PDIV_0)
#define ADC_PREDIVIDER_4 (ADC14PDIV_1)
#define ADC_PREDIVIDER_32 (ADC14PDIV_2)
#define ADC_PREDIVIDER_64 (ADC14PDIV_3)
#define ADC_PREDIVIDER_1 (ADC14_CTL0_PDIV_0)
#define ADC_PREDIVIDER_4 (ADC14_CTL0_PDIV_1)
#define ADC_PREDIVIDER_32 (ADC14_CTL0_PDIV_2)
#define ADC_PREDIVIDER_64 (ADC14_CTL0_PDIV_3)
#define ADC_DIVIDER_1 (ADC14DIV_0)
#define ADC_DIVIDER_2 (ADC14DIV_1)
#define ADC_DIVIDER_3 (ADC14DIV_2)
#define ADC_DIVIDER_4 (ADC14DIV_3)
#define ADC_DIVIDER_5 (ADC14DIV_4)
#define ADC_DIVIDER_6 (ADC14DIV_5)
#define ADC_DIVIDER_7 (ADC14DIV_6)
#define ADC_DIVIDER_8 (ADC14DIV_7)
#define ADC_DIVIDER_1 (ADC14_CTL0_DIV_0)
#define ADC_DIVIDER_2 (ADC14_CTL0_DIV_1)
#define ADC_DIVIDER_3 (ADC14_CTL0_DIV_2)
#define ADC_DIVIDER_4 (ADC14_CTL0_DIV_3)
#define ADC_DIVIDER_5 (ADC14_CTL0_DIV_4)
#define ADC_DIVIDER_6 (ADC14_CTL0_DIV_5)
#define ADC_DIVIDER_7 (ADC14_CTL0_DIV_6)
#define ADC_DIVIDER_8 (ADC14_CTL0_DIV_7)
#define ADC_MAPINTCH3 (ADC14CH3MAP)
#define ADC_MAPINTCH2 (ADC14CH2MAP)
#define ADC_MAPINTCH1 (ADC14CH1MAP)
#define ADC_MAPINTCH0 (ADC14CH0MAP)
#define ADC_TEMPSENSEMAP (ADC14TCMAP)
#define ADC_BATTMAP (ADC14BATMAP)
#define ADC_MAPINTCH3 (ADC14_CTL1_CH3MAP)
#define ADC_MAPINTCH2 (ADC14_CTL1_CH2MAP)
#define ADC_MAPINTCH1 (ADC14_CTL1_CH1MAP)
#define ADC_MAPINTCH0 (ADC14_CTL1_CH0MAP)
#define ADC_TEMPSENSEMAP (ADC14_CTL1_TCMAP)
#define ADC_BATTMAP (ADC14_CTL1_BATMAP)
#define ADC_NOROUTE 0
#define ADC_8BIT ADC14RES_0
#define ADC_10BIT ADC14RES_1
#define ADC_12BIT ADC14RES_2
#define ADC_14BIT ADC14RES_3
#define ADC_8BIT ADC14_CTL1_RES_0
#define ADC_10BIT ADC14_CTL1_RES_1
#define ADC_12BIT ADC14_CTL1_RES_2
#define ADC_14BIT ADC14_CTL1_RES_3
#define ADC_TRIGGER_ADCSC ADC14SHS_0
#define ADC_TRIGGER_SOURCE1 ADC14SHS_1
#define ADC_TRIGGER_SOURCE2 ADC14SHS_2
#define ADC_TRIGGER_SOURCE3 ADC14SHS_3
#define ADC_TRIGGER_SOURCE4 ADC14SHS_4
#define ADC_TRIGGER_SOURCE5 ADC14SHS_5
#define ADC_TRIGGER_SOURCE6 ADC14SHS_6
#define ADC_TRIGGER_SOURCE7 ADC14SHS_7
#define ADC_TRIGGER_ADCSC ADC14_CTL0_SHS_0
#define ADC_TRIGGER_SOURCE1 ADC14_CTL0_SHS_1
#define ADC_TRIGGER_SOURCE2 ADC14_CTL0_SHS_2
#define ADC_TRIGGER_SOURCE3 ADC14_CTL0_SHS_3
#define ADC_TRIGGER_SOURCE4 ADC14_CTL0_SHS_4
#define ADC_TRIGGER_SOURCE5 ADC14_CTL0_SHS_5
#define ADC_TRIGGER_SOURCE6 ADC14_CTL0_SHS_6
#define ADC_TRIGGER_SOURCE7 ADC14_CTL0_SHS_7
#define ADC_PULSE_WIDTH_4 ADC14SHT1_0
#define ADC_PULSE_WIDTH_8 ADC14SHT1_1
#define ADC_PULSE_WIDTH_16 ADC14SHT1_2
#define ADC_PULSE_WIDTH_32 ADC14SHT1_3
#define ADC_PULSE_WIDTH_64 ADC14SHT1_4
#define ADC_PULSE_WIDTH_96 ADC14SHT1_5
#define ADC_PULSE_WIDTH_128 ADC14SHT1_6
#define ADC_PULSE_WIDTH_192 ADC14SHT1_7
#define ADC_PULSE_WIDTH_4 ADC14_CTL0_SHT1_0
#define ADC_PULSE_WIDTH_8 ADC14_CTL0_SHT1_1
#define ADC_PULSE_WIDTH_16 ADC14_CTL0_SHT1_2
#define ADC_PULSE_WIDTH_32 ADC14_CTL0_SHT1_3
#define ADC_PULSE_WIDTH_64 ADC14_CTL0_SHT1_4
#define ADC_PULSE_WIDTH_96 ADC14_CTL0_SHT1_5
#define ADC_PULSE_WIDTH_128 ADC14_CTL0_SHT1_6
#define ADC_PULSE_WIDTH_192 ADC14_CTL0_SHT1_7
#define ADC_NONDIFFERENTIAL_INPUTS false
#define ADC_DIFFERENTIAL_INPUTS true
@@ -159,43 +159,43 @@ extern "C"
#define ADC_MEM30 0x40000000
#define ADC_MEM31 0x80000000
#define ADC_VREFPOS_AVCC_VREFNEG_VSS (ADC14VRSEL_0)
#define ADC_VREFPOS_INTBUF_VREFNEG_VSS (ADC14VRSEL_1)
#define ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG (ADC14VRSEL_14)
#define ADC_VREFPOS_EXTBUF_VREFNEG_EXTNEG (ADC14VRSEL_15)
#define ADC_VREFPOS_AVCC_VREFNEG_VSS (ADC14_MCTLN_VRSEL_0)
#define ADC_VREFPOS_INTBUF_VREFNEG_VSS (ADC14_MCTLN_VRSEL_1)
#define ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG (ADC14_MCTLN_VRSEL_14)
#define ADC_VREFPOS_EXTBUF_VREFNEG_EXTNEG (ADC14_MCTLN_VRSEL_15)
#define ADC_INPUT_A0 (ADC14INCH_0)
#define ADC_INPUT_A1 (ADC14INCH_1)
#define ADC_INPUT_A2 (ADC14INCH_2)
#define ADC_INPUT_A3 (ADC14INCH_3)
#define ADC_INPUT_A4 (ADC14INCH_4)
#define ADC_INPUT_A5 (ADC14INCH_5)
#define ADC_INPUT_A6 (ADC14INCH_6)
#define ADC_INPUT_A7 (ADC14INCH_7)
#define ADC_INPUT_A8 (ADC14INCH_8)
#define ADC_INPUT_A9 (ADC14INCH_9)
#define ADC_INPUT_A10 (ADC14INCH_10)
#define ADC_INPUT_A11 (ADC14INCH_11)
#define ADC_INPUT_A12 (ADC14INCH_12)
#define ADC_INPUT_A13 (ADC14INCH_13)
#define ADC_INPUT_A14 (ADC14INCH_14)
#define ADC_INPUT_A15 (ADC14INCH_15)
#define ADC_INPUT_A16 (ADC14INCH_16)
#define ADC_INPUT_A17 (ADC14INCH_17)
#define ADC_INPUT_A18 (ADC14INCH_18)
#define ADC_INPUT_A19 (ADC14INCH_19)
#define ADC_INPUT_A20 (ADC14INCH_20)
#define ADC_INPUT_A21 (ADC14INCH_21)
#define ADC_INPUT_A22 (ADC14INCH_22)
#define ADC_INPUT_A23 (ADC14INCH_23)
#define ADC_INPUT_A24 (ADC14INCH_24)
#define ADC_INPUT_A25 (ADC14INCH_25)
#define ADC_INPUT_A26 (ADC14INCH_26)
#define ADC_INPUT_A27 (ADC14INCH_27)
#define ADC_INPUT_A28 (ADC14INCH_28)
#define ADC_INPUT_A29 (ADC14INCH_29)
#define ADC_INPUT_A30 (ADC14INCH_30)
#define ADC_INPUT_A31 (ADC14INCH_31)
#define ADC_INPUT_A0 (ADC14_MCTLN_INCH_0)
#define ADC_INPUT_A1 (ADC14_MCTLN_INCH_1)
#define ADC_INPUT_A2 (ADC14_MCTLN_INCH_2)
#define ADC_INPUT_A3 (ADC14_MCTLN_INCH_3)
#define ADC_INPUT_A4 (ADC14_MCTLN_INCH_4)
#define ADC_INPUT_A5 (ADC14_MCTLN_INCH_5)
#define ADC_INPUT_A6 (ADC14_MCTLN_INCH_6)
#define ADC_INPUT_A7 (ADC14_MCTLN_INCH_7)
#define ADC_INPUT_A8 (ADC14_MCTLN_INCH_8)
#define ADC_INPUT_A9 (ADC14_MCTLN_INCH_9)
#define ADC_INPUT_A10 (ADC14_MCTLN_INCH_10)
#define ADC_INPUT_A11 (ADC14_MCTLN_INCH_11)
#define ADC_INPUT_A12 (ADC14_MCTLN_INCH_12)
#define ADC_INPUT_A13 (ADC14_MCTLN_INCH_13)
#define ADC_INPUT_A14 (ADC14_MCTLN_INCH_14)
#define ADC_INPUT_A15 (ADC14_MCTLN_INCH_15)
#define ADC_INPUT_A16 (ADC14_MCTLN_INCH_16)
#define ADC_INPUT_A17 (ADC14_MCTLN_INCH_17)
#define ADC_INPUT_A18 (ADC14_MCTLN_INCH_18)
#define ADC_INPUT_A19 (ADC14_MCTLN_INCH_19)
#define ADC_INPUT_A20 (ADC14_MCTLN_INCH_20)
#define ADC_INPUT_A21 (ADC14_MCTLN_INCH_21)
#define ADC_INPUT_A22 (ADC14_MCTLN_INCH_22)
#define ADC_INPUT_A23 (ADC14_MCTLN_INCH_23)
#define ADC_INPUT_A24 (ADC14_MCTLN_INCH_24)
#define ADC_INPUT_A25 (ADC14_MCTLN_INCH_25)
#define ADC_INPUT_A26 (ADC14_MCTLN_INCH_26)
#define ADC_INPUT_A27 (ADC14_MCTLN_INCH_27)
#define ADC_INPUT_A28 (ADC14_MCTLN_INCH_28)
#define ADC_INPUT_A29 (ADC14_MCTLN_INCH_29)
#define ADC_INPUT_A30 (ADC14_MCTLN_INCH_30)
#define ADC_INPUT_A31 (ADC14_MCTLN_INCH_31)
#define ADC_COMP_WINDOW0 0x00
#define ADC_COMP_WINDOW1 0x01
@@ -204,44 +204,44 @@ extern "C"
#define ADC_UNSIGNED_BINARY 0x01
#define ADC_MANUAL_ITERATION 0x00
#define ADC_AUTOMATIC_ITERATION ADC14MSC
#define ADC_AUTOMATIC_ITERATION ADC14_CTL0_MSC
#define ADC_UNRESTRICTED_POWER_MODE ADC14PWRMD_0
#define ADC_ULTRA_LOW_POWER_MODE ADC14PWRMD_2
#define ADC_UNRESTRICTED_POWER_MODE ADC14_CTL1_PWRMD_0
#define ADC_ULTRA_LOW_POWER_MODE ADC14_CTL1_PWRMD_2
#define ADC_INT0 ADC14IE0
#define ADC_INT1 ADC14IE1
#define ADC_INT2 ADC14IE2
#define ADC_INT3 ADC14IE3
#define ADC_INT4 ADC14IE4
#define ADC_INT5 ADC14IE5
#define ADC_INT6 ADC14IE6
#define ADC_INT7 ADC14IE7
#define ADC_INT8 ADC14IE8
#define ADC_INT9 ADC14IE9
#define ADC_INT10 ADC14IE10
#define ADC_INT11 ADC14IE11
#define ADC_INT12 ADC14IE12
#define ADC_INT13 ADC14IE13
#define ADC_INT14 ADC14IE14
#define ADC_INT15 ADC14IE15
#define ADC_INT16 ADC14IE16
#define ADC_INT17 ADC14IE17
#define ADC_INT18 ADC14IE18
#define ADC_INT19 ADC14IE19
#define ADC_INT20 ADC14IE20
#define ADC_INT21 ADC14IE21
#define ADC_INT22 ADC14IE22
#define ADC_INT23 ADC14IE23
#define ADC_INT24 ADC14IE24
#define ADC_INT25 ADC14IE25
#define ADC_INT26 ADC14IE26
#define ADC_INT27 ADC14IE27
#define ADC_INT28 ADC14IE28
#define ADC_INT29 ADC14IE29
#define ADC_INT30 ADC14IE30
#define ADC_INT31 ADC14IE31
#define ADC_INT0 ADC14_IER0_IE0
#define ADC_INT1 ADC14_IER0_IE1
#define ADC_INT2 ADC14_IER0_IE2
#define ADC_INT3 ADC14_IER0_IE3
#define ADC_INT4 ADC14_IER0_IE4
#define ADC_INT5 ADC14_IER0_IE5
#define ADC_INT6 ADC14_IER0_IE6
#define ADC_INT7 ADC14_IER0_IE7
#define ADC_INT8 ADC14_IER0_IE8
#define ADC_INT9 ADC14_IER0_IE9
#define ADC_INT10 ADC14_IER0_IE10
#define ADC_INT11 ADC14_IER0_IE11
#define ADC_INT12 ADC14_IER0_IE12
#define ADC_INT13 ADC14_IER0_IE13
#define ADC_INT14 ADC14_IER0_IE14
#define ADC_INT15 ADC14_IER0_IE15
#define ADC_INT16 ADC14_IER0_IE16
#define ADC_INT17 ADC14_IER0_IE17
#define ADC_INT18 ADC14_IER0_IE18
#define ADC_INT19 ADC14_IER0_IE19
#define ADC_INT20 ADC14_IER0_IE20
#define ADC_INT21 ADC14_IER0_IE21
#define ADC_INT22 ADC14_IER0_IE22
#define ADC_INT23 ADC14_IER0_IE23
#define ADC_INT24 ADC14_IER0_IE24
#define ADC_INT25 ADC14_IER0_IE25
#define ADC_INT26 ADC14_IER0_IE26
#define ADC_INT27 ADC14_IER0_IE27
#define ADC_INT28 ADC14_IER0_IE28
#define ADC_INT29 ADC14_IER0_IE29
#define ADC_INT30 ADC14_IER0_IE30
#define ADC_INT31 ADC14_IER0_IE31
#define ADC_IN_INT 0x0000000200000000
#define ADC_LO_INT 0x0000000400000000
#define ADC_HI_INT 0x0000000800000000
@@ -542,9 +542,6 @@ extern bool ADC14_toggleConversionTrigger(void);
//!
//! Returns a boolean value that tells if a conversion/sample is in progress
//!
//! Originally a public function, but moved to static. External customers should
//! use the ADC14_isBusy function.
//!
//! \return true if conversion is active, false otherwise
//
//*****************************************************************************
@@ -1026,8 +1023,8 @@ extern void ADC14_unregisterInterrupt(void);
#define ADC14_enableModuleMultipleInstance(a) ADC14_enableModule()
#define ADC14_disableModuleMultipleInstance(a) ADC14_disableModule()
#define ADC14_initModuleMultipleInstance(a,b,c,d,e) ADC14_initModule(b,c,d,e)
#define ADC14_setResolutionMutlipleInstance(a,b) ADC14_setResolution(b)
#define ADC14_getResolutionMutlipleInstance(a) ADC14_getResolution()
#define ADC14_setResolutionMultipleInstance(a,b) ADC14_setResolution(b)
#define ADC14_getResolutionMultipleInstance(a) ADC14_getResolution()
#define ADC14_setSampleHoldTriggerMultipleInstance(a,b,c) ADC14_setSampleHoldTrigger(b,c)
#define ADC14_setSampleHoldTimeMultipleInstance(a,b,c) ADC14_setSampleHoldTime(b,c)
#define ADC14_configureMultiSequenceModeMultipleInstance(a,b,c,d) ADC14_configureMultiSequenceMode(b,c,d)
@@ -1036,7 +1033,7 @@ extern void ADC14_unregisterInterrupt(void);
#define ADC14_disableConversionMultipleInstance(a) ADC14_disableConversion()
#define ADC14_toggleConversionTriggerMultipleInstance(a) ADC14_toggleConversionTrigger()
#define ADC14_isBusyMultipleInstance(a) ADC14_isBusy()
#define ADC14_configureConversionMemoryMultipleInstance(a,b,c,d,e) ADC14_enableModule(b,c,d,e)
#define ADC14_configureConversionMemoryMultipleInstance(a,b,c,d,e) ADC14_configureConversionMemory(b,c,d,e)
#define ADC14_enableComparatorWindowMultipleInstance(a,b,c) ADC14_enableComparatorWindow(b,c)
#define ADC14_disableComparatorWindowMultipleInstance(a,b) ADC14_disableComparatorWindow(b)
#define ADC14_setComparatorWindowValueMultipleInstance(a,b,c,d) ADC14_setComparatorWindowValue(b,c,d)
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.c
+54 -54
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,23 +41,23 @@
bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
uint_fast16_t keyLength)
{
uint8_t i;
uint_fast8_t i;
uint16_t sCipherKey;
AES256_CMSIS(moduleInstance)->rCTL0.r |= 0;
AES256_CMSIS(moduleInstance)->CTL0 |= 0;
switch (keyLength)
{
case AES256_KEYLENGTH_128BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT;
break;
case AES256_KEYLENGTH_192BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT;
break;
case AES256_KEYLENGTH_256BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT;
break;
default:
return false;
@@ -69,11 +69,11 @@ bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
{
sCipherKey = (uint16_t) (cipherKey[i]);
sCipherKey = sCipherKey | ((uint16_t) (cipherKey[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rKEY.r = sCipherKey;
AES256_CMSIS(moduleInstance)->KEY = sCipherKey;
}
// Wait until key is written
while (!BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS))
while (!BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS))
;
return true;
@@ -82,33 +82,33 @@ bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
void AES256_encryptData(uint32_t moduleInstance, const uint8_t * data,
uint8_t * encryptedData)
{
uint8_t i;
uint_fast8_t i;
uint16_t tempData = 0;
uint16_t tempVariable = 0;
// Set module to encrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r &= ~AESOP_M;
AES256_CMSIS(moduleInstance)->CTL0 &= ~AES256_CTL0_OP_MASK;
// Write data to encrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i]);
tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
AES256_CMSIS(moduleInstance)->DIN = tempVariable;
}
// Key that is already written shall be used
// Encryption is initialized by setting AESKEYWR to 1
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
// Encryption is initialized by setting AES256_STAT_KEYWR to 1
BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
// Wait unit finished ~167 MCLK
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
;
// Write encrypted data back to variable
for (i = 0; i < 16; i = i + 2)
{
tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
tempData = AES256_CMSIS(moduleInstance)->DOUT;
*(encryptedData + i) = (uint8_t) tempData;
*(encryptedData + i + 1) = (uint8_t) (tempData >> 8);
}
@@ -117,33 +117,33 @@ void AES256_encryptData(uint32_t moduleInstance, const uint8_t * data,
void AES256_decryptData(uint32_t moduleInstance, const uint8_t * data,
uint8_t * decryptedData)
{
uint8_t i;
uint_fast8_t i;
uint16_t tempData = 0;
uint16_t tempVariable = 0;
// Set module to decrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r |= (AESOP_3);
AES256_CMSIS(moduleInstance)->CTL0 |= (AES256_CTL0_OP_3);
// Write data to decrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i + 1] << 8);
tempVariable = tempVariable | ((uint16_t) (data[i]));
AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
AES256_CMSIS(moduleInstance)->DIN = tempVariable;
}
// Key that is already written shall be used
// Now decryption starts
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
// Wait unit finished ~167 MCLK
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
;
// Write encrypted data back to variable
for (i = 0; i < 16; i = i + 2)
{
tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
tempData = AES256_CMSIS(moduleInstance)->DOUT;
*(decryptedData + i) = (uint8_t) tempData;
*(decryptedData + i + 1) = (uint8_t) (tempData >> 8);
}
@@ -156,21 +156,21 @@ bool AES256_setDecipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
uint16_t tempVariable = 0;
// Set module to decrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r =
(AES256_CMSIS(moduleInstance)->rCTL0.r & ~AESOP_M) | AESOP1;
AES256_CMSIS(moduleInstance)->CTL0 =
(AES256_CMSIS(moduleInstance)->CTL0 & ~AES256_CTL0_OP_MASK) | AES256_CTL0_OP1;
switch (keyLength)
{
case AES256_KEYLENGTH_128BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT;
break;
case AES256_KEYLENGTH_192BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT;
break;
case AES256_KEYLENGTH_256BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT;
break;
default:
@@ -184,11 +184,11 @@ bool AES256_setDecipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
{
tempVariable = (uint16_t) (cipherKey[i]);
tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rKEY.r = tempVariable;
AES256_CMSIS(moduleInstance)->KEY = tempVariable;
}
// Wait until key is processed ~52 MCLK
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
;
return true;
@@ -196,27 +196,27 @@ bool AES256_setDecipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
void AES256_clearInterruptFlag(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIFG_OFS) = 0;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIFG_OFS) = 0;
}
uint32_t AES256_getInterruptFlagStatus(uint32_t moduleInstance)
{
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESRDYIFG_OFS);
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_RDYIFG_OFS);
}
void AES256_enableInterrupt(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIE_OFS) = 1;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIE_OFS) = 1;
}
void AES256_disableInterrupt(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIE_OFS) = 0;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIE_OFS) = 0;
}
void AES256_reset(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESSWRST_OFS) = 1;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_SWRST_OFS) = 1;
}
void AES256_startEncryptData(uint32_t moduleInstance, const uint8_t * data)
@@ -225,63 +225,63 @@ void AES256_startEncryptData(uint32_t moduleInstance, const uint8_t * data)
uint16_t tempVariable = 0;
// Set module to encrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r &= ~AESOP_M;
AES256_CMSIS(moduleInstance)->CTL0 &= ~AES256_CTL0_OP_MASK;
// Write data to encrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i]);
tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
AES256_CMSIS(moduleInstance)->DIN = tempVariable;
}
// Key that is already written shall be used
// Encryption is initialized by setting AESKEYWR to 1
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
// Encryption is initialized by setting AES256_STAT_KEYWR to 1
BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
}
void AES256_startDecryptData(uint32_t moduleInstance, const uint8_t * data)
{
uint8_t i;
uint_fast8_t i;
uint16_t tempVariable = 0;
// Set module to decrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r |= (AESOP_3);
AES256_CMSIS(moduleInstance)->CTL0 |= (AES256_CTL0_OP_3);
// Write data to decrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i + 1] << 8);
tempVariable = tempVariable | ((uint16_t) (data[i]));
AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
AES256_CMSIS(moduleInstance)->DIN = tempVariable;
}
// Key that is already written shall be used
// Now decryption starts
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
}
bool AES256_startSetDecipherKey(uint32_t moduleInstance,
const uint8_t * cipherKey, uint_fast16_t keyLength)
{
uint8_t i;
uint_fast8_t i;
uint16_t tempVariable = 0;
AES256_CMSIS(moduleInstance)->rCTL0.r =
(AES256_CMSIS(moduleInstance)->rCTL0.r & ~AESOP_M) | AESOP1;
AES256_CMSIS(moduleInstance)->CTL0 =
(AES256_CMSIS(moduleInstance)->CTL0 & ~AES256_CTL0_OP_MASK) | AES256_CTL0_OP1;
switch (keyLength)
{
case AES256_KEYLENGTH_128BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT;
break;
case AES256_KEYLENGTH_192BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT;
break;
case AES256_KEYLENGTH_256BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT;
break;
default:
@@ -295,7 +295,7 @@ bool AES256_startSetDecipherKey(uint32_t moduleInstance,
{
tempVariable = (uint16_t) (cipherKey[i]);
tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rKEY.r = tempVariable;
AES256_CMSIS(moduleInstance)->KEY = tempVariable;
}
return true;
@@ -307,13 +307,13 @@ bool AES256_getDataOut(uint32_t moduleInstance, uint8_t *outputData)
uint16_t tempData = 0;
// If module is busy, exit and return failure
if (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
if (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
return false;
// Write encrypted data back to variable
for (i = 0; i < 16; i = i + 2)
{
tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
tempData = AES256_CMSIS(moduleInstance)->DOUT;
*(outputData + i) = (uint8_t) tempData;
*(outputData + i + 1) = (uint8_t) (tempData >> 8);
}
@@ -323,17 +323,17 @@ bool AES256_getDataOut(uint32_t moduleInstance, uint8_t *outputData)
bool AES256_isBusy(uint32_t moduleInstance)
{
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS);
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS);
}
void AES256_clearErrorFlag(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESERRFG_OFS) = 0;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_ERRFG_OFS) = 0;
}
uint32_t AES256_getErrorFlagStatus(uint32_t moduleInstance)
{
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESERRFG_OFS);
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_ERRFG_OFS);
}
void AES256_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.h
+4 -4
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -89,7 +89,7 @@ extern "C"
// can be returned by the AES256_getErrorFlagStatus() function.
//
//*****************************************************************************
#define AES256_ERROR_OCCURRED AESERRFG
#define AES256_ERROR_OCCURRED AES256_CTL0_ERRFG
#define AES256_NO_ERROR 0x00
//*****************************************************************************
@@ -98,7 +98,7 @@ extern "C"
// can be returned by the AES256_isBusy() function.
//
//*****************************************************************************
#define AES256_BUSY AESBUSY
#define AES256_BUSY AES256_STAT_BUSY
#define AES256_NOT_BUSY 0x00
//*****************************************************************************
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.c
+58 -57
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -43,37 +43,37 @@ static uint16_t __getRegisterSettingForInput(uint32_t input)
switch (input)
{
case COMP_E_INPUT0:
return CEIPSEL_0;
return COMP_E_CTL0_IPSEL_0;
case COMP_E_INPUT1:
return CEIPSEL_1;
return COMP_E_CTL0_IPSEL_1;
case COMP_E_INPUT2:
return CEIPSEL_2;
return COMP_E_CTL0_IPSEL_2;
case COMP_E_INPUT3:
return CEIPSEL_3;
return COMP_E_CTL0_IPSEL_3;
case COMP_E_INPUT4:
return CEIPSEL_4;
return COMP_E_CTL0_IPSEL_4;
case COMP_E_INPUT5:
return CEIPSEL_5;
return COMP_E_CTL0_IPSEL_5;
case COMP_E_INPUT6:
return CEIPSEL_6;
return COMP_E_CTL0_IPSEL_6;
case COMP_E_INPUT7:
return CEIPSEL_7;
return COMP_E_CTL0_IPSEL_7;
case COMP_E_INPUT8:
return CEIPSEL_8;
return COMP_E_CTL0_IPSEL_8;
case COMP_E_INPUT9:
return CEIPSEL_9;
return COMP_E_CTL0_IPSEL_9;
case COMP_E_INPUT10:
return CEIPSEL_10;
return COMP_E_CTL0_IPSEL_10;
case COMP_E_INPUT11:
return CEIPSEL_11;
return COMP_E_CTL0_IPSEL_11;
case COMP_E_INPUT12:
return CEIPSEL_12;
return COMP_E_CTL0_IPSEL_12;
case COMP_E_INPUT13:
return CEIPSEL_13;
return COMP_E_CTL0_IPSEL_13;
case COMP_E_INPUT14:
return CEIPSEL_14;
return COMP_E_CTL0_IPSEL_14;
case COMP_E_INPUT15:
return CEIPSEL_15;
return COMP_E_CTL0_IPSEL_15;
case COMP_E_VREF:
return COMP_E_VREF;
default:
@@ -98,40 +98,41 @@ bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config)
<= COMP_E_FILTEROUTPUT_DLYLVL4);
/* Reset COMPE Control 1 & Interrupt Registers for initialization */
COMP_E_CMSIS(comparator)->rCTL0.r = 0;
COMP_E_CMSIS(comparator)->rINT.r = 0;
COMP_E_CMSIS(comparator)->CTL0 = 0;
COMP_E_CMSIS(comparator)->INT = 0;
// Set the Positive Terminal
if (COMP_E_VREF != positiveTerminalInput)
{
// Enable Positive Terminal Input Mux and Set to the appropriate input
COMP_E_CMSIS(comparator)->rCTL0.r |= CEIPEN + positiveTerminalInput;
COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IPEN
+ positiveTerminalInput;
// Disable the input buffer
COMP_E_CMSIS(comparator)->rCTL3.r |= (1 << positiveTerminalInput);
COMP_E_CMSIS(comparator)->CTL3 |= (1 << positiveTerminalInput);
} else
{
// Reset and Set COMPE Control 2 Register
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r,CERSEL_OFS) = 0;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2,COMP_E_CTL2_RSEL_OFS) = 0;
}
// Set the Negative Terminal
if (COMP_E_VREF != negativeTerminalInput)
{
// Enable Negative Terminal Input Mux and Set to the appropriate input
COMP_E_CMSIS(comparator)->rCTL0.r |= CEIMEN
COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IMEN
+ (negativeTerminalInput << 8);
// Disable the input buffer
COMP_E_CMSIS(comparator)->rCTL3.r |= (1 << negativeTerminalInput);
COMP_E_CMSIS(comparator)->CTL3 |= (1 << negativeTerminalInput);
} else
{
// Reset and Set COMPE Control 2 Register
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CERSEL_OFS) = 1;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_RSEL_OFS) = 1;
}
// Reset and Set COMPE Control 1 Register
COMP_E_CMSIS(comparator)->rCTL1.r = config->powerMode
COMP_E_CMSIS(comparator)->CTL1 = config->powerMode
+ config->outputFilterEnableAndDelayLevel
+ config->invertedOutputPolarity;
@@ -149,23 +150,23 @@ void COMP_E_setReferenceVoltage(uint32_t comparator,
upperLimitSupplyVoltageFractionOf32
>= lowerLimitSupplyVoltageFractionOf32);
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEMRVS_OFS) = 0;
COMP_E_CMSIS(comparator)->rCTL2.r &= CERSEL;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_MRVS_OFS) = 0;
COMP_E_CMSIS(comparator)->CTL2 &= COMP_E_CTL2_RSEL;
// Set Voltage Source(Vcc | Vref, resistor ladder or not)
if (COMP_E_REFERENCE_AMPLIFIER_DISABLED == supplyVoltageReferenceBase)
{
COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_1;
COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_1;
} else if (lowerLimitSupplyVoltageFractionOf32 == 32)
{
COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_3;
COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_3;
} else
{
COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_2;
COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_2;
}
// Set COMPE Control 2 Register
COMP_E_CMSIS(comparator)->rCTL2.r |= supplyVoltageReferenceBase
COMP_E_CMSIS(comparator)->CTL2 |= supplyVoltageReferenceBase
+ ((upperLimitSupplyVoltageFractionOf32 - 1) << 8)
+ (lowerLimitSupplyVoltageFractionOf32 - 1);
}
@@ -178,87 +179,87 @@ void COMP_E_setReferenceAccuracy(uint32_t comparator,
|| (referenceAccuracy == COMP_E_ACCURACY_CLOCKED));
if (referenceAccuracy)
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CEREFACC_OFS) = 1;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_REFACC_OFS) = 1;
else
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CEREFACC_OFS) = 0;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_REFACC_OFS) = 0;
}
void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode)
{
COMP_E_CMSIS(comparator)->rCTL1.r = (COMP_E_CMSIS(comparator)->rCTL1.r
& ~(CEPWRMD_M)) | powerMode;
COMP_E_CMSIS(comparator)->CTL1 = (COMP_E_CMSIS(comparator)->CTL1
& ~(COMP_E_CTL1_PWRMD_MASK)) | powerMode;
}
void COMP_E_enableModule(uint32_t comparator)
{
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEON_OFS) = 1;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_ON_OFS) = 1;
}
void COMP_E_disableModule(uint32_t comparator)
{
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEON_OFS) = 0;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_ON_OFS) = 0;
}
void COMP_E_shortInputs(uint32_t comparator)
{
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CESHORT_OFS) = 1;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_SHORT_OFS) = 1;
}
void COMP_E_unshortInputs(uint32_t comparator)
{
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CESHORT_OFS) = 0;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_SHORT_OFS) = 0;
}
void COMP_E_disableInputBuffer(uint32_t comparator, uint_fast16_t inputPort)
{
ASSERT(inputPort <= COMP_E_INPUT15);
COMP_E_CMSIS(comparator)->rCTL3.r |= (inputPort);
COMP_E_CMSIS(comparator)->CTL3 |= (inputPort);
}
void COMP_E_enableInputBuffer(uint32_t comparator, uint_fast16_t inputPort)
{
ASSERT(inputPort <= COMP_E_INPUT15);
COMP_E_CMSIS(comparator)->rCTL3.r &= ~(inputPort);
COMP_E_CMSIS(comparator)->CTL3 &= ~(inputPort);
}
void COMP_E_swapIO(uint32_t comparator)
{
COMP_E_CMSIS(comparator)->rCTL1.r ^= CEEX; // Toggle CEEX bit
COMP_E_CMSIS(comparator)->CTL1 ^= COMP_E_CTL1_EX; // Toggle CEEX bit
}
uint8_t COMP_E_outputValue(uint32_t comparator)
{
return COMP_E_CMSIS(comparator)->rCTL1.r & CEOUT;
return COMP_E_CMSIS(comparator)->CTL1 & COMP_E_CTL1_OUT;
}
void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask)
{
// Set the Interrupt enable bit
COMP_E_CMSIS(comparator)->rINT.r |= mask;
COMP_E_CMSIS(comparator)->INT |= mask;
}
uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator)
{
return COMP_E_getInterruptStatus(comparator) &
COMP_E_CMSIS(comparator)->rINT.r;
COMP_E_CMSIS(comparator)->INT;
}
void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask)
{
COMP_E_CMSIS(comparator)->rINT.r &= ~(mask);
COMP_E_CMSIS(comparator)->INT &= ~(mask);
}
void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask)
{
COMP_E_CMSIS(comparator)->rINT.r &= ~(mask);
COMP_E_CMSIS(comparator)->INT &= ~(mask);
}
uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator)
{
return (COMP_E_CMSIS(comparator)->rINT.r & (COMP_E_OUTPUT_INTERRUPT_FLAG |
return (COMP_E_CMSIS(comparator)->INT & (COMP_E_OUTPUT_INTERRUPT_FLAG |
COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY |
COMP_E_INTERRUPT_FLAG_READY));
}
@@ -270,25 +271,25 @@ void COMP_E_setInterruptEdgeDirection(uint32_t comparator,
// Set the edge direction that will trigger an interrupt
if (COMP_E_RISINGEDGE == edgeDirection)
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEIES_OFS) = 1;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 1;
else if (COMP_E_FALLINGEDGE == edgeDirection)
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEIES_OFS) = 0;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 0;
}
void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator)
{
COMP_E_CMSIS(comparator)->rCTL1.r ^= CEIES;
COMP_E_CMSIS(comparator)->CTL1 ^= COMP_E_CTL1_IES;
}
void COMP_E_registerInterrupt(uint32_t comparator, void (*intHandler)(void))
{
switch (comparator)
{
case COMP_E0_MODULE:
case COMP_E0_BASE:
Interrupt_registerInterrupt(INT_COMP_E0, intHandler);
Interrupt_enableInterrupt(INT_COMP_E0);
break;
case COMP_E1_MODULE:
case COMP_E1_BASE:
Interrupt_registerInterrupt(INT_COMP_E1, intHandler);
Interrupt_enableInterrupt(INT_COMP_E1);
break;
@@ -301,11 +302,11 @@ void COMP_E_unregisterInterrupt(uint32_t comparator)
{
switch (comparator)
{
case COMP_E0_MODULE:
case COMP_E0_BASE:
Interrupt_disableInterrupt(INT_COMP_E0);
Interrupt_unregisterInterrupt(INT_COMP_E0);
break;
case COMP_E1_MODULE:
case COMP_E1_BASE:
Interrupt_disableInterrupt(INT_COMP_E1);
Interrupt_unregisterInterrupt(INT_COMP_E1);
break;
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.h
+69 -69
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -60,13 +60,13 @@ extern "C"
#include <msp.h>
/* Module defines for Comp */
#define COMP_E_CMSIS(x) ((COMP_E0_Type *) x)
#define COMP_E_CMSIS(x) ((COMP_E_Type *) x)
#define COMP_E_FILTEROUTPUT_OFF 0x00
#define COMP_E_FILTEROUTPUT_DLYLVL1 (CEF + CEFDLY_0)
#define COMP_E_FILTEROUTPUT_DLYLVL2 (CEF + CEFDLY_1)
#define COMP_E_FILTEROUTPUT_DLYLVL3 (CEF + CEFDLY_2)
#define COMP_E_FILTEROUTPUT_DLYLVL4 (CEF + CEFDLY_3)
#define COMP_E_FILTEROUTPUT_DLYLVL1 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_0)
#define COMP_E_FILTEROUTPUT_DLYLVL2 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_1)
#define COMP_E_FILTEROUTPUT_DLYLVL3 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_2)
#define COMP_E_FILTEROUTPUT_DLYLVL4 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_3)
#define COMP_E_INPUT0 (0x01)
#define COMP_E_INPUT1 (0x02)
@@ -86,38 +86,38 @@ extern "C"
#define COMP_E_INPUT15 (0x8000)
#define COMP_E_VREF (0x9F)
#define COMP_E_NORMALOUTPUTPOLARITY (!(CEOUTPOL))
#define COMP_E_INVERTEDOUTPUTPOLARITY (CEOUTPOL)
#define COMP_E_NORMALOUTPUTPOLARITY (!(COMP_E_CTL1_OUTPOL))
#define COMP_E_INVERTEDOUTPUTPOLARITY (COMP_E_CTL1_OUTPOL)
#define COMP_E_REFERENCE_AMPLIFIER_DISABLED (CEREFL_0)
#define COMP_E_VREFBASE1_2V (CEREFL_1)
#define COMP_E_VREFBASE2_0V (CEREFL_2)
#define COMP_E_VREFBASE2_5V (CEREFL_3)
#define COMP_E_REFERENCE_AMPLIFIER_DISABLED (COMP_E_CTL2_CEREFL_0)
#define COMP_E_VREFBASE1_2V (COMP_E_CTL2_CEREFL_1)
#define COMP_E_VREFBASE2_0V (COMP_E_CTL2_CEREFL_2)
#define COMP_E_VREFBASE2_5V (COMP_E_CTL2_CEREFL_3)
#define COMP_E_ACCURACY_STATIC (!CEREFACC)
#define COMP_E_ACCURACY_CLOCKED (CEREFACC)
#define COMP_E_ACCURACY_STATIC (!COMP_E_CTL2_REFACC)
#define COMP_E_ACCURACY_CLOCKED (COMP_E_CTL2_REFACC)
#define COMP_E_HIGH_SPEED_MODE (CEPWRMD_0)
#define COMP_E_NORMAL_MODE (CEPWRMD_1)
#define COMP_E_ULTRA_LOW_POWER_MODE (CEPWRMD_2)
#define COMP_E_HIGH_SPEED_MODE (COMP_E_CTL1_PWRMD_0)
#define COMP_E_NORMAL_MODE (COMP_E_CTL1_PWRMD_1)
#define COMP_E_ULTRA_LOW_POWER_MODE (COMP_E_CTL1_PWRMD_2)
#define COMP_E_OUTPUT_INTERRUPT (CEIE)
#define COMP_E_INVERTED_POLARITY_INTERRUPT (CEIIE)
#define COMP_E_READY_INTERRUPT (CERDYIE)
#define COMP_E_OUTPUT_INTERRUPT (COMP_E_INT_IE)
#define COMP_E_INVERTED_POLARITY_INTERRUPT (COMP_E_INT_IIE)
#define COMP_E_READY_INTERRUPT (COMP_E_INT_RDYIE)
#define COMP_E_OUTPUT_INTERRUPT_FLAG (CEIFG)
#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY (CEIIFG)
#define COMP_E_INTERRUPT_FLAG_READY (CERDYIFG)
#define COMP_E_OUTPUT_INTERRUPT_FLAG (COMP_E_INT_IFG)
#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY (COMP_E_INT_IIFG)
#define COMP_E_INTERRUPT_FLAG_READY (COMP_E_INT_RDYIFG)
#define COMP_E_FALLINGEDGE (!(CEIES))
#define COMP_E_RISINGEDGE (CEIES)
#define COMP_E_FALLINGEDGE (!(COMP_E_CTL1_IES))
#define COMP_E_RISINGEDGE (COMP_E_CTL1_IES)
#define COMP_E_LOW (0x0)
#define COMP_E_HIGH (CEOUT)
#define COMP_E_LOW (0x0)
#define COMP_E_HIGH (COMP_E_CTL1_OUT)
//*****************************************************************************
//
//! \typedef COMP_E_Config
//! ypedef COMP_E_Config
//! \brief Type definition for \link _COMP_E_Config \endlink structure
//!
//! \struct _COMP_E_Config
@@ -140,8 +140,8 @@ typedef struct _COMP_E_Config
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param config Configuration structure for the Comparator module
//!
//! <hr>
@@ -230,8 +230,8 @@ extern bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param supplyVoltageReferenceBase decides the source and max amount of
//! Voltage that can be used as a reference.
//! Valid values are
@@ -267,8 +267,8 @@ extern void COMP_E_setReferenceVoltage(uint32_t comparator,
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param referenceAccuracy is the reference accuracy setting of the
//! comparator. Clocked is for low power/low accuracy.
//! Valid values are
@@ -291,8 +291,8 @@ extern void COMP_E_setReferenceAccuracy(uint32_t comparator,
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param powerMode decides the power mode
//! Valid values are
//! - \b COMP_E_HIGH_SPEED_MODE
@@ -311,8 +311,8 @@ extern void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function sets the bit that enables the operation of the
//! Comparator module.
@@ -328,8 +328,8 @@ extern void COMP_E_enableModule(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function clears the CEON bit disabling the operation of the Comparator
//! module, saving from excess power consumption.
@@ -346,8 +346,8 @@ extern void COMP_E_disableModule(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function sets the bit that shorts the devices attached to the input
//! pins chosen from the initialization of the comparator.
@@ -364,8 +364,8 @@ extern void COMP_E_shortInputs(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function clears the bit that shorts the devices attached to the input
//! pins chosen from the initialization of the comparator.
@@ -383,8 +383,8 @@ extern void COMP_E_unshortInputs(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param inputPort is the port in which the input buffer will be disabled.
//! Valid values are a logical OR of the following:
//! - \b COMP_E_INPUT0 [Default]
@@ -425,8 +425,8 @@ extern void COMP_E_disableInputBuffer(uint32_t comparator,
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param inputPort is the port in which the input buffer will be enabled.
//! Valid values are a logical OR of the following:
//! - \b COMP_E_INPUT0 [Default]
@@ -484,8 +484,8 @@ extern void COMP_E_swapIO(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid parameters
//! vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! Returns the output value of the Comparator module.
//!
@@ -501,8 +501,8 @@ extern uint8_t COMP_E_outputValue(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param mask is the bit mask of the interrupt sources to be enabled.
//! Mask value is the logical OR of any of the following
//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt
@@ -527,8 +527,8 @@ extern void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param mask is the bit mask of the interrupt sources to be disabled.
//! Mask value is the logical OR of any of the following
//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt
@@ -551,8 +551,8 @@ extern void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param mask is a bit mask of the interrupt sources to be cleared.
//! Mask value is the logical OR of any of the following
//! - \b COMP_E_INTERRUPT_FLAG - Output interrupt flag
@@ -575,8 +575,8 @@ extern void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This returns the interrupt status for the Comparator module based on which
//! flag is passed.
@@ -595,8 +595,8 @@ extern uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! Enables the indicated Comparator interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
@@ -615,8 +615,8 @@ extern uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param edgeDirection determines which direction the edge would have to go
//! to generate an interrupt based on the non-inverted interrupt flag.
//! Valid values are
@@ -646,8 +646,8 @@ extern void COMP_E_setInterruptEdgeDirection(uint32_t comparator,
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function will toggle which direction the output will have to go,
//! whether rising or falling, to generate an interrupt based on a non-inverted
@@ -670,8 +670,8 @@ extern void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function registers the handler to be called when a Comparator
//! interrupt occurs. This function enables the global interrupt in the
@@ -691,8 +691,8 @@ extern void COMP_E_registerInterrupt(uint32_t comparator,
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function unregisters the handler to be called when Comparator E
//! interrupt occurs. This function also masks off the interrupt in the
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.c
+26 -26
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -44,7 +44,7 @@
// on entry.
//
//*****************************************************************************
#if defined(gcc)
#if defined(__GNUC__)
uint32_t __attribute__((naked)) CPU_cpsid(void)
{
uint32_t ret;
@@ -66,7 +66,7 @@ uint32_t __attribute__((naked)) CPU_cpsid(void)
return(ret);
}
#endif
#if defined(ewarm)
#if defined(__ICCARM__)
uint32_t CPU_cpsid(void)
{
//
@@ -84,7 +84,7 @@ uint32_t CPU_cpsid(void)
}
#pragma diag_default=Pe940
#endif
#if defined(keil)
#if defined(__CC_ARM)
__asm uint32_t CPU_cpsid(void)
{
//
@@ -95,7 +95,7 @@ __asm uint32_t CPU_cpsid(void)
bx lr
}
#endif
#if defined(ccs)
#if defined(__TI_ARM__)
uint32_t CPU_cpsid(void)
{
//
@@ -122,7 +122,7 @@ uint32_t CPU_cpsid(void)
// interrupts are enabled or disabled).
//
//*****************************************************************************
#if defined(gcc)
#if defined(__GNUC__)
uint32_t __attribute__((naked)) CPU_primask(void)
{
uint32_t ret;
@@ -143,7 +143,7 @@ uint32_t __attribute__((naked)) CPU_primask(void)
return(ret);
}
#endif
#if defined(ewarm)
#if defined(__ICCARM__)
uint32_t CPU_primask(void)
{
//
@@ -160,7 +160,7 @@ uint32_t CPU_primask(void)
}
#pragma diag_default=Pe940
#endif
#if defined(keil)
#if defined(__CC_ARM)
__asm uint32_t CPU_primask(void)
{
//
@@ -170,7 +170,7 @@ __asm uint32_t CPU_primask(void)
bx lr
}
#endif
#if defined(ccs)
#if defined(__TI_ARM__)
uint32_t CPU_primask(void)
{
//
@@ -196,7 +196,7 @@ uint32_t CPU_primask(void)
// on entry.
//
//*****************************************************************************
#if defined(gcc)
#if defined(__GNUC__)
uint32_t __attribute__((naked)) CPU_cpsie(void)
{
uint32_t ret;
@@ -218,7 +218,7 @@ uint32_t __attribute__((naked)) CPU_cpsie(void)
return(ret);
}
#endif
#if defined(ewarm)
#if defined(__ICCARM__)
uint32_t CPU_cpsie(void)
{
//
@@ -236,7 +236,7 @@ uint32_t CPU_cpsie(void)
}
#pragma diag_default=Pe940
#endif
#if defined(keil)
#if defined(__CC_ARM)
__asm uint32_t CPU_cpsie(void)
{
//
@@ -247,7 +247,7 @@ __asm uint32_t CPU_cpsie(void)
bx lr
}
#endif
#if defined(ccs)
#if defined(__TI_ARM__)
uint32_t CPU_cpsie(void)
{
//
@@ -273,7 +273,7 @@ uint32_t CPU_cpsie(void)
// Wrapper function for the CPUWFI instruction.
//
//*****************************************************************************
#if defined(gcc)
#if defined(__GNUC__)
void __attribute__((naked)) CPU_wfi(void)
{
//
@@ -283,7 +283,7 @@ void __attribute__((naked)) CPU_wfi(void)
" bx lr\n");
}
#endif
#if defined(ewarm)
#if defined(__ICCARM__)
void CPU_wfi(void)
{
//
@@ -292,7 +292,7 @@ void CPU_wfi(void)
__asm(" wfi\n");
}
#endif
#if defined(keil)
#if defined(__CC_ARM)
__asm void CPU_wfi(void)
{
//
@@ -302,7 +302,7 @@ __asm void CPU_wfi(void)
bx lr
}
#endif
#if defined(ccs)
#if defined(__TI_ARM__)
void CPU_wfi(void)
{
//
@@ -317,7 +317,7 @@ void CPU_wfi(void)
// Wrapper function for writing the BASEPRI register.
//
//*****************************************************************************
#if defined(gcc)
#if defined(__GNUC__)
void __attribute__((naked)) CPU_basepriSet(uint32_t newBasepri)
{
//
@@ -327,7 +327,7 @@ void __attribute__((naked)) CPU_basepriSet(uint32_t newBasepri)
" bx lr\n");
}
#endif
#if defined(ewarm)
#if defined(__ICCARM__)
void CPU_basepriSet(uint32_t newBasepri)
{
//
@@ -336,7 +336,7 @@ void CPU_basepriSet(uint32_t newBasepri)
__asm(" msr BASEPRI, r0\n");
}
#endif
#if defined(keil)
#if defined(__CC_ARM)
__asm void CPU_basepriSet(uint32_t newBasepri)
{
//
@@ -346,7 +346,7 @@ __asm void CPU_basepriSet(uint32_t newBasepri)
bx lr
}
#endif
#if defined(ccs)
#if defined(__TI_ARM__)
void CPU_basepriSet(uint32_t newBasepri)
{
//
@@ -361,7 +361,7 @@ void CPU_basepriSet(uint32_t newBasepri)
// Wrapper function for reading the BASEPRI register.
//
//*****************************************************************************
#if defined(gcc)
#if defined(__GNUC__)
uint32_t __attribute__((naked)) CPU_basepriGet(void)
{
uint32_t ret;
@@ -382,7 +382,7 @@ uint32_t __attribute__((naked)) CPU_basepriGet(void)
return(ret);
}
#endif
#if defined(ewarm)
#if defined(__ICCARM__)
uint32_t CPU_basepriGet(void)
{
//
@@ -399,7 +399,7 @@ uint32_t CPU_basepriGet(void)
}
#pragma diag_default=Pe940
#endif
#if defined(keil)
#if defined(__CC_ARM)
__asm uint32_t CPU_basepriGet(void)
{
//
@@ -409,7 +409,7 @@ __asm uint32_t CPU_basepriGet(void)
bx lr
}
#endif
#if defined(ccs)
#if defined(__TI_ARM__)
uint32_t CPU_basepriGet(void)
{
//
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.h
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.c
+30 -27
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -37,17 +37,18 @@
#include "crc32.h"
#include <msp.h>
#include <debug.h>
#include <hw_memmap.h>
void CRC32_setSeed(uint32_t seed, uint_fast8_t crcType)
{
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
CRC32->rCRC16INIRES = seed;
CRC32->INIRES16 = seed;
else
{
CRC32->rCRC32INIRES_HI = ((seed & 0xFFFF0000) >> 16);
CRC32->rCRC32INIRES_LO = (seed & 0xFFFF);
CRC32->INIRES32_HI = ((seed & 0xFFFF0000) >> 16);
CRC32->INIRES32_LO = (seed & 0xFFFF);
}
}
@@ -56,9 +57,9 @@ void CRC32_set8BitData(uint8_t dataIn, uint_fast8_t crcType)
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
HWREG8(CRC32_BASE + OFS_CRC16DI) = dataIn;
HWREG8(&(CRC32->DI16)) = dataIn;
else
HWREG8(CRC32_BASE + OFS_CRC32DI) = dataIn;
HWREG8(&(CRC32->DI32)) = dataIn;
}
void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType)
@@ -66,18 +67,18 @@ void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType)
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
CRC32->rCRC16DI = dataIn;
CRC32->DI16 = dataIn;
else
CRC32->rCRC32DI = dataIn;
CRC32->DI32 = dataIn;
}
void CRC32_set32BitData(uint32_t dataIn)
{
//CRC32->rCRC32DI = dataIn & 0xFFFF;
//CRC32->rCRC32DI = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
//CRC32->DI32 = dataIn & 0xFFFF;
//CRC32->DI32 = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
HWREG16(CRC32_BASE + OFS_CRC32DI) = dataIn & 0xFFFF;
HWREG16(CRC32_BASE + OFS_CRC32DI) = (uint16_t)(
HWREG16(&(CRC32->DI32)) = dataIn & 0xFFFF;
HWREG16(&(CRC32->DI32)) = (uint16_t)(
(dataIn & 0xFFFF0000) >> 16);
}
@@ -86,9 +87,9 @@ void CRC32_set8BitDataReversed(uint8_t dataIn, uint_fast8_t crcType)
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
HWREG8(CRC32_BASE + OFS_CRC16DIRB) = dataIn;
HWREG8(&(CRC32->DIRB16)) = dataIn;
else
HWREG8(CRC32_BASE + OFS_CRC32DIRB) = dataIn;
HWREG8(&(CRC32->DIRB32)) = dataIn;
}
void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType)
@@ -96,18 +97,20 @@ void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType)
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
CRC32->rCRC16DIRB = dataIn;
CRC32->DIRB16 = dataIn;
else
CRC32->rCRC32DIRB = dataIn;
CRC32->DIRB32 = dataIn;
}
void CRC32_set32BitDataReversed(uint32_t dataIn)
{
HWREG16(CRC32_BASE + OFS_CRC32DIRB) = dataIn & 0xFFFF;
HWREG16(CRC32_BASE + OFS_CRC32DIRB) = (uint16_t)(
//CRC32->DIRB32 = dataIn & 0xFFFF;
//CRC32->DIRB32 = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
HWREG16(&(CRC32->DIRB32)) = dataIn & 0xFFFF;
HWREG16(&(CRC32->DIRB32)) = (uint16_t)(
(dataIn & 0xFFFF0000) >> 16);
//CRC32->rCRC32DIRB = dataIn & 0xFFFF;
//CRC32->rCRC32DIRB = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
}
uint32_t CRC32_getResult(uint_fast8_t crcType)
@@ -116,12 +119,12 @@ uint32_t CRC32_getResult(uint_fast8_t crcType)
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
return CRC32->rCRC16INIRES;
return CRC32->INIRES16;
else
{
result = CRC32->rCRC32INIRES_HI;
result = CRC32->INIRES32_HI;
result = (result << 16);
result |= CRC32->rCRC32INIRES_LO;
result |= CRC32->INIRES32_LO;
return (result);
}
}
@@ -132,12 +135,12 @@ uint32_t CRC32_getResultReversed(uint_fast8_t crcType)
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
return CRC32->rCRC16RESR;
return CRC32->RESR16;
else
{
result = CRC32->rCRC32RESR_HI;
result = CRC32->RESR32_HI;
result = (result << 16);
result |= CRC32->rCRC32RESR_LO;
result |= CRC32->RESR32_LO;
return (result);
}
}
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.h
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.c
+289 -210
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.h
+77 -93
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -64,21 +64,21 @@ extern "C"
// Control specific variables
//
//*****************************************************************************
#define CS_CLOCK_DIVIDER_1 DIVS_0
#define CS_CLOCK_DIVIDER_2 DIVS_1
#define CS_CLOCK_DIVIDER_4 DIVS_2
#define CS_CLOCK_DIVIDER_8 DIVS_3
#define CS_CLOCK_DIVIDER_16 DIVS_4
#define CS_CLOCK_DIVIDER_32 DIVS_5
#define CS_CLOCK_DIVIDER_64 DIVS_6
#define CS_CLOCK_DIVIDER_128 DIVS_7
#define CS_CLOCK_DIVIDER_1 CS_CTL1_DIVS_0
#define CS_CLOCK_DIVIDER_2 CS_CTL1_DIVS_1
#define CS_CLOCK_DIVIDER_4 CS_CTL1_DIVS_2
#define CS_CLOCK_DIVIDER_8 CS_CTL1_DIVS_3
#define CS_CLOCK_DIVIDER_16 CS_CTL1_DIVS_4
#define CS_CLOCK_DIVIDER_32 CS_CTL1_DIVS_5
#define CS_CLOCK_DIVIDER_64 CS_CTL1_DIVS_6
#define CS_CLOCK_DIVIDER_128 CS_CTL1_DIVS_7
#define CS_LFXTCLK_SELECT SELM_0
#define CS_HFXTCLK_SELECT SELM_5
#define CS_VLOCLK_SELECT SELM_1
#define CS_REFOCLK_SELECT SELM_2
#define CS_DCOCLK_SELECT SELM_3
#define CS_MODOSC_SELECT SELM_4
#define CS_LFXTCLK_SELECT CS_CTL1_SELM_0
#define CS_HFXTCLK_SELECT CS_CTL1_SELM_5
#define CS_VLOCLK_SELECT CS_CTL1_SELM_1
#define CS_REFOCLK_SELECT CS_CTL1_SELM_2
#define CS_DCOCLK_SELECT CS_CTL1_SELM_3
#define CS_MODOSC_SELECT CS_CTL1_SELM_4
#define CS_KEY 0x695A
@@ -103,33 +103,29 @@ extern "C"
#define CS_MODCLK_FREQUENCY 24000000
/* Interrupts */
#define CS_LFXT_FAULT LFXTIE
#define CS_HFXT_FAULT HFXTIE
#define CS_DCOMIN_FAULT DCOMINIE
#define CS_DCOMAX_FAULT DCOMAXIE
#define CS_DCORESISTOR_FAULT DCORIE
#define CS_STARTCOUNT_LFXT_FAULT FCNTLFIE
#define CS_STARTCOUNT_HFXT_FAULT FCNTHFIE
#define CS_PLL_OUTOFLOCK PLLOOLIE
#define CS_PLL_OUTOFSIGNAL PLLLOSIE
#define CS_PLL_OUTOFRANGE PLLOORIE
#define CS_REFCNT_PERIOD_COUNTER CALIE
#define CS_LFXT_FAULT CS_IE_LFXTIE
#define CS_HFXT_FAULT CS_IE_HFXTIE
#define CS_DCO_OPEN_FAULT CS_IE_DCOR_OPNIE
#define CS_STARTCOUNT_LFXT_FAULT CS_IE_FCNTLFIE
#define CS_STARTCOUNT_HFXT_FAULT CS_IE_FCNTHFIE
#define CS_DCO_SHORT_FAULT CS_IFG_DCOR_SHTIFG
#define CS_HFXT_DRIVE0 CS_CTL2_HFXTDRIVE_0
#define CS_HFXT_DRIVE1 CS_CTL2_HFXTDRIVE_1
//#define CS_HFXT_DRIVE0 CS_CTL2_HFXTDRIVE_0
//#define CS_HFXT_DRIVE1 CS_CTL2_HFXTDRIVE_1
#define CS_HFXT_DRIVE CS_CTL2_HFXTDRIVE
#define CS_HFXT_BYPASS CS_CTL2_HFXTBYPASS
#define CS_LFXT_DRIVE0 LFXTDRIVE_0
#define CS_LFXT_DRIVE1 LFXTDRIVE_1
#define CS_LFXT_DRIVE2 LFXTDRIVE_2
#define CS_LFXT_DRIVE3 LFXTDRIVE_3
#define CS_LFXT_BYPASS LFXTBYPASS
#define CS_LFXT_DRIVE0 CS_CTL2_LFXTDRIVE_0
#define CS_LFXT_DRIVE1 CS_CTL2_LFXTDRIVE_1
#define CS_LFXT_DRIVE2 CS_CTL2_LFXTDRIVE_2
#define CS_LFXT_DRIVE3 CS_CTL2_LFXTDRIVE_3
#define CS_LFXT_BYPASS CS_CTL2_LFXTBYPASS
#define CS_ACLK ACLK_EN
#define CS_MCLK MCLK_EN
#define CS_SMCLK SMCLK_EN
#define CS_HSMCLK HSMCLK_EN
#define CS_BCLK BCLK_READY
#define CS_ACLK CS_CLKEN_ACLK_EN
#define CS_MCLK CS_CLKEN_MCLK_EN
#define CS_SMCLK CS_CLKEN_SMCLK_EN
#define CS_HSMCLK CS_CLKEN_HSMCLK_EN
#define CS_BCLK CS_STAT_BCLK_READY
#define CS_LFXTCLK 0x01
@@ -146,20 +142,25 @@ extern "C"
#define CS_40MHZ 40000000
#define CS_48MHZ 48000000
#define CS_DCO_FREQUENCY_1_5 DCORSEL_0
#define CS_DCO_FREQUENCY_3 DCORSEL_1
#define CS_DCO_FREQUENCY_6 DCORSEL_2
#define CS_DCO_FREQUENCY_12 DCORSEL_3
#define CS_DCO_FREQUENCY_24 DCORSEL_4
#define CS_DCO_FREQUENCY_48 DCORSEL_5
#define CS_DCO_FREQUENCY_1_5 CS_CTL0_DCORSEL_0
#define CS_DCO_FREQUENCY_3 CS_CTL0_DCORSEL_1
#define CS_DCO_FREQUENCY_6 CS_CTL0_DCORSEL_2
#define CS_DCO_FREQUENCY_12 CS_CTL0_DCORSEL_3
#define CS_DCO_FREQUENCY_24 CS_CTL0_DCORSEL_4
#define CS_DCO_FREQUENCY_48 CS_CTL0_DCORSEL_5
#define CS_HFXT_FAULT_COUNTER 0x01
#define CS_LFXT_FAULT_COUNTER 0x02
#define CS_FAULT_COUNTER_4096_CYCLES FCNTLF_0
#define CS_FAULT_COUNTER_8192_CYCLES FCNTLF_1
#define CS_FAULT_COUNTER_16384_CYCLES FCNTLF_2
#define CS_FAULT_COUNTER_32768_CYCLES FCNTLF_3
#define CS_FAULT_COUNTER_4096_CYCLES CS_CTL3_FCNTLF_0
#define CS_FAULT_COUNTER_8192_CYCLES CS_CTL3_FCNTLF_1
#define CS_FAULT_COUNTER_16384_CYCLES CS_CTL3_FCNTLF_2
#define CS_FAULT_COUNTER_32768_CYCLES CS_CTL3_FCNTLF_3
#define CS_OVER32MHZ 0x01
#define CS_UNDER32MHZ 0x02
#define DEVICE_PG1_1 0x42
//******************************************************************************
//
@@ -188,7 +189,11 @@ extern void CS_setExternalClockSourceFrequency(uint32_t lfxt_XT_CLK_frequency,
//!
//! Note that this function is blocking and will wait on the appropriate bit
//! to be set in the CSSTAT READY register to be set before setting the clock
//! source
//! source.
//!
//! Also note that when HSMCLK and SMCLK share the same clock signal. If you
//! change the clock signal for HSMCLK, the clock signal for SMCLK will change
//! also (and vice-versa).
//!
//! HFXTCLK is not available for BCLK or ACLK.
//!
@@ -235,11 +240,10 @@ extern void CS_initClockSignal(uint32_t selectedClockSignal,
//! \param bypassMode When this variable is set, the oscillator will start
//! in bypass mode and the signal can be generated by a digital square wave.
//!
//!
//! \return NONE
//! \return true if started correctly, false otherwise
//
//******************************************************************************
extern void CS_startHFXT(bool bypassMode);
extern bool CS_startHFXT(bool bypassMode);
//******************************************************************************
//
@@ -257,10 +261,10 @@ extern void CS_startHFXT(bool bypassMode);
//! \param timeout is the count value that gets decremented every time the loop
//! that clears oscillator fault flags gets executed.
//!
//! \return NONE
//! \return true if started correctly, false otherwise
//
//******************************************************************************
extern void CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout);
extern bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout);
//******************************************************************************
//
@@ -283,11 +287,10 @@ extern void CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout);
//! \note When CS_LFXT_BYPASS is passed as a parameter the oscillator will start
//! in bypass mode and the signal can be generated by a digital square wave.
//!
//!
//! \return NONE
//! \return true if started correctly, false otherwise
//
//******************************************************************************
extern void CS_startLFXT(uint32_t xtDrive);
extern bool CS_startLFXT(uint32_t xtDrive);
//******************************************************************************
//
@@ -315,10 +318,10 @@ extern void CS_startLFXT(uint32_t xtDrive);
//! \param timeout is the count value that gets decremented every time the loop
//! that clears oscillator fault flags gets executed.
//!
//! \return NONE
//! \return true if started correctly, false otherwise
//
//******************************************************************************
extern void CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout);
extern bool CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout);
//******************************************************************************
//
@@ -524,12 +527,17 @@ extern void CS_disableDCOExternalResistor(void);
//! default, the value in the CS module is populated by the calibration
//! data of the suggested external resistor (see device datasheet).
//!
//! \param uiCalData is the calibration data constant for the external resistor.
//! \param calData is the calibration data constant for the external resistor.
//!
//! \param freqRange is the range of the DCO to set the external calibration
//! for. Frequencies above 32MHZ have a different calibration value
//! than frequencies below 32MHZ.
//!
//! \return None
//
//******************************************************************************
extern void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData);
extern void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData,
uint_fast8_t freqRange);
//******************************************************************************
//
@@ -647,13 +655,9 @@ extern void CS_startFaultCounter(uint_fast8_t counterSelect,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! This function enables the indicated clock system interrupt sources. Only
//! the sources that are enabled can be reflected to the processor interrupt;
@@ -678,13 +682,9 @@ extern void CS_enableInterrupt(uint32_t flags);
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
@@ -704,15 +704,10 @@ extern void CS_disableInterrupt(uint32_t flags);
//! \return The current interrupt status, enumerated as a bit field of
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_DCO_SHORT_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
@@ -728,15 +723,10 @@ extern uint32_t CS_getEnabledInterruptStatus(void);
//! \return The current interrupt status, enumerated as a bit field of:
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_DCO_SHORT_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
@@ -753,15 +743,9 @@ extern uint32_t CS_getInterruptStatus(void);
//! be a logical OR of:
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! The specified clock system interrupt sources are cleared, so that they no
//! longer assert. This function must be called in the interrupt handler to
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/debug.h
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.c
+60 -60
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,7 +45,7 @@ void DMA_enableModule(void)
//
// Set the master enable bit in the config register.
//
DMA->rCFG.r = DMA_CFG_;
DMA_Control->CFG = DMA_CFG_MASTEN;
}
void DMA_disableModule(void)
@@ -53,7 +53,7 @@ void DMA_disableModule(void)
//
// Clear the master enable bit in the config register.
//
DMA->rCFG.r = 0;
DMA_Control->CFG = 0;
}
uint32_t DMA_getErrorStatus(void)
@@ -61,7 +61,7 @@ uint32_t DMA_getErrorStatus(void)
//
// Return the DMA error status.
//
return DMA->rERRCLR.r;
return DMA_Control->ERRCLR;
}
void DMA_clearErrorStatus(void)
@@ -69,7 +69,7 @@ void DMA_clearErrorStatus(void)
//
// Clear the DMA error interrupt.
//
DMA->rERRCLR.r = 1;
DMA_Control->ERRCLR = 1;
}
void DMA_enableChannel(uint32_t channelNum)
@@ -82,7 +82,7 @@ void DMA_enableChannel(uint32_t channelNum)
//
// Set the bit for this channel in the enable set register.
//
DMA->rENASET = 1 << (channelNum & 0x0F);
DMA_Control->ENASET = 1 << (channelNum & 0x0F);
}
void DMA_disableChannel(uint32_t channelNum)
@@ -95,7 +95,7 @@ void DMA_disableChannel(uint32_t channelNum)
//
// Set the bit for this channel in the enable clear register.
//
DMA->rENACLR = 1 << (channelNum & 0x0F);
DMA_Control->ENACLR = 1 << (channelNum & 0x0F);
}
bool DMA_isChannelEnabled(uint32_t channelNum)
@@ -109,7 +109,7 @@ bool DMA_isChannelEnabled(uint32_t channelNum)
// AND the specified channel bit with the enable register and return the
// result.
//
return ((DMA->rENASET & (1 << (channelNum & 0x0F))) ? true : false);
return ((DMA_Control->ENASET & (1 << (channelNum & 0x0F))) ? true : false);
}
void DMA_setControlBase(void *controlTable)
@@ -123,7 +123,7 @@ void DMA_setControlBase(void *controlTable)
//
// Program the base address into the register.
//
DMA->rCTLBASE.r = (uint32_t) controlTable;
DMA_Control->CTLBASE = (uint32_t) controlTable;
}
void* DMA_getControlBase(void)
@@ -132,7 +132,7 @@ void* DMA_getControlBase(void)
// Read the current value of the control base register and return it to
// the caller.
//
return ((void *) DMA->rCTLBASE.r);
return ((void *) DMA_Control->CTLBASE);
}
void* DMA_getControlAlternateBase(void)
@@ -141,7 +141,7 @@ void* DMA_getControlAlternateBase(void)
// Read the current value of the control base register and return it to
// the caller.
//
return ((void *) DMA->rATLBASE);
return ((void *) DMA_Control->ATLBASE);
}
void DMA_requestChannel(uint32_t channelNum)
@@ -154,7 +154,7 @@ void DMA_requestChannel(uint32_t channelNum)
//
// Set the bit for this channel in the software DMA request register.
//
DMA->rSWREQ = 1 << (channelNum & 0x0F);
DMA_Control->SWREQ = 1 << (channelNum & 0x0F);
}
void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
@@ -181,7 +181,7 @@ void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_USEBURST)
{
DMA->rUSEBURSTSET = 1 << channelNum;
DMA_Control->USEBURSTSET = 1 << channelNum;
}
//
@@ -190,7 +190,7 @@ void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_ALTSELECT)
{
DMA->rALTSET = 1 << channelNum;
DMA_Control->ALTSET = 1 << channelNum;
}
//
@@ -198,7 +198,7 @@ void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_HIGH_PRIORITY)
{
DMA->rPRIOSET = 1 << channelNum;
DMA_Control->PRIOSET = 1 << channelNum;
}
//
@@ -206,7 +206,7 @@ void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_REQMASK)
{
DMA->rREQMASKSET = 1 << channelNum;
DMA_Control->REQMASKSET = 1 << channelNum;
}
}
@@ -234,7 +234,7 @@ void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_USEBURST)
{
DMA->rUSEBURSTCLR = 1 << channelNum;
DMA_Control->USEBURSTCLR = 1 << channelNum;
}
//
@@ -243,7 +243,7 @@ void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_ALTSELECT)
{
DMA->rALTCLR = 1 << channelNum;
DMA_Control->ALTCLR = 1 << channelNum;
}
//
@@ -251,7 +251,7 @@ void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_HIGH_PRIORITY)
{
DMA->rPRIOCLR = 1 << channelNum;
DMA_Control->PRIOCLR = 1 << channelNum;
}
//
@@ -259,7 +259,7 @@ void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_REQMASK)
{
DMA->rREQMASKCLR = 1 << channelNum;
DMA_Control->REQMASKCLR = 1 << channelNum;
}
}
@@ -282,7 +282,7 @@ uint32_t DMA_getChannelAttribute(uint32_t channelNum)
//
// Check to see if useburst bit is set for this channel.
//
if (DMA->rUSEBURSTSET & (1 << channelNum))
if (DMA_Control->USEBURSTSET & (1 << channelNum))
{
attr |= UDMA_ATTR_USEBURST;
}
@@ -290,7 +290,7 @@ uint32_t DMA_getChannelAttribute(uint32_t channelNum)
//
// Check to see if the alternate control bit is set for this channel.
//
if (DMA->rALTSET & (1 << channelNum))
if (DMA_Control->ALTSET & (1 << channelNum))
{
attr |= UDMA_ATTR_ALTSELECT;
}
@@ -298,7 +298,7 @@ uint32_t DMA_getChannelAttribute(uint32_t channelNum)
//
// Check to see if the high priority bit is set for this channel.
//
if (DMA->rPRIOSET & (1 << channelNum))
if (DMA_Control->PRIOSET & (1 << channelNum))
{
attr |= UDMA_ATTR_HIGH_PRIORITY;
}
@@ -306,7 +306,7 @@ uint32_t DMA_getChannelAttribute(uint32_t channelNum)
//
// Check to see if the request mask bit is set for this channel.
//
if (DMA->rREQMASKSET & (1 << channelNum))
if (DMA_Control->REQMASKSET & (1 << channelNum))
{
attr |= UDMA_ATTR_REQMASK;
}
@@ -325,7 +325,7 @@ void DMA_setChannelControl(uint32_t channelStructIndex, uint32_t control)
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 64);
ASSERT(DMA->rCTLBASE != 0);
ASSERT(DMA_Control->CTLBASE != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
@@ -337,7 +337,7 @@ void DMA_setChannelControl(uint32_t channelStructIndex, uint32_t control)
//
// Get the base address of the control table.
//
pCtl = (DMA_ControlTable *) DMA->rCTLBASE.r;
pCtl = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get the current control word value and mask off the fields to be
@@ -361,7 +361,7 @@ void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode,
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 64);
ASSERT(DMA->rCTLBASE != 0);
ASSERT(DMA->CTLBASE != 0);
ASSERT(mode <= UDMA_MODE_PER_SCATTER_GATHER);
ASSERT((transferSize != 0) && (transferSize <= 1024));
@@ -375,7 +375,7 @@ void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode,
//
// Get the base address of the control table.
//
controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get the current control word value and mask off the mode and size
@@ -481,7 +481,7 @@ void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount,
// Check the parameters
//
ASSERT((channelNum & 0xffff) < 8);
ASSERT(DMA->rCTLBASE != 0);
ASSERT(DMA->CTLBASE != 0);
ASSERT(taskList != 0);
ASSERT(taskCount <= 1024);
ASSERT(taskCount != 0);
@@ -496,7 +496,7 @@ void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount,
//
// Get the base address of the control table.
//
controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get a handy pointer to the task list
@@ -537,7 +537,7 @@ void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount,
// alt bit here to ensure that it is always cleared before a new SG
// transfer is started.
//
DMA->rALTCLR = 1 << channelNum;
DMA_Control->ALTCLR = 1 << channelNum;
}
uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
@@ -549,7 +549,7 @@ uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 16);
ASSERT(DMA->rCTLBASE != 0);
ASSERT(DMA->CTLBASE != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
@@ -561,7 +561,7 @@ uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
//
// Get the base address of the control table.
//
controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get the current control word value and mask off all but the size field
@@ -601,7 +601,7 @@ uint32_t DMA_getChannelMode(uint32_t channelStructIndex)
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 64);
ASSERT(DMA->rCTLBASE != 0);
ASSERT(DMA->CTLBASE != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
@@ -613,7 +613,7 @@ uint32_t DMA_getChannelMode(uint32_t channelStructIndex)
//
// Get the base address of the control table.
//
controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get the current control word value and mask off all but the mode field.
@@ -649,7 +649,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH0_EUSCIB1TX3:
case DMA_CH0_TIMERA0CCR0:
case DMA_CH0_AESTRIGGER0:
DMA->rCH0_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[0] = (mapping >> 24) & 0x1F;
break;
case DMA_CH1_RESERVED0:
case DMA_CH1_EUSCIA0RX:
@@ -659,7 +659,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH1_EUSCIB1RX3:
case DMA_CH1_TIMERA0CCR2:
case DMA_CH1_AESTRIGGER1:
DMA->rCH1_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[1] = (mapping >> 24) & 0x1F;
break;
case DMA_CH2_RESERVED0:
case DMA_CH2_EUSCIA1TX:
@@ -669,7 +669,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH2_EUSCIB2TX3:
case DMA_CH2_TIMERA1CCR0:
case DMA_CH2_AESTRIGGER2:
DMA->rCH2_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[2] = (mapping >> 24) & 0x1F;
break;
case DMA_CH3_RESERVED0:
case DMA_CH3_EUSCIA1RX:
@@ -679,7 +679,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH3_EUSCIB2RX3:
case DMA_CH3_TIMERA1CCR2:
case DMA_CH3_RESERVED1:
DMA->rCH3_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[3] = (mapping >> 24) & 0x1F;
break;
case DMA_CH4_RESERVED0:
case DMA_CH4_EUSCIA2TX:
@@ -689,7 +689,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH4_EUSCIB3TX3:
case DMA_CH4_TIMERA2CCR0:
case DMA_CH4_RESERVED1:
DMA->rCH4_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[4] = (mapping >> 24) & 0x1F;
break;
case DMA_CH5_RESERVED0:
case DMA_CH5_EUSCIA2RX:
@@ -699,7 +699,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH5_EUSCIB3RX3:
case DMA_CH5_TIMERA2CCR2:
case DMA_CH5_RESERVED1:
DMA->rCH5_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[5] = (mapping >> 24) & 0x1F;
break;
case DMA_CH6_RESERVED0:
case DMA_CH6_EUSCIA3TX:
@@ -709,7 +709,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH6_EUSCIB0TX3:
case DMA_CH6_TIMERA3CCR0:
case DMA_CH6_EXTERNALPIN:
DMA->rCH6_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[6] = (mapping >> 24) & 0x1F;
break;
case DMA_CH7_RESERVED0:
case DMA_CH7_EUSCIA3RX:
@@ -718,8 +718,8 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH7_EUSCIB1RX2:
case DMA_CH7_EUSCIB0RX3:
case DMA_CH7_TIMERA3CCR2:
case DMA_CH7_ADC12C:
DMA->rCH7_SRCCFG.r = (mapping >> 24) & 0x1F;
case DMA_CH7_ADC14:
DMA_Channel->CH_SRCCFG[7] = (mapping >> 24) & 0x1F;
break;
default:
ASSERT(false);
@@ -735,16 +735,16 @@ void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel)
if (interruptNumber == DMA_INT1)
{
DMA->rINT1_SRCCFG.r = (DMA->rINT1_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
| channel;
DMA_Channel->INT1_SRCCFG = (DMA_Channel->INT1_SRCCFG
& ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
} else if (interruptNumber == DMA_INT2)
{
DMA->rINT2_SRCCFG.r = (DMA->rINT2_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
| channel;
DMA_Channel->INT2_SRCCFG = (DMA_Channel->INT2_SRCCFG
& ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
} else if (interruptNumber == DMA_INT3)
{
DMA->rINT3_SRCCFG.r = (DMA->rINT3_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
| channel;
DMA_Channel->INT3_SRCCFG = (DMA_Channel->INT3_SRCCFG
& ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
}
/* Enabling the assigned interrupt */
@@ -753,17 +753,17 @@ void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel)
void DMA_requestSoftwareTransfer(uint32_t channel)
{
DMA->rSW_CHTRIG.r |= (1 << channel);
DMA_Channel->SW_CHTRIG |= (1 << channel);
}
uint32_t DMA_getInterruptStatus(void)
{
return DMA->rINT0_SRCFLG.r;
return DMA_Channel->INT0_SRCFLG;
}
void DMA_clearInterruptFlag(uint32_t channel)
{
DMA->rINT0_CLRFLG.r |= (1 << channel);
DMA_Channel->INT0_CLRFLG |= (1 << channel);
}
void DMA_enableInterrupt(uint32_t interruptNumber)
@@ -775,13 +775,13 @@ void DMA_enableInterrupt(uint32_t interruptNumber)
if (interruptNumber == DMA_INT1)
{
DMA->rINT1_SRCCFG.r |= DMA_INT1_SRCCFG_EN;
DMA_Channel->INT1_SRCCFG |= DMA_INT1_SRCCFG_EN;
} else if (interruptNumber == DMA_INT2)
{
DMA->rINT2_SRCCFG.r |= DMA_INT2_SRCCFG_EN;
DMA_Channel->INT2_SRCCFG |= DMA_INT2_SRCCFG_EN;
} else if (interruptNumber == DMA_INT3)
{
DMA->rINT3_SRCCFG.r |= DMA_INT3_SRCCFG_EN;
DMA_Channel->INT3_SRCCFG |= DMA_INT3_SRCCFG_EN;
}
}
@@ -795,13 +795,13 @@ void DMA_disableInterrupt(uint32_t interruptNumber)
if (interruptNumber == DMA_INT1)
{
DMA->rINT1_SRCCFG.r &= ~DMA_INT1_SRCCFG_EN;
DMA_Channel->INT1_SRCCFG &= ~DMA_INT1_SRCCFG_EN;
} else if (interruptNumber == DMA_INT2)
{
DMA->rINT2_SRCCFG.r &= ~DMA_INT2_SRCCFG_EN;
DMA_Channel->INT2_SRCCFG &= ~DMA_INT2_SRCCFG_EN;
} else if (interruptNumber == DMA_INT3)
{
DMA->rINT3_SRCCFG.r &= ~DMA_INT3_SRCCFG_EN;
DMA_Channel->INT3_SRCCFG &= ~DMA_INT3_SRCCFG_EN;
}
}
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.h
+3 -3
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -348,7 +348,7 @@ typedef struct _DMA_ControlTable
#define DMA_CH7_EUSCIB1RX2 0x04000007
#define DMA_CH7_EUSCIB0RX3 0x05000007
#define DMA_CH7_TIMERA3CCR2 0x06000007
#define DMA_CH7_ADC12C 0x07000007
#define DMA_CH7_ADC14 0x07000007
//
// Different interrupt handlers to pass into DMA_registerInterrupt and
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/driverlib.h
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/eusci.h
+4 -4
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,7 +39,7 @@
#include <msp.h>
#define EUSCI_A_CMSIS(x) ((EUSCI_A0_Type *) x)
#define EUSCI_B_CMSIS(x) ((EUSCI_B0_Type *) x)
#define EUSCI_A_CMSIS(x) ((EUSCI_A_Type *) x)
#define EUSCI_B_CMSIS(x) ((EUSCI_B_Type *) x)
#endif /* EUSCI_H_ */
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.c
+986 -209
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.h
+149 -19
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -84,7 +84,7 @@ extern "C"
#define FLASH_MARGIN0B_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_9
#define FLASH_MARGIN1B_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_10
#define FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE 0x70000
#define FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7
#define FLASH_BANK0 0x00
#define FLASH_BANK1 0x01
@@ -146,13 +146,8 @@ extern "C"
#define FLASH_COLLATED_WRITE_MODE 0x01
#define FLASH_IMMEDIATE_WRITE_MODE 0x02
#define FlashInternal_eraseSector \
((bool (*)(uint32_t addr, \
bool verify))ROM_FLASHCTLTABLE[9])
#define FlashInternal_performMassErase \
((bool (*)(bool verify))ROM_FLASHCTLTABLE[8])
#define __INFO_FLASH_TECH_START__ 0x00200000
#define __INFO_FLASH_TECH_MIDDLE__ 0x00202000
//*****************************************************************************
@@ -160,6 +155,32 @@ extern "C"
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Calculates the flash bank and sector number given an address. Stores the
//! results into the two pointers given as parameters. The user must provide
//! a valid memory address (an address in SRAM for example will give an invalid
//! result).
//!
//! \param addr Address to calculate the bank/sector information for
//!
//! \param sectorNum The sector number will be stored in here after the function
//! completes.
//!
//! \param sectorNum The bank number will be stored in here after the function
//! completes.
//!
//! \note For simplicity, this API only works with address in MAIN flash memory.
//! For calculating the sector/bank number of an address in info memory,
//! please refer to your device datasheet/
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *sectorNum,
uint32_t *bankNum);
//*****************************************************************************
//
//! Enables read buffering on accesses to a specified bank of flash memory
@@ -251,6 +272,11 @@ extern void FlashCtl_disableReadBuffering(uint_fast8_t memoryBank,
//! depending on the specific device. Also, for INFO memory space, only sectors
//! \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist.
//!
//! \note Not all devices will contain a dedicated INFO memory. Please check the
//! device datasheet to see if your device has INFO memory available for use.
//! For devices without INFO memory, any operation related to the INFO memory
//! will be ignored by the hardware.
//!
//! \return true if sector protection disabled false otherwise.
//
//*****************************************************************************
@@ -308,6 +334,11 @@ extern bool FlashCtl_unprotectSector(uint_fast8_t memorySpace,
//! depending on the specific device. Also, for INFO memory space, only sectors
//! \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist.
//!
//! \note Not all devices will contain a dedicated INFO memory. Please check the
//! device datasheet to see if your device has INFO memory available for use.
//! For devices without INFO memory, any operation related to the INFO memory
//! will be ignored by the hardware.
//!
//! \return true if sector protection enabled false otherwise.
//
//*****************************************************************************
@@ -364,6 +395,11 @@ extern bool FlashCtl_protectSector(uint_fast8_t memorySpace,
//! depending on the specific device. Also, for INFO memory space, only sectors
//! FLASH_SECTOR0 and FLASH_SECTOR1 will exist.
//!
//! \note Not all devices will contain a dedicated INFO memory. Please check the
//! device datasheet to see if your device has INFO memory available for use.
//! For devices without INFO memory, any operation related to the INFO memory
//! will be ignored by the hardware.
//!
//! \return true if sector protection enabled false otherwise.
//
//*****************************************************************************
@@ -384,13 +420,25 @@ extern bool FlashCtl_isSectorProtected(uint_fast8_t memorySpace,
//! of 32 zeros, or a high pattern (each register will be checked versus a
//! pattern of 32 ones). Valid values are: FLASH_0_PATTERN, FLASH_1_PATTERN
//!
//! Note that there are no sector/boundary restrictions for this function,
//! \note There are no sector/boundary restrictions for this function,
//! however it is encouraged to proved a start address aligned on 32-bit
//! boundaries. Providing an unaligned address will result in unaligned data
//! accesses and detriment efficiency.
//!
//! Note that this function is blocking and will not exit until operation has
//! either completed or failed due to an error.
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error. Furthermore, given the
//! complex verification requirements of the flash controller, master
//! interrupts are disabled throughout execution of this function. The original
//! interrupt context is saved at the start of execution and restored prior
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot verify a memory adress in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
//! or reads happen in the flash bank being programmed while this API is
//! being executed.
//!
//! \return true if memory verification is successful, false otherwise.
//
@@ -403,14 +451,38 @@ extern bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length,
//! Performs a mass erase on all unprotected flash sectors. Protected sectors
//! are ignored.
//!
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error.
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error. Furthermore, given the
//! complex verification requirements of the flash controller, master
//! interrupts are disabled throughout execution of this function. The original
//! interrupt context is saved at the start of execution and restored prior
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot erase a memory adress in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
//! or reads happen in the flash bank being programmed while this API is
//! being executed.
//!
//! \return true if mass erase completes successfully, false otherwise
//
//*****************************************************************************
extern bool FlashCtl_performMassErase(void);
//*****************************************************************************
//
//! Initiates a mass erase and returns control back to the program. This is a
//! non-blocking function, however it is the user's responsibility to perform
//! the necessary verification requirements after the interrupt is set to
//! signify completion.
//!
//! \return None
//
//*****************************************************************************
extern void FlashCtl_initiateMassErase(void);
//*****************************************************************************
//
//! Erases a sector of MAIN or INFO flash memory.
@@ -421,8 +493,20 @@ extern bool FlashCtl_performMassErase(void);
//! this function which is not on a 4KB boundary, the entire sector
//! will still be erased.
//!
//! Note that this function is blocking and will not exit until operation has
//! either completed or failed due to an error.
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error. Furthermore, given the
//! complex verification requirements of the flash controller, master
//! interrupts are disabled throughout execution of this function. The original
//! interrupt context is saved at the start of execution and restored prior
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot erase a memory adress in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
//! or reads happen in the flash bank being programmed while this API is
//! being executed.
//!
//! \return true if sector erase is successful, false otherwise.
//
@@ -444,8 +528,20 @@ extern bool FlashCtl_eraseSector(uint32_t addr);
//! boundaries. Providing an unaligned address will result in unaligned data
//! accesses and detriment efficiency.
//!
//! Note that this function is blocking and will not exit until operation has
//! either completed or failed due to an error.
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error. Furthermore, given the
//! complex verification requirements of the flash controller, master
//! interrupts are disabled throughout execution of this function. The original
//! interrupt context is saved at the start of execution and restored prior
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot program a memory adress in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
//! or reads happen in the flash bank being programmed while this API is
//! being executed.
//!
//! \return Whether or not the program succeeded
//
@@ -794,6 +890,40 @@ extern void FlashCtl_registerInterrupt(void (*intHandler)(void));
//*****************************************************************************
extern void FlashCtl_unregisterInterrupt(void);
//*****************************************************************************
//
//! Initiates a sector erase of MAIN or INFO flash memory. Note that this
//! function simply initaites the sector erase, but does no verification
//! which is required by the flash controller. The user must manually set
//! and enable interrupts on the flash controller to fire on erase completion
//! and then use the FlashCtl_verifyMemory function to verify that the sector
//! was actually erased
//!
//! \param addr The start of the sector to erase. Note that with flash,
//! the minimum allowed size that can be erased is a flash sector
//! (which is 4KB on the MSP432 family). If an address is provided to
//! this function which is not on a 4KB boundary, the entire sector
//! will still be erased.
//!
//! \return None
//
//*****************************************************************************
extern void FlashCtl_initiateSectorErase(uint32_t addr);
/* The following functions are advanced functions that are used by the flash
* driver to remask a failed bit in the event of a post or pre verification
* failure. They are meant to be advanced functions and should not be used
* by the majority of users (unless you are writing your own flash driver).
*/
extern uint8_t __FlashCtl_remaskData8Post(uint8_t data, uint32_t addr);
extern uint8_t __FlashCtl_remaskData8Pre(uint8_t data, uint32_t addr);
extern uint32_t __FlashCtl_remaskData32Post(uint32_t data, uint32_t addr);
extern uint32_t __FlashCtl_remaskData32Pre(uint32_t data, uint32_t addr);
extern void __FlashCtl_remaskBurstDataPost(uint32_t addr, uint32_t size);
extern void __FlashCtl_remaskBurstDataPre(uint32_t addr, uint32_t size);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.c
+8 -8
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,8 +41,8 @@ void FPU_enableModule(void)
//
// Enable the coprocessors used by the floating-point unit.
//
SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP11_M | SCB_CPACR_CP10_M))
| SCB_CPACR_CP11_M | SCB_CPACR_CP10_M);
SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP11_MASK | SCB_CPACR_CP10_MASK))
| SCB_CPACR_CP11_MASK | SCB_CPACR_CP10_MASK);
}
void FPU_disableModule(void)
@@ -50,7 +50,7 @@ void FPU_disableModule(void)
//
// Disable the coprocessors used by the floating-point unit.
//
SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP10_M | SCB_CPACR_CP11_M)));
SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP10_MASK | SCB_CPACR_CP11_MASK)));
}
void FPU_enableStacking(void)
@@ -60,7 +60,7 @@ void FPU_enableStacking(void)
// disable lazy state preservation (meaning that the floating-point state
// is always stacked when floating-point instructions are used).
//
FPU->FPCCR = (FPU->FPCCR & ~FPU_FPCCR_LSPEN) | FPU_FPCCR_ASPEN;
FPU->FPCCR = (FPU->FPCCR & ~FPU_FPCCR_LSPEN_Msk) | FPU_FPCCR_ASPEN_Msk;
}
void FPU_enableLazyStacking(void)
@@ -69,7 +69,7 @@ void FPU_enableLazyStacking(void)
// Enable automatic and lazy state preservation for the floating-point
// unit.
//
FPU->FPCCR |= FPU_FPCCR_ASPEN | FPU_FPCCR_LSPEN;
FPU->FPCCR |= FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk;
}
void FPU_disableStacking(void)
@@ -78,7 +78,7 @@ void FPU_disableStacking(void)
// Disable automatic and lazy state preservation for the floating-point
// unit.
//
FPU->FPCCR &= ~(FPU_FPCCR_ASPEN | FPU_FPCCR_LSPEN);
FPU->FPCCR &= ~(FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk);
}
void FPU_setHalfPrecisionMode(uint32_t mode)
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.h
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.c
+77 -64
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,6 +41,21 @@
#include <gpio.h>
#include <debug.h>
#include <interrupt.h>
#include <hw_memmap.h>
/* DriverLib internal GPIO register offset for optimized performace */
#define OFS_LIB_PAIN ((uint32_t)&P1->IN - (uint32_t)P1)
#define OFS_LIB_PAOUT ((uint32_t)&P1->OUT - (uint32_t)P1)
#define OFS_LIB_PADIR ((uint32_t)&P1->DIR - (uint32_t)P1)
#define OFS_LIB_PAREN ((uint32_t)&P1->REN - (uint32_t)P1)
#define OFS_LIB_PADS ((uint32_t)&P1->DS - (uint32_t)P1)
#define OFS_LIB_PASEL0 ((uint32_t)&P1->SEL0 - (uint32_t)P1)
#define OFS_LIB_PASEL1 ((uint32_t)&P1->SEL1 - (uint32_t)P1)
#define OFS_LIB_PAIE ((uint32_t)&P1->IE - (uint32_t)P1)
#define OFS_LIB_PAIES ((uint32_t)&P1->IES - (uint32_t)P1)
#define OFS_LIB_PAIFG ((uint32_t)&P1->IFG - (uint32_t)P1)
#define OFS_LIB_P1IE ((uint32_t)&P1->IE - (uint32_t)P1)
#define OFS_LIB_P2IE ((uint32_t)&P2->IE - (uint32_t)P2)
static const uint32_t GPIO_PORT_TO_INT[] =
{ 0x00,
@@ -51,41 +66,39 @@ INT_PORT4,
INT_PORT5,
INT_PORT6 };
static const uint32_t GPIO_PORT_TO_BASE[] =
static uint32_t GPIO_PORT_TO_BASE[] =
{ 0x00,
0x40004C00,
0x40004C01,
0x40004C20,
0x40004C21,
0x40004C40,
0x40004C41,
0x40004C60,
0x40004C61,
0x40004C80,
0x40004C81,
0x40004D20
(uint32_t)P1,
(uint32_t)P1+1,
(uint32_t)P3,
(uint32_t)P3+1,
(uint32_t)P5,
(uint32_t)P5+1,
(uint32_t)P7,
(uint32_t)P7+1,
(uint32_t)P9,
(uint32_t)P9+1,
(uint32_t)PJ
};
void GPIO_setAsOutputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_PADIR) |= selectedPins;
return;
HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PADIR) |= selectedPins;
}
void GPIO_setAsInputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_PAREN) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAREN) &= ~selectedPins;
}
@@ -95,20 +108,20 @@ void GPIO_setAsPeripheralModuleFunctionOutputPin(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PADIR) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PADIR) |= selectedPins;
switch (mode)
{
case GPIO_PRIMARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
break;
case GPIO_SECONDARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
break;
case GPIO_TERTIARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
break;
}
}
@@ -119,20 +132,20 @@ void GPIO_setAsPeripheralModuleFunctionInputPin(uint_fast8_t selectedPort,
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
switch (mode)
{
case GPIO_PRIMARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
break;
case GPIO_SECONDARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
break;
case GPIO_TERTIARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
break;
}
}
@@ -144,7 +157,7 @@ void GPIO_setOutputHighOnPin(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAOUT) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PAOUT) |= selectedPins;
}
@@ -154,7 +167,7 @@ void GPIO_setOutputLowOnPin(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAOUT) &= ~selectedPins;
}
@@ -164,7 +177,7 @@ void GPIO_toggleOutputOnPin(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAOUT) ^= selectedPins;
HWREG16(baseAddress + OFS_LIB_PAOUT) ^= selectedPins;
}
@@ -174,12 +187,12 @@ void GPIO_setAsInputPinWithPullDownResistor(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_PAREN) |= selectedPins;
HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAREN) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PAOUT) &= ~selectedPins;
}
@@ -189,21 +202,21 @@ void GPIO_setAsInputPinWithPullUpResistor(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_PAREN) |= selectedPins;
HWREG16(baseAddress + OFS_PAOUT) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAREN) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PAOUT) |= selectedPins;
}
uint8_t GPIO_getInputPinValue(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
{
uint16_t inputPinValue;
uint_fast16_t inputPinValue;
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
inputPinValue = HWREG16(baseAddress + OFS_PAIN) & (selectedPins);
inputPinValue = HWREG16(baseAddress + OFS_LIB_PAIN) & (selectedPins);
if (inputPinValue > 0)
return GPIO_INPUT_PIN_HIGH;
@@ -216,7 +229,7 @@ void GPIO_enableInterrupt(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAIE) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PAIE) |= selectedPins;
}
@@ -226,7 +239,7 @@ void GPIO_disableInterrupt(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAIE) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAIE) &= ~selectedPins;
}
@@ -236,7 +249,7 @@ uint_fast16_t GPIO_getInterruptStatus(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
return HWREG16(baseAddress + OFS_PAIFG) & selectedPins;
return HWREG16(baseAddress + OFS_LIB_PAIFG) & selectedPins;
}
@@ -247,7 +260,7 @@ void GPIO_clearInterruptFlag(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAIFG) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAIFG) &= ~selectedPins;
}
@@ -259,9 +272,9 @@ void GPIO_interruptEdgeSelect(uint_fast8_t selectedPort,
if (GPIO_LOW_TO_HIGH_TRANSITION == edgeSelect)
HWREG16(baseAddress + OFS_PAIES) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAIES) &= ~selectedPins;
else
HWREG16(baseAddress + OFS_PAIES) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PAIES) |= selectedPins;
}
uint_fast16_t GPIO_getEnabledInterruptStatus(uint_fast8_t selectedPort)
@@ -281,15 +294,15 @@ uint_fast16_t GPIO_getEnabledInterruptStatus(uint_fast8_t selectedPort)
case GPIO_PORT_P5:
case GPIO_PORT_P7:
case GPIO_PORT_P9:
return (HWREG8(baseAddr + OFS_P1IE) & pendingInts);
return (HWREG8(baseAddr + OFS_LIB_P1IE) & pendingInts);
case GPIO_PORT_P2:
case GPIO_PORT_P4:
case GPIO_PORT_P6:
case GPIO_PORT_P8:
case GPIO_PORT_P10:
return (HWREG8(baseAddr + OFS_P2IE) & pendingInts);
return (HWREG8(baseAddr + OFS_LIB_P2IE) & pendingInts);
case GPIO_PORT_PJ:
return (HWREG16(baseAddr + OFS_PAIE) & pendingInts);
return (HWREG16(baseAddr + OFS_LIB_PAIE) & pendingInts);
default:
return 0;
}
@@ -303,7 +316,7 @@ void GPIO_setDriveStrengthHigh(uint_fast8_t selectedPort,
baseAddr = GPIO_PORT_TO_BASE[selectedPort];
HWREG8(baseAddr + OFS_PADS) |= selectedPins;
HWREG8(baseAddr + OFS_LIB_PADS) |= selectedPins;
}
@@ -314,7 +327,7 @@ void GPIO_setDriveStrengthLow(uint_fast8_t selectedPort,
baseAddr = GPIO_PORT_TO_BASE[selectedPort];
HWREG8(baseAddr + OFS_PADS) &= ~selectedPins;
HWREG8(baseAddr + OFS_LIB_PADS) &= ~selectedPins;
}
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.h
+14 -6
View File
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -68,8 +68,14 @@ extern "C"
#define GPIO_PORT_P8 8
#define GPIO_PORT_P9 9
#define GPIO_PORT_P10 10
#define GPIO_PORT_PJ 11
#define GPIO_PORT_PA 1
#define GPIO_PORT_PB 3
#define GPIO_PORT_PC 5
#define GPIO_PORT_PD 7
#define GPIO_PORT_PE 9
#define GPIO_PORT_PJ 11
#define GPIO_PIN0 (0x0001)
#define GPIO_PIN1 (0x0002)
#define GPIO_PIN2 (0x0004)
@@ -406,8 +412,6 @@ extern void GPIO_setOutputHighOnPin(uint_fast8_t selectedPort,
//! - \b GPIO_PIN14
//! - \b GPIO_PIN15
//!
//! Modified bits of \b PxOUT register.
//!
//! \return None
//
//*****************************************************************************
@@ -998,7 +1002,11 @@ extern void GPIO_setDriveStrengthHigh(uint_fast8_t selectedPort,
//*****************************************************************************
extern void GPIO_setDriveStrengthLow(uint_fast8_t selectedPort,
uint_fast8_t selectedPins);
/* Backwards Compatibility Layer */
#define GPIO_selectInterruptEdge GPIO_interruptEdgeSelect
#define GPIO_clearInterrupt GPIO_clearInterruptFlag
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/hw_memmap.h
+87
View File
@@ -0,0 +1,87 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __HW_MEMMAP__
#define __HW_MEMMAP__
#define __DRIVERLIB_MSP432P4XX_FAMILY__
//*****************************************************************************
//
// Include device specific header file
//
//*****************************************************************************
//*****************************************************************************
//
// SUCCESS and FAILURE for API return value
//
//*****************************************************************************
#define STATUS_SUCCESS 0x01
#define STATUS_FAIL 0x00
//*****************************************************************************
//
// Macros for hardware access
//
//*****************************************************************************
#define HWREG8(x) (*((volatile uint8_t *)(x)))
#define HWREG16(x) (*((volatile uint16_t *)(x)))
#define HWREG32(x) (*((volatile uint32_t *)(x)))
#define HWREG(x) (HWREG16(x))
#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))
#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))
#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
/******************************************************************************
* Device memory map *
******************************************************************************/
#define __MAIN_MEMORY_START__ (0x00000000) /**< Main Flash memory start address */
#define __MAIN_MEMORY_END__ (0x0003FFFF) /**< Main Flash memory end address */
#define __BSL_MEMORY_START__ (0x00202000) /**< BSL memory start address */
#define __BSL_MEMORY_END__ (0x00203FFF) /**< BSL memory end address */
#define __SRAM_START__ (0x20000000) /**< SRAM memory start address */
#define __SRAM_END__ (0x2000FFFF) /**< SRAM memory end address */
/******************************************************************************
* Definitions for 8/16/32-bit wide bit band access *
******************************************************************************/
#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#endif // #ifndef __HW_MEMMAP__
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.c
+152 -131
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.h
+218 -199
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/cmsis_ccs.h
+9 -2
View File
@@ -1,6 +1,6 @@
//*****************************************************************************
//
// Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/
// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -41,12 +41,18 @@
// CMSIS-compatible instruction calls
//*****************************************************************************
#ifndef __cplusplus
// No Operation
__attribute__( ( always_inline ) ) static inline void __nop(void)
{
__asm(" nop");
}
__attribute__( ( always_inline ) ) static inline void __NOP(void)
{
__asm(" nop");
}
// Wait For Interrupt
__attribute__( ( always_inline ) ) static inline void __wfi(void)
{
@@ -58,6 +64,7 @@ __attribute__( ( always_inline ) ) static inline void __wfe(void)
{
__asm(" wfe");
}
#endif
// Enable Interrupts
__attribute__( ( always_inline ) ) static inline void __enable_irq(void)
@@ -194,7 +201,7 @@ static inline void __set_PRIMASK(uint32_t priMask)
#define __SMUAD _smuad
#define __SMUADX _smuadx
#define __SMUSD _smusd
#define __SMUSDX _smusd
#define __SMUSDX _smusdx
#define __SSAT16 _ssat16
#define __SSUB16 _ssub16
#define __SSUB8 _ssub8
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4.h
+762 -605
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmFunc.h
+27 -583
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmInstr.h
+27 -635
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmSimd.h
+94
View File
@@ -0,0 +1,94 @@
/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.20
* @date 02. July 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler -----------------*/
#include <cmsis_armcc.h>
#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
#include <cmsis_armcc_V6.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ----------------------*/
#include <cmsis_gcc.h>
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler ----------------------*/
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*------------------ TI CCS Compiler -------------------*/
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler ------------------*/
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp.h
+1 -1
View File
@@ -32,7 +32,7 @@
//
// MSP432 Family Generic Include File
//
// File creation date: 2015-01-02
// File creation date: 2015-10-26
//
//*****************************************************************************
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432.h
+1 -1
View File
@@ -32,7 +32,7 @@
//
// MSP432 Family Generic Include File
//
// File creation date: 2015-01-05
// File creation date: 2015-10-26
//
//*****************************************************************************

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