Reworked XMC4500 IAR project to use latest system files and include build configurations for the XMC4200 and XMC4400 parts.

2026-08-21 07:18:22 +08:00 · 2013-09-04 15:44:48 +00:00
parent aaf2d32011
commit d8963209c2
33 changed files with 53468 additions and 22519 deletions
@@ -113,16 +113,12 @@

 /* Standard demo application includes. */
 #include "flop.h"
-#include "integer.h"
-#include "PollQ.h"
 #include "semtest.h"
 #include "dynamic.h"
-#include "BlockQ.h"
 #include "blocktim.h"
 #include "countsem.h"
 #include "GenQTest.h"
 #include "recmutex.h"
-#include "death.h"

 /* Priorities for the demo application tasks. */
 #define mainQUEUE_POLL_PRIORITY				( tskIDLE_PRIORITY + 2UL )
@@ -87,12 +87,12 @@

 #define configUSE_PREEMPTION			1
 #define configUSE_IDLE_HOOK				0
-#define configUSE_TICK_HOOK				0
+#define configUSE_TICK_HOOK				1
 #define configCPU_CLOCK_HZ				( SystemCoreClock )
 #define configTICK_RATE_HZ				( ( portTickType ) 1000 )
 #define configMAX_PRIORITIES			( ( unsigned portBASE_TYPE ) 5 )
 #define configMINIMAL_STACK_SIZE		( ( unsigned short ) 130 )
-#define configTOTAL_HEAP_SIZE			( ( size_t ) ( 40960 ) )
+#define configTOTAL_HEAP_SIZE			( ( size_t ) ( 22800 ) )
 #define configMAX_TASK_NAME_LEN			( 10 )
 #define configUSE_TRACE_FACILITY		1
 #define configUSE_16_BIT_TICKS			0
@@ -105,6 +105,7 @@
 #define configUSE_APPLICATION_TASK_TAG	0
 #define configUSE_COUNTING_SEMAPHORES	1
 #define configGENERATE_RUN_TIME_STATS	0
+#define configUSE_QUEUE_SETS			1

 /* Co-routine definitions. */
 #define configUSE_CO_ROUTINES 		0
@@ -150,16 +151,50 @@ to all Cortex-M ports, and do not rely on any particular library functions. */
 /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-	
+
 /* Normal assert() semantics without relying on the provision of an assert.h
 header file. */
-#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }	
-	
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+
 /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
 standard names. */
 #define vPortSVCHandler SVC_Handler
 #define xPortPendSVHandler PendSV_Handler
 #define xPortSysTickHandler SysTick_Handler

+/* Demo application specific settings. */
+#ifdef __ICCARM__
+	#if defined( PART_XMC4500 )
+		/* Hardware includes. */
+		#include "XMC4500.h"
+		#include "System_XMC4500.h"
+
+		/* Configure pin P3.9 for the LED. */
+		#define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 )
+		/* To toggle the single LED */
+		#define configTOGGLE_LED()	( PORT3->OMR =	0x02000200 )
+	#elif defined( PART_XMC4400 )
+		/* Hardware includes. */
+		#include "XMC4400.h"
+		#include "System_XMC4200.h"
+
+		/* Configure pin P5.2 for the LED. */
+		#define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 )
+		/* To toggle the single LED */
+		#define configTOGGLE_LED()	( PORT5->OMR =	0x00040004 )
+	#elif defined( PART_XMC4200 )
+		/* Hardware includes. */
+		#include "XMC4200.h"
+		#include "System_XMC4200.h"
+
+		/* Configure pin P2.1 for the LED. */
+		#define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL
+		/* To toggle the single LED */
+		#define configTOGGLE_LED()	( PORT2->OMR =	0x00020002 )
+	#else
+		#error Part number not specified in project options
+	#endif
+#endif
+
 #endif /* FREERTOS_CONFIG_H */

@@ -75,7 +75,7 @@
 	PUBLIC vRegTest2Task
 	PUBLIC vRegTestClearFlopRegistersToParameterValue
 	PUBLIC ulRegTestCheckFlopRegistersContainParameterValue
-	
+
 /*-----------------------------------------------------------*/

 vRegTest1Task
@@ -117,7 +117,7 @@ reg1_loop:
 	/* Check all the VFP registers still contain the values set above.
 	First save registers that are clobbered by the test. */
 	push { r0-r1 }
-	
+
 	vmov r0, r1, d0
 	cmp r0, #100
 	bne reg1_error_loopf
@@ -198,10 +198,10 @@ reg1_loop:
 	bne reg1_error_loopf
 	cmp r1, #107
 	bne reg1_error_loopf
-	
+
 	/* Restore the registers that were clobbered by the test. */
 	pop {r0-r1}
-	
+
 	/* VFP register test passed.  Jump to the core register test. */
 	b reg1_loopf_pass

@@ -238,7 +238,7 @@ reg1_loopf_pass
 	bne	reg1_error_loop
 	cmp	r12, #112
 	bne	reg1_error_loop
-	
+
 	/* Everything passed, increment the loop counter. */
 	push { r0-r1 }
 	ldr	r0, =ulRegTest1LoopCounter
@@ -246,7 +246,7 @@ reg1_loopf_pass
 	adds r1, r1, #1
 	str r1, [r0]
 	pop { r0-r1 }
-	
+
 	/* Start again. */
 	b reg1_loop

@@ -294,11 +294,11 @@ vRegTest2Task
 	vmov d15, r6, r7

 reg2_loop:
-	
+
 	/* Check all the VFP registers still contain the values set above.
 	First save registers that are clobbered by the test. */
 	push { r0-r1 }
-	
+
 	vmov r0, r1, d0
 	cmp r0, #-1
 	bne reg2_error_loopf
@@ -379,10 +379,10 @@ reg2_loop:
 	bne reg2_error_loopf
 	cmp r1, #7
 	bne reg2_error_loopf
-	
+
 	/* Restore the registers that were clobbered by the test. */
 	pop {r0-r1}
-	
+
 	/* VFP register test passed.  Jump to the core register test. */
 	b reg2_loopf_pass

@@ -419,7 +419,7 @@ reg2_loopf_pass
 	bne	reg2_error_loop
 	cmp	r12, #12
 	bne	reg2_error_loop
-	
+
 	/* Increment the loop counter to indicate this test is still functioning
 	correctly. */
 	push { r0-r1 }
@@ -427,8 +427,16 @@ reg2_loopf_pass
 	ldr r1, [r0]
 	adds r1, r1, #1
 	str r1, [r0]
+
+	/* Yield to increase test coverage. */
+	movs r0, #0x01
+	ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */
+	lsl r0, r0, #28 /* Shift to PendSV bit */
+	str r0, [r1]
+	dsb
+
 	pop { r0-r1 }
-	
+
 	/* Start again. */
 	b reg2_loop

@@ -504,7 +512,7 @@ ulRegTestCheckFlopRegistersContainParameterValue
 	vmov r1, s15
 	cmp r0, r1
 	bne return_error
-	
+
 return_pass
 	mov r0, #1
 	bx lr
@@ -514,4 +522,4 @@ return_error
 	bx lr

 	END
-	
+
@@ -92,9 +92,9 @@
 #include "FreeRTOS.h"
 #include "task.h"

-/* Hardware includes. */
-#include "XMC4500.h"
-#include "System_XMC4500.h"
+/* Standard demo includes. */
+#include "QueueSet.h"
+#include "QueueOverwrite.h"

 /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
 or 0 to run the more comprehensive test and demo application. */
@@ -139,13 +139,7 @@ int main( void )

 static void prvSetupHardware( void )
 {
-extern void SystemCoreClockUpdate( void );
-
-	/* Ensure SystemCoreClock variable is set. */
-	SystemCoreClockUpdate();
-
-	/* Configure pin P3.9 for the LED. */
-	PORT3->IOCR8 = 0x00008000;
+	configCONFIGURE_LED();

 	/* Ensure all priority bits are assigned as preemption priority bits. */
 	NVIC_SetPriorityGrouping( 0 );
@@ -203,6 +197,17 @@ void vApplicationTickHook( void )
 	added here, but the tick hook is called from an interrupt context, so
 	code must not attempt to block, and only the interrupt safe FreeRTOS API
 	functions can be used (those that end in FromISR()). */
+
+	#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0
+	{
+		/* Write to a queue that is in use as part of the queue set demo to
+		demonstrate using queue sets from an ISR. */
+		vQueueSetAccessQueueSetFromISR();
+
+		/* Test the ISR safe queue overwrite functions. */
+		vQueueOverwritePeriodicISRDemo();
+	}
+	#endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */
 }
 /*-----------------------------------------------------------*/

@@ -214,12 +219,12 @@ long lHigherPriorityTaskWoken = pdFALSE;

 	/* Clear the interrupt if necessary. */
 	Dummy_ClearITPendingBit();
-	
+
 	/* This interrupt does nothing more than demonstrate how to synchronise a
 	task with an interrupt.  A semaphore is used for this purpose.  Note
 	lHigherPriorityTaskWoken is initialised to zero. */
 	xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );
-	
+
 	/* If there was a task that was blocked on the semaphore, and giving the
 	semaphore caused the task to unblock, and the unblocked task has a priority
 	higher than the current Running state task (the task that this interrupt
@@ -107,10 +107,6 @@
 #include "task.h"
 #include "semphr.h"

-/* Hardware includes. */
-#include "XMC4500.h"
-#include "System_XMC4500.h"
-
 /* Priorities at which the tasks are created. */
 #define mainQUEUE_RECEIVE_TASK_PRIORITY		( tskIDLE_PRIORITY + 2 )
 #define	mainQUEUE_SEND_TASK_PRIORITY		( tskIDLE_PRIORITY + 1 )
@@ -129,9 +125,6 @@ functionality. */
 #define mainQUEUE_SEND_PARAMETER			( 0x1111UL )
 #define mainQUEUE_RECEIVE_PARAMETER			( 0x22UL )

-/* To toggle the single LED */
-#define mainTOGGLE_LED()					( PORT3->OMR =	0x02000200 )
-
 /*-----------------------------------------------------------*/

 /*
@@ -146,11 +139,6 @@ static void prvQueueSendTask( void *pvParameters );
 */
 void main_blinky( void );

-/*
- * The hardware only has a single LED.  Simply toggle it.
- */
-extern void vMainToggleLED( void );
-
 /*-----------------------------------------------------------*/

 /* The queue used by both tasks. */
@@ -235,7 +223,7 @@ unsigned long ulReceivedValue;
 		is it the expected value?  If it is, toggle the LED. */
 		if( ulReceivedValue == 100UL )
 		{
-			mainTOGGLE_LED();
+			configTOGGLE_LED();
 			ulReceivedValue = 0U;
 		}
 	}
@@ -75,8 +75,8 @@
 ******************************************************************************
 *
 * main_full() creates all the demo application tasks and a software timer, then
- * starts the scheduler.  The web documentation provides more details of the 
- * standard demo application tasks, which provide no particular functionality, 
+ * starts the scheduler.  The web documentation provides more details of the
+ * standard demo application tasks, which provide no particular functionality,
 * but do provide a good example of how to use the FreeRTOS API.
 *
 * In addition to the standard demo tasks, the following tasks and tests are
@@ -113,20 +113,14 @@

 /* Standard demo application includes. */
 #include "flop.h"
-#include "integer.h"
-#include "PollQ.h"
 #include "semtest.h"
 #include "dynamic.h"
-#include "BlockQ.h"
 #include "blocktim.h"
 #include "countsem.h"
 #include "GenQTest.h"
 #include "recmutex.h"
-#include "death.h"
-
-/* Hardware includes. */
-#include "XMC4500.h"
-#include "System_XMC4500.h"
+#include "QueueSet.h"
+#include "QueueOverwrite.h"

 /* Priorities for the demo application tasks. */
 #define mainQUEUE_POLL_PRIORITY				( tskIDLE_PRIORITY + 2UL )
@@ -135,9 +129,6 @@
 #define mainCREATOR_TASK_PRIORITY			( tskIDLE_PRIORITY + 3UL )
 #define mainFLOP_TASK_PRIORITY				( tskIDLE_PRIORITY )

-/* To toggle the single LED */
-#define mainTOGGLE_LED()					( PORT3->OMR =	0x02000200 )
-
 /* A block time of zero simply means "don't block". */
 #define mainDONT_BLOCK						( 0UL )

@@ -183,17 +174,14 @@ xTimerHandle xCheckTimer = NULL;
 	/* Start all the other standard demo/test tasks.  The have not particular
 	functionality, but do demonstrate how to use the FreeRTOS API and test the
 	kernel port. */
-	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vStartQueueSetTasks();
+	vStartQueueOverwriteTask( tskIDLE_PRIORITY );
 	vStartDynamicPriorityTasks();
-	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
 	vCreateBlockTimeTasks();
-	vStartCountingSemaphoreTasks();
 	vStartGenericQueueTasks( tskIDLE_PRIORITY );
 	vStartRecursiveMutexTasks();
-	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
-	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
 	vStartMathTasks( mainFLOP_TASK_PRIORITY );
-	
+
 	/* Create the register check tasks, as described at the top of this
 	file */
 	xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
@@ -206,27 +194,22 @@ xTimerHandle xCheckTimer = NULL;
 								pdTRUE,								/* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
 								( void * ) 0,						/* The ID is not used, so can be set to anything. */
 								prvCheckTimerCallback				/* The callback function that inspects the status of all the other tasks. */
-							  );	
-	
+							  );
+
 	if( xCheckTimer != NULL )
 	{
 		xTimerStart( xCheckTimer, mainDONT_BLOCK );
 	}

-	/* The set of tasks created by the following function call have to be 
-	created last as they keep account of the number of tasks they expect to see 
-	running. */
-	vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
-
 	/* Start the scheduler. */
 	vTaskStartScheduler();
-	
+
 	/* If all is well, the scheduler will now be running, and the following line
 	will never be reached.  If the following line does execute, then there was
 	insufficient FreeRTOS heap memory available for the idle and/or timer tasks
 	to be created.  See the memory management section on the FreeRTOS web site
 	for more details. */
-	for( ;; );	
+	for( ;; );
 }
 /*-----------------------------------------------------------*/

@@ -244,21 +227,11 @@ unsigned long ulErrorFound = pdFALSE;
 		ulErrorFound = pdTRUE;
 	}

-	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
-	{
-		ulErrorFound = pdTRUE;
-	}
-
 	if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
 	{
 		ulErrorFound = pdTRUE;
 	}

-	if( xAreBlockingQueuesStillRunning() != pdTRUE )
-	{
-		ulErrorFound = pdTRUE;
-	}
-
 	if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
 	{
 		ulErrorFound = pdTRUE;
@@ -274,21 +247,16 @@ unsigned long ulErrorFound = pdFALSE;
 		ulErrorFound = pdTRUE;
 	}

-	if( xIsCreateTaskStillRunning() != pdTRUE )
+	if( xAreQueueSetTasksStillRunning() != pdTRUE )
 	{
 		ulErrorFound = pdTRUE;
 	}

-	if( xArePollingQueuesStillRunning() != pdTRUE )
+	if( xIsQueueOverwriteTaskStillRunning() != pdTRUE )
 	{
 		ulErrorFound = pdTRUE;
 	}

-	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
-	{
-		ulErrorFound = pdTRUE;
-	}
-	
 	/* Check that the register test 1 task is still running. */
 	if( ulLastRegTest1Value == ulRegTest1LoopCounter )
 	{
@@ -306,8 +274,8 @@ unsigned long ulErrorFound = pdFALSE;
 	/* Toggle the check LED to give an indication of the system status.  If
 	the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
 	everything is ok.  A faster toggle indicates an error. */
-	mainTOGGLE_LED();	
-	
+	configTOGGLE_LED();
+
 	/* Have any errors been latch in ulErrorFound?  If so, shorten the
 	period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
 	This will result in an increase in the rate at which mainCHECK_LED
@@ -317,7 +285,7 @@ unsigned long ulErrorFound = pdFALSE;
 		if( lChangedTimerPeriodAlready == pdFALSE )
 		{
 			lChangedTimerPeriodAlready = pdTRUE;
-			
+
 			/* This call to xTimerChangePeriod() uses a zero block time.
 			Functions called from inside of a timer callback function must
 			*never* attempt	to block. */
@@ -1,24 +0,0 @@
-@REM This batch file has been generated by the IAR Embedded Workbench
-@REM C-SPY Debugger, as an aid to preparing a command line for running
-@REM the cspybat command line utility using the appropriate settings.
-@REM
-@REM Note that this file is generated every time a new debug session
-@REM is initialized, so you may want to move or rename the file before
-@REM making changes.
-@REM
-@REM You can launch cspybat by typing the name of this batch file followed
-@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
-@REM
-@REM Read about available command line parameters in the C-SPY Debugging
-@REM Guide. Hints about additional command line parameters that may be
-@REM useful in specific cases:
-@REM   --download_only   Downloads a code image without starting a debug
-@REM                     session afterwards.
-@REM   --silent          Omits the sign-on message.
-@REM   --timeout         Limits the maximum allowed execution time.
-@REM 
-
-
-"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armjlink.dll"  %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --macro "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\Infineon\Trace_XMC4500.dmac" --backend -B "--endian=little" "--cpu=Cortex-M4F" "--fpu=VFPv4" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\Infineon\xmc4500.ddf" "--semihosting" "--device=xmc4500" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--drv_catch_exceptions=0x000" "--jlink_script_file=C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\Infineon\XMC4500.jlinkscript" "--drv_swo_clock_setup=72000000,0,2000000" 
-
-
@@ -1,5 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<Project/>
-
-
@@ -1,17 +0,0 @@
-[Stack]
-FillEnabled=0
-OverflowWarningsEnabled=1
-WarningThreshold=90
-SpWarningsEnabled=1
-WarnLogOnly=1
-UseTrigger=1
-TriggerName=main
-LimitSize=0
-ByteLimit=50
-[Disassemble mode]
-mode=0
-[Breakpoints2]
-Count=0
-[Aliases]
-Count=0
-SuppressDialog=0
@@ -1,49 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<Workspace>
-  <ConfigDictionary>
-    
-  <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>
-  <Desktop>
-    <Static>
-      <Workspace>
-        <ColumnWidths>
-          
-          
-          
-          
-        <Column0>124</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
-      </Workspace>
-    <Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build></Static>
-    <Windows>
-      
-    <Wnd2>
-        <Tabs>
-          <Tab>
-            <Identity>TabID-11195-18312</Identity>
-            <TabName>Workspace</TabName>
-            <Factory>Workspace</Factory>
-            <Session>
-              
-            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode></NodeDict></Session>
-          </Tab>
-        </Tabs>
-        
-      <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-6727-18343</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>
-    <Editor>
-      
-      
-      
-      
-    <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>63</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
-    <Positions>
-      
-      
-      
-      
-      
-    <Top><Row0><Sizes><Toolbar-013491e8><key>iaridepm.enu1</key></Toolbar-013491e8></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>198</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
-  </Desktop>
-</Workspace>
-
-
@@ -1,412 +0,0 @@
-/******************************************************************************
- * @file     system_XMC4500.c
- * @brief    Device specific initialization for the XMC4500-Series according to CMSIS
- * @version  V2.2
- * @date     20. January 2012
- *
- * @note
- * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
-
- *
- * @par
- * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.  
- * This file can be freely distributed within development tools that are supporting such microcontrollers. 
-
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- *
- ******************************************************************************/
-
-#include "System_XMC4500.h"
-#include <XMC4500.h>
-
-/*----------------------------------------------------------------------------
-  Define clocks	is located in System_XMC4500.h
- *----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-/*!< System Clock Frequency (Core Clock)*/
-uint32_t SystemCoreClock = CLOCK_OSC_HP;
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-
-
-
-/*--------------------- Watchdog Configuration -------------------------------
-//
-// <e> Watchdog Configuration
-//     <o1.0> Disable Watchdog
-//
-// </e>
-*/
-#define WDT_SETUP               1
-#define WDTENB_nVal             0x00000001
-
-/*--------------------- CLOCK Configuration -------------------------------
-//
-// <e> Main Clock Configuration
-//     <o1.0..1> CPU clock divider
-//                     <0=> fCPU = fSYS 
-//                     <1=> fCPU = fSYS / 2
-//     <o2.0..1>  Peripheral Bus clock divider
-//                     <0=> fPB	= fCPU
-//                     <1=> fPB	= fCPU / 2
-//     <o3.0..1>  CCU Bus clock divider
-//                     <0=> fCCU = fCPU
-//                     <1=> fCCU = fCPU / 2
-//
-// </e>
-// 
-*/
-
-#define SCU_CLOCK_SETUP               1
-#define	SCU_CPUCLKCR_DIV		0x00000000
-#define	SCU_PBCLKCR_DIV		    0x00000000
-#define	SCU_CCUCLKCR_DIV		0x00000000
-
-
-
-/*--------------------- USB CLOCK Configuration ---------------------------
-//
-// <e> USB Clock Configuration
-//
-// </e>
-// 
-*/
-
-#define SCU_USB_CLOCK_SETUP              0
-
-
-/*--------------------- CLOCKOUT Configuration -------------------------------
-//
-// <e> Clock OUT Configuration
-//     <o1.0..1>   Clockout Source Selection
-//                     <0=> System Clock
-//                     <2=> USB Clock
-//                     <3=> Divided value of PLL Clock
-//     <o2.0..1>   Clockout Pin Selection
-//                     <0=> P1.15
-//                     <1=> P0.8
-//                     
-//
-// </e>
-// 
-*/
-
-#define SCU_CLOCKOUT_SETUP              0  // recommended to keep disabled
-#define	SCU_CLOCKOUT_SOURCE		0x00000000
-#define	SCU_CLOCKOUT_PIN		0x00000000
-
-/*----------------------------------------------------------------------------
-  static functions declarations
- *----------------------------------------------------------------------------*/
-#if (SCU_CLOCK_SETUP == 1)
-static int SystemClockSetup(void);
-#endif
-
-#if (SCU_USB_CLOCK_SETUP == 1)
-static void USBClockSetup(void);
-#endif
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the PLL and update the 
-  *         SystemCoreClock variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-/* Setup the WDT */
-#if (WDT_SETUP == 1)
-WDT->CTR &= ~WDTENB_nVal; 
-#endif
-
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
-               (3UL << 11*2)  );               /* set CP11 Full Access */
-#endif
-
-/* Disable branch prediction - PCON.PBS = 1 */
-PREF->PCON |= (PREF_PCON_PBS_Msk);
-
-/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
-SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
-
-/* Setup the clockout */
-/* README README README README README README README README README README */
-/*
- * Please use the CLOCKOUT feature with diligence. Use this only if you know
- * what you are doing.
- *
- * You must be aware that the settings below can potentially be in conflict
- * with DAVE code generation engine preferences.
- *
- * Even worse, the setting below configures the ports as output ports while in
- * reality, the board on which this chip is mounted may have a source driving
- * the ports.
- *
- * So use this feature only when you are absolutely sure that the port must 
- * indeed be configured as an output AND you are NOT linking this startup code
- * with code that was generated by DAVE code engine.
- */
-#if (SCU_CLOCKOUT_SETUP == 1)
-SCU_CLK->EXTCLKCR	|= SCU_CLOCKOUT_SOURCE;
-
-if (SCU_CLOCKOUT_PIN) {
-              PORT0->IOCR8 = 0x00000088;  /*P0.8 --> ALT1 select +  HWSEL */
-              PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
-              }
-else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
-#endif
-
-/* Setup the System clock */ 
-#if (SCU_CLOCK_SETUP == 1)
-SystemClockSetup();
-#endif
-
-/* Setup the USB PL */ 
-#if (SCU_USB_CLOCK_SETUP == 1)
-USBClockSetup();
-#endif
-
-}
-
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  * @note   -  
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/
-
-}
-
-
-/**
-  * @brief  -
-  * @note   -  
-  * @param  None
-  * @retval None
-  */
-#if (SCU_CLOCK_SETUP == 1)
-static int SystemClockSetup(void)
-{
-/* enable PLL first */
-  SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | 
-									                                SCU_PLL_PLLCON0_PLLPWD_Msk);
-
-/* Enable OSC_HP */
-  if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
-  {
-   /* Enable the OSC_HP*/
-   SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4);	 
-   /* Setup OSC WDG devider */
-   SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);         
-   /* Select external OSC as PLL input */
-   SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
-   /* Restart OSC Watchdog */
-   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  
-
-   do 
-   {
-	;  /* here a timeout need to be added */
-   }while(!( (SCU_PLL->PLLSTAT) & 
-					   (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |
-					    SCU_PLL_PLLSTAT_PLLSP_Msk)
-					 )
-         ); 
-
-  }
-
-/* Setup Main PLL */
-   /* Select FOFI as system clock */
-   if(SCU_CLK->SYSCLKCR != 0X000000)
-	  SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/
-
-	 /* Go to bypass the Main PLL */
-   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
-
-	 /* disconnect OSC_HP to PLL */
-   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
-
-	 /* Setup devider settings for main PLL */
-   SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | 
-                                     (PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24));
-
-	 /* we may have to set OSCDISCDIS */
-   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
-
-	 /* connect OSC_HP to PLL */
-   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
-
-	 /* restart PLL Lock detection */
-   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
-
-	 /* wait for PLL Lock */
-   while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk));
-
-	/* Go back to the Main PLL */
-   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
-
-   /*********************************************************
-   here we need to setup the system clock divider
-   *********************************************************/
-
-	SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
-	SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;	
-	SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
-
-   /* Switch system clock to PLL */
-   SCU_CLK->SYSCLKCR |=  0x00010000; 
-															  
-   /*********************************************************
-   here the ramp up of the system clock starts
-   *********************************************************/
-    /* Delay for next K2 step ~50µs */
-   /********************************/
-   /* Set reload register */
-   SysTick->LOAD  = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;
-
-   /* Load the SysTick Counter Value */
-   SysTick->VAL   = 0;                                         
-
-   /* Enable SysTick IRQ and SysTick Timer */
-   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_ENABLE_Msk;                    
-   
-	 /* wait for ~50µs  */
-   while (SysTick->VAL >= 100);								   
-
-   /* Stop SysTick Timer */
-   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 
-   /********************************/
-
-   /* Setup devider settings for main PLL */
-   SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | 
-                                     (PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24));
-
-   /* Delay for next K2 step ~50µs */
-   /********************************/
-   SysTick->LOAD  = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
-
-   /* Load the SysTick Counter Value */
-   SysTick->VAL   = 0;
-
-   /* Enable SysTick IRQ and SysTick Timer */
-   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
-                                                                   
-   /* Wait for ~50µs  */
-   while (SysTick->VAL >= 100);								   
-
-   /* Stop SysTick Timer */
-   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 
-   /********************************/
-
-   /* Setup devider settings for main PLL */
-   SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | 
-									                    (PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24));
-
-   /* Delay for next K2 step ~50µs */
-   /********************************/
-   SysTick->LOAD  = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
-
-   /* Load the SysTick Counter Value */
-   SysTick->VAL   = 0;                                         
-
-   /* Enable SysTick IRQ and SysTick Timer */
-   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
-                                       
-   /* Wait for ~50µs  */
-   while (SysTick->VAL >= 100);								   
-
-   /* Stop SysTick Timer */
-   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 
-   /********************************/
-
-   /* Setup devider settings for main PLL */
-   SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) | 
-                                                               (PLL_PDIV<<24));
-
-	 /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */
-   SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | 
-					                                    SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  
-
-   return(1);
-
-}
-#endif
-
-/**
-  * @brief  -
-  * @note   -  
-  * @param  None
-  * @retval None
-  */
-#if(SCU_USB_CLOCK_SETUP == 1)
-static void USBClockSetup(void)
-{
-/* enable PLL first */
-  SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | 
-									                               SCU_PLL_USBPLLCON_PLLPWD_Msk);
-
-/* check and if not already running enable OSC_HP */
-  if(!((SCU_PLL->PLLSTAT) & 
-			 (SCU_PLL_PLLSTAT_PLLHV_Msk | 
-        SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)))
-  {
-	  if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
-	  {
-	
-	   SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4);	 /*enable the OSC_HP*/
-	   /* setup OSC WDG devider */
-	   SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);         
-	   /* select external OSC as PLL input */
-	   SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
-	   /* restart OSC Watchdog */
-	   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  
-	
-	   do 
-	   {
-		;  /* here a timeout need to be added */
-	   }while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | 
-               SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))); 
-	
-	  }
-  }
-
-
-/* Setup USB PLL */
-   /* Go to bypass the Main PLL */
-   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
-   /* disconnect OSC_FI to PLL */
-   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
-   /* Setup devider settings for main PLL */
-   SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24));
-   /* we may have to set OSCDISCDIS */
-   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
-   /* connect OSC_FI to PLL */
-   SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
-   /* restart PLL Lock detection */
-   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
-   /* wait for PLL Lock */
-   while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
- }
-#endif
@@ -1,445 +0,0 @@
-;*************************************************
-;*
-;* Part one of the system initialization code, contains low-level
-;* initialization, plain thumb variant.
-;*
-;* Copyright 2008 IAR Systems. All rights reserved.
-;*
-;* $Revision: 50748 $
-;*
-;*************************************************
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version with interrupt handler for XMC4500 from Infineon
-;
-
-        MODULE  ?vector_table
-
-        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
-        PRESERVE8
-
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        PUBLIC  __vector_table
-
-        DATA
-
-__iar_init$$done:               ; The vector table is not needed
-                                ; until after copy initialization is done
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     MemManage_Handler
-        DCD     BusFault_Handler
-        DCD     UsageFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     DebugMon_Handler
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-    ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals
-	    DCD   SCU_0_IRQHandler            ; Handler name for SR SCU_0
-	    DCD   ERU0_0_IRQHandler           ; Handler name for SR ERU0_0
-	    DCD   ERU0_1_IRQHandler           ; Handler name for SR ERU0_1
-	    DCD   ERU0_2_IRQHandler           ; Handler name for SR ERU0_2
-	    DCD   ERU0_3_IRQHandler           ; Handler name for SR ERU0_3
-	    DCD   ERU1_0_IRQHandler           ; Handler name for SR ERU1_0
-	    DCD   ERU1_1_IRQHandler           ; Handler name for SR ERU1_1
-	    DCD   ERU1_2_IRQHandler           ; Handler name for SR ERU1_2
-	    DCD   ERU1_3_IRQHandler           ; Handler name for SR ERU1_3
-	    DCD   0                           ; Not Available
-	    DCD   0                           ; Not Available
-	    DCD   0                           ; Not Available
-	    DCD   PMU0_0_IRQHandler           ; Handler name for SR PMU0_0
-	    DCD   0                           ; Not Available
-	    DCD   VADC0_C0_0_IRQHandler       ; Handler name for SR VADC0_C0_0
-	    DCD   VADC0_C0_1_IRQHandler       ; Handler name for SR VADC0_C0_1
-	    DCD   VADC0_C0_2_IRQHandler       ; Handler name for SR VADC0_C0_1
-	    DCD   VADC0_C0_3_IRQHandler       ; Handler name for SR VADC0_C0_3
-	    DCD   VADC0_G0_0_IRQHandler       ; Handler name for SR VADC0_G0_0
-	    DCD   VADC0_G0_1_IRQHandler       ; Handler name for SR VADC0_G0_1
-	    DCD   VADC0_G0_2_IRQHandler       ; Handler name for SR VADC0_G0_2
-	    DCD   VADC0_G0_3_IRQHandler       ; Handler name for SR VADC0_G0_3
-	    DCD   VADC0_G1_0_IRQHandler       ; Handler name for SR VADC0_G1_0
-	    DCD   VADC0_G1_1_IRQHandler       ; Handler name for SR VADC0_G1_1
-	    DCD   VADC0_G1_2_IRQHandler       ; Handler name for SR VADC0_G1_2
-	    DCD   VADC0_G1_3_IRQHandler       ; Handler name for SR VADC0_G1_3
-	    DCD   VADC0_G2_0_IRQHandler       ; Handler name for SR VADC0_G2_0
-	    DCD   VADC0_G2_1_IRQHandler       ; Handler name for SR VADC0_G2_1
-	    DCD   VADC0_G2_2_IRQHandler       ; Handler name for SR VADC0_G2_2
-	    DCD   VADC0_G2_3_IRQHandler       ; Handler name for SR VADC0_G2_3
-	    DCD   VADC0_G3_0_IRQHandler       ; Handler name for SR VADC0_G3_0
-	    DCD   VADC0_G3_1_IRQHandler       ; Handler name for SR VADC0_G3_1
-	    DCD   VADC0_G3_2_IRQHandler       ; Handler name for SR VADC0_G3_2
-	    DCD   VADC0_G3_3_IRQHandler       ; Handler name for SR VADC0_G3_3
-	    DCD   DSD0_0_IRQHandler           ; Handler name for SR DSD0_0
-	    DCD   DSD0_1_IRQHandler           ; Handler name for SR DSD0_1
-	    DCD   DSD0_2_IRQHandler           ; Handler name for SR DSD0_2
-	    DCD   DSD0_3_IRQHandler           ; Handler name for SR DSD0_3
-	    DCD   DSD0_4_IRQHandler           ; Handler name for SR DSD0_4
-	    DCD   DSD0_5_IRQHandler           ; Handler name for SR DSD0_5
-	    DCD   DSD0_6_IRQHandler           ; Handler name for SR DSD0_6
-	    DCD   DSD0_7_IRQHandler           ; Handler name for SR DSD0_7
-	    DCD   DAC0_0_IRQHandler           ; Handler name for SR DAC0_0
-	    DCD   DAC0_1_IRQHandler           ; Handler name for SR DAC0_0
-	    DCD   CCU40_0_IRQHandler          ; Handler name for SR CCU40_0
-	    DCD   CCU40_1_IRQHandler          ; Handler name for SR CCU40_1
-	    DCD   CCU40_2_IRQHandler          ; Handler name for SR CCU40_2
-	    DCD   CCU40_3_IRQHandler          ; Handler name for SR CCU40_3
-	    DCD   CCU41_0_IRQHandler          ; Handler name for SR CCU41_0
-	    DCD   CCU41_1_IRQHandler          ; Handler name for SR CCU41_1
-	    DCD   CCU41_2_IRQHandler          ; Handler name for SR CCU41_2
-	    DCD   CCU41_3_IRQHandler          ; Handler name for SR CCU41_3
-	    DCD   CCU42_0_IRQHandler          ; Handler name for SR CCU42_0
-	    DCD   CCU42_1_IRQHandler          ; Handler name for SR CCU42_1
-	    DCD   CCU42_2_IRQHandler          ; Handler name for SR CCU42_2
-	    DCD   CCU42_3_IRQHandler          ; Handler name for SR CCU42_3
-	    DCD   CCU43_0_IRQHandler          ; Handler name for SR CCU43_0
-	    DCD   CCU43_1_IRQHandler          ; Handler name for SR CCU43_1
-	    DCD   CCU43_2_IRQHandler          ; Handler name for SR CCU43_2
-	    DCD   CCU43_3_IRQHandler          ; Handler name for SR CCU43_3
-	    DCD   CCU80_0_IRQHandler          ; Handler name for SR CCU80_0
-	    DCD   CCU80_1_IRQHandler          ; Handler name for SR CCU80_1
-	    DCD   CCU80_2_IRQHandler          ; Handler name for SR CCU80_2
-	    DCD   CCU80_3_IRQHandler          ; Handler name for SR CCU80_3
-	    DCD   CCU81_0_IRQHandler          ; Handler name for SR CCU81_0
-	    DCD   CCU81_1_IRQHandler          ; Handler name for SR CCU81_1
-	    DCD   CCU81_2_IRQHandler          ; Handler name for SR CCU81_2
-	    DCD   CCU81_3_IRQHandler          ; Handler name for SR CCU81_3
-	    DCD   POSIF0_0_IRQHandler         ; Handler name for SR POSIF0_0
-	    DCD   POSIF0_1_IRQHandler         ; Handler name for SR POSIF0_1
-	    DCD   POSIF1_0_IRQHandler         ; Handler name for SR POSIF1_0
-	    DCD   POSIF1_1_IRQHandler         ; Handler name for SR POSIF1_1
-	    DCD   0                           ; Not Available
-	    DCD   0                           ; Not Available
-	    DCD   0                           ; Not Available
-	    DCD   0                           ; Not Available
-	    DCD   CAN0_0_IRQHandler           ; Handler name for SR CAN0_0
-	    DCD   CAN0_1_IRQHandler           ; Handler name for SR CAN0_1
-	    DCD   CAN0_2_IRQHandler           ; Handler name for SR CAN0_2
-	    DCD   CAN0_3_IRQHandler           ; Handler name for SR CAN0_3
-	    DCD   CAN0_4_IRQHandler           ; Handler name for SR CAN0_4
-	    DCD   CAN0_5_IRQHandler           ; Handler name for SR CAN0_5
-	    DCD   CAN0_6_IRQHandler           ; Handler name for SR CAN0_6
-	    DCD   CAN0_7_IRQHandler           ; Handler name for SR CAN0_7
-	    DCD   USIC0_0_IRQHandler          ; Handler name for SR USIC0_0
-	    DCD   USIC0_1_IRQHandler          ; Handler name for SR USIC0_1
-	    DCD   USIC0_2_IRQHandler          ; Handler name for SR USIC0_2
-	    DCD   USIC0_3_IRQHandler          ; Handler name for SR USIC0_3
-	    DCD   USIC0_4_IRQHandler          ; Handler name for SR USIC0_4
-	    DCD   USIC0_5_IRQHandler          ; Handler name for SR USIC0_5
-	    DCD   USIC1_0_IRQHandler          ; Handler name for SR USIC1_0
-	    DCD   USIC1_1_IRQHandler          ; Handler name for SR USIC1_1
-	    DCD   USIC1_2_IRQHandler          ; Handler name for SR USIC1_2
-	    DCD   USIC1_3_IRQHandler          ; Handler name for SR USIC1_3
-	    DCD   USIC1_4_IRQHandler          ; Handler name for SR USIC1_4
-	    DCD   USIC1_5_IRQHandler          ; Handler name for SR USIC1_5
-	    DCD   USIC2_0_IRQHandler          ; Handler name for SR USIC2_0
-	    DCD   USIC2_1_IRQHandler          ; Handler name for SR USIC2_1
-	    DCD   USIC2_2_IRQHandler          ; Handler name for SR USIC2_2
-	    DCD   USIC2_3_IRQHandler          ; Handler name for SR USIC2_3
-	    DCD   USIC2_4_IRQHandler          ; Handler name for SR USIC2_4
-	    DCD   USIC2_5_IRQHandler          ; Handler name for SR USIC2_5
-	    DCD   LEDTS0_0_IRQHandler         ; Handler name for SR LEDTS0_0
-	    DCD   0                           ; Not Available
-	    DCD   FCE0_0_IRQHandler           ; Handler name for SR FCE0_0
-	    DCD   GPDMA0_0_IRQHandler         ; Handler name for SR GPDMA0_0
-	    DCD   SDMMC0_0_IRQHandler         ; Handler name for SR SDMMC0_0
-	    DCD   USB0_0_IRQHandler           ; Handler name for SR USB0_0
-	    DCD   ETH0_0_IRQHandler           ; Handler name for SR ETH0_0
-	    DCD   0                           ; Not Available
-	    DCD   GPDMA1_0_IRQHandler         ; Handler name for SR GPDMA1_0
-	    DCD   0                           ; Not Available
-
-
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-
-        PUBWEAK NMI_Handler
-        PUBWEAK HardFault_Handler
-        PUBWEAK MemManage_Handler
-        PUBWEAK BusFault_Handler
-        PUBWEAK UsageFault_Handler
-        PUBWEAK SVC_Handler
-        PUBWEAK DebugMon_Handler
-        PUBWEAK PendSV_Handler
-        PUBWEAK SysTick_Handler
-;; XMC4500 interrupt handlers
-      PUBWEAK   SCU_0_IRQHandler
-	    PUBWEAK   ERU0_0_IRQHandler
-	    PUBWEAK   ERU0_1_IRQHandler
-	    PUBWEAK   ERU0_2_IRQHandler
-	    PUBWEAK   ERU0_3_IRQHandler
-	    PUBWEAK   ERU1_0_IRQHandler
-	    PUBWEAK   ERU1_1_IRQHandler
-	    PUBWEAK   ERU1_2_IRQHandler
-	    PUBWEAK   ERU1_3_IRQHandler
-	    PUBWEAK   PMU0_0_IRQHandler
-	    PUBWEAK   PMU0_1_IRQHandler
-	    PUBWEAK   VADC0_C0_0_IRQHandler
-	    PUBWEAK   VADC0_C0_1_IRQHandler
-	    PUBWEAK   VADC0_C0_2_IRQHandler
-	    PUBWEAK   VADC0_C0_3_IRQHandler
-	    PUBWEAK   VADC0_G0_0_IRQHandler
-	    PUBWEAK   VADC0_G0_1_IRQHandler
-	    PUBWEAK   VADC0_G0_2_IRQHandler
-	    PUBWEAK   VADC0_G0_3_IRQHandler
-	    PUBWEAK   VADC0_G1_0_IRQHandler
-	    PUBWEAK   VADC0_G1_1_IRQHandler
-	    PUBWEAK   VADC0_G1_2_IRQHandler
-	    PUBWEAK   VADC0_G1_3_IRQHandler
-	    PUBWEAK   VADC0_G2_0_IRQHandler
-	    PUBWEAK   VADC0_G2_1_IRQHandler
-	    PUBWEAK   VADC0_G2_2_IRQHandler
-	    PUBWEAK   VADC0_G2_3_IRQHandler
-	    PUBWEAK   VADC0_G3_0_IRQHandler
-	    PUBWEAK   VADC0_G3_1_IRQHandler
-	    PUBWEAK   VADC0_G3_2_IRQHandler
-	    PUBWEAK   VADC0_G3_3_IRQHandler
-	    PUBWEAK   DSD0_0_IRQHandler
-	    PUBWEAK   DSD0_1_IRQHandler
-	    PUBWEAK   DSD0_2_IRQHandler
-	    PUBWEAK   DSD0_3_IRQHandler
-	    PUBWEAK   DSD0_4_IRQHandler
-	    PUBWEAK   DSD0_5_IRQHandler
-	    PUBWEAK   DSD0_6_IRQHandler
-	    PUBWEAK   DSD0_7_IRQHandler
-	    PUBWEAK   DAC0_0_IRQHandler
-	    PUBWEAK   DAC0_1_IRQHandler
-	    PUBWEAK   CCU40_0_IRQHandler
-	    PUBWEAK   CCU40_1_IRQHandler
-	    PUBWEAK   CCU40_2_IRQHandler
-	    PUBWEAK   CCU40_3_IRQHandler
-	    PUBWEAK   CCU41_0_IRQHandler
-	    PUBWEAK   CCU41_1_IRQHandler
-	    PUBWEAK   CCU41_2_IRQHandler
-	    PUBWEAK   CCU41_3_IRQHandler
-	    PUBWEAK   CCU42_0_IRQHandler
-	    PUBWEAK   CCU42_1_IRQHandler
-	    PUBWEAK   CCU42_2_IRQHandler
-	    PUBWEAK   CCU42_3_IRQHandler
-	    PUBWEAK   CCU43_0_IRQHandler
-	    PUBWEAK   CCU43_1_IRQHandler
-	    PUBWEAK   CCU43_2_IRQHandler
-	    PUBWEAK   CCU43_3_IRQHandler
-	    PUBWEAK   CCU80_0_IRQHandler
-	    PUBWEAK   CCU80_1_IRQHandler
-	    PUBWEAK   CCU80_2_IRQHandler
-	    PUBWEAK   CCU80_3_IRQHandler
-	    PUBWEAK   CCU81_0_IRQHandler
-	    PUBWEAK   CCU81_1_IRQHandler
-	    PUBWEAK   CCU81_2_IRQHandler
-	    PUBWEAK   CCU81_3_IRQHandler
-	    PUBWEAK   POSIF0_0_IRQHandler
-	    PUBWEAK   POSIF0_1_IRQHandler
-	    PUBWEAK   POSIF1_0_IRQHandler
-	    PUBWEAK   POSIF1_1_IRQHandler
-	    PUBWEAK   CAN0_0_IRQHandler
-	    PUBWEAK   CAN0_1_IRQHandler
-	    PUBWEAK   CAN0_2_IRQHandler
-	    PUBWEAK   CAN0_3_IRQHandler
-	    PUBWEAK   CAN0_4_IRQHandler
-	    PUBWEAK   CAN0_5_IRQHandler
-	    PUBWEAK   CAN0_6_IRQHandler
-	    PUBWEAK   CAN0_7_IRQHandler
-	    PUBWEAK   USIC0_0_IRQHandler
-	    PUBWEAK   USIC0_1_IRQHandler
-	    PUBWEAK   USIC0_2_IRQHandler
-	    PUBWEAK   USIC0_3_IRQHandler
-	    PUBWEAK   USIC0_4_IRQHandler
-	    PUBWEAK   USIC0_5_IRQHandler
-	    PUBWEAK   USIC1_0_IRQHandler
-	    PUBWEAK   USIC1_1_IRQHandler
-	    PUBWEAK   USIC1_2_IRQHandler
-	    PUBWEAK   USIC1_3_IRQHandler
-	    PUBWEAK   USIC1_4_IRQHandler
-	    PUBWEAK   USIC1_5_IRQHandler
-	    PUBWEAK   USIC2_0_IRQHandler
-	    PUBWEAK   USIC2_1_IRQHandler
-	    PUBWEAK   USIC2_2_IRQHandler
-	    PUBWEAK   USIC2_3_IRQHandler
-	    PUBWEAK   USIC2_4_IRQHandler
-	    PUBWEAK   USIC2_5_IRQHandler
-	    PUBWEAK   LEDTS0_0_IRQHandler
-	    PUBWEAK   FCE0_0_IRQHandler
-	    PUBWEAK   GPDMA0_0_IRQHandler
-	    PUBWEAK   SDMMC0_0_IRQHandler
-	    PUBWEAK   USB0_0_IRQHandler
-	    PUBWEAK   ETH0_0_IRQHandler
-	    PUBWEAK   GPDMA1_0_IRQHandler
-
-        SECTION .text:CODE:REORDER(2)
-        THUMB
-
-NMI_Handler
-HardFault_Handler
-MemManage_Handler
-BusFault_Handler
-UsageFault_Handler
-SVC_Handler
-DebugMon_Handler
-PendSV_Handler
-SysTick_Handler
-
-SCU_0_IRQHandler
-ERU0_0_IRQHandler
-ERU0_1_IRQHandler
-ERU0_2_IRQHandler
-ERU0_3_IRQHandler
-ERU1_0_IRQHandler
-ERU1_1_IRQHandler
-ERU1_2_IRQHandler
-ERU1_3_IRQHandler
-PMU0_0_IRQHandler
-PMU0_1_IRQHandler
-VADC0_C0_0_IRQHandler
-VADC0_C0_1_IRQHandler
-VADC0_C0_2_IRQHandler
-VADC0_C0_3_IRQHandler
-VADC0_G0_0_IRQHandler
-VADC0_G0_1_IRQHandler
-VADC0_G0_2_IRQHandler
-VADC0_G0_3_IRQHandler
-VADC0_G1_0_IRQHandler
-VADC0_G1_1_IRQHandler
-VADC0_G1_2_IRQHandler
-VADC0_G1_3_IRQHandler
-VADC0_G2_0_IRQHandler
-VADC0_G2_1_IRQHandler
-VADC0_G2_2_IRQHandler
-VADC0_G2_3_IRQHandler
-VADC0_G3_0_IRQHandler
-VADC0_G3_1_IRQHandler
-VADC0_G3_2_IRQHandler
-VADC0_G3_3_IRQHandler
-DSD0_0_IRQHandler
-DSD0_1_IRQHandler
-DSD0_2_IRQHandler
-DSD0_3_IRQHandler
-DSD0_4_IRQHandler
-DSD0_5_IRQHandler
-DSD0_6_IRQHandler
-DSD0_7_IRQHandler
-DAC0_0_IRQHandler
-DAC0_1_IRQHandler
-CCU40_0_IRQHandler
-CCU40_1_IRQHandler
-CCU40_2_IRQHandler
-CCU40_3_IRQHandler
-CCU41_0_IRQHandler
-CCU41_1_IRQHandler
-CCU41_2_IRQHandler
-CCU41_3_IRQHandler
-CCU42_0_IRQHandler
-CCU42_1_IRQHandler
-CCU42_2_IRQHandler
-CCU42_3_IRQHandler
-CCU43_0_IRQHandler
-CCU43_1_IRQHandler
-CCU43_2_IRQHandler
-CCU43_3_IRQHandler
-CCU80_0_IRQHandler
-CCU80_1_IRQHandler
-CCU80_2_IRQHandler
-CCU80_3_IRQHandler
-CCU81_0_IRQHandler
-CCU81_1_IRQHandler
-CCU81_2_IRQHandler
-CCU81_3_IRQHandler
-POSIF0_0_IRQHandler
-POSIF0_1_IRQHandler
-POSIF1_0_IRQHandler
-POSIF1_1_IRQHandler
-CAN0_0_IRQHandler
-CAN0_1_IRQHandler
-CAN0_2_IRQHandler
-CAN0_3_IRQHandler
-CAN0_4_IRQHandler
-CAN0_5_IRQHandler
-CAN0_6_IRQHandler
-CAN0_7_IRQHandler
-USIC0_0_IRQHandler
-USIC0_1_IRQHandler
-USIC0_2_IRQHandler
-USIC0_3_IRQHandler
-USIC0_4_IRQHandler
-USIC0_5_IRQHandler
-USIC1_0_IRQHandler
-USIC1_1_IRQHandler
-USIC1_2_IRQHandler
-USIC1_3_IRQHandler
-USIC1_4_IRQHandler
-USIC1_5_IRQHandler
-USIC2_0_IRQHandler
-USIC2_1_IRQHandler
-USIC2_2_IRQHandler
-USIC2_3_IRQHandler
-USIC2_4_IRQHandler
-USIC2_5_IRQHandler
-LEDTS0_0_IRQHandler
-FCE0_0_IRQHandler
-GPDMA0_0_IRQHandler
-SDMMC0_0_IRQHandler
-USB0_0_IRQHandler
-ETH0_0_IRQHandler
-GPDMA1_0_IRQHandler
-
-Default_Handler
-        NOCALL Default_Handler
-        B Default_Handler
-
-PREF_PCON       EQU 0x58004000
-SCU_GCU_PEEN    EQU 0x5000413C
-SCU_GCU_PEFLAG  EQU 0x50004150
-
-        SECTION .text:CODE:REORDER(2)
-        THUMB
-Reset_Handler:
-        ; A11 workaround for branch prediction and parity
-        LDR R0,=PREF_PCON        /* switch off branch prediction required in A11 step to use cached memory*/
-        LDR R1,[R0]
-        ORR R1,R1,#0x00010000
-        STR R1,[R0]
-
-        /* Clear existing parity errors if any required in A11 step */
-        LDR R0,=SCU_GCU_PEFLAG
-        MOV R1,#0xFFFFFFFF
-        STR R1,[R0]
-
-        /* Disable parity  required in A11 step*/
-        LDR R0,=SCU_GCU_PEEN
-        MOV R1,#0
-        STR R1,[R0]
-        B __iar_program_start
-        
-        END
@@ -1,60 +0,0 @@
-/**************************************************
- *
- * This module contains the function `__low_level_init', a function
- * that is called before the `main' function of the program.  Normally
- * low-level initializations - such as setting the prefered interrupt
- * level or setting the watchdog - can be performed here.
- *
- * Note that this function is called before the data segments are
- * initialized, this means that this function cannot rely on the
- * values of global or static variables.
- *
- * When this function returns zero, the startup code will inhibit the
- * initialization of the data segments. The result is faster startup,
- * the drawback is that neither global nor static data will be
- * initialized.
- *
- * Copyright 1999-2004 IAR Systems. All rights reserved.
- *
- * $Revision: 50082 $
- *
- **************************************************/
-
- 
- 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "System_XMC4500.h"
-
-#pragma language=extended
-
-__interwork int __low_level_init(void);
-
-__interwork int __low_level_init(void)
-{
-  /*==================================*/
-  /*  Initialize hardware.            */
-  /*==================================*/
-
-  /*==================================*/
-  /* Choose if segment initialization */
-  /* should be done or not.           */
-  /* Return: 0 to omit seg_init       */
-  /*         1 to run seg_init        */
-  /*==================================*/
-  
-  
-  /* Init clock Sys clk 96MHz, MCU clk 96MHz, PB clk 48MHz */
-  SystemInit();
-  
-  
-  return 1;
-}
-
-#pragma language=default
-
-#ifdef __cplusplus
-}
-#endif
@@ -0,0 +1,358 @@
+/*****************************************************************************/
+/* Startup_XMC4200.s: Startup file for XMC4200 device series for EWARM                */
+/*****************************************************************************/
+/*
+* @file     Startup_XMC4200.s
+*           XMC4000 Device Series
+* @version  V1.0
+* @date     Jan 2013
+*
+* Copyright (C) 2012 IAR Systems. All rights reserved.
+* Copyright (C) 2012 Infineon Technologies AG. All rights reserved.
+*
+*
+* @par
+* Infineon Technologies AG (Infineon) is supplying this software for use with
+* Infineon's microcontrollers.  This file can be freely distributed
+* within development tools that are supporting such microcontrollers.
+*
+* @par
+* THIS SOFTWARE IS PROVIDED AS IS.  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+*
+******************************************************************************/
+/* ********************* Version History *********************************** */
+/* ***************************************************************************
+V1.0 January, 30 2013:  In ths version a workoraound for the erratum PMU_CM.001
+is implmented (patch for the Exception and interrupt handlers)
+
+**************************************************************************** */
+
+        MODULE  ?vector_table
+
+        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
+        PRESERVE8
+
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+
+__iar_init$$done:               ; The vector table is not needed
+                                ; until after copy initialization is done
+
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
+;/*
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
+; * A veneer defined below will first be executed which in turn branches to the final
+; * exception handler.
+; *
+; * In addition to defining the veneers, the vector table must for these buggy
+; * devices contain the veneers.
+; */
+
+;set WORKAROUND_PMU_CM001 under Options for target
+;Initialize varaible WORKAROUND_PMU_CM001 as FALSE
+WORKAROUND_PMU_CM001 SET 1
+
+;/* A macro to setup a vector table entry based on STEP ID */
+#ifdef WORKAROUND_PMU_CM001
+ExcpVector  macro
+            DCD \1_Veneer
+            endm
+#else
+ExcpVector  macro
+            DCD \1
+            endm
+#endif
+
+;/* A macro to ease definition of the various handlers based on STEP ID */
+#ifdef WORKAROUND_PMU_CM001
+;/* First define the final exception handler */
+ProxyHandler  macro
+              PUBWEAK \1
+              SECTION .text:CODE:REORDER:NOROOT(1)
+\1
+              B \1
+              endm
+;/* And then define a veneer that will branch to the final excp handler */
+ProxyHandler_Veneer  macro
+              PUBWEAK \1
+              SECTION .text:CODE:REORDER:NOROOT(2)
+\1
+              LDR   R0, =ProxyHandler
+              PUSH	{LR}
+              BLX   R0
+              POP   {PC}
+              endm
+ ;/* No prefetch bug, hence define only the final exception handler */
+#else
+ProxyHandler  macro
+              PUBWEAK \1
+              SECTION .text:CODE:REORDER:NOROOT(1)
+\1
+              B \1
+              endm
+#endif
+
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
+
+__vector_table
+    DCD   sfe(CSTACK)
+    DCD   Reset_Handler          	    ; Reset Handler
+
+    ExcpVector   NMI_Handler                 ; NMI Handler
+    ExcpVector   HardFault_Handler           ; Hard Fault Handler
+    ExcpVector   MemManage_Handler           ; MPU Fault Handler
+    ExcpVector   BusFault_Handler            ; Bus Fault Handler
+    ExcpVector   UsageFault_Handler          ; Usage Fault Handler
+    DCD   0                           ; Reserved
+    DCD   0                           ; Reserved
+    DCD   0                           ; Reserved
+    DCD   0                           ; Reserved
+    DCD          SVC_Handler                 ; SVCall Handler
+    DCD          DebugMon_Handler            ; Debug Monitor Handler
+    DCD   0                           ; Reserved
+    ExcpVector   PendSV_Handler              ; PendSV Handler
+    DCD          SysTick_Handler             ; SysTick Handler
+
+    ; Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals
+    ExcpVector   SCU_0_IRQHandler            ; Handler name for SR SCU_0
+    ExcpVector   ERU0_0_IRQHandler           ; Handler name for SR ERU0_0
+    ExcpVector   ERU0_1_IRQHandler           ; Handler name for SR ERU0_1
+    ExcpVector   ERU0_2_IRQHandler           ; Handler name for SR ERU0_2
+    ExcpVector   ERU0_3_IRQHandler           ; Handler name for SR ERU0_3
+    ExcpVector   ERU1_0_IRQHandler           ; Handler name for SR ERU1_0
+    ExcpVector   ERU1_1_IRQHandler           ; Handler name for SR ERU1_1
+    ExcpVector   ERU1_2_IRQHandler           ; Handler name for SR ERU1_2
+    ExcpVector   ERU1_3_IRQHandler           ; Handler name for SR ERU1_3
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    ExcpVector   PMU0_0_IRQHandler           ; Handler name for SR PMU0_0
+    DCD   0                           ; Not Available
+    ExcpVector   VADC0_C0_0_IRQHandler       ; Handler name for SR VADC0_C0_0
+    ExcpVector   VADC0_C0_1_IRQHandler       ; Handler name for SR VADC0_C0_1
+    ExcpVector   VADC0_C0_2_IRQHandler       ; Handler name for SR VADC0_C0_1
+    ExcpVector   VADC0_C0_3_IRQHandler       ; Handler name for SR VADC0_C0_3
+    ExcpVector   VADC0_G0_0_IRQHandler       ; Handler name for SR VADC0_G0_0
+    ExcpVector   VADC0_G0_1_IRQHandler       ; Handler name for SR VADC0_G0_1
+    ExcpVector   VADC0_G0_2_IRQHandler       ; Handler name for SR VADC0_G0_2
+    ExcpVector   VADC0_G0_3_IRQHandler       ; Handler name for SR VADC0_G0_3
+    ExcpVector   VADC0_G1_0_IRQHandler       ; Handler name for SR VADC0_G1_0
+    ExcpVector   VADC0_G1_1_IRQHandler       ; Handler name for SR VADC0_G1_1
+    ExcpVector   VADC0_G1_2_IRQHandler       ; Handler name for SR VADC0_G1_2
+    ExcpVector   VADC0_G1_3_IRQHandler       ; Handler name for SR VADC0_G1_3
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    ExcpVector   DAC0_0_IRQHandler           ; Handler name for SR DAC0_0
+    ExcpVector   DAC0_1_IRQHandler           ; Handler name for SR DAC0_1
+    ExcpVector   CCU40_0_IRQHandler          ; Handler name for SR CCU40_0
+    ExcpVector   CCU40_1_IRQHandler          ; Handler name for SR CCU40_1
+    ExcpVector   CCU40_2_IRQHandler          ; Handler name for SR CCU40_2
+    ExcpVector   CCU40_3_IRQHandler          ; Handler name for SR CCU40_3
+    ExcpVector   CCU41_0_IRQHandler          ; Handler name for SR CCU41_0
+    ExcpVector   CCU41_1_IRQHandler          ; Handler name for SR CCU41_1
+    ExcpVector   CCU41_2_IRQHandler          ; Handler name for SR CCU41_2
+    ExcpVector   CCU41_3_IRQHandler          ; Handler name for SR CCU41_3
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    ExcpVector   CCU80_0_IRQHandler          ; Handler name for SR CCU80_0
+    ExcpVector   CCU80_1_IRQHandler          ; Handler name for SR CCU80_1
+    ExcpVector   CCU80_2_IRQHandler          ; Handler name for SR CCU80_2
+    ExcpVector   CCU80_3_IRQHandler          ; Handler name for SR CCU80_3
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    ExcpVector   POSIF0_0_IRQHandler         ; Handler name for SR POSIF0_0
+    ExcpVector   POSIF0_1_IRQHandler         ; Handler name for SR POSIF0_1
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    ExcpVector   HRPWM_0_IRQHandler          ; Handler name for SR HRPWM_0
+    ExcpVector   HRPWM_1_IRQHandler          ; Handler name for SR HRPWM_1
+    ExcpVector   HRPWM_2_IRQHandler          ; Handler name for SR HRPWM_2
+    ExcpVector   HRPWM_3_IRQHandler          ; Handler name for SR HRPWM_3
+    ExcpVector   CAN0_0_IRQHandler           ; Handler name for SR CAN0_0
+    ExcpVector   CAN0_1_IRQHandler           ; Handler name for SR CAN0_1
+    ExcpVector   CAN0_2_IRQHandler           ; Handler name for SR CAN0_2
+    ExcpVector   CAN0_3_IRQHandler           ; Handler name for SR CAN0_3
+    ExcpVector   CAN0_4_IRQHandler           ; Handler name for SR CAN0_4
+    ExcpVector   CAN0_5_IRQHandler           ; Handler name for SR CAN0_5
+    ExcpVector   CAN0_6_IRQHandler           ; Handler name for SR CAN0_6
+    ExcpVector   CAN0_7_IRQHandler           ; Handler name for SR CAN0_7
+    ExcpVector   USIC0_0_IRQHandler          ; Handler name for SR USIC0_0
+    ExcpVector   USIC0_1_IRQHandler          ; Handler name for SR USIC0_1
+    ExcpVector   USIC0_2_IRQHandler          ; Handler name for SR USIC0_2
+    ExcpVector   USIC0_3_IRQHandler          ; Handler name for SR USIC0_3
+    ExcpVector   USIC0_4_IRQHandler          ; Handler name for SR USIC0_4
+    ExcpVector   USIC0_5_IRQHandler          ; Handler name for SR USIC0_5
+    ExcpVector   USIC1_0_IRQHandler          ; Handler name for SR USIC1_0
+    ExcpVector   USIC1_1_IRQHandler          ; Handler name for SR USIC1_1
+    ExcpVector   USIC1_2_IRQHandler          ; Handler name for SR USIC1_2
+    ExcpVector   USIC1_3_IRQHandler          ; Handler name for SR USIC1_3
+    ExcpVector   USIC1_4_IRQHandler          ; Handler name for SR USIC1_4
+    ExcpVector   USIC1_5_IRQHandler          ; Handler name for SR USIC1_5
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    ExcpVector   LEDTS0_0_IRQHandler         ; Handler name for SR LEDTS0_0
+    DCD   0                           ; Not Available
+    ExcpVector   FCE0_0_IRQHandler           ; Handler name for SR FCE0_0
+    ExcpVector   GPDMA0_0_IRQHandler         ; Handler name for SR GPDMA0_0
+    DCD   0                           ; Not Available
+    ExcpVector   USB0_0_IRQHandler           ; Handler name for SR USB0_0
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =SystemInit_DAVE3
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+
+        ProxyHandler NMI_Handler
+        ProxyHandler HardFault_Handler
+        ProxyHandler MemManage_Handler
+        ProxyHandler BusFault_Handler
+        ProxyHandler UsageFault_Handler
+        ProxyHandler SVC_Handler
+        ProxyHandler DebugMon_Handler
+        ProxyHandler PendSV_Handler
+        ProxyHandler SysTick_Handler
+
+        ProxyHandler SCU_0_IRQHandler
+        ProxyHandler ERU0_0_IRQHandler
+        ProxyHandler ERU0_1_IRQHandler
+        ProxyHandler ERU0_2_IRQHandler
+        ProxyHandler ERU0_3_IRQHandler
+        ProxyHandler ERU1_0_IRQHandler
+        ProxyHandler ERU1_1_IRQHandler
+        ProxyHandler ERU1_2_IRQHandler
+        ProxyHandler ERU1_3_IRQHandler
+        ProxyHandler PMU0_0_IRQHandler
+        ProxyHandler VADC0_C0_0_IRQHandler
+        ProxyHandler VADC0_C0_1_IRQHandler
+        ProxyHandler VADC0_C0_2_IRQHandler
+        ProxyHandler VADC0_C0_3_IRQHandler
+        ProxyHandler VADC0_G0_0_IRQHandler
+        ProxyHandler VADC0_G0_1_IRQHandler
+        ProxyHandler VADC0_G0_2_IRQHandler
+        ProxyHandler VADC0_G0_3_IRQHandler
+        ProxyHandler VADC0_G1_0_IRQHandler
+        ProxyHandler VADC0_G1_1_IRQHandler
+        ProxyHandler VADC0_G1_2_IRQHandler
+        ProxyHandler VADC0_G1_3_IRQHandler
+        ProxyHandler DAC0_0_IRQHandler
+        ProxyHandler DAC0_1_IRQHandler
+        ProxyHandler CCU40_0_IRQHandler
+        ProxyHandler CCU40_1_IRQHandler
+        ProxyHandler CCU40_2_IRQHandler
+        ProxyHandler CCU40_3_IRQHandler
+        ProxyHandler CCU41_0_IRQHandler
+        ProxyHandler CCU41_1_IRQHandler
+        ProxyHandler CCU41_2_IRQHandler
+        ProxyHandler CCU41_3_IRQHandler
+        ProxyHandler CCU80_0_IRQHandler
+        ProxyHandler CCU80_1_IRQHandler
+        ProxyHandler CCU80_2_IRQHandler
+        ProxyHandler CCU80_3_IRQHandler
+        ProxyHandler POSIF0_0_IRQHandler
+        ProxyHandler POSIF0_1_IRQHandler
+        ProxyHandler HRPWM_0_IRQHandler
+        ProxyHandler HRPWM_1_IRQHandler
+        ProxyHandler HRPWM_2_IRQHandler
+        ProxyHandler HRPWM_3_IRQHandler
+        ProxyHandler CAN0_0_IRQHandler
+        ProxyHandler CAN0_1_IRQHandler
+        ProxyHandler CAN0_2_IRQHandler
+        ProxyHandler CAN0_3_IRQHandler
+        ProxyHandler CAN0_4_IRQHandler
+        ProxyHandler CAN0_5_IRQHandler
+        ProxyHandler CAN0_6_IRQHandler
+        ProxyHandler CAN0_7_IRQHandler
+        ProxyHandler USIC0_0_IRQHandler
+        ProxyHandler USIC0_1_IRQHandler
+        ProxyHandler USIC0_2_IRQHandler
+        ProxyHandler USIC0_3_IRQHandler
+        ProxyHandler USIC0_4_IRQHandler
+        ProxyHandler USIC0_5_IRQHandler
+        ProxyHandler USIC1_0_IRQHandler
+        ProxyHandler USIC1_1_IRQHandler
+        ProxyHandler USIC1_2_IRQHandler
+        ProxyHandler USIC1_3_IRQHandler
+        ProxyHandler USIC1_4_IRQHandler
+        ProxyHandler USIC1_5_IRQHandler
+        ProxyHandler LEDTS0_0_IRQHandler
+        ProxyHandler FCE0_0_IRQHandler
+        ProxyHandler GPDMA0_0_IRQHandler
+        ProxyHandler USB0_0_IRQHandler
+
+; Definition of the default weak SystemInit_DAVE3 function for DAVE3 system init.
+        PUBWEAK SystemInit_DAVE3
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SystemInit_DAVE3
+        NOP
+        BX LR
+
+; Definition of the default weak DAVE3 function for clock App usage.
+; AllowPLLInitByStartup Handler
+        PUBWEAK AllowPLLInitByStartup
+        SECTION .text:CODE:REORDER:NOROOT(2)
+AllowPLLInitByStartup
+        MOV R0,#1
+        BX LR
+
+PREF_PCON       EQU 0x58004000
+SCU_GCU_PEEN    EQU 0x5000413C
+SCU_GCU_PEFLAG  EQU 0x50004150
+
+
+        END
@@ -0,0 +1,391 @@
+/*****************************************************************************/
+/* Startup_XMC4400.s: Startup file for XMC4400 device series for EWARM                */
+/*****************************************************************************/
+/**
+* @file     Startup_XMC4400.s
+*           XMC4000 Device Series
+* @version  V1.0
+* @date     Jan 2013
+*
+* Copyright (C) 2012 IAR Systems. All rights reserved.
+* Copyright (C) 2012 Infineon Technologies AG. All rights reserved.
+*
+*
+* @par
+* Infineon Technologies AG (Infineon) is supplying this software for use with
+* Infineon's microcontrollers.  This file can be freely distributed
+* within development tools that are supporting such microcontrollers.
+*
+* @par
+* THIS SOFTWARE IS PROVIDED AS IS.  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+*
+******************************************************************************/
+/* ********************* Version History *********************************** */
+/* ***************************************************************************
+V1.0 January, 30 2013:  In ths version a workoraound for the erratum PMU_CM.001
+is implmented (patch for the Exception and interrupt handlers)
+
+**************************************************************************** */
+
+        MODULE  ?vector_table
+
+        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
+        PRESERVE8
+
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+
+__iar_init$$done:               ; The vector table is not needed
+                                ; until after copy initialization is done
+
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
+;/*
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
+; * A veneer defined below will first be executed which in turn branches to the final
+; * exception handler.
+; *
+; * In addition to defining the veneers, the vector table must for these buggy
+; * devices contain the veneers.
+; */
+
+;set WORKAROUND_PMU_CM001 under Options for target
+;Initialize varaible WORKAROUND_PMU_CM001 as FALSE
+WORKAROUND_PMU_CM001 SET 1
+
+;/* A macro to setup a vector table entry based on STEP ID */
+#ifdef WORKAROUND_PMU_CM001
+ExcpVector  macro
+            DCD \1_Veneer
+            endm
+#else
+ExcpVector  macro
+            DCD \1
+            endm
+#endif
+
+;/* A macro to ease definition of the various handlers based on STEP ID */
+#ifdef WORKAROUND_PMU_CM001
+;/* First define the final exception handler */
+ProxyHandler  macro
+              PUBWEAK \1
+              SECTION .text:CODE:REORDER:NOROOT(1)
+\1
+              B \1
+              endm
+;/* And then define a veneer that will branch to the final excp handler */
+ProxyHandler_Veneer  macro
+              PUBWEAK \1
+              SECTION .text:CODE:REORDER:NOROOT(2)
+\1
+              LDR   R0, =ProxyHandler
+              PUSH	{LR}
+              BLX   R0
+              POP   {PC}
+              endm
+ ;/* No prefetch bug, hence define only the final exception handler */
+#else
+ProxyHandler  macro
+              PUBWEAK \1
+              SECTION .text:CODE:REORDER:NOROOT(1)
+\1
+              B \1
+              endm
+#endif
+
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
+
+__vector_table
+    DCD   sfe(CSTACK)
+    DCD   Reset_Handler          	    ; Reset Handler
+
+    ExcpVector   NMI_Handler                 ; NMI Handler
+    ExcpVector   HardFault_Handler           ; Hard Fault Handler
+    ExcpVector   MemManage_Handler           ; MPU Fault Handler
+    ExcpVector   BusFault_Handler            ; Bus Fault Handler
+    ExcpVector   UsageFault_Handler          ; Usage Fault Handler
+    DCD   0                           ; Reserved
+    DCD   0                           ; Reserved
+    DCD   0                           ; Reserved
+    DCD   0                           ; Reserved
+    DCD          SVC_Handler                 ; SVCall Handler
+    ExcpVector   DebugMon_Handler            ; Debug Monitor Handler
+    DCD   0                           ; Reserved
+    DCD          PendSV_Handler              ; PendSV Handler
+    DCD          SysTick_Handler             ; SysTick Handler
+
+    ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals
+	  ExcpVector   SCU_0_IRQHandler            ; Handler name for SR SCU_0
+    ExcpVector   ERU0_0_IRQHandler           ; Handler name for SR ERU0_0
+    ExcpVector   ERU0_1_IRQHandler           ; Handler name for SR ERU0_1
+    ExcpVector   ERU0_2_IRQHandler           ; Handler name for SR ERU0_2
+    ExcpVector   ERU0_3_IRQHandler           ; Handler name for SR ERU0_3
+    ExcpVector   ERU1_0_IRQHandler           ; Handler name for SR ERU1_0
+    ExcpVector   ERU1_1_IRQHandler           ; Handler name for SR ERU1_1
+    ExcpVector   ERU1_2_IRQHandler           ; Handler name for SR ERU1_2
+    ExcpVector   ERU1_3_IRQHandler           ; Handler name for SR ERU1_3
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    ExcpVector   PMU0_0_IRQHandler           ; Handler name for SR PMU0_0
+    DCD   0                           ; Not Available
+    ExcpVector   VADC0_C0_0_IRQHandler       ; Handler name for SR VADC0_C0_0
+    ExcpVector   VADC0_C0_1_IRQHandler       ; Handler name for SR VADC0_C0_1
+    ExcpVector   VADC0_C0_2_IRQHandler       ; Handler name for SR VADC0_C0_1
+    ExcpVector   VADC0_C0_3_IRQHandler       ; Handler name for SR VADC0_C0_3
+    ExcpVector   VADC0_G0_0_IRQHandler       ; Handler name for SR VADC0_G0_0
+    ExcpVector   VADC0_G0_1_IRQHandler       ; Handler name for SR VADC0_G0_1
+    ExcpVector   VADC0_G0_2_IRQHandler       ; Handler name for SR VADC0_G0_2
+    ExcpVector   VADC0_G0_3_IRQHandler       ; Handler name for SR VADC0_G0_3
+    ExcpVector   VADC0_G1_0_IRQHandler       ; Handler name for SR VADC0_G1_0
+    ExcpVector   VADC0_G1_1_IRQHandler       ; Handler name for SR VADC0_G1_1
+    ExcpVector   VADC0_G1_2_IRQHandler       ; Handler name for SR VADC0_G1_2
+    ExcpVector   VADC0_G1_3_IRQHandler       ; Handler name for SR VADC0_G1_3
+    ExcpVector   VADC0_G2_0_IRQHandler       ; Handler name for SR VADC0_G2_0
+    ExcpVector   VADC0_G2_1_IRQHandler       ; Handler name for SR VADC0_G2_1
+    ExcpVector   VADC0_G2_2_IRQHandler       ; Handler name for SR VADC0_G2_2
+    ExcpVector   VADC0_G2_3_IRQHandler       ; Handler name for SR VADC0_G2_3
+    ExcpVector   VADC0_G3_0_IRQHandler       ; Handler name for SR VADC0_G3_0
+    ExcpVector   VADC0_G3_1_IRQHandler       ; Handler name for SR VADC0_G3_1
+    ExcpVector   VADC0_G3_2_IRQHandler       ; Handler name for SR VADC0_G3_2
+    ExcpVector   VADC0_G3_3_IRQHandler       ; Handler name for SR VADC0_G3_3
+    ExcpVector   DSD0_0_IRQHandler           ; Handler name for SR DSD_SRM_0
+    ExcpVector   DSD0_1_IRQHandler           ; Handler name for SR DSD_SRM_1
+    ExcpVector   DSD0_2_IRQHandler           ; Handler name for SR DSD_SRM_2
+    ExcpVector   DSD0_3_IRQHandler           ; Handler name for SR DSD_SRM_3
+    ExcpVector   DSD0_4_IRQHandler           ; Handler name for SR DSD_SRA_0
+    ExcpVector   DSD0_5_IRQHandler           ; Handler name for SR DSD_SRA_1
+    ExcpVector   DSD0_6_IRQHandler           ; Handler name for SR DSD_SRA_2
+    ExcpVector   DSD0_7_IRQHandler           ; Handler name for SR DSD_SRA_3
+    ExcpVector   DAC0_0_IRQHandler           ; Handler name for SR DAC0_0
+    ExcpVector   DAC0_1_IRQHandler           ; Handler name for SR DAC0_1
+    ExcpVector   CCU40_0_IRQHandler          ; Handler name for SR CCU40_0
+    ExcpVector   CCU40_1_IRQHandler          ; Handler name for SR CCU40_1
+    ExcpVector   CCU40_2_IRQHandler          ; Handler name for SR CCU40_2
+    ExcpVector   CCU40_3_IRQHandler          ; Handler name for SR CCU40_3
+    ExcpVector   CCU41_0_IRQHandler          ; Handler name for SR CCU41_0
+    ExcpVector   CCU41_1_IRQHandler          ; Handler name for SR CCU41_1
+    ExcpVector   CCU41_2_IRQHandler          ; Handler name for SR CCU41_2
+    ExcpVector   CCU41_3_IRQHandler          ; Handler name for SR CCU41_3
+    ExcpVector   CCU42_0_IRQHandler          ; Handler name for SR CCU42_0
+    ExcpVector   CCU42_1_IRQHandler          ; Handler name for SR CCU42_1
+    ExcpVector   CCU42_2_IRQHandler          ; Handler name for SR CCU42_2
+    ExcpVector   CCU42_3_IRQHandler          ; Handler name for SR CCU42_3
+    ExcpVector   CCU43_0_IRQHandler          ; Handler name for SR CCU43_0
+    ExcpVector   CCU43_1_IRQHandler          ; Handler name for SR CCU43_1
+    ExcpVector   CCU43_2_IRQHandler          ; Handler name for SR CCU43_2
+    ExcpVector   CCU43_3_IRQHandler          ; Handler name for SR CCU43_3
+    ExcpVector   CCU80_0_IRQHandler          ; Handler name for SR CCU80_0
+    ExcpVector   CCU80_1_IRQHandler          ; Handler name for SR CCU80_1
+    ExcpVector   CCU80_2_IRQHandler          ; Handler name for SR CCU80_2
+    ExcpVector   CCU80_3_IRQHandler          ; Handler name for SR CCU80_3
+    ExcpVector   CCU81_0_IRQHandler          ; Handler name for SR CCU81_0
+    ExcpVector   CCU81_1_IRQHandler          ; Handler name for SR CCU81_1
+    ExcpVector   CCU81_2_IRQHandler          ; Handler name for SR CCU81_2
+    ExcpVector   CCU81_3_IRQHandler          ; Handler name for SR CCU81_3
+    ExcpVector   POSIF0_0_IRQHandler         ; Handler name for SR POSIF0_0
+    ExcpVector   POSIF0_1_IRQHandler         ; Handler name for SR POSIF0_1
+    ExcpVector   POSIF1_0_IRQHandler         ; Handler name for SR POSIF1_0
+    ExcpVector   POSIF1_1_IRQHandler         ; Handler name for SR POSIF1_1
+    ExcpVector   HRPWM_0_IRQHandler          ; Handler name for SR HRPWM_0
+    ExcpVector   HRPWM_1_IRQHandler          ; Handler name for SR HRPWM_1
+    ExcpVector   HRPWM_2_IRQHandler          ; Handler name for SR HRPWM_2
+    ExcpVector   HRPWM_3_IRQHandler          ; Handler name for SR HRPWM_3
+    ExcpVector   CAN0_0_IRQHandler           ; Handler name for SR CAN0_0
+    ExcpVector   CAN0_1_IRQHandler           ; Handler name for SR CAN0_1
+    ExcpVector   CAN0_2_IRQHandler           ; Handler name for SR CAN0_2
+    ExcpVector   CAN0_3_IRQHandler           ; Handler name for SR CAN0_3
+    ExcpVector   CAN0_4_IRQHandler           ; Handler name for SR CAN0_4
+    ExcpVector   CAN0_5_IRQHandler           ; Handler name for SR CAN0_5
+    ExcpVector   CAN0_6_IRQHandler           ; Handler name for SR CAN0_6
+    ExcpVector   CAN0_7_IRQHandler           ; Handler name for SR CAN0_7
+    ExcpVector   USIC0_0_IRQHandler          ; Handler name for SR USIC0_0
+    ExcpVector   USIC0_1_IRQHandler          ; Handler name for SR USIC0_1
+    ExcpVector   USIC0_2_IRQHandler          ; Handler name for SR USIC0_2
+    ExcpVector   USIC0_3_IRQHandler          ; Handler name for SR USIC0_3
+    ExcpVector   USIC0_4_IRQHandler          ; Handler name for SR USIC0_4
+    ExcpVector   USIC0_5_IRQHandler          ; Handler name for SR USIC0_5
+    ExcpVector   USIC1_0_IRQHandler          ; Handler name for SR USIC1_0
+    ExcpVector   USIC1_1_IRQHandler          ; Handler name for SR USIC1_1
+    ExcpVector   USIC1_2_IRQHandler          ; Handler name for SR USIC1_2
+    ExcpVector   USIC1_3_IRQHandler          ; Handler name for SR USIC1_3
+    ExcpVector   USIC1_4_IRQHandler          ; Handler name for SR USIC1_4
+    ExcpVector   USIC1_5_IRQHandler          ; Handler name for SR USIC1_5
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    ExcpVector   LEDTS0_0_IRQHandler         ; Handler name for SR LEDTS0_0
+    DCD   0                           ; Not Available
+    ExcpVector   FCE0_0_IRQHandler           ; Handler name for SR FCE0_0
+    ExcpVector   GPDMA0_0_IRQHandler         ; Handler name for SR GPDMA0_0
+    DCD   0                           ; Not Available
+    ExcpVector   USB0_0_IRQHandler           ; Handler name for SR USB0_0
+    ExcpVector   ETH0_0_IRQHandler           ; Handler name for SR ETH0_0
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+    DCD   0                           ; Not Available
+
+
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =SystemInit_DAVE3
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+
+       ProxyHandler NMI_Handler
+       ProxyHandler HardFault_Handler
+       ProxyHandler MemManage_Handler
+       ProxyHandler BusFault_Handler
+       ProxyHandler UsageFault_Handler
+       ProxyHandler SVC_Handler
+       ProxyHandler DebugMon_Handler
+       ProxyHandler PendSV_Handler
+       ProxyHandler SysTick_Handler
+
+       ProxyHandler SCU_0_IRQHandler
+       ProxyHandler ERU0_0_IRQHandler
+       ProxyHandler ERU0_1_IRQHandler
+       ProxyHandler ERU0_2_IRQHandler
+       ProxyHandler ERU0_3_IRQHandler
+       ProxyHandler ERU1_0_IRQHandler
+       ProxyHandler ERU1_1_IRQHandler
+       ProxyHandler ERU1_2_IRQHandler
+       ProxyHandler ERU1_3_IRQHandler
+       ProxyHandler PMU0_0_IRQHandler
+       ProxyHandler VADC0_C0_0_IRQHandler
+       ProxyHandler VADC0_C0_1_IRQHandler
+       ProxyHandler VADC0_C0_2_IRQHandler
+       ProxyHandler VADC0_C0_3_IRQHandler
+       ProxyHandler VADC0_G0_0_IRQHandler
+       ProxyHandler VADC0_G0_1_IRQHandler
+       ProxyHandler VADC0_G0_2_IRQHandler
+       ProxyHandler VADC0_G0_3_IRQHandler
+       ProxyHandler VADC0_G1_0_IRQHandler
+       ProxyHandler VADC0_G1_1_IRQHandler
+       ProxyHandler VADC0_G1_2_IRQHandler
+       ProxyHandler VADC0_G1_3_IRQHandler
+       ProxyHandler VADC0_G2_0_IRQHandler
+       ProxyHandler VADC0_G2_1_IRQHandler
+       ProxyHandler VADC0_G2_2_IRQHandler
+       ProxyHandler VADC0_G2_3_IRQHandler
+       ProxyHandler VADC0_G3_0_IRQHandler
+       ProxyHandler VADC0_G3_1_IRQHandler
+       ProxyHandler VADC0_G3_2_IRQHandler
+       ProxyHandler VADC0_G3_3_IRQHandler
+       ProxyHandler DSD0_0_IRQHandler
+       ProxyHandler DSD0_1_IRQHandler
+       ProxyHandler DSD0_2_IRQHandler
+       ProxyHandler DSD0_3_IRQHandler
+       ProxyHandler DSD0_4_IRQHandler
+       ProxyHandler DSD0_5_IRQHandler
+       ProxyHandler DSD0_6_IRQHandler
+       ProxyHandler DSD0_7_IRQHandler
+       ProxyHandler DAC0_0_IRQHandler
+       ProxyHandler DAC0_1_IRQHandler
+       ProxyHandler CCU40_0_IRQHandler
+       ProxyHandler CCU40_1_IRQHandler
+       ProxyHandler CCU40_2_IRQHandler
+       ProxyHandler CCU40_3_IRQHandler
+       ProxyHandler CCU41_0_IRQHandler
+       ProxyHandler CCU41_1_IRQHandler
+       ProxyHandler CCU41_2_IRQHandler
+       ProxyHandler CCU41_3_IRQHandler
+       ProxyHandler CCU42_0_IRQHandler
+       ProxyHandler CCU42_1_IRQHandler
+       ProxyHandler CCU42_2_IRQHandler
+       ProxyHandler CCU42_3_IRQHandler
+       ProxyHandler CCU43_0_IRQHandler
+       ProxyHandler CCU43_1_IRQHandler
+       ProxyHandler CCU43_2_IRQHandler
+       ProxyHandler CCU43_3_IRQHandler
+       ProxyHandler CCU80_0_IRQHandler
+       ProxyHandler CCU80_1_IRQHandler
+       ProxyHandler CCU80_2_IRQHandler
+       ProxyHandler CCU80_3_IRQHandler
+       ProxyHandler CCU81_0_IRQHandler
+       ProxyHandler CCU81_1_IRQHandler
+       ProxyHandler CCU81_2_IRQHandler
+       ProxyHandler CCU81_3_IRQHandler
+       ProxyHandler POSIF0_0_IRQHandler
+       ProxyHandler POSIF0_1_IRQHandler
+       ProxyHandler POSIF1_0_IRQHandler
+       ProxyHandler POSIF1_1_IRQHandler
+       ProxyHandler HRPWM_0_IRQHandler
+       ProxyHandler HRPWM_1_IRQHandler
+       ProxyHandler HRPWM_2_IRQHandler
+       ProxyHandler HRPWM_3_IRQHandler
+       ProxyHandler CAN0_0_IRQHandler
+       ProxyHandler CAN0_1_IRQHandler
+       ProxyHandler CAN0_2_IRQHandler
+       ProxyHandler CAN0_3_IRQHandler
+       ProxyHandler CAN0_4_IRQHandler
+       ProxyHandler CAN0_5_IRQHandler
+       ProxyHandler CAN0_6_IRQHandler
+       ProxyHandler CAN0_7_IRQHandler
+       ProxyHandler USIC0_0_IRQHandler
+       ProxyHandler USIC0_1_IRQHandler
+       ProxyHandler USIC0_2_IRQHandler
+       ProxyHandler USIC0_3_IRQHandler
+       ProxyHandler USIC0_4_IRQHandler
+       ProxyHandler USIC0_5_IRQHandler
+       ProxyHandler USIC1_0_IRQHandler
+       ProxyHandler USIC1_1_IRQHandler
+       ProxyHandler USIC1_2_IRQHandler
+       ProxyHandler USIC1_3_IRQHandler
+       ProxyHandler USIC1_4_IRQHandler
+       ProxyHandler USIC1_5_IRQHandler
+       ProxyHandler LEDTS0_0_IRQHandler
+       ProxyHandler FCE0_0_IRQHandler
+       ProxyHandler GPDMA0_0_IRQHandler
+       ProxyHandler USB0_0_IRQHandler
+       ProxyHandler ETH0_0_IRQHandler
+
+; Definition of the default weak SystemInit_DAVE3 function for DAVE3 system init.
+        PUBWEAK SystemInit_DAVE3
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SystemInit_DAVE3
+        NOP
+        BX LR
+
+; Definition of the default weak DAVE3 function for clock App usage.
+; AllowPLLInitByStartup Handler
+        PUBWEAK AllowPLLInitByStartup
+        SECTION .text:CODE:REORDER:NOROOT(2)
+AllowPLLInitByStartup
+        MOV R0,#1
+        BX LR
+
+PREF_PCON       EQU 0x58004000
+SCU_GCU_PEEN    EQU 0x5000413C
+SCU_GCU_PEFLAG  EQU 0x50004150
+
+
+        END
@@ -0,0 +1,397 @@
+/*****************************************************************************/
+/* Startup_XMC4500.s: Startup file for XMC4500 device series for EWARM                */
+/*****************************************************************************/
+/**
+* @file     Startup_XMC4500.s
+*           XMC4000 Device Series
+* @version  V1.0
+* @date     Jan 2013
+*
+* Copyright (C) 2012 IAR Systems. All rights reserved.
+* Copyright (C) 2012 Infineon Technologies AG. All rights reserved.
+*
+*
+* @par
+* Infineon Technologies AG (Infineon) is supplying this software for use with
+* Infineon's microcontrollers.  This file can be freely distributed
+* within development tools that are supporting such microcontrollers.
+*
+* @par
+* THIS SOFTWARE IS PROVIDED AS IS.  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+*
+******************************************************************************/
+/* ********************* Version History *********************************** */
+/* ***************************************************************************
+V1.0 January, 30 2013:  In ths version a workoraound for the erratum PMU_CM.001
+is implmented (patch for the Exception and interrupt handlers)
+
+**************************************************************************** */
+
+        MODULE  ?vector_table
+
+        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
+        PRESERVE8
+
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+
+__iar_init$$done:               ; The vector table is not needed
+                                ; until after copy initialization is done
+
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
+;/*
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
+; * A veneer defined below will first be executed which in turn branches to the final
+; * exception handler.
+; *
+; * In addition to defining the veneers, the vector table must for these buggy
+; * devices contain the veneers.
+; */
+
+;set WORKAROUND_PMU_CM001 under Options for target
+;Initialize varaible WORKAROUND_PMU_CM001 as TRUE
+WORKAROUND_PMU_CM001 SET 1
+
+;/* A macro to setup a vector table entry based on STEP ID */
+#ifdef WORKAROUND_PMU_CM001
+ExcpVector  macro
+            DCD \1_Veneer
+            endm
+#else
+ExcpVector  macro
+            DCD \1
+            endm
+#endif
+
+;/* A macro to ease definition of the various handlers based on STEP ID */
+#ifdef WORKAROUND_PMU_CM001
+;/* First define the final exception handler */
+ProxyHandler  macro
+              PUBWEAK \1
+              SECTION .text:CODE:REORDER:NOROOT(1)
+\1
+              B \1
+              endm
+;/* And then define a veneer that will branch to the final excp handler */
+ProxyHandler_Veneer  macro
+              PUBWEAK \1
+              SECTION .text:CODE:REORDER:NOROOT(2)
+\1
+              LDR   R0, =ProxyHandler
+              PUSH	{LR}
+              BLX   R0
+              POP   {PC}
+              endm
+ ;/* No prefetch bug, hence define only the final exception handler */
+#else
+ProxyHandler  macro
+              PUBWEAK \1
+              SECTION .text:CODE:REORDER:NOROOT(1)
+\1
+              B \1
+              endm
+#endif
+
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        ExcpVector     NMI_Handler
+        ExcpVector     HardFault_Handler
+        ExcpVector     MemManage_Handler
+        ExcpVector     BusFault_Handler
+        ExcpVector     UsageFault_Handler
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD            SVC_Handler
+        ExcpVector     DebugMon_Handler
+        DCD     0
+        DCD            PendSV_Handler
+        DCD            SysTick_Handler
+
+    ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals
+	ExcpVector   SCU_0_IRQHandler            ; Handler name for SR SCU_0
+	ExcpVector   ERU0_0_IRQHandler           ; Handler name for SR ERU0_0
+	ExcpVector   ERU0_1_IRQHandler           ; Handler name for SR ERU0_1
+	ExcpVector   ERU0_2_IRQHandler           ; Handler name for SR ERU0_2
+	ExcpVector   ERU0_3_IRQHandler           ; Handler name for SR ERU0_3
+	ExcpVector   ERU1_0_IRQHandler           ; Handler name for SR ERU1_0
+	ExcpVector   ERU1_1_IRQHandler           ; Handler name for SR ERU1_1
+	ExcpVector   ERU1_2_IRQHandler           ; Handler name for SR ERU1_2
+	ExcpVector   ERU1_3_IRQHandler           ; Handler name for SR ERU1_3
+	DCD   0                           ; Not Available
+	DCD   0                           ; Not Available
+	DCD   0                           ; Not Available
+	ExcpVector   PMU0_0_IRQHandler           ; Handler name for SR PMU0_0
+	DCD   0                           ; Handler name for SR PMU0_1
+	ExcpVector   VADC0_C0_0_IRQHandler       ; Handler name for SR VADC0_C0_0
+	ExcpVector   VADC0_C0_1_IRQHandler       ; Handler name for SR VADC0_C0_1
+	ExcpVector   VADC0_C0_2_IRQHandler       ; Handler name for SR VADC0_C0_1
+	ExcpVector   VADC0_C0_3_IRQHandler       ; Handler name for SR VADC0_C0_3
+	ExcpVector   VADC0_G0_0_IRQHandler       ; Handler name for SR VADC0_G0_0
+	ExcpVector   VADC0_G0_1_IRQHandler       ; Handler name for SR VADC0_G0_1
+	ExcpVector   VADC0_G0_2_IRQHandler       ; Handler name for SR VADC0_G0_2
+	ExcpVector   VADC0_G0_3_IRQHandler       ; Handler name for SR VADC0_G0_3
+	ExcpVector   VADC0_G1_0_IRQHandler       ; Handler name for SR VADC0_G1_0
+	ExcpVector   VADC0_G1_1_IRQHandler       ; Handler name for SR VADC0_G1_1
+	ExcpVector   VADC0_G1_2_IRQHandler       ; Handler name for SR VADC0_G1_2
+	ExcpVector   VADC0_G1_3_IRQHandler       ; Handler name for SR VADC0_G1_3
+	ExcpVector   VADC0_G2_0_IRQHandler       ; Handler name for SR VADC0_G2_0
+	ExcpVector   VADC0_G2_1_IRQHandler       ; Handler name for SR VADC0_G2_1
+	ExcpVector   VADC0_G2_2_IRQHandler       ; Handler name for SR VADC0_G2_2
+	ExcpVector   VADC0_G2_3_IRQHandler       ; Handler name for SR VADC0_G2_3
+	ExcpVector   VADC0_G3_0_IRQHandler       ; Handler name for SR VADC0_G3_0
+	ExcpVector   VADC0_G3_1_IRQHandler       ; Handler name for SR VADC0_G3_1
+	ExcpVector   VADC0_G3_2_IRQHandler       ; Handler name for SR VADC0_G3_2
+	ExcpVector   VADC0_G3_3_IRQHandler       ; Handler name for SR VADC0_G3_3
+	ExcpVector   DSD0_0_IRQHandler           ; Handler name for SR DSD0_0
+	ExcpVector   DSD0_1_IRQHandler           ; Handler name for SR DSD0_1
+	ExcpVector   DSD0_2_IRQHandler           ; Handler name for SR DSD0_2
+	ExcpVector   DSD0_3_IRQHandler           ; Handler name for SR DSD0_3
+	ExcpVector   DSD0_4_IRQHandler           ; Handler name for SR DSD0_4
+	ExcpVector   DSD0_5_IRQHandler           ; Handler name for SR DSD0_5
+	ExcpVector   DSD0_6_IRQHandler           ; Handler name for SR DSD0_6
+	ExcpVector   DSD0_7_IRQHandler           ; Handler name for SR DSD0_7
+	ExcpVector   DAC0_0_IRQHandler           ; Handler name for SR DAC0_0
+	ExcpVector   DAC0_1_IRQHandler           ; Handler name for SR DAC0_0
+	ExcpVector   CCU40_0_IRQHandler          ; Handler name for SR CCU40_0
+	ExcpVector   CCU40_1_IRQHandler          ; Handler name for SR CCU40_1
+	ExcpVector   CCU40_2_IRQHandler          ; Handler name for SR CCU40_2
+	ExcpVector   CCU40_3_IRQHandler          ; Handler name for SR CCU40_3
+	ExcpVector   CCU41_0_IRQHandler          ; Handler name for SR CCU41_0
+	ExcpVector   CCU41_1_IRQHandler          ; Handler name for SR CCU41_1
+	ExcpVector   CCU41_2_IRQHandler          ; Handler name for SR CCU41_2
+	ExcpVector   CCU41_3_IRQHandler          ; Handler name for SR CCU41_3
+	ExcpVector   CCU42_0_IRQHandler          ; Handler name for SR CCU42_0
+	ExcpVector   CCU42_1_IRQHandler          ; Handler name for SR CCU42_1
+	ExcpVector   CCU42_2_IRQHandler          ; Handler name for SR CCU42_2
+	ExcpVector   CCU42_3_IRQHandler          ; Handler name for SR CCU42_3
+	ExcpVector   CCU43_0_IRQHandler          ; Handler name for SR CCU43_0
+	ExcpVector   CCU43_1_IRQHandler          ; Handler name for SR CCU43_1
+	ExcpVector   CCU43_2_IRQHandler          ; Handler name for SR CCU43_2
+	ExcpVector   CCU43_3_IRQHandler          ; Handler name for SR CCU43_3
+	ExcpVector   CCU80_0_IRQHandler          ; Handler name for SR CCU80_0
+	ExcpVector   CCU80_1_IRQHandler          ; Handler name for SR CCU80_1
+	ExcpVector   CCU80_2_IRQHandler          ; Handler name for SR CCU80_2
+	ExcpVector   CCU80_3_IRQHandler          ; Handler name for SR CCU80_3
+	ExcpVector   CCU81_0_IRQHandler          ; Handler name for SR CCU81_0
+	ExcpVector   CCU81_1_IRQHandler          ; Handler name for SR CCU81_1
+	ExcpVector   CCU81_2_IRQHandler          ; Handler name for SR CCU81_2
+	ExcpVector   CCU81_3_IRQHandler          ; Handler name for SR CCU81_3
+	ExcpVector   POSIF0_0_IRQHandler         ; Handler name for SR POSIF0_0
+	ExcpVector   POSIF0_1_IRQHandler         ; Handler name for SR POSIF0_1
+	ExcpVector   POSIF1_0_IRQHandler         ; Handler name for SR POSIF1_0
+	ExcpVector   POSIF1_1_IRQHandler         ; Handler name for SR POSIF1_1
+	DCD   0                           ; Not Available
+	DCD   0                           ; Not Available
+	DCD   0                           ; Not Available
+	DCD   0                           ; Not Available
+	ExcpVector   CAN0_0_IRQHandler           ; Handler name for SR CAN0_0
+	ExcpVector   CAN0_1_IRQHandler           ; Handler name for SR CAN0_1
+	ExcpVector   CAN0_2_IRQHandler           ; Handler name for SR CAN0_2
+	ExcpVector   CAN0_3_IRQHandler           ; Handler name for SR CAN0_3
+	ExcpVector   CAN0_4_IRQHandler           ; Handler name for SR CAN0_4
+	ExcpVector   CAN0_5_IRQHandler           ; Handler name for SR CAN0_5
+	ExcpVector   CAN0_6_IRQHandler           ; Handler name for SR CAN0_6
+	ExcpVector   CAN0_7_IRQHandler           ; Handler name for SR CAN0_7
+	ExcpVector   USIC0_0_IRQHandler          ; Handler name for SR USIC0_0
+	ExcpVector   USIC0_1_IRQHandler          ; Handler name for SR USIC0_1
+	ExcpVector   USIC0_2_IRQHandler          ; Handler name for SR USIC0_2
+	ExcpVector   USIC0_3_IRQHandler          ; Handler name for SR USIC0_3
+	ExcpVector   USIC0_4_IRQHandler          ; Handler name for SR USIC0_4
+	ExcpVector   USIC0_5_IRQHandler          ; Handler name for SR USIC0_5
+	ExcpVector   USIC1_0_IRQHandler          ; Handler name for SR USIC1_0
+	ExcpVector   USIC1_1_IRQHandler          ; Handler name for SR USIC1_1
+	ExcpVector   USIC1_2_IRQHandler          ; Handler name for SR USIC1_2
+	ExcpVector   USIC1_3_IRQHandler          ; Handler name for SR USIC1_3
+	ExcpVector   USIC1_4_IRQHandler          ; Handler name for SR USIC1_4
+	ExcpVector   USIC1_5_IRQHandler          ; Handler name for SR USIC1_5
+	ExcpVector   USIC2_0_IRQHandler          ; Handler name for SR USIC2_0
+	ExcpVector   USIC2_1_IRQHandler          ; Handler name for SR USIC2_1
+	ExcpVector   USIC2_2_IRQHandler          ; Handler name for SR USIC2_2
+	ExcpVector   USIC2_3_IRQHandler          ; Handler name for SR USIC2_3
+	ExcpVector   USIC2_4_IRQHandler          ; Handler name for SR USIC2_4
+	ExcpVector   USIC2_5_IRQHandler          ; Handler name for SR USIC2_5
+	ExcpVector   LEDTS0_0_IRQHandler         ; Handler name for SR LEDTS0_0
+	DCD   0                           ; Not Available
+	ExcpVector   FCE0_0_IRQHandler           ; Handler name for SR FCE0_0
+	ExcpVector   GPDMA0_0_IRQHandler         ; Handler name for SR GPDMA0_0
+	ExcpVector   SDMMC0_0_IRQHandler         ; Handler name for SR SDMMC0_0
+	ExcpVector   USB0_0_IRQHandler           ; Handler name for SR USB0_0
+	ExcpVector   ETH0_0_IRQHandler           ; Handler name for SR ETH0_0
+	DCD   0                           ; Not Available
+	ExcpVector   GPDMA1_0_IRQHandler         ; Handler name for SR GPDMA1_0
+	DCD   0                           ; Not Available
+
+
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =SystemInit_DAVE3
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+
+        ProxyHandler NMI_Handler
+        ProxyHandler HardFault_Handler
+        ProxyHandler MemManage_Handler
+        ProxyHandler BusFault_Handler
+        ProxyHandler UsageFault_Handler
+        ProxyHandler SVC_Handler
+        ProxyHandler DebugMon_Handler
+        ProxyHandler PendSV_Handler
+        ProxyHandler SysTick_Handler
+
+        ProxyHandler SCU_0_IRQHandler
+        ProxyHandler ERU0_0_IRQHandler
+        ProxyHandler ERU0_1_IRQHandler
+        ProxyHandler ERU0_2_IRQHandler
+        ProxyHandler ERU0_3_IRQHandler
+        ProxyHandler ERU1_0_IRQHandler
+        ProxyHandler ERU1_1_IRQHandler
+        ProxyHandler ERU1_2_IRQHandler
+        ProxyHandler ERU1_3_IRQHandler
+        ProxyHandler PMU0_0_IRQHandler
+        ProxyHandler PMU0_1_IRQHandler
+        ProxyHandler VADC0_C0_0_IRQHandler
+        ProxyHandler VADC0_C0_1_IRQHandler
+        ProxyHandler VADC0_C0_2_IRQHandler
+        ProxyHandler VADC0_C0_3_IRQHandler
+        ProxyHandler VADC0_G0_0_IRQHandler
+        ProxyHandler VADC0_G0_1_IRQHandler
+        ProxyHandler VADC0_G0_2_IRQHandler
+        ProxyHandler VADC0_G0_3_IRQHandler
+        ProxyHandler VADC0_G1_0_IRQHandler
+        ProxyHandler VADC0_G1_1_IRQHandler
+        ProxyHandler VADC0_G1_2_IRQHandler
+        ProxyHandler VADC0_G1_3_IRQHandler
+        ProxyHandler VADC0_G2_0_IRQHandler
+        ProxyHandler VADC0_G2_1_IRQHandler
+        ProxyHandler VADC0_G2_2_IRQHandler
+        ProxyHandler VADC0_G2_3_IRQHandler
+        ProxyHandler VADC0_G3_0_IRQHandler
+        ProxyHandler VADC0_G3_1_IRQHandler
+        ProxyHandler VADC0_G3_2_IRQHandler
+        ProxyHandler VADC0_G3_3_IRQHandler
+        ProxyHandler DSD0_0_IRQHandler
+        ProxyHandler DSD0_1_IRQHandler
+        ProxyHandler DSD0_2_IRQHandler
+        ProxyHandler DSD0_3_IRQHandler
+        ProxyHandler DSD0_4_IRQHandler
+        ProxyHandler DSD0_5_IRQHandler
+        ProxyHandler DSD0_6_IRQHandler
+        ProxyHandler DSD0_7_IRQHandler
+        ProxyHandler DAC0_0_IRQHandler
+        ProxyHandler DAC0_1_IRQHandler
+        ProxyHandler CCU40_0_IRQHandler
+        ProxyHandler CCU40_1_IRQHandler
+        ProxyHandler CCU40_2_IRQHandler
+        ProxyHandler CCU40_3_IRQHandler
+        ProxyHandler CCU41_0_IRQHandler
+        ProxyHandler CCU41_1_IRQHandler
+        ProxyHandler CCU41_2_IRQHandler
+        ProxyHandler CCU41_3_IRQHandler
+        ProxyHandler CCU42_0_IRQHandler
+        ProxyHandler CCU42_1_IRQHandler
+        ProxyHandler CCU42_2_IRQHandler
+        ProxyHandler CCU42_3_IRQHandler
+        ProxyHandler CCU43_0_IRQHandler
+        ProxyHandler CCU43_1_IRQHandler
+        ProxyHandler CCU43_2_IRQHandler
+        ProxyHandler CCU43_3_IRQHandler
+        ProxyHandler CCU80_0_IRQHandler
+        ProxyHandler CCU80_1_IRQHandler
+        ProxyHandler CCU80_2_IRQHandler
+        ProxyHandler CCU80_3_IRQHandler
+        ProxyHandler CCU81_0_IRQHandler
+        ProxyHandler CCU81_1_IRQHandler
+        ProxyHandler CCU81_2_IRQHandler
+        ProxyHandler CCU81_3_IRQHandler
+        ProxyHandler POSIF0_0_IRQHandler
+        ProxyHandler POSIF0_1_IRQHandler
+        ProxyHandler POSIF1_0_IRQHandler
+        ProxyHandler POSIF1_1_IRQHandler
+        ProxyHandler CAN0_0_IRQHandler
+        ProxyHandler CAN0_1_IRQHandler
+        ProxyHandler CAN0_2_IRQHandler
+        ProxyHandler CAN0_3_IRQHandler
+        ProxyHandler CAN0_4_IRQHandler
+        ProxyHandler CAN0_5_IRQHandler
+        ProxyHandler CAN0_6_IRQHandler
+        ProxyHandler CAN0_7_IRQHandler
+        ProxyHandler USIC0_0_IRQHandler
+        ProxyHandler USIC0_1_IRQHandler
+        ProxyHandler USIC0_2_IRQHandler
+        ProxyHandler USIC0_3_IRQHandler
+        ProxyHandler USIC0_4_IRQHandler
+        ProxyHandler USIC0_5_IRQHandler
+        ProxyHandler USIC1_0_IRQHandler
+        ProxyHandler USIC1_1_IRQHandler
+        ProxyHandler USIC1_2_IRQHandler
+        ProxyHandler USIC1_3_IRQHandler
+        ProxyHandler USIC1_4_IRQHandler
+        ProxyHandler USIC1_5_IRQHandler
+        ProxyHandler USIC2_0_IRQHandler
+        ProxyHandler USIC2_1_IRQHandler
+        ProxyHandler USIC2_2_IRQHandler
+        ProxyHandler USIC2_3_IRQHandler
+        ProxyHandler USIC2_4_IRQHandler
+        ProxyHandler USIC2_5_IRQHandler
+        ProxyHandler LEDTS0_0_IRQHandler
+        ProxyHandler FCE0_0_IRQHandler
+        ProxyHandler GPDMA0_0_IRQHandler
+        ProxyHandler SDMMC0_0_IRQHandler
+        ProxyHandler USB0_0_IRQHandler
+        ProxyHandler ETH0_0_IRQHandler
+        ProxyHandler GPDMA1_0_IRQHandler
+
+
+; Definition of the default weak SystemInit_DAVE3 function for DAVE3 system init.
+        PUBWEAK SystemInit_DAVE3
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SystemInit_DAVE3
+        NOP
+        BX LR
+
+; Definition of the default weak DAVE3 function for clock App usage.
+; AllowPLLInitByStartup Handler
+        PUBWEAK AllowPLLInitByStartup
+        SECTION .text:CODE:REORDER:NOROOT(2)
+AllowPLLInitByStartup
+        MOV R0,#1
+        BX LR
+
+PREF_PCON       EQU 0x58004000
+SCU_GCU_PEEN    EQU 0x5000413C
+SCU_GCU_PEFLAG  EQU 0x50004150
+
+
+        END
@@ -0,0 +1,72 @@
+/**************************************************************************//**
+ * @file     system_XMC4200.h
+ * @brief    Header file for the XMC4400-Series systeminit
+ *           
+ * @version  V1.0
+ * @date     17. September 2012
+ *
+ * @note
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.  
+ * This file can be freely distributed within development tools that are supporting such microcontrollers. 
+
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_XMC4200_H
+#define __SYSTEM_XMC4200_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+extern void SystemInit (void);
+
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/* this weak function enables DAVE3 clock App usage */		
+extern uint32_t AllowPLLInitByStartup(void);		
+				
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
@@ -0,0 +1,72 @@
+/**************************************************************************//**
+ * @file     system_XMC4400.h
+ * @brief    Header file for the XMC4400-Series systeminit
+ *           
+ * @version  V1.0
+ * @date     17. August 2012
+ *
+ * @note
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.  
+ * This file can be freely distributed within development tools that are supporting such microcontrollers. 
+
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_XMC4400_H
+#define __SYSTEM_XMC4400_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+extern void SystemInit (void);
+
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/* this weak function enables DAVE3 clock App usage */		
+extern uint32_t AllowPLLInitByStartup(void);		
+				
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
@@ -2,8 +2,8 @@
 * @file     system_XMC4500.h
 * @brief    Header file for the XMC4500-Series systeminit
 *           
- * @version  V1.4
- * @date     31. Januar 2012
+ * @version  V1.6
+ * @date     23. October 2012
 *
 * @note
 * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
@@ -59,6 +59,9 @@ extern void SystemInit (void);
 */
 extern void SystemCoreClockUpdate (void);

+/* this weak function enables DAVE3 clock App usage */		
+extern uint32_t AllowPLLInitByStartup(void);				
+

 /* clock definitions, do not modify! */
 #define SCU_CLOCK_CRYSTAL              1
@@ -70,11 +73,12 @@ extern void SystemCoreClockUpdate (void);
 */				
 /* source for clock generation				
 * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)				
- *        				
+ * mandatory for old system_xmc4500.c files - please do not remove!!!       				
 **************************************************************************************/				
 				
 #define	SCU_PLL_CLOCK_INPUT	SCU_CLOCK_CRYSTAL
-#define CLOCK_OSC_HP	24000000			 
+#define CLOCK_OSC_HP	24000000
+#define CLOCK_BACK_UP	24000000		 
 #define	CLOCK_CRYSTAL_FREQUENCY	12000000		
 #define	SYSTEM_FREQUENCY	120000000		
 				
@@ -734,7 +734,7 @@

  <Group>
    <GroupName>Demo_Source</GroupName>
-    <tvExp>0</tvExp>
+    <tvExp>1</tvExp>
    <tvExpOptDlg>0</tvExpOptDlg>
    <cbSel>0</cbSel>
    <RteFlg>0</RteFlg>
@@ -744,9 +744,9 @@
      <FileType>1</FileType>
      <tvExp>0</tvExp>
      <Focus>0</Focus>
-      <ColumnNumber>0</ColumnNumber>
+      <ColumnNumber>4</ColumnNumber>
      <tvExpOptDlg>0</tvExpOptDlg>
-      <TopLine>64</TopLine>
+      <TopLine>113</TopLine>
      <CurrentLine>140</CurrentLine>
      <bDave2>0</bDave2>
      <PathWithFileName>.\main.c</PathWithFileName>
@@ -778,8 +778,8 @@
      <Focus>0</Focus>
      <ColumnNumber>0</ColumnNumber>
      <tvExpOptDlg>0</tvExpOptDlg>
-      <TopLine>0</TopLine>
-      <CurrentLine>0</CurrentLine>
+      <TopLine>367</TopLine>
+      <CurrentLine>418</CurrentLine>
      <bDave2>0</bDave2>
      <PathWithFileName>.\RegTest.c</PathWithFileName>
      <FilenameWithoutPath>RegTest.c</FilenameWithoutPath>
@@ -926,7 +926,7 @@

  <Group>
    <GroupName>Common_Demo_Source</GroupName>
-    <tvExp>0</tvExp>
+    <tvExp>1</tvExp>
    <tvExpOptDlg>0</tvExpOptDlg>
    <cbSel>0</cbSel>
    <RteFlg>0</RteFlg>
@@ -418,6 +418,14 @@ reg2_loopf_pass
 	ldr r1, [r0]
 	adds r1, r1, #1
 	str r1, [r0]
+	
+	/* Yield to increase test coverage. */
+	movs r0, #0x01
+	ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */
+	lsl r0, r0, #28 /* Shift to PendSV bit */
+	str r0, [r1]
+	dsb
+	
 	pop { r0-r1 }
 	
 	/* Start again. */
@@ -135,8 +135,8 @@ int main( void )

 static void prvSetupHardware( void )
 {
-extern void SystemCoreClockUpdate( void );
-
+	configCONFIGURE_LED();
+	
 	/* Ensure all priority bits are assigned as preemption priority bits. */
 	NVIC_SetPriorityGrouping( 0 );
 }
@@ -113,16 +113,12 @@

 /* Standard demo application includes. */
 #include "flop.h"
-#include "integer.h"
-#include "PollQ.h"
 #include "semtest.h"
 #include "dynamic.h"
-#include "BlockQ.h"
 #include "blocktim.h"
 #include "countsem.h"
 #include "GenQTest.h"
 #include "recmutex.h"
-#include "death.h"

 /* Priorities for the demo application tasks. */
 #define mainQUEUE_POLL_PRIORITY				( tskIDLE_PRIORITY + 2UL )