mirror of
https://github.com/FreeRTOS/FreeRTOS.git
synced 2026-09-21 10:33:55 +08:00
Update the Keil XMC4500 demo project to include build configurations for the XMC4200 and XMC4400 application boards.
This commit is contained in:
Richard Barry
@@ -89,7 +89,7 @@ extern uint32_t SystemCoreClock;
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#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
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#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
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#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
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#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) )
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#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) )
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#define configMAX_TASK_NAME_LEN ( 10 )
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#define configUSE_TRACE_FACILITY 1
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#define configUSE_16_BIT_TICKS 0
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@@ -158,5 +158,39 @@ standard names. */
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#define xPortPendSVHandler PendSV_Handler
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#define xPortSysTickHandler SysTick_Handler
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/* Demo application specific settings. */
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#if defined( PART_XMC4500 )
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/* Hardware includes. */
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#include "XMC4500.h"
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#include "System_XMC4500.h"
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/* Configure pin P3.9 for the LED. */
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#define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 )
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/* To toggle the single LED */
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#define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
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#elif defined( PART_XMC4400 )
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/* Hardware includes. */
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#include "XMC4400.h"
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#include "System_XMC4200.h"
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/* Configure pin P5.2 for the LED. */
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#define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 )
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/* To toggle the single LED */
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#define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 )
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#elif defined( PART_XMC4200 )
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/* Hardware includes. */
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#include "XMC4200.h"
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#include "System_XMC4200.h"
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/* Configure pin P2.1 for the LED. */
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#define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL
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/* To toggle the single LED */
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#define configTOGGLE_LED() ( PORT2->OMR = 0x00020002 )
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#else
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#error Part number not specified in project options
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#endif
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#endif /* FREERTOS_CONFIG_H */
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,114 @@
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/**************************************************************************//**
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* @file system_XMC4500.h
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* @brief Header file for the XMC4500-Series systeminit
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*
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* @version V1.6
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* @date 23. October 2012
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*
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* @note
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* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
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*
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* @par
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* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
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* This file can be freely distributed within development tools that are supporting such microcontrollers.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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*
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******************************************************************************/
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#ifndef __SYSTEM_XMC4500_H
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#define __SYSTEM_XMC4500_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System.
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*/
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extern void SystemInit (void);
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/**
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* Update SystemCoreClock variable
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*
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* @param none
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* @return none
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*
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* @brief Updates the SystemCoreClock with current core Clock
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* retrieved from cpu registers.
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*/
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extern void SystemCoreClockUpdate (void);
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/* this weak function enables DAVE3 clock App usage */
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extern uint32_t AllowPLLInitByStartup(void);
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/* clock definitions, do not modify! */
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#define SCU_CLOCK_CRYSTAL 1
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/*
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* mandatory clock parameters **************************************************
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*/
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/* source for clock generation
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* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
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* mandatory for old system_xmc4500.c files - please do not remove!!!
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**************************************************************************************/
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#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
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#define CLOCK_OSC_HP 24000000
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#define CLOCK_BACK_UP 24000000
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#define CLOCK_CRYSTAL_FREQUENCY 12000000
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#define SYSTEM_FREQUENCY 120000000
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/* OSC_HP setup parameters */
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#define OSC_HP_MODE 0
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#define OSCHPWDGDIV 2
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/* MAIN PLL setup parameters */
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#define PLL_K1DIV 1
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#define PLL_K2DIV 3
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#define PLL_PDIV 1
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#define PLL_NDIV 79
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#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz
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#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz
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#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz
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#define USBPLL_PDIV 1
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#define USBPLL_NDIV 15
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -92,13 +92,9 @@
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#include "FreeRTOS.h"
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#include "task.h"
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/* Hardware includes. */
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#include "XMC4500.h"
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#include "System_XMC4500.h"
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/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
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or 0 to run the more comprehensive test and demo application. */
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#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1
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#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
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/*-----------------------------------------------------------*/
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@@ -141,12 +137,6 @@ static void prvSetupHardware( void )
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{
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extern void SystemCoreClockUpdate( void );
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/* Ensure SystemCoreClock variable is set. */
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SystemCoreClockUpdate();
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/* Configure pin P3.9 for the LED. */
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PORT3->IOCR8 = 0x00008000;
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/* Ensure all priority bits are assigned as preemption priority bits. */
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NVIC_SetPriorityGrouping( 0 );
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}
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@@ -107,10 +107,6 @@
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#include "task.h"
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#include "semphr.h"
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/* Hardware includes. */
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#include "XMC4500.h"
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#include "System_XMC4500.h"
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/* Priorities at which the tasks are created. */
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#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
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#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
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@@ -129,9 +125,6 @@ functionality. */
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#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )
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#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )
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/* To toggle the single LED */
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#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
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/*-----------------------------------------------------------*/
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/*
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@@ -146,11 +139,6 @@ static void prvQueueSendTask( void *pvParameters );
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*/
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void main_blinky( void );
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/*
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* The hardware only has a single LED. Simply toggle it.
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*/
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extern void vMainToggleLED( void );
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/*-----------------------------------------------------------*/
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/* The queue used by both tasks. */
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@@ -235,7 +223,7 @@ unsigned long ulReceivedValue;
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is it the expected value? If it is, toggle the LED. */
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if( ulReceivedValue == 100UL )
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{
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mainTOGGLE_LED();
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configTOGGLE_LED();
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ulReceivedValue = 0U;
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}
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}
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@@ -124,10 +124,6 @@
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#include "recmutex.h"
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#include "death.h"
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/* Hardware includes. */
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#include "XMC4500.h"
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#include "System_XMC4500.h"
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/* Priorities for the demo application tasks. */
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#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )
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#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
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@@ -135,9 +131,6 @@
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#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
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#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
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/* To toggle the single LED */
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#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
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/* A block time of zero simply means "don't block". */
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#define mainDONT_BLOCK ( 0UL )
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@@ -183,14 +176,11 @@ xTimerHandle xCheckTimer = NULL;
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/* Start all the other standard demo/test tasks. The have not particular
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functionality, but do demonstrate how to use the FreeRTOS API and test the
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kernel port. */
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vStartIntegerMathTasks( tskIDLE_PRIORITY );
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vStartDynamicPriorityTasks();
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vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
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vCreateBlockTimeTasks();
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vStartCountingSemaphoreTasks();
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vStartGenericQueueTasks( tskIDLE_PRIORITY );
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vStartRecursiveMutexTasks();
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vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
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vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
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vStartMathTasks( mainFLOP_TASK_PRIORITY );
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@@ -213,11 +203,6 @@ xTimerHandle xCheckTimer = NULL;
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xTimerStart( xCheckTimer, mainDONT_BLOCK );
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}
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/* The set of tasks created by the following function call have to be
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created last as they keep account of the number of tasks they expect to see
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running. */
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vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
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/* Start the scheduler. */
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vTaskStartScheduler();
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@@ -244,21 +229,11 @@ unsigned long ulErrorFound = pdFALSE;
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ulErrorFound = pdTRUE;
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}
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if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
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{
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ulErrorFound = pdTRUE;
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}
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if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
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{
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ulErrorFound = pdTRUE;
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}
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if( xAreBlockingQueuesStillRunning() != pdTRUE )
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{
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ulErrorFound = pdTRUE;
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}
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if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
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{
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ulErrorFound = pdTRUE;
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@@ -274,16 +249,6 @@ unsigned long ulErrorFound = pdFALSE;
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ulErrorFound = pdTRUE;
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}
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if( xIsCreateTaskStillRunning() != pdTRUE )
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{
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ulErrorFound = pdTRUE;
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}
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if( xArePollingQueuesStillRunning() != pdTRUE )
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{
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ulErrorFound = pdTRUE;
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}
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if( xAreSemaphoreTasksStillRunning() != pdTRUE )
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{
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ulErrorFound = pdTRUE;
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@@ -306,7 +271,7 @@ unsigned long ulErrorFound = pdFALSE;
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/* Toggle the check LED to give an indication of the system status. If
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the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
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everything is ok. A faster toggle indicates an error. */
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mainTOGGLE_LED();
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configTOGGLE_LED();
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/* Have any errors been latch in ulErrorFound? If so, shorten the
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period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
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@@ -0,0 +1,455 @@
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;*****************************************************************************/
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; * @file startup_XMC4200.s
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; * @brief CMSIS Cortex-M4 Core Device Startup File for
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; * Infineon XMC4200 Device Series
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; * @version V1.00
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; * @date 05. February 2013
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; *
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; * @note
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; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
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; *
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; * @par
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * @par
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; ******************************************************************************/
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;/* ********************* Version History *********************************** */
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;/* ***************************************************************************
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; V0.1 , September 2012, First version
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; V1.0 , February 2013, FIX for CPU prefetch bug implemented
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;**************************************************************************** */
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;* <<< Use Configuration Wizard in Context Menu >>>
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
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;/*
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; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
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; * A veneer defined below will first
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; * be executed which in turn branches to the final exception handler.
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; *
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; * In addition to defining the veneers, the vector table must for these buggy
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; * devices contain the veneers.
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; */
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;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define
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;or use define below
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GBLL WORKAROUND_PMU_CM001
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;/* A macro to setup a vector table entry based on STEP ID */
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IF :DEF:WORKAROUND_PMU_CM001
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MACRO
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ExcpVector $Handler
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DCD $Handler._Veneer
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MEND
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ELSE
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MACRO
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ExcpVector $Handler
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DCD $Handler
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MEND
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ENDIF
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;/* A macro to ease definition of the various handlers based on STEP ID */
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IF :DEF:WORKAROUND_PMU_CM001
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;/* First define the final exception handler */
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MACRO
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ExcpHandler $Handler_Func
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$Handler_Func\
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PROC
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EXPORT $Handler_Func [WEAK]
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B .
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ENDP
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;/* And then define a veneer that will branch to the final excp handler */
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$Handler_Func._Veneer\
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PROC
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EXPORT $Handler_Func._Veneer [WEAK]
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LDR R0, =$Handler_Func
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PUSH {LR}
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BLX R0
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POP {PC}
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ALIGN
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LTORG
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ENDP
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MEND
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ELSE
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;/* No prefetch bug, hence define only the final exception handler */
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MACRO
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ExcpHandler $Handler_Func
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$Handler_Func\
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PROC
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EXPORT $Handler_Func [WEAK]
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B .
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ENDP
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MEND
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ENDIF
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;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
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;* ================== START OF VECTOR TABLE DEFINITION ====================== */
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;* Vector Table - This gets programed into VTOR register */
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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||||
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__Vectors
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DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
|
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ExcpVector NMI_Handler ; NMI Handler
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ExcpVector HardFault_Handler ; Hard Fault Handler
|
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ExcpVector MemManage_Handler ; MPU Fault Handler
|
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ExcpVector BusFault_Handler ; Bus Fault Handler
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ExcpVector UsageFault_Handler ; Usage Fault Handler
|
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DCD 0 ; Reserved
|
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DCD 0 ; Reserved
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||||
DCD 0 ; Reserved
|
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
|
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ExcpVector DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
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||||
|
||||
; Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals
|
||||
ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0
|
||||
ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0
|
||||
ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1
|
||||
ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2
|
||||
ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3
|
||||
ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0
|
||||
ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1
|
||||
ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2
|
||||
ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
|
||||
ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
|
||||
ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
|
||||
ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
|
||||
ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
|
||||
ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
|
||||
ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
|
||||
ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
|
||||
ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
|
||||
ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
|
||||
ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
|
||||
ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0
|
||||
ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1
|
||||
ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0
|
||||
ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1
|
||||
ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2
|
||||
ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3
|
||||
ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0
|
||||
ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1
|
||||
ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2
|
||||
ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0
|
||||
ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1
|
||||
ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2
|
||||
ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
|
||||
ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0
|
||||
ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1
|
||||
ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2
|
||||
ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3
|
||||
ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0
|
||||
ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1
|
||||
ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2
|
||||
ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3
|
||||
ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4
|
||||
ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5
|
||||
ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6
|
||||
ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7
|
||||
ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0
|
||||
ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1
|
||||
ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2
|
||||
ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3
|
||||
ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4
|
||||
ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5
|
||||
ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0
|
||||
ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1
|
||||
ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2
|
||||
ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3
|
||||
ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4
|
||||
ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0
|
||||
ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
;* ================== END OF VECTOR TABLE DEFINITION ======================= */
|
||||
|
||||
;* ================== START OF VECTOR ROUTINES ============================= */
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;* Reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
; Remap vector table
|
||||
LDR R0, =__Vectors
|
||||
LDR R1, =0xE000ED08 ;*VTOR register
|
||||
STR R0,[R1]
|
||||
|
||||
;* C routines are likely to be called. Setup the stack now
|
||||
LDR SP,=__initial_sp
|
||||
|
||||
LDR R0, = SystemInit
|
||||
BLX R0
|
||||
|
||||
;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
|
||||
;weakly defined here though for a potential override.
|
||||
|
||||
LDR R0, = SystemInit_DAVE3
|
||||
BLX R0
|
||||
|
||||
;* Reset stack pointer before zipping off to user application
|
||||
LDR SP,=__initial_sp
|
||||
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
|
||||
ALIGN
|
||||
ENDP
|
||||
|
||||
|
||||
|
||||
|
||||
;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
|
||||
|
||||
|
||||
|
||||
;/* Default exception Handlers - Users may override this default functionality by
|
||||
; defining handlers of the same name in their C code */
|
||||
|
||||
ExcpHandler NMI_Handler
|
||||
ExcpHandler HardFault_Handler
|
||||
ExcpHandler MemManage_Handler
|
||||
ExcpHandler BusFault_Handler
|
||||
ExcpHandler UsageFault_Handler
|
||||
ExcpHandler SVC_Handler
|
||||
ExcpHandler DebugMon_Handler
|
||||
ExcpHandler PendSV_Handler
|
||||
ExcpHandler SysTick_Handler
|
||||
|
||||
;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
|
||||
|
||||
;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
|
||||
|
||||
;* IRQ Handlers */
|
||||
ExcpHandler SCU_0_IRQHandler
|
||||
ExcpHandler ERU0_0_IRQHandler
|
||||
ExcpHandler ERU0_1_IRQHandler
|
||||
ExcpHandler ERU0_2_IRQHandler
|
||||
ExcpHandler ERU0_3_IRQHandler
|
||||
ExcpHandler ERU1_0_IRQHandler
|
||||
ExcpHandler ERU1_1_IRQHandler
|
||||
ExcpHandler ERU1_2_IRQHandler
|
||||
ExcpHandler ERU1_3_IRQHandler
|
||||
ExcpHandler PMU0_0_IRQHandler
|
||||
ExcpHandler VADC0_C0_0_IRQHandler
|
||||
ExcpHandler VADC0_C0_1_IRQHandler
|
||||
ExcpHandler VADC0_C0_2_IRQHandler
|
||||
ExcpHandler VADC0_C0_3_IRQHandler
|
||||
ExcpHandler VADC0_G0_0_IRQHandler
|
||||
ExcpHandler VADC0_G0_1_IRQHandler
|
||||
ExcpHandler VADC0_G0_2_IRQHandler
|
||||
ExcpHandler VADC0_G0_3_IRQHandler
|
||||
ExcpHandler VADC0_G1_0_IRQHandler
|
||||
ExcpHandler VADC0_G1_1_IRQHandler
|
||||
ExcpHandler VADC0_G1_2_IRQHandler
|
||||
ExcpHandler VADC0_G1_3_IRQHandler
|
||||
ExcpHandler DAC0_0_IRQHandler
|
||||
ExcpHandler DAC0_1_IRQHandler
|
||||
ExcpHandler CCU40_0_IRQHandler
|
||||
ExcpHandler CCU40_1_IRQHandler
|
||||
ExcpHandler CCU40_2_IRQHandler
|
||||
ExcpHandler CCU40_3_IRQHandler
|
||||
ExcpHandler CCU41_0_IRQHandler
|
||||
ExcpHandler CCU41_1_IRQHandler
|
||||
ExcpHandler CCU41_2_IRQHandler
|
||||
ExcpHandler CCU41_3_IRQHandler
|
||||
ExcpHandler CCU80_0_IRQHandler
|
||||
ExcpHandler CCU80_1_IRQHandler
|
||||
ExcpHandler CCU80_2_IRQHandler
|
||||
ExcpHandler CCU80_3_IRQHandler
|
||||
ExcpHandler POSIF0_0_IRQHandler
|
||||
ExcpHandler POSIF0_1_IRQHandler
|
||||
ExcpHandler HRPWM_0_IRQHandler
|
||||
ExcpHandler HRPWM_1_IRQHandler
|
||||
ExcpHandler HRPWM_2_IRQHandler
|
||||
ExcpHandler HRPWM_3_IRQHandler
|
||||
ExcpHandler CAN0_0_IRQHandler
|
||||
ExcpHandler CAN0_1_IRQHandler
|
||||
ExcpHandler CAN0_2_IRQHandler
|
||||
ExcpHandler CAN0_3_IRQHandler
|
||||
ExcpHandler CAN0_4_IRQHandler
|
||||
ExcpHandler CAN0_5_IRQHandler
|
||||
ExcpHandler CAN0_6_IRQHandler
|
||||
ExcpHandler CAN0_7_IRQHandler
|
||||
ExcpHandler USIC0_0_IRQHandler
|
||||
ExcpHandler USIC0_1_IRQHandler
|
||||
ExcpHandler USIC0_2_IRQHandler
|
||||
ExcpHandler USIC0_3_IRQHandler
|
||||
ExcpHandler USIC0_4_IRQHandler
|
||||
ExcpHandler USIC0_5_IRQHandler
|
||||
ExcpHandler USIC1_0_IRQHandler
|
||||
ExcpHandler USIC1_1_IRQHandler
|
||||
ExcpHandler USIC1_2_IRQHandler
|
||||
ExcpHandler USIC1_3_IRQHandler
|
||||
ExcpHandler USIC1_4_IRQHandler
|
||||
ExcpHandler USIC1_5_IRQHandler
|
||||
ExcpHandler LEDTS0_0_IRQHandler
|
||||
ExcpHandler FCE0_0_IRQHandler
|
||||
ExcpHandler GPDMA0_0_IRQHandler
|
||||
ExcpHandler USB0_0_IRQHandler
|
||||
|
||||
;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
|
||||
|
||||
;* Definition of the default weak SystemInit_DAVE3 function.
|
||||
;* This function will be called by the CMSIS SystemInit function.
|
||||
;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
|
||||
;* which will overule this weak definition
|
||||
SystemInit_DAVE3 PROC
|
||||
EXPORT SystemInit_DAVE3 [WEAK]
|
||||
NOP
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
;* Definition of the default weak DAVE3 function for clock App usage.
|
||||
;* AllowPLLInitByStartup Handler */
|
||||
AllowPLLInitByStartup PROC
|
||||
EXPORT AllowPLLInitByStartup [WEAK]
|
||||
MOV R0,#1
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****
|
||||
@@ -0,0 +1,486 @@
|
||||
;*****************************************************************************/
|
||||
; * @file startup_XMC4400.s
|
||||
; * @brief CMSIS Cortex-M4 Core Device Startup File for
|
||||
; * Infineon XMC4400 Device Series
|
||||
; * @version V1.00
|
||||
; * @date 05. February 2013
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
|
||||
;/* ********************* Version History *********************************** */
|
||||
;/* ***************************************************************************
|
||||
; V0.2 , August 2012, First version
|
||||
; V1.0 , February 2013, FIX for CPU prefetch bug implemented
|
||||
;**************************************************************************** */
|
||||
|
||||
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
|
||||
;/*
|
||||
; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
|
||||
; * A veneer defined below will first
|
||||
; * be executed which in turn branches to the final exception handler.
|
||||
; *
|
||||
; * In addition to defining the veneers, the vector table must for these buggy
|
||||
; * devices contain the veneers.
|
||||
; */
|
||||
|
||||
;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define
|
||||
;or use define below
|
||||
GBLL WORKAROUND_PMU_CM001
|
||||
|
||||
;/* A macro to setup a vector table entry based on STEP ID */
|
||||
IF :DEF:WORKAROUND_PMU_CM001
|
||||
MACRO
|
||||
ExcpVector $Handler
|
||||
DCD $Handler._Veneer
|
||||
MEND
|
||||
ELSE
|
||||
MACRO
|
||||
ExcpVector $Handler
|
||||
DCD $Handler
|
||||
MEND
|
||||
ENDIF
|
||||
|
||||
;/* A macro to ease definition of the various handlers based on STEP ID */
|
||||
IF :DEF:WORKAROUND_PMU_CM001
|
||||
|
||||
;/* First define the final exception handler */
|
||||
MACRO
|
||||
ExcpHandler $Handler_Func
|
||||
$Handler_Func\
|
||||
PROC
|
||||
EXPORT $Handler_Func [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
;/* And then define a veneer that will branch to the final excp handler */
|
||||
$Handler_Func._Veneer\
|
||||
PROC
|
||||
EXPORT $Handler_Func._Veneer [WEAK]
|
||||
LDR R0, =$Handler_Func
|
||||
PUSH {LR}
|
||||
BLX R0
|
||||
POP {PC}
|
||||
ALIGN
|
||||
LTORG
|
||||
ENDP
|
||||
MEND
|
||||
|
||||
ELSE
|
||||
|
||||
;/* No prefetch bug, hence define only the final exception handler */
|
||||
MACRO
|
||||
ExcpHandler $Handler_Func
|
||||
$Handler_Func\
|
||||
PROC
|
||||
EXPORT $Handler_Func [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MEND
|
||||
|
||||
ENDIF
|
||||
;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
|
||||
|
||||
|
||||
;* ================== START OF VECTOR TABLE DEFINITION ====================== */
|
||||
;* Vector Table - This gets programed into VTOR register */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
|
||||
|
||||
__Vectors
|
||||
DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
ExcpVector NMI_Handler ; NMI Handler
|
||||
ExcpVector HardFault_Handler ; Hard Fault Handler
|
||||
ExcpVector MemManage_Handler ; MPU Fault Handler
|
||||
ExcpVector BusFault_Handler ; Bus Fault Handler
|
||||
ExcpVector UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
ExcpVector DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; Interrupt Handlers for Service Requests (SR) from XMC4400 Peripherals
|
||||
ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0
|
||||
ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0
|
||||
ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1
|
||||
ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2
|
||||
ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3
|
||||
ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0
|
||||
ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1
|
||||
ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2
|
||||
ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
|
||||
ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
|
||||
ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
|
||||
ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
|
||||
ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
|
||||
ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
|
||||
ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
|
||||
ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
|
||||
ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
|
||||
ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
|
||||
ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
|
||||
ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
|
||||
ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0
|
||||
ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1
|
||||
ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2
|
||||
ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3
|
||||
ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0
|
||||
ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1
|
||||
ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2
|
||||
ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3
|
||||
ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD0_0
|
||||
ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD0_1
|
||||
ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD0_2
|
||||
ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD0_3
|
||||
ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD0_4
|
||||
ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD0_5
|
||||
ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD0_6
|
||||
ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD0_7
|
||||
ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0
|
||||
ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1
|
||||
ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0
|
||||
ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1
|
||||
ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2
|
||||
ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3
|
||||
ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0
|
||||
ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1
|
||||
ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2
|
||||
ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3
|
||||
ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0
|
||||
ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1
|
||||
ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2
|
||||
ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3
|
||||
ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0
|
||||
ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1
|
||||
ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2
|
||||
ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3
|
||||
ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0
|
||||
ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1
|
||||
ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2
|
||||
ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3
|
||||
ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0
|
||||
ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1
|
||||
ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2
|
||||
ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3
|
||||
ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
|
||||
ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
|
||||
ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0
|
||||
ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1
|
||||
ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0
|
||||
ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1
|
||||
ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2
|
||||
ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3
|
||||
ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0
|
||||
ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1
|
||||
ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2
|
||||
ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3
|
||||
ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4
|
||||
ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5
|
||||
ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6
|
||||
ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7
|
||||
ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0
|
||||
ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1
|
||||
ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2
|
||||
ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3
|
||||
ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4
|
||||
ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5
|
||||
ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0
|
||||
ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1
|
||||
ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2
|
||||
ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3
|
||||
ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4
|
||||
ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0
|
||||
ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
|
||||
DCD 0 ; Reserved
|
||||
ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0
|
||||
ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
;* ================== END OF VECTOR TABLE DEFINITION ======================= */
|
||||
|
||||
;* ================== START OF VECTOR ROUTINES ============================= */
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;* Reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
; Remap vector table
|
||||
LDR R0, =__Vectors
|
||||
LDR R1, =0xE000ED08 ;*VTOR register
|
||||
STR R0,[R1]
|
||||
|
||||
;* C routines are likely to be called. Setup the stack now
|
||||
LDR SP,=__initial_sp
|
||||
|
||||
LDR R0, = SystemInit
|
||||
BLX R0
|
||||
|
||||
;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
|
||||
;weakly defined here though for a potential override.
|
||||
|
||||
LDR R0, = SystemInit_DAVE3
|
||||
BLX R0
|
||||
|
||||
;* Reset stack pointer before zipping off to user application
|
||||
LDR SP,=__initial_sp
|
||||
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
|
||||
ALIGN
|
||||
ENDP
|
||||
|
||||
|
||||
|
||||
|
||||
;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
|
||||
|
||||
|
||||
|
||||
;/* Default exception Handlers - Users may override this default functionality by
|
||||
; defining handlers of the same name in their C code */
|
||||
|
||||
ExcpHandler NMI_Handler
|
||||
ExcpHandler HardFault_Handler
|
||||
ExcpHandler MemManage_Handler
|
||||
ExcpHandler BusFault_Handler
|
||||
ExcpHandler UsageFault_Handler
|
||||
ExcpHandler SVC_Handler
|
||||
ExcpHandler DebugMon_Handler
|
||||
ExcpHandler PendSV_Handler
|
||||
ExcpHandler SysTick_Handler
|
||||
|
||||
;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
|
||||
|
||||
;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
|
||||
|
||||
;* IRQ Handlers */
|
||||
ExcpHandler SCU_0_IRQHandler
|
||||
ExcpHandler ERU0_0_IRQHandler
|
||||
ExcpHandler ERU0_1_IRQHandler
|
||||
ExcpHandler ERU0_2_IRQHandler
|
||||
ExcpHandler ERU0_3_IRQHandler
|
||||
ExcpHandler ERU1_0_IRQHandler
|
||||
ExcpHandler ERU1_1_IRQHandler
|
||||
ExcpHandler ERU1_2_IRQHandler
|
||||
ExcpHandler ERU1_3_IRQHandler
|
||||
ExcpHandler PMU0_0_IRQHandler
|
||||
ExcpHandler VADC0_C0_0_IRQHandler
|
||||
ExcpHandler VADC0_C0_1_IRQHandler
|
||||
ExcpHandler VADC0_C0_2_IRQHandler
|
||||
ExcpHandler VADC0_C0_3_IRQHandler
|
||||
ExcpHandler VADC0_G0_0_IRQHandler
|
||||
ExcpHandler VADC0_G0_1_IRQHandler
|
||||
ExcpHandler VADC0_G0_2_IRQHandler
|
||||
ExcpHandler VADC0_G0_3_IRQHandler
|
||||
ExcpHandler VADC0_G1_0_IRQHandler
|
||||
ExcpHandler VADC0_G1_1_IRQHandler
|
||||
ExcpHandler VADC0_G1_2_IRQHandler
|
||||
ExcpHandler VADC0_G1_3_IRQHandler
|
||||
ExcpHandler VADC0_G2_0_IRQHandler
|
||||
ExcpHandler VADC0_G2_1_IRQHandler
|
||||
ExcpHandler VADC0_G2_2_IRQHandler
|
||||
ExcpHandler VADC0_G2_3_IRQHandler
|
||||
ExcpHandler VADC0_G3_0_IRQHandler
|
||||
ExcpHandler VADC0_G3_1_IRQHandler
|
||||
ExcpHandler VADC0_G3_2_IRQHandler
|
||||
ExcpHandler VADC0_G3_3_IRQHandler
|
||||
ExcpHandler DSD0_0_IRQHandler
|
||||
ExcpHandler DSD0_1_IRQHandler
|
||||
ExcpHandler DSD0_2_IRQHandler
|
||||
ExcpHandler DSD0_3_IRQHandler
|
||||
ExcpHandler DSD0_4_IRQHandler
|
||||
ExcpHandler DSD0_5_IRQHandler
|
||||
ExcpHandler DSD0_6_IRQHandler
|
||||
ExcpHandler DSD0_7_IRQHandler
|
||||
ExcpHandler DAC0_0_IRQHandler
|
||||
ExcpHandler DAC0_1_IRQHandler
|
||||
ExcpHandler CCU40_0_IRQHandler
|
||||
ExcpHandler CCU40_1_IRQHandler
|
||||
ExcpHandler CCU40_2_IRQHandler
|
||||
ExcpHandler CCU40_3_IRQHandler
|
||||
ExcpHandler CCU41_0_IRQHandler
|
||||
ExcpHandler CCU41_1_IRQHandler
|
||||
ExcpHandler CCU41_2_IRQHandler
|
||||
ExcpHandler CCU41_3_IRQHandler
|
||||
ExcpHandler CCU42_0_IRQHandler
|
||||
ExcpHandler CCU42_1_IRQHandler
|
||||
ExcpHandler CCU42_2_IRQHandler
|
||||
ExcpHandler CCU42_3_IRQHandler
|
||||
ExcpHandler CCU43_0_IRQHandler
|
||||
ExcpHandler CCU43_1_IRQHandler
|
||||
ExcpHandler CCU43_2_IRQHandler
|
||||
ExcpHandler CCU43_3_IRQHandler
|
||||
ExcpHandler CCU80_0_IRQHandler
|
||||
ExcpHandler CCU80_1_IRQHandler
|
||||
ExcpHandler CCU80_2_IRQHandler
|
||||
ExcpHandler CCU80_3_IRQHandler
|
||||
ExcpHandler CCU81_0_IRQHandler
|
||||
ExcpHandler CCU81_1_IRQHandler
|
||||
ExcpHandler CCU81_2_IRQHandler
|
||||
ExcpHandler CCU81_3_IRQHandler
|
||||
ExcpHandler POSIF0_0_IRQHandler
|
||||
ExcpHandler POSIF0_1_IRQHandler
|
||||
ExcpHandler POSIF1_0_IRQHandler
|
||||
ExcpHandler POSIF1_1_IRQHandler
|
||||
ExcpHandler HRPWM_0_IRQHandler
|
||||
ExcpHandler HRPWM_1_IRQHandler
|
||||
ExcpHandler HRPWM_2_IRQHandler
|
||||
ExcpHandler HRPWM_3_IRQHandler
|
||||
ExcpHandler CAN0_0_IRQHandler
|
||||
ExcpHandler CAN0_1_IRQHandler
|
||||
ExcpHandler CAN0_2_IRQHandler
|
||||
ExcpHandler CAN0_3_IRQHandler
|
||||
ExcpHandler CAN0_4_IRQHandler
|
||||
ExcpHandler CAN0_5_IRQHandler
|
||||
ExcpHandler CAN0_6_IRQHandler
|
||||
ExcpHandler CAN0_7_IRQHandler
|
||||
ExcpHandler USIC0_0_IRQHandler
|
||||
ExcpHandler USIC0_1_IRQHandler
|
||||
ExcpHandler USIC0_2_IRQHandler
|
||||
ExcpHandler USIC0_3_IRQHandler
|
||||
ExcpHandler USIC0_4_IRQHandler
|
||||
ExcpHandler USIC0_5_IRQHandler
|
||||
ExcpHandler USIC1_0_IRQHandler
|
||||
ExcpHandler USIC1_1_IRQHandler
|
||||
ExcpHandler USIC1_2_IRQHandler
|
||||
ExcpHandler USIC1_3_IRQHandler
|
||||
ExcpHandler USIC1_4_IRQHandler
|
||||
ExcpHandler USIC1_5_IRQHandler
|
||||
ExcpHandler LEDTS0_0_IRQHandler
|
||||
ExcpHandler FCE0_0_IRQHandler
|
||||
ExcpHandler GPDMA0_0_IRQHandler
|
||||
ExcpHandler USB0_0_IRQHandler
|
||||
ExcpHandler ETH0_0_IRQHandler
|
||||
|
||||
;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
|
||||
|
||||
;* Definition of the default weak SystemInit_DAVE3 function.
|
||||
;* This function will be called by the CMSIS SystemInit function.
|
||||
;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
|
||||
;* which will overule this weak definition
|
||||
SystemInit_DAVE3 PROC
|
||||
EXPORT SystemInit_DAVE3 [WEAK]
|
||||
NOP
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
;* Definition of the default weak DAVE3 function for clock App usage.
|
||||
;* AllowPLLInitByStartup Handler */
|
||||
AllowPLLInitByStartup PROC
|
||||
EXPORT AllowPLLInitByStartup [WEAK]
|
||||
MOV R0,#1
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,72 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_XMC4200.h
|
||||
* @brief Header file for the XMC4200-Series systeminit
|
||||
*
|
||||
* @version V1.0
|
||||
* @date 27. August 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
|
||||
|
||||
*
|
||||
* @par
|
||||
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
|
||||
* This file can be freely distributed within development tools that are supporting such microcontrollers.
|
||||
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_XMC4200_H
|
||||
#define __SYSTEM_XMC4200_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
/* this weak function enables DAVE3 clock App usage */
|
||||
extern uint32_t AllowPLLInitByStartup(void);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,72 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_XMC4400.h
|
||||
* @brief Header file for the XMC4400-Series systeminit
|
||||
*
|
||||
* @version V1.0
|
||||
* @date 17. August 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
|
||||
|
||||
*
|
||||
* @par
|
||||
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
|
||||
* This file can be freely distributed within development tools that are supporting such microcontrollers.
|
||||
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_XMC4400_H
|
||||
#define __SYSTEM_XMC4400_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
/* this weak function enables DAVE3 clock App usage */
|
||||
extern uint32_t AllowPLLInitByStartup(void);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user