mirror of
https://github.com/FreeRTOS/FreeRTOS.git
synced 2026-09-22 11:14:03 +08:00
Modify RZ/T e2studio directory structure to accommodate an IAR project.
Start RZ/T port and demo project.
This commit is contained in:
Richard Barry
@@ -48,7 +48,6 @@
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/Full_Demo/Standard_Demo_Tasks/include}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/FreeRTOS_Source/include}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/FreeRTOS_Source/portable/GCC/ARM_CRx_No_GIC}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/cg_src}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/System/GCC/inc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src}""/>
|
||||
@@ -92,7 +91,7 @@
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning30.1994659686" name="Issue Warning about c and ansi c construct incompatibility(-Wtraditional)" superClass="com.renesas.cdt.core.Compiler.option.warning30" value="false" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning31.531473224" name="Give string constants the type 'const char[length]'(-Wwrite-strings)" superClass="com.renesas.cdt.core.Compiler.option.warning31" value="false" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.CPUSeries.114360178" name="Cpu Series" superClass="com.renesas.cdt.core.Compiler.option.CPUSeries"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Compiler.option.optimizationLevel.2026925660" name="Optimization Level" superClass="com.renesas.cdt.rz.HardwareDebug.Compiler.option.optimizationLevel" value="com.renesas.cdt.rz.HardwareDebug.Compiler.option.optimizationLevel.speedCodeSize" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Compiler.option.optimizationLevel.2026925660" name="Optimization Level" superClass="com.renesas.cdt.rz.HardwareDebug.Compiler.option.optimizationLevel" value="com.renesas.cdt.rz.HardwareDebug.Compiler.option.optimizationLevel.none" valueType="enumerated"/>
|
||||
<inputType id="%Base.Compiler.C.InputType.Id.321945067" name="C Input" superClass="%Base.Compiler.C.InputType.Id"/>
|
||||
<inputType id="Base.Compiler.CPP.InputType.Id.678276075" name="C++ Input" superClass="Base.Compiler.CPP.InputType.Id"/>
|
||||
</tool>
|
||||
@@ -144,8 +143,11 @@
|
||||
<tool id="com.renesas.cdt.rz.hardwaredebug.win32.tool.objcopy.Id.1674695683" name="Objcopy" superClass="com.renesas.cdt.rz.hardwaredebug.win32.tool.objcopy.Id"/>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<fileInfo id="com.renesas.cdt.rz.hardwaredebug.win32.configuration.Id.137003302.1449590210" name="reg_test_IAR.asm" rcbsApplicability="disable" resourcePath="src/Full_Demo/reg_test_IAR.asm" toolsToInvoke="com.renesas.cdt.rz.hardwaredebug.win32.tool.compiler.Id.542544613.984236333">
|
||||
<tool id="com.renesas.cdt.rz.hardwaredebug.win32.tool.compiler.Id.542544613.984236333" name="Compiler" superClass="com.renesas.cdt.rz.hardwaredebug.win32.tool.compiler.Id.542544613"/>
|
||||
</fileInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="System/GCC/src/gnu_io.c|System/GCC/src/syscalls.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
<entry excluding="src/Full_Demo/reg_test_IAR.asm|src/cg_src/r_cg_s12ad_user.c|src/cg_src/r_cg_scifa.c|src/cg_src/r_cg_s12ad.c|src/cg_src/r_cg_scifa_user.c|src/cg_src/r_cg_cmt.c|System/GCC/src/siorw.c|System/GCC/src/siochar.c|System/GCC/src/gnu_io.c|System/GCC/src/syscalls.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
|
||||
@@ -42,6 +42,15 @@
|
||||
</link>
|
||||
</linkedResources>
|
||||
<filteredResources>
|
||||
<filter>
|
||||
<id>1442133034715</id>
|
||||
<name>System</name>
|
||||
<type>9</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-GCC</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1440591358527</id>
|
||||
<name>src/FreeRTOS_Source/portable</name>
|
||||
|
||||
@@ -44,7 +44,6 @@
|
||||
.code 32
|
||||
|
||||
.global undefined_handler
|
||||
.global FreeRTOS_SVC_Handler
|
||||
.global prefetch_handler
|
||||
.global abort_handler
|
||||
.global reserved_handler
|
||||
|
||||
+6
-6
@@ -75,14 +75,14 @@ Private variables and functions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
/*******************************************************************************
|
||||
* Function Name : r_rst_write_enable
|
||||
* Description : Enables writing to the registers related to RESET and Low-
|
||||
* Power function. And dummy read the register in order to fix
|
||||
* the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
*******************************************************************************/
|
||||
void r_rst_write_enable(void)
|
||||
{
|
||||
volatile uint32_t dummy=0;
|
||||
@@ -95,18 +95,18 @@ void r_rst_write_enable(void)
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
/*******************************************************************************
|
||||
End of function r_rst_write_enable
|
||||
***********************************************************************************************************************/
|
||||
*******************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
/*******************************************************************************
|
||||
* Function Name : r_rst_write_disable
|
||||
* Description : Disables writing to the registers related to RESET and Low-
|
||||
* Power function. And dummy read the register in order to fix
|
||||
* the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
*******************************************************************************/
|
||||
void r_rst_write_disable(void)
|
||||
{
|
||||
volatile uint32_t dummy=0;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,117 @@
|
||||
/*
|
||||
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
SECTION intvec:CODE:ROOT(2)
|
||||
ARM
|
||||
|
||||
EXTERN pxISRFunction
|
||||
EXTERN FreeRTOS_Tick_Handler
|
||||
EXTERN FreeRTOS_IRQ_Handler
|
||||
EXTERN vCMT_1_Channel_0_ISR
|
||||
EXTERN vCMT_1_Channel_1_ISR
|
||||
|
||||
PUBLIC FreeRTOS_Tick_Handler_Entry
|
||||
PUBLIC vCMT_1_Channel_0_ISR_Entry
|
||||
PUBLIC vCMT_1_Channel_1_ISR_Entry
|
||||
|
||||
FreeRTOS_Tick_Handler_Entry:
|
||||
/* Save used registers (probably not necessary). */
|
||||
PUSH {r0-r1}
|
||||
/* Save the address of the C portion of this handler in pxISRFunction. */
|
||||
LDR r0, =pxISRFunction
|
||||
LDR R1, =FreeRTOS_Tick_Handler
|
||||
STR R1, [r0]
|
||||
/* Restore used registers then branch to the FreeRTOS IRQ handler. */
|
||||
POP {r0-r1}
|
||||
B FreeRTOS_IRQ_Handler
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
vCMT_1_Channel_0_ISR_Entry:
|
||||
/* Save used registers (probably not necessary). */
|
||||
PUSH {r0-r1}
|
||||
/* Save the address of the C portion of this handler in pxISRFunction. */
|
||||
LDR r0, =pxISRFunction
|
||||
LDR R1, =vCMT_1_Channel_0_ISR
|
||||
STR R1, [r0]
|
||||
/* Restore used registers then branch to the FreeRTOS IRQ handler. */
|
||||
POP {r0-r1}
|
||||
B FreeRTOS_IRQ_Handler
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
vCMT_1_Channel_1_ISR_Entry:
|
||||
/* Save used registers (probably not necessary). */
|
||||
PUSH {r0-r1}
|
||||
/* Save the address of the C portion of this handler in pxISRFunction. */
|
||||
LDR r0, =pxISRFunction
|
||||
LDR R1, =vCMT_1_Channel_1_ISR
|
||||
STR R1, [r0]
|
||||
/* Restore used registers then branch to the FreeRTOS IRQ handler. */
|
||||
POP {r0-r1}
|
||||
B FreeRTOS_IRQ_Handler
|
||||
|
||||
END
|
||||
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
*
|
||||
* C-SPY macro information
|
||||
*
|
||||
* __jtagCP15ReadReg(CRn, CRm, op1, op2)
|
||||
* __jtagCP15WriteReg(CRn, CRm, op1, op2, value)
|
||||
* __readMemory8(address, zone)
|
||||
* __writeMemory8(value, address, zone)
|
||||
* __writeMemory32(value, address, zone)
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
__init_TCM()
|
||||
{
|
||||
__var v_reg;
|
||||
|
||||
__message "Initialize ATCM";
|
||||
/*
|
||||
MRC p15, 0, <Rd>, c1, c0, 1 ; Read ACTLR
|
||||
MCR p15, 0, <Rd>, c1, c0, 1 ; Write ACTLR
|
||||
*/
|
||||
|
||||
/* enable ECC in ACTLR */
|
||||
v_reg = __jtagCP15ReadReg(1, 0, 0, 1);
|
||||
v_reg = v_reg | 0x06000000; // set 26 and 25 bits for enabling ECC
|
||||
__message "ACTRL: ", v_reg:%x; // output ACTRL value for check
|
||||
__jtagCP15WriteReg(1, 0, 0, 1, v_reg);
|
||||
|
||||
__fillMemory32(0x0, 0x00000000, "Memory", 0x20000, "Copy");
|
||||
__message "ATCM initialization finished";
|
||||
}
|
||||
|
||||
|
||||
__init_VIC_ProvideHandler()
|
||||
{
|
||||
__var v_reg;
|
||||
|
||||
__message "Initialize VIC provide handler \n";
|
||||
/*
|
||||
MRC p15, 0, <Rd>, c1, c0, 0 ; Read SCTLR
|
||||
MCR p15, 0, <Rd>, c1, c0, 0 ; Write SCTLR
|
||||
*/
|
||||
|
||||
/* Set VIC to provide handler address */
|
||||
v_reg = __jtagCP15ReadReg(1, 0, 0, 0);
|
||||
v_reg = v_reg | 0x01000000; // set 24 bit for setting VE bit
|
||||
__jtagCP15WriteReg(1, 0, 0, 0, v_reg);
|
||||
|
||||
}
|
||||
|
||||
execUserPreload()
|
||||
{
|
||||
__var t ;
|
||||
|
||||
__message "Executing execUserPreload() function";
|
||||
|
||||
__hwReset(0);
|
||||
__delay(100);
|
||||
__init_TCM();
|
||||
|
||||
__message "FINISH Executing execUserPreload() function";
|
||||
}
|
||||
|
||||
|
||||
execUserReset()
|
||||
{
|
||||
__var t;
|
||||
__message "Executing execUserReset() function";
|
||||
|
||||
__init_VIC_ProvideHandler();
|
||||
|
||||
t = #CPSR; // Clear CPSR.F bit
|
||||
__message "CPSR ",t:%x;
|
||||
t = t & 0xFFFFFFBF;
|
||||
#CPSR = t;
|
||||
t = #CPSR;
|
||||
__message "CPSR ",t:%x;
|
||||
|
||||
__message "FINISH Executing execUserReset() function";
|
||||
}
|
||||
@@ -0,0 +1,163 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x40020040;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x4008FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x00070000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x0007FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_svcstack__ = 0x200;
|
||||
define symbol __ICFEDIT_size_irqstack__ = 0x100;
|
||||
define symbol __ICFEDIT_size_fiqstack__ = 0x100;
|
||||
define symbol __ICFEDIT_size_undstack__ = 0x100;
|
||||
define symbol __ICFEDIT_size_abtstack__ = 0x100;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define symbol __region_USER_PRG_start__ = 0x00000040;
|
||||
define symbol __region_USER_PRG_end__ = 0x0006FFFF;
|
||||
|
||||
define symbol __region_D_LDR_DATA_start__ = 0x00800000;
|
||||
define symbol __region_D_LDR_DATA_end__ = 0x00801FFF;
|
||||
define symbol __region_D_LDR_PRG_start__ = 0x00802000;
|
||||
define symbol __region_D_LDR_PRG_end__ = 0x00807FFF;
|
||||
|
||||
define symbol __region_D_LDR_M3PRG_start__ = 0x04000000;
|
||||
define symbol __region_D_LDR_M3PRG_end__ = 0x0407FFFF;
|
||||
|
||||
define symbol __region_S_LDR_M3PRG_start__ = 0x00050000;
|
||||
define symbol __region_S_LDR_M3PRG_end__ = 0x0006FFFF;
|
||||
|
||||
define symbol __region_EXT_RAM1_start__ = 0x22000000;
|
||||
define symbol __region_EXT_RAM1_end__ = 0x2207FFFF;
|
||||
define symbol __region_EXT_RAM2_start__ = 0x24000000;
|
||||
define symbol __region_EXT_RAM2_end__ = 0x2407FFFF;
|
||||
define symbol __region_SPIBSC_start__ = 0x30000000;
|
||||
define symbol __region_SPIBSC_end__ = 0x33FFFFFF;
|
||||
|
||||
define symbol __region_CS0_start__ = 0x40000000;
|
||||
define symbol __region_CS0_end__ = 0x43FFFFFF;
|
||||
define symbol __region_CS1_start__ = 0x44000000;
|
||||
define symbol __region_CS1_end__ = 0x47FFFFFF;
|
||||
define symbol __region_CS2_start__ = 0x48000000;
|
||||
define symbol __region_CS2_end__ = 0x4BFFFFFF;
|
||||
define symbol __region_CS3_start__ = 0x4C000000;
|
||||
define symbol __region_CS3_end__ = 0x4FFFFFFF;
|
||||
define symbol __region_CS4_start__ = 0x50000000;
|
||||
define symbol __region_CS4_end__ = 0x53FFFFFF;
|
||||
define symbol __region_CS5_start__ = 0x54000000;
|
||||
define symbol __region_CS5_end__ = 0x57FFFFFF;
|
||||
|
||||
define region USER_PRG_region = mem:[from __region_USER_PRG_start__ to __region_USER_PRG_end__];
|
||||
define region D_LDR_DATA_region = mem:[from __region_D_LDR_DATA_start__ to __region_D_LDR_DATA_end__];
|
||||
define region D_LDR_PRG_region = mem:[from __region_D_LDR_PRG_start__ to __region_D_LDR_PRG_end__];
|
||||
|
||||
define region D_LDR_M3PRG_region = mem:[from __region_D_LDR_M3PRG_start__ to __region_D_LDR_M3PRG_end__];
|
||||
define region S_LDR_M3PRG_region = mem:[from __region_S_LDR_M3PRG_start__ to __region_S_LDR_M3PRG_end__];
|
||||
|
||||
define region EXT_RAM1_region = mem:[from __region_EXT_RAM1_start__ to __region_EXT_RAM1_end__];
|
||||
define region EXT_RAM2_region = mem:[from __region_EXT_RAM2_start__ to __region_EXT_RAM2_end__];
|
||||
define region SPIBSC_region = mem:[from __region_SPIBSC_start__ to __region_SPIBSC_end__];
|
||||
define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__];
|
||||
define region CS1_region = mem:[from __region_CS1_start__ to __region_CS1_end__];
|
||||
define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__];
|
||||
define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__];
|
||||
define region CS4_region = mem:[from __region_CS4_start__ to __region_CS4_end__];
|
||||
define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
|
||||
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
|
||||
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
|
||||
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
|
||||
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
|
||||
define block LDR_PRG_RBLOCK with fixed order
|
||||
{ ro code object loader_init.o,
|
||||
ro code object loader_init2.o,
|
||||
ro code object r_atcm_init.o,
|
||||
ro code object r_cpg.o,
|
||||
ro code object r_ram_init.o,
|
||||
ro code object r_mpc.o,
|
||||
ro code object r_reset.o,
|
||||
ro code object data_init.o,
|
||||
ro code object copy_init3.o };
|
||||
define block LDR_DATA_ZBLOCK { section .bss object loader_init.o,
|
||||
section .bss object loader_init2.o,
|
||||
section .bss object r_atcm_init.o,
|
||||
section .bss object r_cpg.o,
|
||||
section .bss object r_ram_init.o,
|
||||
section .bss object r_mpc.o,
|
||||
section .bss object r_reset.o,
|
||||
section .bss object data_init.o,
|
||||
section .bss object copy_init3.o };
|
||||
define block LDR_DATA_RBLOCK { section .data_init object loader_init.o,
|
||||
section .data_init object loader_init2.o,
|
||||
section .data_init object r_atcm_init.o,
|
||||
section .data_init object r_cpg.o,
|
||||
section .data_init object r_ram_init.o,
|
||||
section .data_init object r_mpc.o,
|
||||
section .data_init object r_reset.o,
|
||||
section .data_init object data_init.o,
|
||||
section .data_init object copy_init3.o };
|
||||
define block LDR_DATA_WBLOCK { section .data object loader_init.o,
|
||||
section .data object loader_init2.o,
|
||||
section .data object r_atcm_init.o,
|
||||
section .data object r_cpg.o,
|
||||
section .data object r_ram_init.o,
|
||||
section .data object r_mpc.o,
|
||||
section .data object r_reset.o,
|
||||
section .data object data_init.o,
|
||||
section .data object copy_init3.o };
|
||||
define block VECTOR_RBLOCK { ro code object vector.o };
|
||||
define block USER_PRG_RBLOCK { ro code };
|
||||
define block USER_DATA_ZBLOCK { section .bss };
|
||||
define block USER_DATA_RBLOCK { section .data_init };
|
||||
define block USER_DATA_WBLOCK { section .data };
|
||||
|
||||
define block M3_PRG_RBLOCK { section __M3prg_init };
|
||||
define block M3_PRG_WBLOCK { section __M3prg };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
|
||||
do not initialize { section .noinit, section .bss };
|
||||
|
||||
initialize manually { section __M3prg };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { block VECTOR_RBLOCK };
|
||||
|
||||
place in USER_PRG_region { block USER_PRG_RBLOCK,
|
||||
block USER_DATA_RBLOCK,
|
||||
readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in RAM_region { block USER_DATA_WBLOCK,
|
||||
block USER_DATA_ZBLOCK,
|
||||
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
|
||||
block UND_STACK, block ABT_STACK, block HEAP };
|
||||
place in D_LDR_DATA_region { block LDR_DATA_WBLOCK, block LDR_DATA_ZBLOCK };
|
||||
place in D_LDR_PRG_region { block LDR_PRG_RBLOCK,
|
||||
block LDR_DATA_RBLOCK };
|
||||
|
||||
place in S_LDR_M3PRG_region { block M3_PRG_RBLOCK };
|
||||
place in D_LDR_M3PRG_region { block M3_PRG_WBLOCK };
|
||||
|
||||
place in EXT_RAM1_region {};
|
||||
place in EXT_RAM2_region {};
|
||||
place in SPIBSC_region {};
|
||||
place in CS0_region {};
|
||||
place in CS1_region {};
|
||||
place in CS2_region {};
|
||||
place in CS3_region {};
|
||||
place in CS4_region {};
|
||||
place in CS5_region {};
|
||||
@@ -0,0 +1,64 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_atcm.h
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for ATCM function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : ATCM access wait setting API of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _R_ATCM_HEADER_
|
||||
#define _R_ATCM_HEADER_
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define ATCM_WAIT_1_OPT (0)
|
||||
#define ATCM_WAIT_1 (1)
|
||||
#define ATCM_WAIT_0 (2)
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
void R_ATCM_WaitSet(uint32_t atcm_wait);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
@@ -0,0 +1,186 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_cpg.h
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for CPG function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : BSC setting API of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _R_BSC_HEADER_
|
||||
#define _R_BSC_HEADER_
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define BSC_IDLE_CYCLE_0 (0)
|
||||
#define BSC_IDLE_CYCLE_1 (1)
|
||||
#define BSC_IDLE_CYCLE_2 (2)
|
||||
#define BSC_IDLE_CYCLE_4 (3)
|
||||
#define BSC_IDLE_CYCLE_6 (4)
|
||||
#define BSC_IDLE_CYCLE_8 (5)
|
||||
#define BSC_IDLE_CYCLE_10 (6)
|
||||
#define BSC_IDLE_CYCLE_12 (7)
|
||||
|
||||
#define BSC_TYPE_NORMAL (0)
|
||||
#define BSC_TYPE_BURST_ROM_ASYNC (1)
|
||||
#define BSC_TYPE_MPX_IO (2)
|
||||
#define BSC_TYPE_SRAM_BYTE (3)
|
||||
#define BSC_TYPE_SDRAM (4)
|
||||
#define BSC_TYPE_BURST_ROM_SYNC (7)
|
||||
|
||||
#define BSC_WIDTH_8_BIT (1)
|
||||
#define BSC_WIDTH_16_BIT (2)
|
||||
#define BSC_WIDTH_32_BIT (3)
|
||||
|
||||
#define BSC_DELAY_STATE_CYCLE_0_5 (0)
|
||||
#define BSC_DELAY_STATE_CYCLE_1_5 (1)
|
||||
#define BSC_DELAY_STATE_CYCLE_2_5 (2)
|
||||
#define BSC_DELAY_STATE_CYCLE_3_5 (3)
|
||||
|
||||
#define BSC_EXT_WAIT_VALID (0)
|
||||
#define BSC_EXT_WAIT_IGNORED (1)
|
||||
|
||||
#define BSC_ACCESS_WAIT_0 (0)
|
||||
#define BSC_ACCESS_WAIT_1 (1)
|
||||
#define BSC_ACCESS_WAIT_2 (2)
|
||||
#define BSC_ACCESS_WAIT_3 (3)
|
||||
#define BSC_ACCESS_WAIT_4 (4)
|
||||
#define BSC_ACCESS_WAIT_5 (5)
|
||||
#define BSC_ACCESS_WAIT_6 (6)
|
||||
#define BSC_ACCESS_WAIT_8 (7)
|
||||
#define BSC_ACCESS_WAIT_10 (8)
|
||||
#define BSC_ACCESS_WAIT_12 (9)
|
||||
#define BSC_ACCESS_WAIT_14 (10)
|
||||
#define BSC_ACCESS_WAIT_18 (11)
|
||||
#define BSC_ACCESS_WAIT_24 (12)
|
||||
|
||||
#define BSC_WRITE_ACCESS_WAIT_SAME (0) // Set same settings of WR[3:0]bit
|
||||
#define BSC_WRITE_ACCESS_WAIT_0 (1)
|
||||
#define BSC_WRITE_ACCESS_WAIT_1 (2)
|
||||
#define BSC_WRITE_ACCESS_WAIT_2 (3)
|
||||
#define BSC_WRITE_ACCESS_WAIT_3 (4)
|
||||
#define BSC_WRITE_ACCESS_WAIT_4 (5)
|
||||
#define BSC_WRITE_ACCESS_WAIT_5 (6)
|
||||
#define BSC_WRITE_ACCESS_WAIT_6 (7)
|
||||
|
||||
#define BSC_BYTE_ENABLE_RD_WR (0)
|
||||
#define BSC_BYTE_ENABLE_WE (1)
|
||||
|
||||
#define BSC_CAS_LATENCY_1 (0)
|
||||
#define BSC_CAS_LATENCY_2 (1)
|
||||
#define BSC_CAS_LATENCY_3 (2)
|
||||
#define BSC_CAS_LATENCY_4 (3)
|
||||
|
||||
#define BSC_WTRC_IDLE_2 (0)
|
||||
#define BSC_WTRC_IDLE_3 (1)
|
||||
#define BSC_WTRC_IDLE_5 (2)
|
||||
#define BSC_WTRC_IDLE_8 (3)
|
||||
|
||||
#define BSC_TRWL_CYCLE_0 (0)
|
||||
#define BSC_TRWL_CYCLE_1 (1)
|
||||
#define BSC_TRWL_CYCLE_2 (2)
|
||||
#define BSC_TRWL_CYCLE_3 (3)
|
||||
|
||||
#define BSC_PRECHARGE_0 (0x00000000)
|
||||
#define BSC_PRECHARGE_1 (0x00000008)
|
||||
#define BSC_PRECHARGE_2 (0x00000010)
|
||||
#define BSC_PRECHARGE_3 (0x00000018)
|
||||
|
||||
#define BSC_WTRCD_WAIT_0 (0)
|
||||
#define BSC_WTRCD_WAIT_1 (1)
|
||||
#define BSC_WTRCD_WAIT_2 (2)
|
||||
#define BSC_WTRCD_WAIT_3 (3)
|
||||
|
||||
#define BSC_WTRP_WAIT_0 (0)
|
||||
#define BSC_WTRP_WAIT_1 (1)
|
||||
#define BSC_WTRP_WAIT_2 (2)
|
||||
#define BSC_WTRP_WAIT_3 (3)
|
||||
|
||||
#define BSC_ROW_11_BIT (0)
|
||||
#define BSC_ROW_12_BIT (1)
|
||||
#define BSC_ROW_13_BIT (2)
|
||||
|
||||
#define BSC_COL_8_BIT (0)
|
||||
#define BSC_COL_9_BIT (1)
|
||||
#define BSC_COL_10_BIT (2)
|
||||
|
||||
#define BSC_BACTV_AUTO (0)
|
||||
#define BSC_BACTV_BANK (1)
|
||||
|
||||
#define BSC_PDOWN_INVALID (0)
|
||||
#define BSC_PDOWN_VALID (1)
|
||||
|
||||
#define BSC_RMODE_AUTO (0)
|
||||
#define BSC_RMODE_SELF (1)
|
||||
|
||||
#define BSC_RFSH_NONE (0)
|
||||
#define BSC_RFSH_DONE (1)
|
||||
|
||||
#define BSC_DEEP_SELF (0)
|
||||
#define BSC_DEEP_DEEP (1)
|
||||
|
||||
#define BSC_PROTECT_KEY (0xA55A0000)
|
||||
|
||||
#define BSC_RFSH_TIME_1 (0)
|
||||
#define BSC_RFSH_TIME_2 (1)
|
||||
#define BSC_RFSH_TIME_4 (2)
|
||||
#define BSC_RFSH_TIME_6 (3)
|
||||
#define BSC_RFSH_TIME_8 (4)
|
||||
|
||||
#define BSC_CKS_DIV_STOP (0x00000000)
|
||||
#define BSC_CKS_DIV_4 (0x00000008)
|
||||
#define BSC_CKS_DIV_16 (0x00000010)
|
||||
#define BSC_CKS_DIV_64 (0x00000018)
|
||||
#define BSC_CKS_DIV_256 (0x00000020)
|
||||
#define BSC_CKS_DIV_1024 (0x00000028)
|
||||
#define BSC_CKS_DIV_2048 (0x00000030)
|
||||
#define BSC_CKS_DIV_4096 (0x00000038)
|
||||
|
||||
#define BSC_CMIE_DISABLE (0x00000000)
|
||||
#define BSC_CMIE_ENABLE (0x00000040)
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
@@ -0,0 +1,83 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_cpg.h
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for CPG function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : CPG setting API of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _R_CPG_HEADER_
|
||||
#define _R_CPG_HEADER_
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define CPG_CPUCLK_150_MHz (0)
|
||||
#define CPG_CPUCLK_300_MHz (1)
|
||||
#define CPG_CPUCLK_450_MHz (2)
|
||||
#define CPG_CPUCLK_600_MHz (3)
|
||||
|
||||
#define CPG_PLL1_OFF (0)
|
||||
#define CPG_PLL1_ON (1)
|
||||
|
||||
#define CPG_SELECT_PLL0 (0)
|
||||
#define CPG_SELECT_PLL1 (1)
|
||||
|
||||
#define CPG_CKIO_75_MHz (0)
|
||||
#define CPG_CKIO_50_MHz (1)
|
||||
#define CPG_CKIO_37_5_MHz (2)
|
||||
#define CPG_CKIO_30_MHz (3)
|
||||
#define CPG_CKIO_25_MHz (4)
|
||||
#define CPG_CKIO_21_43_MHz (5)
|
||||
#define CPG_CKIO_18_75_MHz (6)
|
||||
|
||||
#define CPG_LOCO_ENABLE (0x00000000)
|
||||
#define CPG_LOCO_DISABLE (0x00000001)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
void R_CPG_WriteEnable(void);
|
||||
void R_CPG_WriteDisable(void);
|
||||
void R_CPG_PLL_Wait(void);
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
@@ -0,0 +1,72 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_ecm.h
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for ecm function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : ecm function API of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _R_ECM_HEADER_
|
||||
#define _R_ECM_HEADER_
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define ECM_COMMAND_KEY (0x000000A5)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
ECM_MASTER,
|
||||
ECM_CHECKER,
|
||||
ECM_COMMON,
|
||||
ECM_TYPE_MAX
|
||||
} ecm_reg_type_t;
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
void R_ECM_Init(void);
|
||||
void R_ECM_CompareError_Wait(void);
|
||||
uint8_t R_ECM_Write_Reg8(uint8_t reg_type, volatile unsigned char *reg, uint8_t value);
|
||||
uint8_t R_ECM_Write_Reg32(uint8_t reg_type, volatile unsigned long *reg, uint32_t value);
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
@@ -0,0 +1,389 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_icu_init.h
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for ICU init
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Initialize interrupt controller unit.
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _R_ICU_INIT_HEADER_
|
||||
#define _R_ICU_INIT_HEADER_
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
#define ICU_EXT_PIN_0 (0)
|
||||
#define ICU_EXT_PIN_1 (1)
|
||||
#define ICU_EXT_PIN_2 (2)
|
||||
#define ICU_EXT_PIN_3 (3)
|
||||
#define ICU_EXT_PIN_4 (4)
|
||||
#define ICU_EXT_PIN_5 (5)
|
||||
#define ICU_EXT_PIN_6 (6)
|
||||
#define ICU_EXT_PIN_7 (7)
|
||||
#define ICU_EXT_PIN_8 (8)
|
||||
#define ICU_EXT_PIN_9 (9)
|
||||
#define ICU_EXT_PIN_10 (10)
|
||||
#define ICU_EXT_PIN_11 (11)
|
||||
#define ICU_EXT_PIN_12 (12)
|
||||
#define ICU_EXT_PIN_13 (13)
|
||||
#define ICU_EXT_PIN_14 (14)
|
||||
#define ICU_EXT_PIN_15 (15)
|
||||
|
||||
#define ICU_DETECT_LOW (0x00)
|
||||
#define ICU_DETECT_FALL (0x04)
|
||||
#define ICU_DETECT_RISE (0x08)
|
||||
#define ICU_DETECT_RISE_FALL (0x0C)
|
||||
|
||||
#define ICU_DNF_DIVISION_1 (0)
|
||||
#define ICU_DNF_DIVISION_8 (1)
|
||||
#define ICU_DNF_DIVISION_32 (2)
|
||||
#define ICU_DNF_DIVISION_64 (3)
|
||||
#define ICU_DNF_NO_USE (4)
|
||||
|
||||
#define ICU_VEC_NUM_1 (1)
|
||||
#define ICU_VEC_NUM_2 (2)
|
||||
#define ICU_VEC_NUM_3 (3)
|
||||
#define ICU_VEC_NUM_4 (4)
|
||||
#define ICU_VEC_NUM_5 (5)
|
||||
#define ICU_VEC_NUM_6 (6)
|
||||
#define ICU_VEC_NUM_7 (7)
|
||||
#define ICU_VEC_NUM_8 (8)
|
||||
#define ICU_VEC_NUM_9 (9)
|
||||
#define ICU_VEC_NUM_10 (10)
|
||||
#define ICU_VEC_NUM_11 (11)
|
||||
#define ICU_VEC_NUM_12 (12)
|
||||
#define ICU_VEC_NUM_13 (13)
|
||||
#define ICU_VEC_NUM_14 (14)
|
||||
#define ICU_VEC_NUM_15 (15)
|
||||
#define ICU_VEC_NUM_16 (16)
|
||||
#define ICU_VEC_NUM_17 (17)
|
||||
#define ICU_VEC_NUM_18 (18)
|
||||
#define ICU_VEC_NUM_19 (19)
|
||||
#define ICU_VEC_NUM_20 (20)
|
||||
#define ICU_VEC_NUM_21 (21)
|
||||
#define ICU_VEC_NUM_22 (22)
|
||||
#define ICU_VEC_NUM_23 (23)
|
||||
#define ICU_VEC_NUM_24 (24)
|
||||
#define ICU_VEC_NUM_25 (25)
|
||||
#define ICU_VEC_NUM_26 (26)
|
||||
#define ICU_VEC_NUM_27 (27)
|
||||
#define ICU_VEC_NUM_28 (28)
|
||||
#define ICU_VEC_NUM_29 (29)
|
||||
#define ICU_VEC_NUM_30 (30)
|
||||
#define ICU_VEC_NUM_31 (31)
|
||||
#define ICU_VEC_NUM_32 (32)
|
||||
#define ICU_VEC_NUM_33 (33)
|
||||
#define ICU_VEC_NUM_34 (34)
|
||||
#define ICU_VEC_NUM_35 (35)
|
||||
#define ICU_VEC_NUM_36 (36)
|
||||
#define ICU_VEC_NUM_37 (37)
|
||||
#define ICU_VEC_NUM_38 (38)
|
||||
#define ICU_VEC_NUM_39 (39)
|
||||
#define ICU_VEC_NUM_40 (40)
|
||||
#define ICU_VEC_NUM_41 (41)
|
||||
#define ICU_VEC_NUM_42 (42)
|
||||
#define ICU_VEC_NUM_43 (43)
|
||||
#define ICU_VEC_NUM_44 (44)
|
||||
#define ICU_VEC_NUM_45 (45)
|
||||
#define ICU_VEC_NUM_46 (46)
|
||||
#define ICU_VEC_NUM_47 (47)
|
||||
#define ICU_VEC_NUM_48 (48)
|
||||
#define ICU_VEC_NUM_49 (49)
|
||||
#define ICU_VEC_NUM_50 (50)
|
||||
#define ICU_VEC_NUM_51 (51)
|
||||
#define ICU_VEC_NUM_52 (52)
|
||||
#define ICU_VEC_NUM_53 (53)
|
||||
#define ICU_VEC_NUM_54 (54)
|
||||
#define ICU_VEC_NUM_55 (55)
|
||||
#define ICU_VEC_NUM_56 (56)
|
||||
#define ICU_VEC_NUM_57 (57)
|
||||
#define ICU_VEC_NUM_58 (58)
|
||||
#define ICU_VEC_NUM_59 (59)
|
||||
#define ICU_VEC_NUM_60 (60)
|
||||
#define ICU_VEC_NUM_61 (61)
|
||||
#define ICU_VEC_NUM_62 (62)
|
||||
#define ICU_VEC_NUM_63 (63)
|
||||
#define ICU_VEC_NUM_64 (64)
|
||||
#define ICU_VEC_NUM_65 (65)
|
||||
#define ICU_VEC_NUM_66 (66)
|
||||
#define ICU_VEC_NUM_67 (67)
|
||||
#define ICU_VEC_NUM_68 (68)
|
||||
#define ICU_VEC_NUM_69 (69)
|
||||
#define ICU_VEC_NUM_70 (70)
|
||||
#define ICU_VEC_NUM_73 (73)
|
||||
#define ICU_VEC_NUM_74 (74)
|
||||
#define ICU_VEC_NUM_75 (75)
|
||||
#define ICU_VEC_NUM_76 (76)
|
||||
#define ICU_VEC_NUM_77 (77)
|
||||
#define ICU_VEC_NUM_78 (78)
|
||||
#define ICU_VEC_NUM_79 (79)
|
||||
#define ICU_VEC_NUM_80 (80)
|
||||
#define ICU_VEC_NUM_81 (81)
|
||||
#define ICU_VEC_NUM_82 (82)
|
||||
#define ICU_VEC_NUM_83 (83)
|
||||
#define ICU_VEC_NUM_84 (84)
|
||||
#define ICU_VEC_NUM_85 (85)
|
||||
#define ICU_VEC_NUM_86 (86)
|
||||
#define ICU_VEC_NUM_87 (87)
|
||||
#define ICU_VEC_NUM_88 (88)
|
||||
#define ICU_VEC_NUM_89 (89)
|
||||
#define ICU_VEC_NUM_90 (90)
|
||||
#define ICU_VEC_NUM_91 (91)
|
||||
#define ICU_VEC_NUM_92 (92)
|
||||
#define ICU_VEC_NUM_93 (93)
|
||||
#define ICU_VEC_NUM_94 (94)
|
||||
#define ICU_VEC_NUM_95 (95)
|
||||
#define ICU_VEC_NUM_96 (96)
|
||||
#define ICU_VEC_NUM_97 (97)
|
||||
#define ICU_VEC_NUM_98 (98)
|
||||
#define ICU_VEC_NUM_99 (99)
|
||||
#define ICU_VEC_NUM_100 (100)
|
||||
#define ICU_VEC_NUM_101 (101)
|
||||
#define ICU_VEC_NUM_102 (102)
|
||||
#define ICU_VEC_NUM_103 (103)
|
||||
#define ICU_VEC_NUM_104 (104)
|
||||
#define ICU_VEC_NUM_105 (105)
|
||||
#define ICU_VEC_NUM_106 (106)
|
||||
#define ICU_VEC_NUM_107 (107)
|
||||
#define ICU_VEC_NUM_108 (108)
|
||||
#define ICU_VEC_NUM_109 (109)
|
||||
#define ICU_VEC_NUM_110 (110)
|
||||
#define ICU_VEC_NUM_111 (111)
|
||||
#define ICU_VEC_NUM_112 (112)
|
||||
#define ICU_VEC_NUM_113 (113)
|
||||
#define ICU_VEC_NUM_114 (114)
|
||||
#define ICU_VEC_NUM_115 (115)
|
||||
#define ICU_VEC_NUM_116 (116)
|
||||
#define ICU_VEC_NUM_117 (117)
|
||||
#define ICU_VEC_NUM_118 (118)
|
||||
#define ICU_VEC_NUM_119 (119)
|
||||
#define ICU_VEC_NUM_120 (120)
|
||||
#define ICU_VEC_NUM_121 (121)
|
||||
#define ICU_VEC_NUM_122 (122)
|
||||
#define ICU_VEC_NUM_123 (123)
|
||||
#define ICU_VEC_NUM_124 (124)
|
||||
#define ICU_VEC_NUM_125 (125)
|
||||
#define ICU_VEC_NUM_126 (126)
|
||||
#define ICU_VEC_NUM_127 (127)
|
||||
#define ICU_VEC_NUM_128 (128)
|
||||
#define ICU_VEC_NUM_145 (145)
|
||||
#define ICU_VEC_NUM_146 (146)
|
||||
#define ICU_VEC_NUM_147 (147)
|
||||
#define ICU_VEC_NUM_148 (148)
|
||||
#define ICU_VEC_NUM_149 (149)
|
||||
#define ICU_VEC_NUM_150 (150)
|
||||
#define ICU_VEC_NUM_151 (151)
|
||||
#define ICU_VEC_NUM_152 (152)
|
||||
#define ICU_VEC_NUM_153 (153)
|
||||
#define ICU_VEC_NUM_154 (154)
|
||||
#define ICU_VEC_NUM_155 (155)
|
||||
#define ICU_VEC_NUM_156 (156)
|
||||
#define ICU_VEC_NUM_157 (157)
|
||||
#define ICU_VEC_NUM_158 (158)
|
||||
#define ICU_VEC_NUM_159 (159)
|
||||
#define ICU_VEC_NUM_160 (160)
|
||||
#define ICU_VEC_NUM_161 (161)
|
||||
#define ICU_VEC_NUM_162 (162)
|
||||
#define ICU_VEC_NUM_163 (163)
|
||||
#define ICU_VEC_NUM_164 (164)
|
||||
#define ICU_VEC_NUM_165 (165)
|
||||
#define ICU_VEC_NUM_166 (166)
|
||||
#define ICU_VEC_NUM_167 (167)
|
||||
#define ICU_VEC_NUM_168 (168)
|
||||
#define ICU_VEC_NUM_169 (169)
|
||||
#define ICU_VEC_NUM_170 (170)
|
||||
#define ICU_VEC_NUM_171 (171)
|
||||
#define ICU_VEC_NUM_172 (172)
|
||||
#define ICU_VEC_NUM_173 (173)
|
||||
#define ICU_VEC_NUM_174 (174)
|
||||
#define ICU_VEC_NUM_175 (175)
|
||||
#define ICU_VEC_NUM_176 (176)
|
||||
#define ICU_VEC_NUM_177 (177)
|
||||
#define ICU_VEC_NUM_178 (178)
|
||||
#define ICU_VEC_NUM_179 (179)
|
||||
#define ICU_VEC_NUM_180 (180)
|
||||
#define ICU_VEC_NUM_181 (181)
|
||||
#define ICU_VEC_NUM_182 (182)
|
||||
#define ICU_VEC_NUM_183 (183)
|
||||
#define ICU_VEC_NUM_184 (184)
|
||||
#define ICU_VEC_NUM_185 (185)
|
||||
#define ICU_VEC_NUM_186 (186)
|
||||
#define ICU_VEC_NUM_187 (187)
|
||||
#define ICU_VEC_NUM_188 (188)
|
||||
#define ICU_VEC_NUM_189 (189)
|
||||
#define ICU_VEC_NUM_190 (190)
|
||||
#define ICU_VEC_NUM_191 (191)
|
||||
#define ICU_VEC_NUM_192 (192)
|
||||
#define ICU_VEC_NUM_193 (193)
|
||||
#define ICU_VEC_NUM_194 (194)
|
||||
#define ICU_VEC_NUM_195 (195)
|
||||
#define ICU_VEC_NUM_196 (196)
|
||||
#define ICU_VEC_NUM_197 (197)
|
||||
#define ICU_VEC_NUM_198 (198)
|
||||
#define ICU_VEC_NUM_199 (199)
|
||||
#define ICU_VEC_NUM_200 (200)
|
||||
#define ICU_VEC_NUM_201 (201)
|
||||
#define ICU_VEC_NUM_202 (202)
|
||||
#define ICU_VEC_NUM_203 (203)
|
||||
#define ICU_VEC_NUM_204 (204)
|
||||
#define ICU_VEC_NUM_205 (205)
|
||||
#define ICU_VEC_NUM_206 (206)
|
||||
#define ICU_VEC_NUM_207 (207)
|
||||
#define ICU_VEC_NUM_208 (208)
|
||||
#define ICU_VEC_NUM_209 (209)
|
||||
#define ICU_VEC_NUM_210 (210)
|
||||
#define ICU_VEC_NUM_211 (211)
|
||||
#define ICU_VEC_NUM_212 (212)
|
||||
#define ICU_VEC_NUM_213 (213)
|
||||
#define ICU_VEC_NUM_214 (214)
|
||||
#define ICU_VEC_NUM_215 (215)
|
||||
#define ICU_VEC_NUM_216 (216)
|
||||
#define ICU_VEC_NUM_217 (217)
|
||||
#define ICU_VEC_NUM_218 (218)
|
||||
#define ICU_VEC_NUM_219 (219)
|
||||
#define ICU_VEC_NUM_220 (220)
|
||||
#define ICU_VEC_NUM_221 (221)
|
||||
#define ICU_VEC_NUM_222 (222)
|
||||
#define ICU_VEC_NUM_223 (223)
|
||||
#define ICU_VEC_NUM_224 (224)
|
||||
#define ICU_VEC_NUM_225 (225)
|
||||
#define ICU_VEC_NUM_226 (226)
|
||||
#define ICU_VEC_NUM_227 (227)
|
||||
#define ICU_VEC_NUM_228 (228)
|
||||
#define ICU_VEC_NUM_229 (229)
|
||||
#define ICU_VEC_NUM_230 (230)
|
||||
#define ICU_VEC_NUM_231 (231)
|
||||
#define ICU_VEC_NUM_232 (232)
|
||||
#define ICU_VEC_NUM_233 (233)
|
||||
#define ICU_VEC_NUM_234 (234)
|
||||
#define ICU_VEC_NUM_235 (235)
|
||||
#define ICU_VEC_NUM_236 (236)
|
||||
#define ICU_VEC_NUM_237 (237)
|
||||
#define ICU_VEC_NUM_238 (238)
|
||||
#define ICU_VEC_NUM_239 (239)
|
||||
#define ICU_VEC_NUM_240 (240)
|
||||
#define ICU_VEC_NUM_241 (241)
|
||||
#define ICU_VEC_NUM_242 (242)
|
||||
#define ICU_VEC_NUM_243 (243)
|
||||
#define ICU_VEC_NUM_246 (246)
|
||||
#define ICU_VEC_NUM_247 (247)
|
||||
#define ICU_VEC_NUM_248 (248)
|
||||
#define ICU_VEC_NUM_249 (249)
|
||||
#define ICU_VEC_NUM_250 (250)
|
||||
#define ICU_VEC_NUM_251 (251)
|
||||
#define ICU_VEC_NUM_252 (252)
|
||||
#define ICU_VEC_NUM_254 (254)
|
||||
#define ICU_VEC_NUM_256 (256)
|
||||
#define ICU_VEC_NUM_257 (257)
|
||||
#define ICU_VEC_NUM_258 (258)
|
||||
#define ICU_VEC_NUM_259 (259)
|
||||
#define ICU_VEC_NUM_260 (260)
|
||||
#define ICU_VEC_NUM_261 (261)
|
||||
#define ICU_VEC_NUM_262 (262)
|
||||
#define ICU_VEC_NUM_263 (263)
|
||||
#define ICU_VEC_NUM_264 (264)
|
||||
#define ICU_VEC_NUM_265 (265)
|
||||
#define ICU_VEC_NUM_266 (266)
|
||||
#define ICU_VEC_NUM_267 (267)
|
||||
#define ICU_VEC_NUM_268 (268)
|
||||
#define ICU_VEC_NUM_269 (269)
|
||||
#define ICU_VEC_NUM_270 (270)
|
||||
#define ICU_VEC_NUM_271 (271)
|
||||
#define ICU_VEC_NUM_272 (272)
|
||||
#define ICU_VEC_NUM_273 (273)
|
||||
#define ICU_VEC_NUM_274 (274)
|
||||
#define ICU_VEC_NUM_275 (275)
|
||||
#define ICU_VEC_NUM_276 (276)
|
||||
#define ICU_VEC_NUM_277 (277)
|
||||
#define ICU_VEC_NUM_278 (278)
|
||||
#define ICU_VEC_NUM_279 (279)
|
||||
#define ICU_VEC_NUM_280 (280)
|
||||
#define ICU_VEC_NUM_281 (281)
|
||||
#define ICU_VEC_NUM_282 (282)
|
||||
#define ICU_VEC_NUM_283 (283)
|
||||
#define ICU_VEC_NUM_284 (284)
|
||||
#define ICU_VEC_NUM_285 (285)
|
||||
#define ICU_VEC_NUM_286 (286)
|
||||
#define ICU_VEC_NUM_287 (287)
|
||||
#define ICU_VEC_NUM_288 (288)
|
||||
#define ICU_VEC_NUM_289 (289)
|
||||
#define ICU_VEC_NUM_290 (290)
|
||||
#define ICU_VEC_NUM_291 (291)
|
||||
#define ICU_VEC_NUM_292 (292)
|
||||
#define ICU_VEC_NUM_293 (293)
|
||||
#define ICU_VEC_NUM_294 (294)
|
||||
|
||||
#define ICU_TYPE_LEVEL (0)
|
||||
#define ICU_TYPE_EDGE (1)
|
||||
|
||||
#define ICU_PRIORITY_0 (0)
|
||||
#define ICU_PRIORITY_1 (1)
|
||||
#define ICU_PRIORITY_2 (2)
|
||||
#define ICU_PRIORITY_3 (3)
|
||||
#define ICU_PRIORITY_4 (4)
|
||||
#define ICU_PRIORITY_5 (5)
|
||||
#define ICU_PRIORITY_6 (6)
|
||||
#define ICU_PRIORITY_7 (7)
|
||||
#define ICU_PRIORITY_8 (8)
|
||||
#define ICU_PRIORITY_9 (9)
|
||||
#define ICU_PRIORITY_10 (10)
|
||||
#define ICU_PRIORITY_11 (11)
|
||||
#define ICU_PRIORITY_12 (12)
|
||||
#define ICU_PRIORITY_13 (13)
|
||||
#define ICU_PRIORITY_14 (14)
|
||||
#define ICU_PRIORITY_15 (15)
|
||||
|
||||
#define ICU_IEC_MASK_SET (1)
|
||||
|
||||
#define ICU_PIC_EDGE_CLEAR (1)
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
void R_ICU_Disable(uint32_t vec_num);
|
||||
void R_ICU_Enable(uint32_t vec_num);
|
||||
void R_ICU_ExtPinInit(uint16_t pin_num, uint8_t detect, uint32_t dnf_set);
|
||||
void R_ICU_Regist(uint32_t vec_num, uint32_t type, uint32_t priority, uint32_t isr_addr);
|
||||
void R_ICU_Disable(uint32_t vec_num);
|
||||
void R_ICU_Enable(uint32_t vec_num);
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
@@ -0,0 +1,118 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_mpc.h
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for MPC function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : MPC setting API of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _R_MPC_HEADER_
|
||||
#define _R_MPC_HEADER_
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define MPC_IRQ_DISABLE (0)
|
||||
#define MPC_IRQ_ENABLE (1)
|
||||
|
||||
#define MPC_PSEL_PT6_A21 (0x23)
|
||||
#define MPC_PSEL_PT7_A22 (0x23)
|
||||
#define MPC_PSEL_PK2_A23 (0x23)
|
||||
#define MPC_PSEL_PK3_A24 (0x23)
|
||||
#define MPC_PSEL_P97_A25 (0x23)
|
||||
#define MPC_PSEL_P36_WE0_DQMLL (0x22)
|
||||
#define MPC_PSEL_P37_WE1_DQMLU (0x22)
|
||||
#define MPC_PSEL_PD1_CS1 (0x23)
|
||||
#define MPC_PSEL_P45_CS2 (0x22)
|
||||
#define MPC_PSEL_PT4_CS3 (0x23)
|
||||
#define MPC_PSEL_P90_RAS (0x23)
|
||||
#define MPC_PSEL_PK0_CAS (0x23)
|
||||
#define MPC_PSEL_P24_RD_WR (0x22)
|
||||
#define MPC_PSEL_P46_CKE (0x22)
|
||||
#define MPC_PSEL_P10_CKIO (0x22)
|
||||
#define MPC_PSEL_P23_A0 (0x22)
|
||||
#define MPC_PSEL_PG0_A1 (0x22)
|
||||
#define MPC_PSEL_PG1_A2 (0x22)
|
||||
#define MPC_PSEL_PG2_A3 (0x22)
|
||||
#define MPC_PSEL_PG3_A4 (0x22)
|
||||
#define MPC_PSEL_PG4_A5 (0x22)
|
||||
#define MPC_PSEL_PG5_A6 (0x22)
|
||||
#define MPC_PSEL_PG6_A7 (0x22)
|
||||
#define MPC_PSEL_PG7_A8 (0x22)
|
||||
#define MPC_PSEL_PH0_A9 (0x22)
|
||||
#define MPC_PSEL_PH1_A10 (0x22)
|
||||
#define MPC_PSEL_PH2_A11 (0x22)
|
||||
#define MPC_PSEL_PH3_A12 (0x22)
|
||||
#define MPC_PSEL_PH4_A13 (0x22)
|
||||
#define MPC_PSEL_PH5_A14 (0x22)
|
||||
#define MPC_PSEL_PH6_A15 (0x22)
|
||||
#define MPC_PSEL_PH7_A16 (0x22)
|
||||
#define MPC_PSEL_P20_A17 (0x22)
|
||||
#define MPC_PSEL_P25_A18 (0x22)
|
||||
#define MPC_PSEL_P26_A19 (0x22)
|
||||
#define MPC_PSEL_P27_A20 (0x22)
|
||||
#define MPC_PSEL_P00_D0 (0x22)
|
||||
#define MPC_PSEL_P01_D1 (0x22)
|
||||
#define MPC_PSEL_P02_D2 (0x22)
|
||||
#define MPC_PSEL_P03_D3 (0x22)
|
||||
#define MPC_PSEL_P04_D4 (0x22)
|
||||
#define MPC_PSEL_P05_D5 (0x22)
|
||||
#define MPC_PSEL_P06_D6 (0x22)
|
||||
#define MPC_PSEL_P07_D7 (0x22)
|
||||
#define MPC_PSEL_PE0_D8 (0x22)
|
||||
#define MPC_PSEL_PE1_D9 (0x22)
|
||||
#define MPC_PSEL_PE2_D10 (0x22)
|
||||
#define MPC_PSEL_PE3_D11 (0x22)
|
||||
#define MPC_PSEL_PE4_D12 (0x22)
|
||||
#define MPC_PSEL_PE5_D13 (0x22)
|
||||
#define MPC_PSEL_PE6_D14 (0x22)
|
||||
#define MPC_PSEL_PE7_D15 (0x22)
|
||||
#define MPC_PSEL_P22_RD (0x22)
|
||||
#define MPC_PSEL_P21_CS0 (0x22)
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
void R_MPC_WriteEnable(void);
|
||||
void R_MPC_WriteDisable(void);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
@@ -0,0 +1,76 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_port.h
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for PORT function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : PORT setting API of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _R_PORT_HEADER_
|
||||
#define _R_PORT_HEADER_
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define PORT_DIRECTION_HIZ (0)
|
||||
#define PORT_DIRECTION_INPUT (2)
|
||||
#define PORT_DIRECTION_OUTPUT (3)
|
||||
|
||||
#define PORT_OUTPUT_LOW (0)
|
||||
#define PORT_OUTPUT_HIGH (1)
|
||||
|
||||
#define PORT_MODE_GENERAL (0)
|
||||
#define PORT_MODE_PERIPHERAL (1)
|
||||
|
||||
#define PORT_PULL_UPDOWN_DISABLE (0)
|
||||
#define PORT_PULL_DOWN (1)
|
||||
#define PORT_PULL_UP (2)
|
||||
|
||||
#define PORT_P10_NORMAL_DRIVE (0)
|
||||
#define PORT_P10_HIGH_DRIVE (1)
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
@@ -0,0 +1,64 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_ram.h
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for internal extended RAM function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Internal extended RAM setting API of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _R_RAM_HEADER_
|
||||
#define _R_RAM_HEADER_
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
void R_RAM_Init(void);
|
||||
void R_RAM_ECC_Enable(void);
|
||||
void R_RAM_WriteEnable(void);
|
||||
void R_RAM_WriteDisable(void);
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
@@ -0,0 +1,64 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_reset.h
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for reset function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Reset function API of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _R_RESET_HEADER_
|
||||
#define _R_RESET_HEADER_
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define RST_SOURCE_RES (0x00000002)
|
||||
#define RST_SOURCE_ECM (0x00000004)
|
||||
#define RST_SOURCE_SWR1 (0x00000008)
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
void r_rst_write_enable(void);
|
||||
void r_rst_write_disable(void);
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
@@ -0,0 +1,116 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_system.h
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : Definition for System
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Define the system settings ans value.
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _R_SYSTEM_HEADER_
|
||||
#define _R_SYSTEM_HEADER_
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPCRA0
|
||||
#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPCRA1
|
||||
#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPCRA2
|
||||
#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPCRA3
|
||||
#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPCRA4
|
||||
#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPCRA5
|
||||
#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPCRA6
|
||||
#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPCRA7
|
||||
#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPCRA8
|
||||
#define MSTP_GPTA SYSTEM.MSTPCRA.BIT.MSTPCRA9
|
||||
#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPCRA11
|
||||
|
||||
#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPCRB1
|
||||
#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPCRB2
|
||||
#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPCRB3
|
||||
#define MSTP_SCIFA4 SYSTEM.MSTPCRB.BIT.MSTPCRB5
|
||||
#define MSTP_SCIFA3 SYSTEM.MSTPCRB.BIT.MSTPCRB6
|
||||
#define MSTP_SCIFA2 SYSTEM.MSTPCRB.BIT.MSTPCRB7
|
||||
#define MSTP_SCIFA1 SYSTEM.MSTPCRB.BIT.MSTPCRB8
|
||||
#define MSTP_SCIFA0 SYSTEM.MSTPCRB.BIT.MSTPCRB9
|
||||
#define MSTP_RSPI3 SYSTEM.MSTPCRB.BIT.MSTPCRB10
|
||||
#define MSTP_RSPI2 SYSTEM.MSTPCRB.BIT.MSTPCRB11
|
||||
#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPCRB12
|
||||
#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPCRB13
|
||||
#define MSTP_ETHERSW SYSTEM.MSTPCRB.BIT.MSTPCRB14
|
||||
#define MSTP_ECATC SYSTEM.MSTPCRB.BIT.MSTPCRB15
|
||||
#define MSTP_EMDIO SYSTEM.MSTPCRB.BIT.MSTPCRB16
|
||||
#define MSTP_ERMII SYSTEM.MSTPCRB.BIT.MSTPCRB17
|
||||
#define MSTP_HWRTOS SYSTEM.MSTPCRB.BIT.MSTPCRB18
|
||||
#define MSTP_CLKOUT25M SYSTEM.MSTPCRB.BIT.MSTPCRB19
|
||||
|
||||
#define MSTP_USB SYSTEM.MSTPCRC.BIT.MSTPCRC1
|
||||
#define MSTP_DSMIF SYSTEM.MSTPCRC.BIT.MSTPCRC2
|
||||
#define MSTP_TEMPS SYSTEM.MSTPCRC.BIT.MSTPCRC3
|
||||
#define MSTP_S12ADC1 SYSTEM.MSTPCRC.BIT.MSTPCRC4
|
||||
#define MSTP_S12ADC0 SYSTEM.MSTPCRC.BIT.MSTPCRC5
|
||||
#define MSTP_ELC SYSTEM.MSTPCRC.BIT.MSTPCRC6
|
||||
#define MSTP_BSC SYSTEM.MSTPCRC.BIT.MSTPCRC7
|
||||
#define MSTP_CKIO SYSTEM.MSTPCRC.BIT.MSTPCRC8
|
||||
#define MSTP_SPIBSC SYSTEM.MSTPCRC.BIT.MSTPCRC9
|
||||
#define MSTP_DOC SYSTEM.MSTPCRC.BIT.MSTPCRC10
|
||||
#define MSTP_CRC SYSTEM.MSTPCRC.BIT.MSTPCRC11
|
||||
#define MSTP_CLMA2 SYSTEM.MSTPCRC.BIT.MSTPCRC12
|
||||
#define MSTP_CLMA1 SYSTEM.MSTPCRC.BIT.MSTPCRC13
|
||||
#define MSTP_CLMA0 SYSTEM.MSTPCRC.BIT.MSTPCRC14
|
||||
|
||||
#define MSTP_SSI SYSTEM.MSTPCRD.BIT.MSTPCRD2
|
||||
|
||||
#define MSTP_DMAC1 SYSTEM.MSTPCRE.BIT.MSTPCRE4
|
||||
#define MSTP_DMAC0 SYSTEM.MSTPCRE.BIT.MSTPCRE5
|
||||
|
||||
#define MSTP_CORESIGHT SYSTEM.MSTPCRF.BIT.MSTPCRF0
|
||||
|
||||
#define __MSTP( x ) MSTP ## x
|
||||
#define _MSTP( x ) __MSTP( x )
|
||||
#define MSTP( x ) _MSTP( _ ## x )
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#endif // End _R_SYSTEM_HEADER_
|
||||
|
||||
/* End of File */
|
||||
+39
-64
@@ -19,86 +19,61 @@
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
****************************************************************************************************************************************************************/
|
||||
/****************************************************************************************************************************************************************
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
|
||||
****************************************************************************************************************************************************************/
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* File Name : gnu_io.c
|
||||
* Device(s) : RZ/A1H RSK+T1
|
||||
* File Name : r_typedefs.h
|
||||
* Device(s) : RZ/A1H (R7S910018)
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* H/W Platform : RSK+T1 CPU Board
|
||||
* Description : Sample Program - GCC support for serial I/O
|
||||
* : Variants of this file can be created for each compiler
|
||||
* Description : basic type definition
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00
|
||||
* : 21.10.2014 1.00
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
/* Standard IO header */
|
||||
#include <stdio.h>
|
||||
/* Default type definition header */
|
||||
#include "r_typedefs.h"
|
||||
/* Character I/O header */
|
||||
#include "siochar.h"
|
||||
/* I/O Register root header */
|
||||
#include "iodefine.h"
|
||||
/* Compiler specific UART i/O support header */
|
||||
#include "gnu_io.h"
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: put_string
|
||||
* Description : GNU interface to low-level I/O putchar replacement
|
||||
* Arguments : char * pString
|
||||
* Return Value : none
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
void put_string (char *pString)
|
||||
{
|
||||
while(0 != (*pString))
|
||||
{
|
||||
io_put_char(*pString++);
|
||||
}
|
||||
}
|
||||
#include <stdint.h>
|
||||
/* Multiple inclusion prevention macro */
|
||||
#ifndef R_TYPEDEFS_H
|
||||
#define R_TYPEDEFS_H
|
||||
|
||||
|
||||
/* in case <stdio.h> has defined it. */
|
||||
#ifndef NULL
|
||||
#define NULL (0)
|
||||
#endif
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function put_string
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#if !defined(__bool_true_false_are_defined) && !defined(__cplusplus)
|
||||
|
||||
#define FALSE (0)
|
||||
#define TRUE (1)
|
||||
|
||||
#endif
|
||||
|
||||
/* These two macros are used to suppress warnings generated by unused variables.
|
||||
Writing to some registers require a read instruction following the write.
|
||||
A dummy variable is declared and used to read the register written to. */
|
||||
#define UNUSED_PARAM(param) ((void)(param))
|
||||
#define UNUSED_VARIABLE(param) ((void)(param))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: get_string
|
||||
* Description : GNU interface to low-level I/O getchar replacement
|
||||
* Arguments : char * pString
|
||||
* Return Value : none
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
void get_string (char * pString)
|
||||
{
|
||||
char * ptr = pString;
|
||||
typedef char char_t;
|
||||
typedef unsigned int bool_t;
|
||||
typedef int int_t;
|
||||
typedef float float32_t;
|
||||
typedef double float64_t;
|
||||
typedef long double float128_t;
|
||||
|
||||
do
|
||||
{
|
||||
(*ptr) = io_get_char();
|
||||
|
||||
io_put_char(*ptr);
|
||||
|
||||
if('\r' == (*ptr))
|
||||
{
|
||||
(*ptr) = 0;
|
||||
|
||||
/* This is intentional since no more input is expected */
|
||||
break;
|
||||
}
|
||||
}
|
||||
while('\0' != (*ptr++));
|
||||
io_put_char('\r');
|
||||
io_put_char('\n');
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function get_string
|
||||
***********************************************************************************************************************/
|
||||
/* R_TYPEDEFS_H */
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,163 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x40020040;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x4008FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x00070000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x0007FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_svcstack__ = 0x200;
|
||||
define symbol __ICFEDIT_size_irqstack__ = 0x100;
|
||||
define symbol __ICFEDIT_size_fiqstack__ = 0x100;
|
||||
define symbol __ICFEDIT_size_undstack__ = 0x100;
|
||||
define symbol __ICFEDIT_size_abtstack__ = 0x100;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define symbol __region_USER_PRG_start__ = 0x00000040;
|
||||
define symbol __region_USER_PRG_end__ = 0x0006FFFF;
|
||||
|
||||
define symbol __region_D_LDR_DATA_start__ = 0x00800000;
|
||||
define symbol __region_D_LDR_DATA_end__ = 0x00801FFF;
|
||||
define symbol __region_D_LDR_PRG_start__ = 0x00802000;
|
||||
define symbol __region_D_LDR_PRG_end__ = 0x00807FFF;
|
||||
|
||||
define symbol __region_D_LDR_M3PRG_start__ = 0x04000000;
|
||||
define symbol __region_D_LDR_M3PRG_end__ = 0x0407FFFF;
|
||||
|
||||
define symbol __region_S_LDR_M3PRG_start__ = 0x00050000;
|
||||
define symbol __region_S_LDR_M3PRG_end__ = 0x0006FFFF;
|
||||
|
||||
define symbol __region_EXT_RAM1_start__ = 0x22000000;
|
||||
define symbol __region_EXT_RAM1_end__ = 0x2207FFFF;
|
||||
define symbol __region_EXT_RAM2_start__ = 0x24000000;
|
||||
define symbol __region_EXT_RAM2_end__ = 0x2407FFFF;
|
||||
define symbol __region_SPIBSC_start__ = 0x30000000;
|
||||
define symbol __region_SPIBSC_end__ = 0x33FFFFFF;
|
||||
|
||||
define symbol __region_CS0_start__ = 0x40000000;
|
||||
define symbol __region_CS0_end__ = 0x43FFFFFF;
|
||||
define symbol __region_CS1_start__ = 0x44000000;
|
||||
define symbol __region_CS1_end__ = 0x47FFFFFF;
|
||||
define symbol __region_CS2_start__ = 0x48000000;
|
||||
define symbol __region_CS2_end__ = 0x4BFFFFFF;
|
||||
define symbol __region_CS3_start__ = 0x4C000000;
|
||||
define symbol __region_CS3_end__ = 0x4FFFFFFF;
|
||||
define symbol __region_CS4_start__ = 0x50000000;
|
||||
define symbol __region_CS4_end__ = 0x53FFFFFF;
|
||||
define symbol __region_CS5_start__ = 0x54000000;
|
||||
define symbol __region_CS5_end__ = 0x57FFFFFF;
|
||||
|
||||
define region USER_PRG_region = mem:[from __region_USER_PRG_start__ to __region_USER_PRG_end__];
|
||||
define region D_LDR_DATA_region = mem:[from __region_D_LDR_DATA_start__ to __region_D_LDR_DATA_end__];
|
||||
define region D_LDR_PRG_region = mem:[from __region_D_LDR_PRG_start__ to __region_D_LDR_PRG_end__];
|
||||
|
||||
define region D_LDR_M3PRG_region = mem:[from __region_D_LDR_M3PRG_start__ to __region_D_LDR_M3PRG_end__];
|
||||
define region S_LDR_M3PRG_region = mem:[from __region_S_LDR_M3PRG_start__ to __region_S_LDR_M3PRG_end__];
|
||||
|
||||
define region EXT_RAM1_region = mem:[from __region_EXT_RAM1_start__ to __region_EXT_RAM1_end__];
|
||||
define region EXT_RAM2_region = mem:[from __region_EXT_RAM2_start__ to __region_EXT_RAM2_end__];
|
||||
define region SPIBSC_region = mem:[from __region_SPIBSC_start__ to __region_SPIBSC_end__];
|
||||
define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__];
|
||||
define region CS1_region = mem:[from __region_CS1_start__ to __region_CS1_end__];
|
||||
define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__];
|
||||
define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__];
|
||||
define region CS4_region = mem:[from __region_CS4_start__ to __region_CS4_end__];
|
||||
define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
|
||||
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
|
||||
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
|
||||
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
|
||||
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
|
||||
define block LDR_PRG_RBLOCK with fixed order
|
||||
{ ro code object loader_init.o,
|
||||
ro code object loader_init2.o,
|
||||
ro code object r_atcm_init.o,
|
||||
ro code object r_cpg.o,
|
||||
ro code object r_ram_init.o,
|
||||
ro code object r_mpc.o,
|
||||
ro code object r_reset.o,
|
||||
ro code object data_init.o,
|
||||
ro code object copy_init3.o };
|
||||
define block LDR_DATA_ZBLOCK { section .bss object loader_init.o,
|
||||
section .bss object loader_init2.o,
|
||||
section .bss object r_atcm_init.o,
|
||||
section .bss object r_cpg.o,
|
||||
section .bss object r_ram_init.o,
|
||||
section .bss object r_mpc.o,
|
||||
section .bss object r_reset.o,
|
||||
section .bss object data_init.o,
|
||||
section .bss object copy_init3.o };
|
||||
define block LDR_DATA_RBLOCK { section .data_init object loader_init.o,
|
||||
section .data_init object loader_init2.o,
|
||||
section .data_init object r_atcm_init.o,
|
||||
section .data_init object r_cpg.o,
|
||||
section .data_init object r_ram_init.o,
|
||||
section .data_init object r_mpc.o,
|
||||
section .data_init object r_reset.o,
|
||||
section .data_init object data_init.o,
|
||||
section .data_init object copy_init3.o };
|
||||
define block LDR_DATA_WBLOCK { section .data object loader_init.o,
|
||||
section .data object loader_init2.o,
|
||||
section .data object r_atcm_init.o,
|
||||
section .data object r_cpg.o,
|
||||
section .data object r_ram_init.o,
|
||||
section .data object r_mpc.o,
|
||||
section .data object r_reset.o,
|
||||
section .data object data_init.o,
|
||||
section .data object copy_init3.o };
|
||||
define block VECTOR_RBLOCK { ro code object vector.o };
|
||||
define block USER_PRG_RBLOCK { ro code };
|
||||
define block USER_DATA_ZBLOCK { section .bss };
|
||||
define block USER_DATA_RBLOCK { section .data_init };
|
||||
define block USER_DATA_WBLOCK { section .data };
|
||||
|
||||
define block M3_PRG_RBLOCK { section __M3prg_init };
|
||||
define block M3_PRG_WBLOCK { section __M3prg };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
|
||||
do not initialize { section .noinit, section .bss };
|
||||
|
||||
initialize manually { section __M3prg };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { block VECTOR_RBLOCK };
|
||||
|
||||
place in USER_PRG_region { block USER_PRG_RBLOCK,
|
||||
block USER_DATA_RBLOCK,
|
||||
readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in RAM_region { block USER_DATA_WBLOCK,
|
||||
block USER_DATA_ZBLOCK,
|
||||
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
|
||||
block UND_STACK, block ABT_STACK, block HEAP };
|
||||
place in D_LDR_DATA_region { block LDR_DATA_WBLOCK, block LDR_DATA_ZBLOCK };
|
||||
place in D_LDR_PRG_region { block LDR_PRG_RBLOCK,
|
||||
block LDR_DATA_RBLOCK };
|
||||
|
||||
place in S_LDR_M3PRG_region { block M3_PRG_RBLOCK };
|
||||
place in D_LDR_M3PRG_region { block M3_PRG_WBLOCK };
|
||||
|
||||
place in EXT_RAM1_region {};
|
||||
place in EXT_RAM2_region {};
|
||||
place in SPIBSC_region {};
|
||||
place in CS0_region {};
|
||||
place in CS1_region {};
|
||||
place in CS2_region {};
|
||||
place in CS3_region {};
|
||||
place in CS4_region {};
|
||||
place in CS5_region {};
|
||||
@@ -0,0 +1,84 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : exit.c
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : exit program
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : exit sequence from main function
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Private variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Outline : exit processing
|
||||
* Function Name: __exit
|
||||
* Description : exit sequence from main function.
|
||||
* Arguments : code
|
||||
* The return value of main function.
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void __exit(int code)
|
||||
{
|
||||
|
||||
while (1)
|
||||
{
|
||||
/* Please describe the exit sequence */
|
||||
}
|
||||
|
||||
}
|
||||
/*******************************************************************************
|
||||
End of function __exit
|
||||
*******************************************************************************/
|
||||
@@ -0,0 +1,371 @@
|
||||
;*******************************************************************************
|
||||
; DISCLAIMER
|
||||
; This software is supplied by Renesas Electronics Corporation and is only
|
||||
; intended for use with Renesas products. No other uses are authorized. This
|
||||
; software is owned by Renesas Electronics Corporation and is protected under
|
||||
; all applicable laws, including copyright laws.
|
||||
; THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
; THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
; LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
; AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
; TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
; ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
; FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
; ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
; BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
; Renesas reserves the right, without notice, to make changes to this software
|
||||
; and to discontinue the availability of this software. By using this software,
|
||||
; you agree to the additional terms and conditions found by accessing the
|
||||
; following link:
|
||||
; http://www.renesas.com/disclaimer
|
||||
;
|
||||
; Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
; System Name : RZ/T1 Init program
|
||||
; File Name : loader_init.asm
|
||||
; Version : 0.1
|
||||
; Device : R7S9100xx
|
||||
; Abstract : Loader program 1
|
||||
; Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
; OS : not use
|
||||
; H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
; Description : Description interrupt service routine of RZ/T1
|
||||
; Limitation : none
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
; History : DD.MM.YYYY Version Description
|
||||
; : First Release
|
||||
;******************************************************************************
|
||||
|
||||
SECTION IRQ_STACK:DATA:NOROOT(3)
|
||||
SECTION FIQ_STACK:DATA:NOROOT(3)
|
||||
SECTION SVC_STACK:DATA:NOROOT(3)
|
||||
SECTION ABT_STACK:DATA:NOROOT(3)
|
||||
SECTION UND_STACK:DATA:NOROOT(3)
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION LDR_DATA_RBLOCK:DATA:ROOT(2)
|
||||
SECTION LDR_DATA_WBLOCK:DATA:ROOT(2)
|
||||
|
||||
SECTION M3_PRG_RBLOCK:DATA:ROOT(2)
|
||||
SECTION M3_PRG_WBLOCK:DATA:ROOT(2)
|
||||
|
||||
; This program is allocated to section "d_ldr_prg"
|
||||
SECTION d_ldr_prg:CODE:ROOT(2)
|
||||
|
||||
ARM
|
||||
|
||||
PUBLIC loader_init1
|
||||
PUBLIC set_low_vec
|
||||
PUBLIC cache_init
|
||||
PUBLIC mpu_init
|
||||
IMPORT loader_init2
|
||||
|
||||
|
||||
;***********************************************************************
|
||||
; Function Name : loader_init1
|
||||
; Description : Initialize sysytem by loader program
|
||||
; Arguments : none
|
||||
; Return Value : none
|
||||
;***********************************************************************
|
||||
loader_init1:
|
||||
|
||||
stack_init:
|
||||
; Stack setting
|
||||
cps #17 ; FIQ mode
|
||||
ldr sp, =SFE(FIQ_STACK)
|
||||
cps #18 ; IRQ mode
|
||||
ldr sp, =SFE(IRQ_STACK)
|
||||
cps #23 ; Abort mode
|
||||
ldr sp, =SFE(ABT_STACK)
|
||||
cps #27 ; Undef mode
|
||||
ldr sp, =SFE(UND_STACK)
|
||||
cps #31 ; System mode
|
||||
ldr sp, =SFE(CSTACK)
|
||||
cps #19 ; SVC mode
|
||||
ldr sp, =SFE(SVC_STACK)
|
||||
|
||||
vfp_init:
|
||||
; Initialize VFP setting
|
||||
mrc p15, #0, r0, c1, c0, #2 ; Enables cp10 and cp11 accessing
|
||||
orr r0, r0, #0xF00000
|
||||
mcr p15, #0, r0, c1, c0, #2
|
||||
isb ; Ensuring Context-changing
|
||||
|
||||
mov r0, #0x40000000 ; Enables VFP operation
|
||||
vmsr fpexc, r0
|
||||
|
||||
data_init:
|
||||
; Initialize variables has initialized value of loader_init2.
|
||||
; Variables has no initialized value already be initialized to zero
|
||||
; in boot sequence(Clear ATCM and BTCM).
|
||||
ldr r0, =SFB(LDR_DATA_RBLOCK)
|
||||
ldr r1, =SFB(LDR_DATA_WBLOCK)
|
||||
ldr r2, =SIZEOF(LDR_DATA_WBLOCK)
|
||||
cmp r2, #0
|
||||
#ifdef DUAL_CORE
|
||||
beq m3_init
|
||||
#else
|
||||
beq jump_loader_init2
|
||||
#endif
|
||||
|
||||
copy_to_LDR_DATA:
|
||||
ldrb r3, [r0], #1
|
||||
strb r3, [r1], #1
|
||||
subs r2, r2, #1
|
||||
bne copy_to_LDR_DATA
|
||||
dsb ; Ensuring data-changing
|
||||
|
||||
#ifdef DUAL_CORE
|
||||
|
||||
m3_init:
|
||||
; Initialize image for Cortex-M3 core
|
||||
ldr r0, =SFB(M3_PRG_RBLOCK)
|
||||
ldr r1, =SFB(M3_PRG_WBLOCK)
|
||||
ldr r2, =SIZEOF(M3_PRG_WBLOCK)
|
||||
cmp r2, #0
|
||||
beq jump_loader_init2
|
||||
|
||||
copy_to_M3_PRG:
|
||||
ldrb r3, [r0], #1
|
||||
strb r3, [r1], #1
|
||||
subs r2, r2, #1
|
||||
bne copy_to_M3_PRG
|
||||
dsb ; Ensuring data-changing
|
||||
|
||||
#endif
|
||||
|
||||
; Jump to loader_init2
|
||||
jump_loader_init2:
|
||||
ldr r0, =loader_init2
|
||||
bx r0
|
||||
|
||||
;***********************************************************************
|
||||
; Function Name : cache_init
|
||||
; Description : Initialize I1, D1 cache and MPU settings
|
||||
; Arguments : none
|
||||
; Return Value : none
|
||||
;***********************************************************************
|
||||
|
||||
;*******************************************************************************
|
||||
; Macro definitions
|
||||
;*******************************************************************************
|
||||
|
||||
SCTLR_BR: dcd 0x00020000
|
||||
SCTLR_M: dcd 0x00000001
|
||||
SCTLR_I_C: dcd 0x00001004
|
||||
|
||||
DRBAR_REGION_0: dcd 0x04000000 ; Base address = 0400_0000h
|
||||
DRACR_REGION_0: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share
|
||||
DRSR_REGION_0: dcd 0x00000025 ; Size 512KB, MPU enable
|
||||
|
||||
DRBAR_REGION_1: dcd 0x10000000 ; Base address = 1000_0000h
|
||||
DRACR_REGION_1: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share
|
||||
DRSR_REGION_1: dcd 0x00000033 ; Size 64MB, MPU enable
|
||||
|
||||
DRBAR_REGION_2: dcd 0x20000000 ; Base address = 2000_0000h
|
||||
DRACR_REGION_2: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share
|
||||
DRSR_REGION_2: dcd 0x00000025 ; Size 512KB, MPU enable
|
||||
|
||||
DRBAR_REGION_3: dcd 0x22000000 ; Base address = 2200_0000h
|
||||
DRACR_REGION_3: dcd 0x00000307 ; R/W(full), Normal, Write-back no allocate, share
|
||||
DRSR_REGION_3: dcd 0x00000033 ; Size 64MB, MPU enable
|
||||
|
||||
DRBAR_REGION_4: dcd 0x30000000 ; Base address = 3000_0000h
|
||||
DRACR_REGION_4: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share
|
||||
DRSR_REGION_4: dcd 0x00000033 ; Size 64MB, MPU enable
|
||||
|
||||
DRBAR_REGION_5: dcd 0x40000000 ; Base address = 4000_0000h
|
||||
DRACR_REGION_5: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share
|
||||
DRSR_REGION_5: dcd 0x00000035 ; Size 128MB, MPU enable
|
||||
|
||||
DRBAR_REGION_6: dcd 0x48000000 ; Base address = 4800_0000h
|
||||
DRACR_REGION_6: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share
|
||||
DRSR_REGION_6: dcd 0x00000035 ; Size 128MB, MPU enable
|
||||
|
||||
DRBAR_REGION_7: dcd 0x50000000 ; Base address = 5000_0000h
|
||||
DRACR_REGION_7: dcd 0x00001305 ; R/W(full), XN, Device, share
|
||||
DRSR_REGION_7: dcd 0x00000035 ; Size 128MB, MPU enable
|
||||
|
||||
DRBAR_REGION_8: dcd 0x60000000 ; Base address = 6000_0000h
|
||||
DRACR_REGION_8: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share
|
||||
DRSR_REGION_8: dcd 0x00000035 ; Size 128MB, MPU enable
|
||||
|
||||
DRBAR_REGION_9: dcd 0x68000000 ; Base address = 6800_0000h
|
||||
DRACR_REGION_9: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share
|
||||
DRSR_REGION_9: dcd 0x00000035 ; Size 128MB, MPU enable
|
||||
|
||||
DRBAR_REGION_10: dcd 0x70000000 ; Base address = 7000_0000h
|
||||
DRACR_REGION_10: dcd 0x00001305 ; R/W(full), XN, Device, share
|
||||
DRSR_REGION_10: dcd 0x00000035 ; Size 128MB, MPU enable
|
||||
|
||||
DRBAR_REGION_11: dcd 0x80000000 ; Base address = 8000_0000h
|
||||
DRACR_REGION_11: dcd 0x00001305 ; R/W(full), XN, Device, share
|
||||
DRSR_REGION_11: dcd 0x0000003D ; Size 2GB, MPU enable
|
||||
|
||||
cache_init:
|
||||
push {lr}
|
||||
|
||||
cache_invalidate:
|
||||
; Invalidate the I1, D1 cache
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c7, c5, #0 ; Invalidate all Instruction Caches (Write-value is Ignored)
|
||||
isb ; Ensuring Context-changing
|
||||
mcr p15, #0, r0, c15, c5, #0 ; Invalidate all Data Caches (Write-value is Ignored)
|
||||
isb ; Ensuring Context-changing
|
||||
|
||||
; Adopt default memory map as background map.
|
||||
ldr r0, SCTLR_BR ; Set SCTLR.BR bit to 1
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
orr r1, r1, r0
|
||||
dsb
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
isb ; Ensuring Context-changing
|
||||
|
||||
; Initialize MPU settings (region 0 to 11)
|
||||
; Define region 0
|
||||
mov r0, #0
|
||||
ldr r1, DRBAR_REGION_0
|
||||
ldr r2, DRACR_REGION_0
|
||||
ldr r3, DRSR_REGION_0
|
||||
bl mpu_init
|
||||
|
||||
; Define region 1
|
||||
mov r0, #1
|
||||
ldr r1, DRBAR_REGION_1
|
||||
ldr r2, DRACR_REGION_1
|
||||
ldr r3, DRSR_REGION_1
|
||||
bl mpu_init
|
||||
|
||||
; Define region 2
|
||||
mov r0, #2
|
||||
ldr r1, DRBAR_REGION_2
|
||||
ldr r2, DRACR_REGION_2
|
||||
ldr r3, DRSR_REGION_2
|
||||
bl mpu_init
|
||||
|
||||
; Define region 3
|
||||
mov r0, #3
|
||||
ldr r1, DRBAR_REGION_3
|
||||
ldr r2, DRACR_REGION_3
|
||||
ldr r3, DRSR_REGION_3
|
||||
bl mpu_init
|
||||
|
||||
; Define region 4
|
||||
mov r0, #4
|
||||
ldr r1, DRBAR_REGION_4
|
||||
ldr r2, DRACR_REGION_4
|
||||
ldr r3, DRSR_REGION_4
|
||||
bl mpu_init
|
||||
|
||||
; Define region 5
|
||||
mov r0, #5
|
||||
ldr r1, DRBAR_REGION_5
|
||||
ldr r2, DRACR_REGION_5
|
||||
ldr r3, DRSR_REGION_5
|
||||
bl mpu_init
|
||||
|
||||
; Define region 6
|
||||
mov r0, #6
|
||||
ldr r1, DRBAR_REGION_6
|
||||
ldr r2, DRACR_REGION_6
|
||||
ldr r3, DRSR_REGION_6
|
||||
bl mpu_init
|
||||
|
||||
; Define region 7
|
||||
mov r0, #7
|
||||
ldr r1, DRBAR_REGION_7
|
||||
ldr r2, DRACR_REGION_7
|
||||
ldr r3, DRSR_REGION_7
|
||||
bl mpu_init
|
||||
|
||||
; Define region 8
|
||||
mov r0, #8
|
||||
ldr r1, DRBAR_REGION_8
|
||||
ldr r2, DRACR_REGION_8
|
||||
ldr r3, DRSR_REGION_8
|
||||
bl mpu_init
|
||||
|
||||
; Define region 9
|
||||
mov r0, #9
|
||||
ldr r1, DRBAR_REGION_9
|
||||
ldr r2, DRACR_REGION_9
|
||||
ldr r3, DRSR_REGION_9
|
||||
bl mpu_init
|
||||
|
||||
; Define region 10
|
||||
mov r0, #10
|
||||
ldr r1, DRBAR_REGION_10
|
||||
ldr r2, DRACR_REGION_10
|
||||
ldr r3, DRSR_REGION_10
|
||||
bl mpu_init
|
||||
|
||||
; Define region 11
|
||||
mov r0, #11
|
||||
ldr r1, DRBAR_REGION_11
|
||||
ldr r2, DRACR_REGION_11
|
||||
ldr r3, DRSR_REGION_11
|
||||
bl mpu_init
|
||||
|
||||
; Enables MPU operation
|
||||
ldr r0, SCTLR_M ; Set SCTLR.M bit to 1
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
orr r1, r1, r0
|
||||
dsb
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
isb ; Ensuring Context-changing
|
||||
|
||||
; Enables I1,D1 cache operation
|
||||
ldr r0, SCTLR_I_C ; Set SCTLR.I and C bit to 1
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
orr r1, r1, r0
|
||||
dsb
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
isb ; Ensuring Context-changing
|
||||
|
||||
pop {pc}
|
||||
bx lr
|
||||
|
||||
;***********************************************************************
|
||||
; Function Name : mpu_init
|
||||
; Description : Initialize MPU settings
|
||||
; Arguments : none
|
||||
; Return Value : none
|
||||
;***********************************************************************
|
||||
mpu_init:
|
||||
; RGNR(MPU Memory Region Number Register)
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
isb ; Ensuring Context-changing
|
||||
|
||||
; DRBAR(Data Region Base Address Register)
|
||||
mcr p15, #0, r1, c6, c1, #0
|
||||
isb ; Ensuring Context-changing
|
||||
|
||||
; DRACR(Data Region Access Control Register)
|
||||
mcr p15, #0, r2, c6, c1, #4
|
||||
isb ; Ensuring Context-changing
|
||||
|
||||
; DRSR(Data Region Size and Enable Register)
|
||||
mcr p15, #0, r3, c6, c1, #2
|
||||
isb ; Ensuring Context-changing
|
||||
|
||||
bx lr
|
||||
|
||||
|
||||
;***********************************************************************
|
||||
; Function Name : set_low_vec
|
||||
; Description : Initialize sysytem by loader program
|
||||
; Arguments : none
|
||||
; Return Value : none
|
||||
;***********************************************************************
|
||||
set_low_vec:
|
||||
mrc p15, 0, r0, c1, c0, 0 ; Set SCTLR.V bit to 1 (low-vector)
|
||||
and r0, r0, #0xFFFFDFFF
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
isb ; Ensuring Context-changing
|
||||
|
||||
bx lr
|
||||
|
||||
END
|
||||
; End of File
|
||||
@@ -0,0 +1,233 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : loader_init2.c
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : Loader program 2
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Initialize the peripheral settings of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
#ifdef __ICCARM__
|
||||
|
||||
#pragma section="VECTOR_RBLOCK"
|
||||
#pragma section="VECTOR_WBLOCK"
|
||||
#pragma section="USER_PRG_RBLOCK"
|
||||
#pragma section="USER_PRG_WBLOCK"
|
||||
#pragma section="USER_DATA_RBLOCK"
|
||||
#pragma section="USER_DATA_WBLOCK"
|
||||
|
||||
#endif // __ICCARM__
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include <Renesas/ior7s910017.h>
|
||||
#include "r_system.h"
|
||||
#include "r_reset.h"
|
||||
#include "r_cpg.h"
|
||||
#include "r_atcm_init.h"
|
||||
#include "r_port.h"
|
||||
#include "r_mpc.h"
|
||||
#include "r_ecm.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
extern int _main(void);
|
||||
extern void bus_init(void);
|
||||
extern void set_low_vec(void);
|
||||
extern void cache_init(void);
|
||||
extern void __iar_data_init3(void);
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Private variables and functions
|
||||
*******************************************************************************/
|
||||
void loader_init2(void);
|
||||
void reset_check(void);
|
||||
void cpg_init(void);
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : loader_init2
|
||||
* Description : Initialize sysytem by loader program 2
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void loader_init2(void)
|
||||
{
|
||||
/* Check the reset source */
|
||||
reset_check();
|
||||
|
||||
/* Set CPU clock and LOCO clock */
|
||||
cpg_init();
|
||||
|
||||
/* Set ATCM access wait to 1-wait with optimization */
|
||||
/* Caution: ATCM_WAIT_0 is permitted if CPUCLK = 150MHz or 300MHz.
|
||||
ATCM_WAIT_1_OPT is permitted if CPUCLK = 450MHz or 600MHz.*/
|
||||
R_ATCM_WaitSet(ATCM_WAIT_1_OPT);
|
||||
|
||||
/* Copy the variable data */
|
||||
__iar_data_init3();
|
||||
|
||||
/* Initialize I1, D1 Cache and MPU setting */
|
||||
cache_init();
|
||||
|
||||
/* Set RZ/T1 to Low-vector (SCTLR.V = 0) */
|
||||
set_low_vec();
|
||||
|
||||
/* Jump to _main() */
|
||||
_main();
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function loader_init2
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : reset_check
|
||||
* Description : Check the reset source and execute the each sequence.
|
||||
* When error source number 35 is generated, set P77 pin to High.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void reset_check(void)
|
||||
{
|
||||
volatile uint8_t result;
|
||||
volatile uint32_t dummy;
|
||||
|
||||
/* Check the reset status flag and execute the each sequence */
|
||||
if (RST_SOURCE_ECM == SYSTEM.RSTSR0.LONG) // ECM reset is generated
|
||||
{
|
||||
/* Clear reset status flag */
|
||||
r_rst_write_enable(); // Enable writing to the RSTSR0 register
|
||||
SYSTEM.RSTSR0.LONG = 0x00000000; // Clear reset factor flag
|
||||
r_rst_write_disable(); // Disable writing to the RSTSR0 register
|
||||
|
||||
/* Please coding the User program */
|
||||
|
||||
}
|
||||
else if (RST_SOURCE_SWR1 == SYSTEM.RSTSR0.LONG) // Software reset 1 is generated
|
||||
{
|
||||
/* Clear reset status flag */
|
||||
r_rst_write_enable(); // Enable writing to the RSTSR0 register
|
||||
SYSTEM.RSTSR0.LONG = 0x00000000; // Clear reset factor flag
|
||||
r_rst_write_disable(); // Disable writing to the RSTSR0 register
|
||||
|
||||
/* Please coding the User program */
|
||||
|
||||
}
|
||||
else if (RST_SOURCE_RES == SYSTEM.RSTSR0.LONG) // RES# pin reset is generated
|
||||
{
|
||||
/* Clear reset status flag */
|
||||
r_rst_write_enable(); // Enable writing to the RSTSR0 register
|
||||
SYSTEM.RSTSR0.LONG = 0x00000000; // Clear reset factor flag
|
||||
r_rst_write_disable(); // Disable writing to the RSTSR0 register
|
||||
|
||||
/* Please coding the User program */
|
||||
|
||||
}
|
||||
else // Any reset is not generated
|
||||
{
|
||||
/* Please coding the User program */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function reset_check
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : cpg_init
|
||||
* Description : Set CPU clock and LOCO clock by CPG function
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void cpg_init(void)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
|
||||
/* Enables writing to the registers related to CPG function */
|
||||
R_CPG_WriteEnable();
|
||||
|
||||
/* Enables LOCO clock operation */
|
||||
SYSTEM.LOCOCR.BIT.LCSTP = CPG_LOCO_ENABLE;
|
||||
|
||||
/* Set CPUCLK to 450MHz, and dummy read at three times */
|
||||
SYSTEM.PLL1CR.LONG = CPG_CPUCLK_450_MHz;
|
||||
dummy = SYSTEM.PLL1CR.LONG;
|
||||
dummy = SYSTEM.PLL1CR.LONG;
|
||||
dummy = SYSTEM.PLL1CR.LONG;
|
||||
|
||||
/* Enables PLL1 operation */
|
||||
SYSTEM.PLL1CR2.LONG = CPG_PLL1_ON;
|
||||
|
||||
/* Disables writing to the registers related to CPG function */
|
||||
R_CPG_WriteDisable();
|
||||
|
||||
/* Wait about 100us for PLL1 (and LOCO) stabilization */
|
||||
R_CPG_PLL_Wait();
|
||||
|
||||
/* Enables writing to the registers related to CPG function */
|
||||
R_CPG_WriteEnable();
|
||||
|
||||
/* Selects the PLL1 as clock source */
|
||||
SYSTEM.SCKCR2.LONG = CPG_SELECT_PLL1;
|
||||
|
||||
/* Disables writing to the registers related to CPG function */
|
||||
R_CPG_WriteDisable();
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function cpg_init
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* End of File */
|
||||
|
||||
|
||||
@@ -0,0 +1,108 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_atcm_init.c
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for ATCM function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : ATCM access wait setting API of RZ/T1
|
||||
* Limitation : This wait setting could not be executed in ATCM program area.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include <Renesas/ior7s910017.h>
|
||||
#include "r_system.h"
|
||||
#include "r_atcm_init.h"
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define ATCM_WRITE_ENABLE (0x0000A508)
|
||||
#define ATCM_WRITE_DISABLE (0x0000A500)
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : R_ATCM_WaitSet
|
||||
* Description : Sets ATCM access wait.
|
||||
* Arguments : atcm_wait
|
||||
* Wait settings for ATCM access
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void R_ATCM_WaitSet(uint32_t atcm_wait)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
|
||||
/* Enables writing to the ATCM register */
|
||||
SYSTEM.PRCR.LONG = ATCM_WRITE_ENABLE;
|
||||
dummy = SYSTEM.PRCR.LONG;
|
||||
|
||||
/* Sets ATCM access wait to atcm_wait value */
|
||||
SYSTEM.SYTATCMWAIT.LONG = atcm_wait;
|
||||
|
||||
/* Disables writing to the ATCM register */
|
||||
SYSTEM.PRCR.LONG = ATCM_WRITE_DISABLE;
|
||||
dummy = SYSTEM.PRCR.LONG;
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function R_ATCM_WaitSet
|
||||
*******************************************************************************/
|
||||
|
||||
/* End of File */
|
||||
|
||||
|
||||
@@ -0,0 +1,162 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_cpg.c
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for CPG function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : CPG setting API of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include <Renesas/ior7s910017.h>
|
||||
#include "r_system.h"
|
||||
#include "r_cpg.h"
|
||||
#include "r_reset.h"
|
||||
#include "r_icu_init.h"
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define CPG_WRITE_ENABLE (0x0000A501)
|
||||
#define CPG_WRITE_DISABLE (0x0000A500)
|
||||
|
||||
#define CPG_CMT0_CLOCK_PCLKD_32 (1)
|
||||
#define CPG_CMT0_CMI0_ENABLE (1)
|
||||
#define CPG_CMT0_CONST_100_us (0xEA)
|
||||
#define CPG_CMT0_START (1)
|
||||
#define CPG_CMT0_STOP (0)
|
||||
|
||||
#define CPG_CMT_REG_CLEAR (0x0000)
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : R_CPG_PLL_Wait
|
||||
* Description : Wait about 100us for PLL stabilization by using CMT0
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void R_CPG_PLL_Wait(void)
|
||||
{
|
||||
|
||||
/* Enables writing to the registers related to Reset and Low-Power function */
|
||||
r_rst_write_enable();
|
||||
|
||||
/* Release from the CMT0 module-stop state */
|
||||
MSTP(CMT0) = 0;
|
||||
|
||||
/* Disables writing to the registers related to Reset and Low-Power function */
|
||||
r_rst_write_disable();
|
||||
|
||||
/* Set CMT0 to 100us interval operation */
|
||||
CMT0.CMCR.BIT.CKS = CPG_CMT0_CLOCK_PCLKD_32; // Count clock = PCLKD/32
|
||||
CMT0.CMCR.BIT.CMIE = CPG_CMT0_CMI0_ENABLE; // Enable CMI0 interrupt
|
||||
CMT0.CMCNT = CPG_CMT_REG_CLEAR; // Clear CMCNT counter
|
||||
CMT0.CMCOR = CPG_CMT0_CONST_100_us; // Set constant value for 100us
|
||||
|
||||
|
||||
/* Set IRQ21(CMI0) for polloing sequence */
|
||||
VIC.IEC0.BIT.IEC21 = ICU_IEC_MASK_SET; // Mask IRQ21 interrupt
|
||||
VIC.PLS0.BIT.PLS21 = ICU_TYPE_EDGE; // Set EDGE type interrupt
|
||||
VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge
|
||||
|
||||
/* Enable IRQ interrupt (Clear CPSR.I bit to 0) */
|
||||
asm("cpsie i"); // Clear CPSR.I bit to 0
|
||||
asm("isb"); // Ensuring Context-changing
|
||||
|
||||
/* Start CMT0 count */
|
||||
CMT.CMSTR0.BIT.STR0 = CPG_CMT0_START;
|
||||
|
||||
/* Wait for 100us (IRQ21 is generated) */
|
||||
while ( !(VIC.RAIS0.BIT.RAI21) )
|
||||
{
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
/* Stop CMT0 count */
|
||||
CMT.CMSTR0.BIT.STR0 = CPG_CMT0_STOP;
|
||||
|
||||
/* Initialize CMT0 settings and clear interrupt detection edge */
|
||||
CMT0.CMCR.WORD = CPG_CMT_REG_CLEAR;
|
||||
CMT0.CMCNT = CPG_CMT_REG_CLEAR;
|
||||
CMT0.CMCOR = CPG_CMT_REG_CLEAR;
|
||||
CMT.CMSTR0.WORD = CPG_CMT_REG_CLEAR;
|
||||
|
||||
VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge
|
||||
|
||||
|
||||
/* Disable IRQ interrupt (Set CPSR.I bit to 1) */
|
||||
asm("cpsid i");
|
||||
asm("isb");
|
||||
|
||||
/* Enables writing to the registers related to Reset and Low-Power function */
|
||||
r_rst_write_enable();
|
||||
|
||||
/* Set CMT0 to module-stop state */
|
||||
MSTP(CMT0) = 1;
|
||||
|
||||
/* Disables writing to the registers related to Reset and Low-Power function */
|
||||
r_rst_write_disable();
|
||||
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function R_CPG_PLL_Wait
|
||||
*******************************************************************************/
|
||||
|
||||
/* End of File */
|
||||
|
||||
|
||||
@@ -0,0 +1,289 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_ecm.c
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for ECM function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : ECM API of RZ/T1
|
||||
* Limitation : LOCO operation is necessary for clearing ERROROUT# pin.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include <Renesas/ior7s910017.h>
|
||||
#include "r_system.h"
|
||||
#include "r_ecm.h"
|
||||
#include "r_reset.h"
|
||||
#include "r_icu_init.h"
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define ECM_CMT0_CLOCK_PCLKD_32 (1)
|
||||
#define ECM_CMT0_CMI0_ENABLE (1)
|
||||
#define ECM_CMT0_CONST_15_us (0x22)
|
||||
#define ECM_CMT0_START (1)
|
||||
#define ECM_CMT0_STOP (0)
|
||||
|
||||
#define ECM_CMT_REG_CLEAR (0x0000)
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private variables and functions
|
||||
*******************************************************************************/
|
||||
static uint32_t *g_pcmd_reg_adrr[ECM_TYPE_MAX] =
|
||||
{
|
||||
(uint32_t *) &ECMM.ECMMPCMD0.LONG,
|
||||
(uint32_t *) &ECMC.ECMCPCMD0.LONG,
|
||||
(uint32_t *) &ECM.ECMPCMD1.LONG
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : R_ECM_Init
|
||||
* Description : Initialize ECM function.
|
||||
* - Clear all error source
|
||||
* - Clear ERROROUT# pin output to in-active (High) level.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void R_ECM_Init(void)
|
||||
{
|
||||
volatile uint8_t result;
|
||||
|
||||
/* Clear all error source (ECMESSTC0, ECMESSTC1, ECMESSTC2) */
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC0.LONG), 0xDFFFFFF7);
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC1.LONG), 0x000001FF);
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC2.LONG), 0x70000000);
|
||||
|
||||
/* Mask all error source (ECMEMK0, ECMEMK1, ECMEMK2) for clearing ERROROUT# */
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK0.LONG), 0xDFFFFFF7);
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK1.LONG), 0x000001FF);
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK2.LONG), 0x30000000);
|
||||
|
||||
/* Mask ECM maskable, non-maskable interrupt and ECM reset of ECM compare match
|
||||
error (ECMMICFG2, ECMNMICFG2, ECMIRCFG2) */
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMMICFG2.LONG), 0x00000000);
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMNMICFG2.LONG), 0x00000000);
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMIRCFG2.LONG), 0x00000000);
|
||||
|
||||
/* Clear ERROROUT# pin output to in-active (High) level */
|
||||
result = R_ECM_Write_Reg8(ECM_MASTER, &(ECMM.ECMMECLR.BYTE), 0x01);
|
||||
result = R_ECM_Write_Reg8(ECM_CHECKER, &(ECMC.ECMCECLR.BYTE), 0x01);
|
||||
|
||||
/* Wait 15us for ECM compare error stabilization */
|
||||
R_ECM_CompareError_Wait();
|
||||
|
||||
/* Clear ECM compare error (ECMESSTC2) again */
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC2.LONG), 0x10000000);
|
||||
|
||||
/* Initialize the all error mask settings (ECMEMK0, ECMEMK1, ECMEMK2) */
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK0.LONG), 0x00000000);
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK1.LONG), 0x00000000);
|
||||
result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK2.LONG), 0x00000000);
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function R_ECM_Init
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : R_ECM_CompareError_Wait
|
||||
* Description : Wait about 15 us for ECM compare error stabilizeation by using CMT0
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void R_ECM_CompareError_Wait(void)
|
||||
{
|
||||
/* Enables writing to the registers related to Reset and Low-Power function */
|
||||
r_rst_write_enable();
|
||||
|
||||
/* Release from the CMT0 module-stop state */
|
||||
MSTP(CMT0) = 0;
|
||||
|
||||
/* Disables writing to the registers related to Reset and Low-Power function */
|
||||
r_rst_write_disable();
|
||||
|
||||
/* Set CMT0 to 100us interval operation */
|
||||
CMT0.CMCR.BIT.CKS = ECM_CMT0_CLOCK_PCLKD_32; // Count clock = PCLKD/32
|
||||
CMT0.CMCR.BIT.CMIE = ECM_CMT0_CMI0_ENABLE; // Enable CMI0 interrupt
|
||||
CMT0.CMCNT = ECM_CMT_REG_CLEAR; // Clear CMCNT counter
|
||||
CMT0.CMCOR = ECM_CMT0_CONST_15_us; // Set constant value for 15us
|
||||
|
||||
|
||||
/* Set IRQ21(CMI0) for polloing sequence */
|
||||
VIC.IEC0.BIT.IEC21 = ICU_IEC_MASK_SET; // Mask IRQ21 interrupt
|
||||
VIC.PLS0.BIT.PLS21 = ICU_TYPE_EDGE; // Set EDGE type interrupt
|
||||
VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge
|
||||
|
||||
/* Enable IRQ interrupt (Clear CPSR.I bit to 0) */
|
||||
asm("cpsie i"); // Clear CPSR.I bit to 0
|
||||
asm("isb"); // Ensuring Context-changing
|
||||
|
||||
/* Start CMT0 count */
|
||||
CMT.CMSTR0.BIT.STR0 = ECM_CMT0_START;
|
||||
|
||||
/* Wait for 15us (IRQ21 is generated) */
|
||||
while ( ! (VIC.RAIS0.BIT.RAI21) )
|
||||
{
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
/* Stop CMT0 count */
|
||||
CMT.CMSTR0.BIT.STR0 = ECM_CMT0_STOP;
|
||||
|
||||
/* Initialize CMT0 settings and clear interrupt detection edge */
|
||||
CMT0.CMCR.WORD = ECM_CMT_REG_CLEAR;
|
||||
CMT0.CMCNT = ECM_CMT_REG_CLEAR;
|
||||
CMT0.CMCOR = ECM_CMT_REG_CLEAR;
|
||||
CMT.CMSTR0.WORD = ECM_CMT_REG_CLEAR;
|
||||
|
||||
VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge
|
||||
|
||||
|
||||
/* Disable IRQ interrupt (Set CPSR.I bit to 1) */
|
||||
asm("cpsid i");
|
||||
asm("isb");
|
||||
|
||||
/* Enables writing to the registers related to Reset and Low-Power function */
|
||||
r_rst_write_enable();
|
||||
|
||||
/* Set CMT0 to module-stop state */
|
||||
MSTP(CMT0) = 1;
|
||||
|
||||
/* Disables writing to the registers related to Reset and Low-Power function */
|
||||
r_rst_write_disable();
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function R_ECM_CompareError_Wait
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : R_ECM_Write_Reg8
|
||||
* Description : Writing the special sequence for 8-bit ECM protected register
|
||||
* Arguments : reg_type
|
||||
* The type of ECM register (ECM_MASETR, ECM_CHECKER, ECM_COMMON)
|
||||
* *reg
|
||||
* The address of ECM protected register
|
||||
* value
|
||||
* The 8-bit value of writing to protected register
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
uint8_t R_ECM_Write_Reg8( uint8_t reg_type, volatile unsigned char *reg, uint8_t value)
|
||||
{
|
||||
uint8_t result;
|
||||
volatile uint8_t dummy_8;
|
||||
volatile uint32_t dummy_32;
|
||||
|
||||
/* Special write sequence */
|
||||
*g_pcmd_reg_adrr[reg_type] = ECM_COMMAND_KEY; // Write fixed value
|
||||
dummy_32 = *g_pcmd_reg_adrr[reg_type];
|
||||
|
||||
*reg = value; // Write expected value
|
||||
*reg = ~value; // Write inversed value of the expected value
|
||||
*reg = value; // Write expected value
|
||||
dummy_8 = *reg;
|
||||
|
||||
/* Check the ECMPS register whether special sequence is success or failure
|
||||
result = 0 : Special sequence is success.
|
||||
= 1 : Special sequence is failure. */
|
||||
result = ECM.ECMPS.BYTE;
|
||||
|
||||
return result;
|
||||
|
||||
}
|
||||
/*******************************************************************************
|
||||
End of function R_ECM_Write_Reg8
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : R_ECM_Write_Reg32
|
||||
* Description : Writing the special sequence for 32-bit ECM protected register
|
||||
* Arguments : reg_type
|
||||
* The type of ECM register (ECM_MASETR, ECM_CHECKER, ECM_COMMON)
|
||||
* *reg
|
||||
* The address of ECM protected register
|
||||
* value
|
||||
* The 32-bit value of writing to protected register
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
uint8_t R_ECM_Write_Reg32( uint8_t reg_type, volatile unsigned long *reg, uint32_t value)
|
||||
{
|
||||
uint8_t result;
|
||||
volatile uint32_t dummy_32;
|
||||
|
||||
/* Special write sequence */
|
||||
*g_pcmd_reg_adrr[reg_type] = ECM_COMMAND_KEY; // Write fixed value
|
||||
dummy_32 = *g_pcmd_reg_adrr[reg_type];
|
||||
|
||||
*reg = value; // Write expected value
|
||||
*reg = ~value; // Write inversed value of the expected value
|
||||
*reg = value; // Write expected value
|
||||
dummy_32 = *reg;
|
||||
|
||||
/* Check the ECMPS register whether special sequence is success or failure
|
||||
result = 0 : Special sequence is success.
|
||||
= 1 : Special sequence is failure. */
|
||||
result = ECM.ECMPS.BYTE;
|
||||
|
||||
return result;
|
||||
|
||||
}
|
||||
/*******************************************************************************
|
||||
End of function R_ECM_Write_Reg32
|
||||
*******************************************************************************/
|
||||
|
||||
/* End of File */
|
||||
|
||||
|
||||
@@ -0,0 +1,329 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_icu_init.c
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for ICU init
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Initialize the peripheral settings of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include <Renesas/ior7s910017.h>
|
||||
#include "r_icu_init.h"
|
||||
#include "r_system.h"
|
||||
#include "r_mpc.h"
|
||||
#include "r_ecm.h"
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Private variables and functions
|
||||
*******************************************************************************/
|
||||
#ifdef __ICCARM__
|
||||
#pragma type_attribute=__irq __arm
|
||||
#endif // __ICCARM__
|
||||
void R_IRQ9_isr(void);
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: R_ICU_Disable
|
||||
* Description : Disable IRQ interrupt
|
||||
* Arguments : vec_num
|
||||
Vector interrupt number (1 to 294).
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void R_ICU_Disable(uint32_t vec_num)
|
||||
{
|
||||
/* Define IECn register address pointer */
|
||||
volatile uint32_t *p_iec_base;
|
||||
|
||||
/* Variable to specify register suffix */
|
||||
uint32_t reg_num; // IECn (n = reg_num)
|
||||
uint32_t bit_num; // IECn.IECm (m = bit_num)
|
||||
|
||||
/* Calcurate register address and register suffix number */
|
||||
if ( 255 >= vec_num ) // Vector number : 1 to 255
|
||||
{
|
||||
/* Set each pointer base address as IEC0 */
|
||||
/* Casting the pointer to a (uint32_t *) is valid because this pointer
|
||||
will reference 32 bit I/O register address */
|
||||
p_iec_base = (uint32_t*)&(VIC.IEC0.LONG);
|
||||
|
||||
/* Calcurate register suffix number */
|
||||
reg_num = vec_num / 32; // IECn (n = reg_num)
|
||||
bit_num = vec_num % 32; // IECn.IECm (m = bit_num)
|
||||
}
|
||||
else // Vector number : 256 to 294
|
||||
{
|
||||
/* Set each pointer address as IEC8 */
|
||||
/* Casting the pointer to a (uint32_t *) is valid because this pointer
|
||||
will reference 32 bit I/O register address */
|
||||
p_iec_base = (uint32_t*)&(VIC.IEC8.LONG);
|
||||
|
||||
/* Calcurate register suffix number. And subtract 8 from reg_num
|
||||
because IEC8 is base address in this case */
|
||||
reg_num = (vec_num / 32) - 8; // IECn (n = 8 + reg_num)
|
||||
bit_num = (vec_num % 32); // IECn.IECm (m = bit_num)
|
||||
}
|
||||
|
||||
/* Set interrupt enable clear register (disable interrupt) */
|
||||
p_iec_base += reg_num; // Specify IECn register address
|
||||
*p_iec_base |= ( 1 << bit_num ); // Set IECn.IECm bit
|
||||
|
||||
}
|
||||
/*******************************************************************************
|
||||
End of function R_ICU_Disable
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: R_ICU_Enable
|
||||
* Description : Enable IRQ interrupt
|
||||
* Arguments : vec_num
|
||||
Vector interrupt number (1 to 294).
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void R_ICU_Enable(uint32_t vec_num)
|
||||
{
|
||||
/* Define IENn register address pointer */
|
||||
volatile uint32_t *p_ien_base;
|
||||
|
||||
/* Variable to specify register suffix */
|
||||
uint32_t reg_num; // IENn (n = reg_num)
|
||||
uint32_t bit_num; // IENn.IENm (m = bit_num)
|
||||
|
||||
|
||||
/* Calcurate register address and register suffix number */
|
||||
if ( 255 >= vec_num ) // Vector number : 1 to 255
|
||||
{
|
||||
/* Set each pointer base address as IEN0 */
|
||||
/* Casting the pointer to a (uint32_t *) is valid because this pointer
|
||||
will reference 32 bit I/O register address */
|
||||
p_ien_base = (uint32_t*)&(VIC.IEN0.LONG);
|
||||
|
||||
/* Calcurate register suffix number */
|
||||
reg_num = vec_num / 32; // IENn (n = reg_num)
|
||||
bit_num = vec_num % 32; // IENn.IENm (m = bit_num)
|
||||
}
|
||||
else // Vector number : 256 to 294
|
||||
{
|
||||
/* Set each pointer address as IEN8 */
|
||||
/* Casting the pointer to a (uint32_t *) is valid because this pointer
|
||||
will reference 32 bit I/O register address */
|
||||
p_ien_base = (uint32_t*)&(VIC.IEN8.LONG);
|
||||
|
||||
/* Calcurate register suffix number. And subtract 8 from reg_num
|
||||
because IEN8 is base address in this case */
|
||||
reg_num = (vec_num / 32) - 8; // IENn (n = 8 + reg_num)
|
||||
bit_num = (vec_num % 32); // IENn.IENm (m = bit_num)
|
||||
}
|
||||
|
||||
/* Set interrupt enable register (enable interrupt) */
|
||||
p_ien_base += reg_num; // Specify IENn register address
|
||||
*p_ien_base |= ( 1 << bit_num ); // Set IENn.IENm bit
|
||||
|
||||
}
|
||||
/*******************************************************************************
|
||||
End of function R_ICU_Enable
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: R_ICU_ExtPinInit
|
||||
* Description : Initialize external interrupt pin setting.
|
||||
* Arguments : pin_num
|
||||
External interrupt pin number (0 to 15).
|
||||
detect
|
||||
Interrupt pin detection sense (Low, Fall, Rise, RIse&Fall).
|
||||
dnf_set
|
||||
Setting of degital noise filter
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void R_ICU_ExtPinInit(uint16_t pin_num, uint8_t detect, uint32_t dnf_set)
|
||||
{
|
||||
/* Define IRQCRn register address pointer */
|
||||
/* Casting the pointer to a (void *) is valid because this pointer will
|
||||
reference 32 bit I/O register address */
|
||||
volatile uint32_t *p_irqcr_base = (void *)(&(ICU.IRQCR0.LONG));
|
||||
|
||||
/* Disable digital noise filter (Clear IRQFLTEn bit (n = pin_num))*/
|
||||
ICU.IRQFLTE.LONG &= (0x0000FFFF & ~( 1 << pin_num ));
|
||||
|
||||
/* Set IRQ detection sense */
|
||||
p_irqcr_base += pin_num; // Specify IRQCRn register address
|
||||
*p_irqcr_base = detect; // Set IRQCRn.IRQMD[1:0]
|
||||
|
||||
/* Set digital noise filter and enable */
|
||||
if ( ICU_DNF_NO_USE != dnf_set )
|
||||
{
|
||||
/* Set digital noise filter */
|
||||
ICU.IRQFLTC.LONG &= ~( 3 << ( pin_num * 2 ) ); // Clear FCLKSELn[1:0]
|
||||
ICU.IRQFLTC.LONG |= (dnf_set << ( pin_num * 2)); // Set FCLKSELn[1:0] to dnf_set value
|
||||
|
||||
/* Enable digital noise filter */
|
||||
ICU.IRQFLTE.LONG |= ( 1 << pin_num );
|
||||
}
|
||||
|
||||
}
|
||||
/*******************************************************************************
|
||||
End of function R_ICU_ExtPinInit
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: R_ICU_Regist
|
||||
* Description : Registration interrupt controller setting.
|
||||
* Arguments : vec_num
|
||||
Vector interrupt number (1 to 294).
|
||||
type
|
||||
IRQ detection type(Level or Edge).
|
||||
priority
|
||||
IRQ priority level ( Vector number 1 to 255 : 0 to 15,
|
||||
Vector number 256 to 294 : 16 to 31)
|
||||
isr_addr
|
||||
Interrupt service routine address
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void R_ICU_Regist(uint32_t vec_num, uint32_t type, uint32_t priority, uint32_t isr_addr)
|
||||
{
|
||||
/* Define PLSn, PRLn, VADn and PICn registers address pointer */
|
||||
volatile uint32_t *p_pls_base;
|
||||
volatile uint32_t *p_prl_base;
|
||||
volatile uint32_t *p_vad_base;
|
||||
volatile uint32_t *p_pic_base;
|
||||
|
||||
/* Variable to specify register suffix */
|
||||
uint32_t reg_num; // PLSn, PICn (n = reg_num)
|
||||
uint32_t bit_num; // PLSn.PLSm, PICn.PICm (m = bit_num)
|
||||
|
||||
|
||||
/* Calcurate register address and register suffix number */
|
||||
if ( 255 >= vec_num ) // Vector number : 1 to 255
|
||||
{
|
||||
/* Set each pointer base address as PLS0, PRL1, VAD1 and PIC0 */
|
||||
/* Casting the pointer to a (uint32_t *) is valid because this pointer
|
||||
will reference 32 bit I/O register address */
|
||||
p_pls_base = (uint32_t*)&(VIC.PLS0.LONG);
|
||||
p_prl_base = (uint32_t*)&(VIC.PRL1.LONG);
|
||||
p_vad_base = (uint32_t*)&(VIC.VAD1.LONG);
|
||||
p_pic_base = (uint32_t*)&(VIC.PIC0.LONG);
|
||||
|
||||
/* Calcurate register suffix number */
|
||||
reg_num = vec_num / 32; // PLSn, PICn (n = reg_num)
|
||||
bit_num = vec_num % 32; // PLSn.PLSm, PICn.PICm (m = bit_num)
|
||||
}
|
||||
else // Vector number : 256 to 294
|
||||
{
|
||||
/* Set each pointer address as PLS8, PRL256, VAD256 and PIC8 */
|
||||
/* Casting the pointer to a (uint32_t *) is valid because this pointer
|
||||
will reference 32 bit I/O register address */
|
||||
p_pls_base = (uint32_t*)&(VIC.PLS8.LONG);
|
||||
p_prl_base = (uint32_t*)&(VIC.PRL256.LONG);
|
||||
p_vad_base = (uint32_t*)&(VIC.VAD256.LONG);
|
||||
p_pic_base = (uint32_t*)&(VIC.PIC8.LONG);
|
||||
|
||||
/* Calcurate register suffix number. And subtract 8 from reg_num
|
||||
because PLS8 and PIC8 are base address in this case */
|
||||
reg_num = (vec_num / 32) - 8; // PLSn, PICn (n = 8 + reg_num)
|
||||
bit_num = (vec_num % 32); // PLSn.PLSm, PICn.PICm (m = bit_num)
|
||||
vec_num -= 255; // Offset (PRLn and VADn base is changed (eg. VAD1 to VAD256)
|
||||
}
|
||||
|
||||
/* Set interrupt detection type (Level or Edge) by PLSn */
|
||||
p_pls_base += reg_num; // Specify PLSn register address
|
||||
*p_pls_base &= ~( 1 << bit_num ); // Clear PLSn.PLSm bit
|
||||
*p_pls_base |= ( type << bit_num ); // Set PLSn.PLSm bit to type value
|
||||
|
||||
/* Set interrupt priority level (0 to 15) or (16 to 31) */
|
||||
p_prl_base += ( vec_num - 1 ); // Specify PRLn register address
|
||||
*p_prl_base = priority; // Set PRLn to priority value
|
||||
|
||||
/* Set interrupt service routine address */
|
||||
p_vad_base += ( vec_num - 1 ); // Specify VADn register address
|
||||
*p_vad_base = isr_addr; // Set VADn to isr_addr value
|
||||
|
||||
/* Clear interrupt edge detection (edge type only)*/
|
||||
if ( ICU_TYPE_EDGE == type )
|
||||
{
|
||||
p_pic_base += reg_num; // Specify PICn register address
|
||||
*p_pic_base |= ( 1 << bit_num ); // Set PICn.PICm bit to 1
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function R_ICU_Regist
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: R_IRQ9_isr
|
||||
* Description : Interrupt service routine of IRQ9 (IRQ5 pin interrupt).
|
||||
* Toggle the P56 output level (LED1)
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
#ifdef __ICCARM__
|
||||
#pragma type_attribute=__irq __arm
|
||||
#endif // __ICCARM__
|
||||
void R_IRQ9_isr(void)
|
||||
{
|
||||
/* Clear interrupt edge detection */
|
||||
VIC.PIC0.BIT.PIC9 = ICU_PIC_EDGE_CLEAR;
|
||||
|
||||
/* Toggle the P56 output level(LED1) */
|
||||
PORT5.PODR.BIT.B6 ^= 1;
|
||||
|
||||
/* End interrupt sequence (dummy writing to HVA0 register) */
|
||||
VIC.HVA0.LONG = 0x00000000;
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function R_IRQ9_isr
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* End of File */
|
||||
@@ -0,0 +1,148 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_ram_init.c
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for internal extended RAM function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : internal extended RAM setting API of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include <Renesas/ior7s910017.h>
|
||||
#include "r_system.h"
|
||||
#include "r_ram_init.h"
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define RAM_ECC_ENABLE (0x00000001)
|
||||
#define RAM_ECC_DISABLE (0x00000000)
|
||||
#define RAM_PROTECT (0x00000000)
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : R_RAM_ECC_Enable
|
||||
* Description : Enable ECC function for internal extended RAM.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void R_RAM_ECC_Enable(void)
|
||||
{
|
||||
/* Enables writing to the protected registers related to RAM function */
|
||||
R_RAM_WriteEnable();
|
||||
|
||||
/* Enable ECC function */
|
||||
ECCRAM.RAMEDC.LONG = RAM_ECC_ENABLE;
|
||||
|
||||
/* Disables writing to the protected registers related to RAM function */
|
||||
R_RAM_WriteDisable();
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function R_RAM_ECC_Enable
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : R_RAM_WriteEnable
|
||||
* Description : Enable writing to the protected registers related to RAM.
|
||||
* And dummy read the register in order to fix the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void R_RAM_WriteEnable(void)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
|
||||
/* Special sequence for protect release */
|
||||
ECCRAM.RAMPCMD.LONG = 0x000000A5; // Write fixed value 0x000000A5
|
||||
ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value
|
||||
ECCRAM.RAMPCMD.LONG = 0x0000FFFE; // Write inversed value of the expected value
|
||||
ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value again
|
||||
dummy = ECCRAM.RAMPCMD.LONG;
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function R_RAM_WriteEnable
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : R_RAM_WriteDisable
|
||||
* Description : Disable writing to the protected registers related to RAM.
|
||||
* And dummy read the register in order to fix the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void R_RAM_WriteDisable(void)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
|
||||
/* Clear RAMPCMD register to zero */
|
||||
ECCRAM.RAMPCMD.LONG = RAM_PROTECT;
|
||||
dummy = ECCRAM.RAMPCMD.LONG;
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function R_RAM_WriteDisable
|
||||
*******************************************************************************/
|
||||
|
||||
/* End of File */
|
||||
|
||||
|
||||
@@ -0,0 +1,123 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_reset.c
|
||||
* Version : 0.1
|
||||
* Device : R7S9100xx
|
||||
* Abstract : API for RESET and Low-Power function
|
||||
* Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : RESET and Low-Power API of RZ/T1
|
||||
* Limitation : none
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : First Release
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include <Renesas/ior7s910017.h>
|
||||
#include "r_system.h"
|
||||
#include "r_reset.h"
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define RST_WRITE_ENABLE (0x0000A502)
|
||||
#define RST_WRITE_DISABLE (0x0000A500)
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : r_rst_write_enable
|
||||
* Description : Enables writing to the registers related to RESET and Low-
|
||||
* Power function. And dummy read the register in order to fix
|
||||
* the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void r_rst_write_enable(void)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
|
||||
/* Enables writing to the Reset and Low-Power register */
|
||||
SYSTEM.PRCR.LONG = RST_WRITE_ENABLE;
|
||||
dummy = SYSTEM.PRCR.LONG;
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function r_rst_write_enable
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : r_rst_write_disable
|
||||
* Description : Disables writing to the registers related to RESET and Low-
|
||||
* Power function. And dummy read the register in order to fix
|
||||
* the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void r_rst_write_disable(void)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
|
||||
/* Disables writing to the Reset and Low-Power register */
|
||||
SYSTEM.PRCR.LONG = RST_WRITE_DISABLE;
|
||||
dummy = SYSTEM.PRCR.LONG;
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
End of function r_rst_write_disable
|
||||
*******************************************************************************/
|
||||
|
||||
/* End of File */
|
||||
|
||||
|
||||
@@ -0,0 +1,73 @@
|
||||
;*******************************************************************************
|
||||
; DISCLAIMER
|
||||
; This software is supplied by Renesas Electronics Corporation and is only
|
||||
; intended for use with Renesas products. No other uses are authorized. This
|
||||
; software is owned by Renesas Electronics Corporation and is protected under
|
||||
; all applicable laws, including copyright laws.
|
||||
; THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
; THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
; LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
; AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
; TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
; ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
; FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
; ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
; BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
; Renesas reserves the right, without notice, to make changes to this software
|
||||
; and to discontinue the availability of this software. By using this software,
|
||||
; you agree to the additional terms and conditions found by accessing the
|
||||
; following link:
|
||||
; http://www.renesas.com/disclaimer
|
||||
;
|
||||
; Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
; System Name : RZ/T1 Init program
|
||||
; File Name : vector.asm
|
||||
; Version : 0.1
|
||||
; Device : R7S9100xx
|
||||
; Abstract : vector address (in low vector)
|
||||
; Tool-Chain : IAR Embedded Workbench Ver.7.20
|
||||
; OS : not use
|
||||
; H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
; Description : vector address for RZ/T1 (in low vector)
|
||||
; Limitation : none
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
; History : DD.MM.YYYY Version Description
|
||||
; : First Release
|
||||
;******************************************************************************
|
||||
|
||||
/* This program is allocated to section "intvec" */
|
||||
SECTION intvec:CODE:ROOT(2)
|
||||
|
||||
EXTERN FreeRTOS_SVC_Handler
|
||||
|
||||
ARM
|
||||
|
||||
reset_handler:
|
||||
b reset_handler
|
||||
|
||||
undefined_handler:
|
||||
b undefined_handler
|
||||
|
||||
svc_handler:
|
||||
b FreeRTOS_SVC_Handler
|
||||
|
||||
prefetch_handler:
|
||||
b prefetch_handler
|
||||
|
||||
abort_handler:
|
||||
b abort_handler
|
||||
|
||||
reserved_handler:
|
||||
b reserved_handler
|
||||
|
||||
irq_handler:
|
||||
b irq_handler
|
||||
|
||||
fiq_handler:
|
||||
b fiq_handler
|
||||
|
||||
END
|
||||
; End of File
|
||||
@@ -1,196 +0,0 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 SCIF program
|
||||
* File Name : siochar.c
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : Serial I/O settings controlling the character
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Control the character with serial I/O
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_userdefine.h"
|
||||
#include "r_cg_scifa.h"
|
||||
#include "siochar.h"
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Private global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: io_init_scifa2
|
||||
* Description : This function initialises SCIFA channel 2 as UART mode.
|
||||
* : The transmit and the receive of SCIFA channel 2 are enabled.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void io_init_scifa2 (void)
|
||||
{
|
||||
/* === Initialisation of SCIFA2 if not already initialised ==== */
|
||||
if (1 == MSTP_SCIFA2)
|
||||
{
|
||||
R_SCIFA2_Create();
|
||||
}
|
||||
|
||||
/* Ensure receive FIFO trigger is set to 1 */
|
||||
SCIFA2.FCR.BIT.RTRG = 0U;
|
||||
|
||||
/* Reception triggered by one data */
|
||||
SCIFA2.FTCR.BIT.RFTC = 1u;
|
||||
|
||||
/* Enable reception and receive interrupts */
|
||||
SCIFA2.SCR.BIT.RE = 1U;
|
||||
SCIFA2.SCR.BIT.RIE = 1U;
|
||||
SCIFA2.SCR.BIT.REIE = 1U;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function io_init_scifa2
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: io_get_char
|
||||
* Description : One character is received from SCIFA2, and it's data is returned.
|
||||
* : This function keeps waiting until it can obtain the receiving data.
|
||||
* Arguments : none
|
||||
* Return Value : Character to receive (Byte).
|
||||
***********************************************************************************************************************/
|
||||
char io_get_char (void)
|
||||
{
|
||||
char data;
|
||||
|
||||
/* Confirming receive error (ER,BRK,FER,PER) */
|
||||
if (SCIFA2.FSR.WORD & 0x09Cu)
|
||||
{
|
||||
/* ---- Detect receive error ---- */
|
||||
|
||||
/* Disable reception */
|
||||
SCIFA2.SCR.BIT.RE = 0U;
|
||||
|
||||
/* Reset receiving FIFO */
|
||||
SCIFA2.FCR.BIT.RFRST = 1U;
|
||||
|
||||
/* Clearing FIFO reception reset */
|
||||
SCIFA2.FCR.BIT.RFRST = 0U;
|
||||
|
||||
/* Error bit clear */
|
||||
SCIFA2.FSR.BIT.DR = 0U;
|
||||
SCIFA2.FSR.BIT.RDF = 0U;
|
||||
|
||||
/* Enable reception */
|
||||
SCIFA2.SCR.BIT.RE = 1U;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* Is there receive FIFO data? */
|
||||
while (0 == SCIFA2.FSR.BIT.RDF)
|
||||
{
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
/* Read receive data */
|
||||
data = SCIFA2.FRDR;
|
||||
|
||||
/* Clear RDF */
|
||||
SCIFA2.FSR.BIT.RDF = 0U;
|
||||
|
||||
/* Is it overflowed? */
|
||||
if (1 == SCIFA2.LSR.BIT.ORER)
|
||||
{
|
||||
/* ORER clear */
|
||||
SCIFA2.LSR.BIT.ORER = 0U;
|
||||
}
|
||||
|
||||
return (data);
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function io_get_char
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: io_put_char
|
||||
* Description : Character "buffer" is output to SCIFA2.
|
||||
* : This function keeps waiting until it becomes the transmission
|
||||
* : enabled state.
|
||||
* Arguments : char buffer : character to output
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void io_put_char (char buffer)
|
||||
{
|
||||
/* Check if it is possible to transmit (TDFE flag) */
|
||||
while (0 == SCIFA2.FSR.BIT.TDFE)
|
||||
{
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
/* Send the character via the terminal output */
|
||||
R_SCIFA2_Serial_Send((uint8_t *)&buffer, 1);
|
||||
|
||||
/* Clear TEND flag */
|
||||
SCIFA2.FSR.BIT.TEND = 0u;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* End of function io_put_char
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/* End of File */
|
||||
|
||||
@@ -1,226 +0,0 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 SCIF program
|
||||
* File Name : siorw.c
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : Serial I/O settings controlling the read and write command
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Control the read/write command with serial I/O
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
#include <stdio.h>
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_userdefine.h"
|
||||
#include "r_cg_scifa.h"
|
||||
#include "siochar.h"
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
/* File descriptor */
|
||||
#define STDIN (0)
|
||||
#define STDOUT (1)
|
||||
#define STDERR (2)
|
||||
|
||||
#define SIORW_SUCCESS (0)
|
||||
#define SIORW_ERROR (-1)
|
||||
#define SIORW_FLAG_OFF (0)
|
||||
#define SIORW_FLAG_ON (1)
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Private global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: sio_write
|
||||
* Description : The character strings specified with buffer is output for n
|
||||
* : bytes from serial port. The output is determined by file number fileno.
|
||||
* : The effective outputs in this version are STDOUT and STDERR, and
|
||||
* : it is output to the same serial port.
|
||||
* : The line-feed code '\n'(LF) is converted in '\r'(CR)+'\n'(LF) to output.
|
||||
* Arguments : int32_t file_no ; I : File number to be the target of writing
|
||||
* : int_t * buffer ; O : Pointer to the area in which writing data is stored
|
||||
* : uint32_t writing_b; I : Writing bytes
|
||||
* Return Value : >=0 : Number of transmitting characters
|
||||
* : -1 : File number error
|
||||
***********************************************************************************************************************/
|
||||
int32_t sio_write (int32_t file_no, const char * buffer, uint32_t writing_b)
|
||||
{
|
||||
uint32_t offset;
|
||||
|
||||
if ((STDOUT == file_no) || (STDERR == file_no))
|
||||
{
|
||||
for (offset = 0; offset < writing_b; offset++)
|
||||
|
||||
{
|
||||
/* Writing in buffer converting line-feed code */
|
||||
if ('\n' == (*(buffer + offset)))
|
||||
{
|
||||
if (0 == offset)
|
||||
{
|
||||
io_put_char('\r');
|
||||
}
|
||||
else
|
||||
{
|
||||
if ('\r' != (*((buffer + offset) - 1)))
|
||||
{
|
||||
io_put_char('\r');
|
||||
}
|
||||
}
|
||||
io_put_char('\n');
|
||||
}
|
||||
else
|
||||
{
|
||||
io_put_char(*(buffer + offset));
|
||||
}
|
||||
}
|
||||
return ((int32_t)offset);
|
||||
}
|
||||
|
||||
/* File number error */
|
||||
return SIORW_ERROR;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* End of function sio_write
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: sio_read
|
||||
* Description : The character strings specified with buffer is input for
|
||||
* : n bytes from serial port.The input is determined by file number fileno.
|
||||
* : The effective input in this version is STDIN.
|
||||
* Arguments : int32_t file_no ; I : File number to be the target of reading
|
||||
* : int_t * buffer ; O : Pointer to the area in which reading data is stored
|
||||
* : uint32_t reading_b; I : Reading bytes
|
||||
* Return Value : >0 : Number of receiving characters
|
||||
* : -1 : File number, receiving data error
|
||||
***********************************************************************************************************************/
|
||||
int32_t sio_read (int32_t file_no, char * buffer, uint32_t reading_b)
|
||||
{
|
||||
int32_t char_mem;
|
||||
int32_t sp_char;
|
||||
uint32_t offset;
|
||||
static int32_t sjis_flg = SIORW_FLAG_OFF;
|
||||
|
||||
if (STDIN == file_no)
|
||||
{
|
||||
for (offset = 0; offset < reading_b; )
|
||||
{
|
||||
/* Reading receiving data */
|
||||
char_mem = io_get_char();
|
||||
|
||||
/* -1 is returned when it is receiving data error */
|
||||
if ((-1) == char_mem)
|
||||
{
|
||||
return SIORW_ERROR;
|
||||
}
|
||||
|
||||
if (SIORW_FLAG_ON == sjis_flg)
|
||||
{
|
||||
sjis_flg = SIORW_FLAG_OFF;
|
||||
sio_write(STDOUT, (char *)&char_mem, 1);
|
||||
|
||||
(*(buffer + offset)) = (char)char_mem;
|
||||
offset++;
|
||||
}
|
||||
if ((0x20 <= char_mem) && (char_mem <= 0x7E))
|
||||
{
|
||||
/* Data possible to display */
|
||||
sio_write(STDOUT, (char *)&char_mem, 1);
|
||||
(*(buffer + offset)) = (char)char_mem;
|
||||
offset++;
|
||||
}
|
||||
|
||||
/* BS process */
|
||||
if (('\b' == char_mem) && (offset > 0))
|
||||
{ sp_char = 0x20;
|
||||
sio_write(STDOUT, (char *)&char_mem, 1);
|
||||
sio_write(STDOUT, (char *)&sp_char, 1);
|
||||
sio_write(STDOUT, (char *)&char_mem, 1);
|
||||
offset--;
|
||||
}
|
||||
|
||||
/* CR process */
|
||||
if ('\r' == char_mem)
|
||||
{
|
||||
(*(buffer + offset)) = '\n';
|
||||
sio_write(STDOUT, buffer + offset, 1);
|
||||
offset++;
|
||||
}
|
||||
|
||||
/* Japanese SJIS ? */
|
||||
if (((char_mem >= 0x80) && (char_mem < 0xA0)) || ((char_mem >= 0xE0) && (char_mem < 0xFE)))
|
||||
{
|
||||
/* Data possible to display */
|
||||
sio_write(STDOUT, (char *)&char_mem, 1);
|
||||
(*(buffer + offset)) = (char)char_mem;
|
||||
offset++;
|
||||
sjis_flg = SIORW_FLAG_ON;
|
||||
}
|
||||
}
|
||||
return ((int32_t)offset);
|
||||
}
|
||||
|
||||
/* File number error */
|
||||
return SIORW_ERROR;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function sio_read
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/* End of File */
|
||||
|
||||
@@ -0,0 +1,187 @@
|
||||
/*
|
||||
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
#define configCPU_CLOCK_HZ 450000000
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#define configUSE_TICKLESS_IDLE 0
|
||||
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_IDLE_HOOK 1
|
||||
#define configUSE_TICK_HOOK 1
|
||||
#define configMAX_PRIORITIES ( 5 )
|
||||
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 )
|
||||
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 38 * 1024 ) )
|
||||
#define configMAX_TASK_NAME_LEN ( 10 )
|
||||
#define configUSE_TRACE_FACILITY 1
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configIDLE_SHOULD_YIELD 1
|
||||
#define configUSE_MUTEXES 1
|
||||
#define configQUEUE_REGISTRY_SIZE 8
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 2
|
||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
#define configUSE_MALLOC_FAILED_HOOK 1
|
||||
#define configUSE_APPLICATION_TASK_TAG 0
|
||||
#define configUSE_COUNTING_SEMAPHORES 1
|
||||
#define configGENERATE_RUN_TIME_STATS 0
|
||||
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
|
||||
|
||||
/* Software timer definitions. */
|
||||
#define configUSE_TIMERS 1
|
||||
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
|
||||
#define configTIMER_QUEUE_LENGTH 5
|
||||
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 1
|
||||
#define INCLUDE_vTaskDelete 1
|
||||
#define INCLUDE_vTaskCleanUpResources 1
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_eTaskGetState 1
|
||||
#define INCLUDE_xEventGroupSetBitFromISR 1
|
||||
#define INCLUDE_xTimerPendFunctionCall 1
|
||||
|
||||
/* This demo makes use of one or more example stats formatting functions. These
|
||||
format the raw data provided by the uxTaskGetSystemState() function in to human
|
||||
readable ASCII form. See the notes in the implementation of vTaskList() within
|
||||
FreeRTOS/Source/tasks.c for limitations. */
|
||||
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
|
||||
|
||||
/* Cortex-R specific setting: FPU has 16 (rather than 32) d registers. */
|
||||
#define configFPU_D32 0
|
||||
|
||||
/* Cortex-R specific setting: The address of the register within the interrupt
|
||||
controller from which the address of the current interrupt's handling function
|
||||
can be obtained. */
|
||||
#define configINTERRUPT_VECTOR_ADDRESS
|
||||
|
||||
/* Cortex-R specific setting: The address of End of Interrupt register within
|
||||
the interrupt controller. */
|
||||
#define configEOI_ADDRESS 0xA0010200UL /* VIC HVA0 register */
|
||||
|
||||
/* Cortex-R specific setting: configCLEAR_TICK_INTERRUPT() is a macro that is
|
||||
called by the RTOS kernel's tick handler to clear the source of the tick
|
||||
interrupt. */
|
||||
#define configCLEAR_TICK_INTERRUPT() VIC.PIC9.LONG = 0x00001000UL;
|
||||
|
||||
/* Prevent C code being included in assembly files when the IAR compiler is
|
||||
used. */
|
||||
#ifndef __IASMARM__
|
||||
|
||||
/* Renesas hardware definitions. */
|
||||
#include "iodefine.h"
|
||||
|
||||
/* Application specific definition. See _TBD_ for usage instructions. */
|
||||
typedef void (*ISRFunction_t)( void );
|
||||
|
||||
/* Normal assert() semantics without relying on the provision of an assert.h
|
||||
header file. */
|
||||
#define configASSERT( x ) if( ( x ) == 0 ) { portDISABLE_INTERRUPTS(); for( ;; ); }
|
||||
|
||||
|
||||
|
||||
/****** Hardware specific settings. *******************************************/
|
||||
|
||||
/*
|
||||
* The application must provide a function that configures a peripheral to
|
||||
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
|
||||
* in FreeRTOSConfig.h to call the function. FreeRTOS_Tick_Handler() must
|
||||
* be installed as the peripheral's interrupt handler.
|
||||
*/
|
||||
void vConfigureTickInterrupt( void );
|
||||
#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()
|
||||
|
||||
#endif /* __IASMARM__ */
|
||||
|
||||
/* To allow the debugger to find the end of the interrupt stack frame. */
|
||||
#define configTASK_RETURN_ADDRESS NULL
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
||||
|
||||
@@ -82,7 +82,14 @@
|
||||
* variable to point to the RTOS tick handler, then branches to the FreeRTOS
|
||||
* IRQ handler.
|
||||
*/
|
||||
static void FreeRTOS_Tick_Handler_Entry( void ) __attribute__((naked));
|
||||
#ifdef __GNUC__
|
||||
static void FreeRTOS_Tick_Handler_Entry( void ) __attribute__((naked));
|
||||
#endif /* __GNUC__ */
|
||||
#ifdef __ICCARM__
|
||||
/* IAR requires the entry point to be in an assembly file. The function is
|
||||
implemented in $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm. */
|
||||
extern void FreeRTOS_Tick_Handler_Entry( void );
|
||||
#endif /* __ICCARM__ */
|
||||
|
||||
/*
|
||||
* The FreeRTOS IRQ handler, which is implemented in the RTOS port layer.
|
||||
@@ -184,17 +191,21 @@ ISRFunction_t pxISRToCall = pxISRFunction;
|
||||
* saved in the pxISRFunction variable. NOTE: This entry point is a naked
|
||||
* function - do not add C code to this function.
|
||||
*/
|
||||
static void FreeRTOS_Tick_Handler_Entry( void )
|
||||
{
|
||||
__asm volatile ( \
|
||||
"PUSH {r0-r1} \t\n" \
|
||||
"LDR r0, =pxISRFunction \t\n" \
|
||||
"LDR R1, =FreeRTOS_Tick_Handler \t\n" \
|
||||
"STR R1, [r0] \t\n" \
|
||||
"POP {r0-r1} \t\n" \
|
||||
"B FreeRTOS_IRQ_Handler "
|
||||
);
|
||||
}
|
||||
#ifdef __GNUC__
|
||||
/* The IAR equivalent is implemented in
|
||||
$PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */
|
||||
static void FreeRTOS_Tick_Handler_Entry( void )
|
||||
{
|
||||
__asm volatile ( \
|
||||
"PUSH {r0-r1} \t\n" \
|
||||
"LDR r0, =pxISRFunction \t\n" \
|
||||
"LDR R1, =FreeRTOS_Tick_Handler \t\n" \
|
||||
"STR R1, [r0] \t\n" \
|
||||
"POP {r0-r1} \t\n" \
|
||||
"B FreeRTOS_IRQ_Handler "
|
||||
);
|
||||
}
|
||||
#endif /* __GNUC__ */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
@@ -101,9 +101,16 @@ void vCMT_1_Channel_1_ISR( void );
|
||||
* Entry point for the handlers. These set the pxISRFunction variable to point
|
||||
* to the C handler for each timer, then branch to the FreeRTOS IRQ handler.
|
||||
*/
|
||||
static void vCMT_1_Channel_0_ISR_Entry( void ) __attribute__((naked));
|
||||
static void vCMT_1_Channel_1_ISR_Entry( void ) __attribute__((naked));
|
||||
|
||||
#ifdef __GNUC__
|
||||
static void vCMT_1_Channel_0_ISR_Entry( void ) __attribute__((naked));
|
||||
static void vCMT_1_Channel_1_ISR_Entry( void ) __attribute__((naked));
|
||||
#endif /* __GNUC__ */
|
||||
#ifdef __ICCARM__
|
||||
/* IAR requires the entry point to be in an assembly file. The functions
|
||||
are implemented in $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm. */
|
||||
extern void vCMT_1_Channel_0_ISR_Entry( void );
|
||||
extern void vCMT_1_Channel_1_ISR_Entry( void );
|
||||
#endif /* __ICCARM__ */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vInitialiseTimerForIntQueueTest( void )
|
||||
@@ -196,30 +203,38 @@ void vCMT_1_Channel_1_ISR( void )
|
||||
* saved in the pxISRFunction variable. NOTE: The entry points are naked
|
||||
* functions - do not add C code to these functions.
|
||||
*/
|
||||
static void vCMT_1_Channel_0_ISR_Entry( void )
|
||||
{
|
||||
__asm volatile ( \
|
||||
"PUSH {r0-r1} \t\n" \
|
||||
"LDR r0, =pxISRFunction \t\n" \
|
||||
"LDR r1, =vCMT_1_Channel_0_ISR \t\n" \
|
||||
"STR r1, [r0] \t\n" \
|
||||
"POP {r0-r1} \t\n" \
|
||||
"B FreeRTOS_IRQ_Handler "
|
||||
);
|
||||
}
|
||||
#ifdef __GNUC__
|
||||
/* The IAR equivalent is implemented in
|
||||
$PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */
|
||||
static void vCMT_1_Channel_0_ISR_Entry( void )
|
||||
{
|
||||
__asm volatile ( \
|
||||
"PUSH {r0-r1} \t\n" \
|
||||
"LDR r0, =pxISRFunction \t\n" \
|
||||
"LDR r1, =vCMT_1_Channel_0_ISR \t\n" \
|
||||
"STR r1, [r0] \t\n" \
|
||||
"POP {r0-r1} \t\n" \
|
||||
"B FreeRTOS_IRQ_Handler "
|
||||
);
|
||||
}
|
||||
#endif /* __GNUC__ */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void vCMT_1_Channel_1_ISR_Entry( void )
|
||||
{
|
||||
__asm volatile ( \
|
||||
"PUSH {r0-r1} \t\n" \
|
||||
"LDR r0, =pxISRFunction \t\n" \
|
||||
"LDR r1, =vCMT_1_Channel_1_ISR \t\n" \
|
||||
"STR r1, [r0] \t\n" \
|
||||
"POP {r0-r1} \t\n" \
|
||||
"B FreeRTOS_IRQ_Handler "
|
||||
);
|
||||
}
|
||||
#ifdef __GNUC__
|
||||
/* The IAR equivalent is implemented in
|
||||
$PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */
|
||||
static void vCMT_1_Channel_1_ISR_Entry( void )
|
||||
{
|
||||
__asm volatile ( \
|
||||
"PUSH {r0-r1} \t\n" \
|
||||
"LDR r0, =pxISRFunction \t\n" \
|
||||
"LDR r1, =vCMT_1_Channel_1_ISR \t\n" \
|
||||
"STR r1, [r0] \t\n" \
|
||||
"POP {r0-r1} \t\n" \
|
||||
"B FreeRTOS_IRQ_Handler "
|
||||
);
|
||||
}
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,462 @@
|
||||
/*
|
||||
FreeRTOS V8.2.2 - Copyright (C) 2014 Real Time Engineers Ltd.
|
||||
|
||||
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
|
||||
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
|
||||
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
|
||||
details. You should have received a copy of the GNU General Public License
|
||||
and the FreeRTOS license exception along with FreeRTOS; if not itcan be
|
||||
viewed here: http://www.freertos.org/a00114.html and also obtained by
|
||||
writing to Real Time Engineers Ltd., contact details for whom are available
|
||||
on the FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* Having a problem? Start by reading the FAQ "My application does *
|
||||
* not run, what could be wrong?" *
|
||||
* *
|
||||
* http://www.FreeRTOS.org/FAQHelp.html *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
|
||||
license and Real Time Engineers Ltd. contact details.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, and our new
|
||||
fully thread aware and reentrant UDP/IP stack.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
|
||||
Integrity Systems, who sell the code with commercial support,
|
||||
indemnification and middleware, under the OpenRTOS brand.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
*/
|
||||
|
||||
PUBLIC vRegTest1Implementation
|
||||
PUBLIC vRegTest2Implementation
|
||||
EXTERN ulRegTest1LoopCounter
|
||||
EXTERN ulRegTest2LoopCounter
|
||||
|
||||
SECTION intvec:CODE:ROOT(2)
|
||||
ARM
|
||||
|
||||
/* This function is explained in the comments at the top of main-full.c. */
|
||||
vRegTest1Implementation:
|
||||
|
||||
/* Fill each general purpose register with a known value. */
|
||||
mov r0, #0xFF
|
||||
mov r1, #0x11
|
||||
mov r2, #0x22
|
||||
mov r3, #0x33
|
||||
mov r4, #0x44
|
||||
mov r5, #0x55
|
||||
mov r6, #0x66
|
||||
mov r7, #0x77
|
||||
mov r8, #0x88
|
||||
mov r9, #0x99
|
||||
mov r10, #0xAA
|
||||
mov r11, #0xBB
|
||||
mov r12, #0xCC
|
||||
mov r14, #0xEE
|
||||
|
||||
|
||||
/* Fill each FPU register with a known value. */
|
||||
vmov d0, r0, r1
|
||||
vmov d1, r2, r3
|
||||
vmov d2, r4, r5
|
||||
vmov d3, r6, r7
|
||||
vmov d4, r8, r9
|
||||
vmov d5, r10, r11
|
||||
vmov d6, r0, r1
|
||||
vmov d7, r2, r3
|
||||
vmov d8, r4, r5
|
||||
vmov d9, r6, r7
|
||||
vmov d10, r8, r9
|
||||
vmov d11, r10, r11
|
||||
vmov d12, r0, r1
|
||||
vmov d13, r2, r3
|
||||
vmov d14, r4, r5
|
||||
vmov d15, r6, r7
|
||||
|
||||
/* Loop, checking each itteration that each register still contains the
|
||||
expected value. */
|
||||
reg1_loop:
|
||||
/* Yield to increase test coverage */
|
||||
svc 0
|
||||
|
||||
/* Check all the VFP registers still contain the values set above.
|
||||
First save registers that are clobbered by the test. */
|
||||
push { r0-r1 }
|
||||
|
||||
vmov r0, r1, d0
|
||||
cmp r0, #0xFF
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x11
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d1
|
||||
cmp r0, #0x22
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x33
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d2
|
||||
cmp r0, #0x44
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x55
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d3
|
||||
cmp r0, #0x66
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x77
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d4
|
||||
cmp r0, #0x88
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x99
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d5
|
||||
cmp r0, #0xAA
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0xBB
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d6
|
||||
cmp r0, #0xFF
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x11
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d7
|
||||
cmp r0, #0x22
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x33
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d8
|
||||
cmp r0, #0x44
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x55
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d9
|
||||
cmp r0, #0x66
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x77
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d10
|
||||
cmp r0, #0x88
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x99
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d11
|
||||
cmp r0, #0xAA
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0xBB
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d12
|
||||
cmp r0, #0xFF
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x11
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d13
|
||||
cmp r0, #0x22
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x33
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d14
|
||||
cmp r0, #0x44
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x55
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d15
|
||||
cmp r0, #0x66
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #0x77
|
||||
bne reg1_error_loopf
|
||||
|
||||
|
||||
/* Restore the registers that were clobbered by the test. */
|
||||
pop {r0-r1}
|
||||
|
||||
/* VFP register test passed. Jump to the core register test. */
|
||||
b reg1_loopf_pass
|
||||
|
||||
reg1_error_loopf:
|
||||
/* If this line is hit then a VFP register value was found to be
|
||||
incorrect. */
|
||||
b reg1_error_loopf
|
||||
|
||||
reg1_loopf_pass:
|
||||
|
||||
/* Test each general purpose register to check that it still contains the
|
||||
expected known value, jumping to reg1_error_loop if any register contains
|
||||
an unexpected value. */
|
||||
cmp r0, #0xFF
|
||||
bne reg1_error_loop
|
||||
cmp r1, #0x11
|
||||
bne reg1_error_loop
|
||||
cmp r2, #0x22
|
||||
bne reg1_error_loop
|
||||
cmp r3, #0x33
|
||||
bne reg1_error_loop
|
||||
cmp r4, #0x44
|
||||
bne reg1_error_loop
|
||||
cmp r5, #0x55
|
||||
bne reg1_error_loop
|
||||
cmp r6, #0x66
|
||||
bne reg1_error_loop
|
||||
cmp r7, #0x77
|
||||
bne reg1_error_loop
|
||||
cmp r8, #0x88
|
||||
bne reg1_error_loop
|
||||
cmp r9, #0x99
|
||||
bne reg1_error_loop
|
||||
cmp r10, #0xAA
|
||||
bne reg1_error_loop
|
||||
cmp r11, #0xBB
|
||||
bne reg1_error_loop
|
||||
cmp r12, #0xCC
|
||||
bne reg1_error_loop
|
||||
cmp r14, #0xEE
|
||||
bne reg1_error_loop
|
||||
|
||||
/* Everything passed, increment the loop counter. */
|
||||
push { r0-r1 }
|
||||
ldr r0, =ulRegTest1LoopCounter
|
||||
ldr r1, [r0]
|
||||
adds r1, r1, #1
|
||||
str r1, [r0]
|
||||
pop { r0-r1 }
|
||||
|
||||
/* Start again. */
|
||||
b reg1_loop
|
||||
|
||||
reg1_error_loop:
|
||||
/* If this line is hit then there was an error in a core register value.
|
||||
The loop ensures the loop counter stops incrementing. */
|
||||
b reg1_error_loop
|
||||
nop
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
vRegTest2Implementation:
|
||||
|
||||
/* Put a known value in each register. */
|
||||
mov r0, #0xFF000000
|
||||
mov r1, #0x11000000
|
||||
mov r2, #0x22000000
|
||||
mov r3, #0x33000000
|
||||
mov r4, #0x44000000
|
||||
mov r5, #0x55000000
|
||||
mov r6, #0x66000000
|
||||
mov r7, #0x77000000
|
||||
mov r8, #0x88000000
|
||||
mov r9, #0x99000000
|
||||
mov r10, #0xAA000000
|
||||
mov r11, #0xBB000000
|
||||
mov r12, #0xCC000000
|
||||
mov r14, #0xEE000000
|
||||
|
||||
/* Likewise the floating point registers */
|
||||
vmov d0, r0, r1
|
||||
vmov d1, r2, r3
|
||||
vmov d2, r4, r5
|
||||
vmov d3, r6, r7
|
||||
vmov d4, r8, r9
|
||||
vmov d5, r10, r11
|
||||
vmov d6, r0, r1
|
||||
vmov d7, r2, r3
|
||||
vmov d8, r4, r5
|
||||
vmov d9, r6, r7
|
||||
vmov d10, r8, r9
|
||||
vmov d11, r10, r11
|
||||
vmov d12, r0, r1
|
||||
vmov d13, r2, r3
|
||||
vmov d14, r4, r5
|
||||
vmov d15, r6, r7
|
||||
|
||||
/* Loop, checking each itteration that each register still contains the
|
||||
expected value. */
|
||||
reg2_loop:
|
||||
/* Check all the VFP registers still contain the values set above.
|
||||
First save registers that are clobbered by the test. */
|
||||
push { r0-r1 }
|
||||
|
||||
vmov r0, r1, d0
|
||||
cmp r0, #0xFF000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x11000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d1
|
||||
cmp r0, #0x22000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x33000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d2
|
||||
cmp r0, #0x44000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x55000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d3
|
||||
cmp r0, #0x66000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x77000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d4
|
||||
cmp r0, #0x88000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x99000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d5
|
||||
cmp r0, #0xAA000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0xBB000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d6
|
||||
cmp r0, #0xFF000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x11000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d7
|
||||
cmp r0, #0x22000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x33000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d8
|
||||
cmp r0, #0x44000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x55000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d9
|
||||
cmp r0, #0x66000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x77000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d10
|
||||
cmp r0, #0x88000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x99000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d11
|
||||
cmp r0, #0xAA000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0xBB000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d12
|
||||
cmp r0, #0xFF000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x11000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d13
|
||||
cmp r0, #0x22000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x33000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d14
|
||||
cmp r0, #0x44000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x55000000
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d15
|
||||
cmp r0, #0x66000000
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #0x77000000
|
||||
bne reg2_error_loopf
|
||||
|
||||
/* Restore the registers that were clobbered by the test. */
|
||||
pop {r0-r1}
|
||||
|
||||
/* VFP register test passed. Jump to the core register test. */
|
||||
b reg2_loopf_pass
|
||||
|
||||
reg2_error_loopf:
|
||||
/* If this line is hit then a VFP register value was found to be
|
||||
incorrect. */
|
||||
b reg2_error_loopf
|
||||
|
||||
reg2_loopf_pass:
|
||||
|
||||
cmp r0, #0xFF000000
|
||||
bne reg2_error_loop
|
||||
cmp r1, #0x11000000
|
||||
bne reg2_error_loop
|
||||
cmp r2, #0x22000000
|
||||
bne reg2_error_loop
|
||||
cmp r3, #0x33000000
|
||||
bne reg2_error_loop
|
||||
cmp r4, #0x44000000
|
||||
bne reg2_error_loop
|
||||
cmp r5, #0x55000000
|
||||
bne reg2_error_loop
|
||||
cmp r6, #0x66000000
|
||||
bne reg2_error_loop
|
||||
cmp r7, #0x77000000
|
||||
bne reg2_error_loop
|
||||
cmp r8, #0x88000000
|
||||
bne reg2_error_loop
|
||||
cmp r9, #0x99000000
|
||||
bne reg2_error_loop
|
||||
cmp r10, #0xAA000000
|
||||
bne reg2_error_loop
|
||||
cmp r11, #0xBB000000
|
||||
bne reg2_error_loop
|
||||
cmp r12, #0xCC000000
|
||||
bne reg2_error_loop
|
||||
cmp r14, #0xEE000000
|
||||
bne reg2_error_loop
|
||||
|
||||
/* Everything passed, increment the loop counter. */
|
||||
push { r0-r1 }
|
||||
ldr r0, =ulRegTest2LoopCounter
|
||||
ldr r1, [r0]
|
||||
adds r1, r1, #1
|
||||
str r1, [r0]
|
||||
pop { r0-r1 }
|
||||
|
||||
/* Start again. */
|
||||
b reg2_loop
|
||||
|
||||
reg2_error_loop:
|
||||
/* If this line is hit then there was an error in a core register value.
|
||||
The loop ensures the loop counter stops incrementing. */
|
||||
b reg2_error_loop
|
||||
nop
|
||||
|
||||
|
||||
END
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user