mirror of
https://github.com/FreeRTOS/FreeRTOS.git
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Add Cortex M23 GCC and IAR ports. Add demo projects for Nuvoton NuMaker-PFM-2351.
This commit is contained in:
Gaurav Aggarwal
+121
@@ -0,0 +1,121 @@
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/* ----------------------------------------------------------------------
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* Project: CMSIS DSP Library
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* Title: arm_common_tables.h
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* Description: Extern declaration for common tables
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*
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* $Date: 27. January 2017
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* $Revision: V.1.5.1
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*
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* Target Processor: Cortex-M cores
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* -------------------------------------------------------------------- */
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/*
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* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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||||
* www.apache.org/licenses/LICENSE-2.0
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*
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||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _ARM_COMMON_TABLES_H
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#define _ARM_COMMON_TABLES_H
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#include "arm_math.h"
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extern const uint16_t armBitRevTable[1024];
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extern const q15_t armRecipTableQ15[64];
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extern const q31_t armRecipTableQ31[64];
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extern const float32_t twiddleCoef_16[32];
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extern const float32_t twiddleCoef_32[64];
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extern const float32_t twiddleCoef_64[128];
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extern const float32_t twiddleCoef_128[256];
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extern const float32_t twiddleCoef_256[512];
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extern const float32_t twiddleCoef_512[1024];
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extern const float32_t twiddleCoef_1024[2048];
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extern const float32_t twiddleCoef_2048[4096];
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extern const float32_t twiddleCoef_4096[8192];
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#define twiddleCoef twiddleCoef_4096
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extern const q31_t twiddleCoef_16_q31[24];
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extern const q31_t twiddleCoef_32_q31[48];
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extern const q31_t twiddleCoef_64_q31[96];
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extern const q31_t twiddleCoef_128_q31[192];
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extern const q31_t twiddleCoef_256_q31[384];
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extern const q31_t twiddleCoef_512_q31[768];
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extern const q31_t twiddleCoef_1024_q31[1536];
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extern const q31_t twiddleCoef_2048_q31[3072];
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extern const q31_t twiddleCoef_4096_q31[6144];
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extern const q15_t twiddleCoef_16_q15[24];
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extern const q15_t twiddleCoef_32_q15[48];
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extern const q15_t twiddleCoef_64_q15[96];
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extern const q15_t twiddleCoef_128_q15[192];
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extern const q15_t twiddleCoef_256_q15[384];
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extern const q15_t twiddleCoef_512_q15[768];
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extern const q15_t twiddleCoef_1024_q15[1536];
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extern const q15_t twiddleCoef_2048_q15[3072];
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extern const q15_t twiddleCoef_4096_q15[6144];
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extern const float32_t twiddleCoef_rfft_32[32];
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extern const float32_t twiddleCoef_rfft_64[64];
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extern const float32_t twiddleCoef_rfft_128[128];
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extern const float32_t twiddleCoef_rfft_256[256];
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extern const float32_t twiddleCoef_rfft_512[512];
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extern const float32_t twiddleCoef_rfft_1024[1024];
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extern const float32_t twiddleCoef_rfft_2048[2048];
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extern const float32_t twiddleCoef_rfft_4096[4096];
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/* floating-point bit reversal tables */
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#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
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#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
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#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
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#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
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#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
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#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
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#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
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#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
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#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
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extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
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/* fixed-point bit reversal tables */
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#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
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#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
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#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
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#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
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#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
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#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
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#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
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#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
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#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
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extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
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/* Tables for Fast Math Sine and Cosine */
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extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
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extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
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extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
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#endif /* ARM_COMMON_TABLES_H */
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+66
@@ -0,0 +1,66 @@
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/* ----------------------------------------------------------------------
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* Project: CMSIS DSP Library
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* Title: arm_const_structs.h
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* Description: Constant structs that are initialized for user convenience.
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* For example, some can be given as arguments to the arm_cfft_f32() function.
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*
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* $Date: 27. January 2017
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* $Revision: V.1.5.1
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*
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* Target Processor: Cortex-M cores
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* -------------------------------------------------------------------- */
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/*
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* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
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||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
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#ifndef _ARM_CONST_STRUCTS_H
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#define _ARM_CONST_STRUCTS_H
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#include "arm_math.h"
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#include "arm_common_tables.h"
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
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#endif
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+353
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/**************************************************************************//**
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* @file cmsis_compiler.h
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* @brief CMSIS compiler generic header file
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* @version V5.0.2
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* @date 13. February 2017
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******************************************************************************/
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/*
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* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
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*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
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|
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#ifndef __CMSIS_COMPILER_H
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#define __CMSIS_COMPILER_H
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#include <stdint.h>
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/*
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* ARM Compiler 4/5
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*/
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#if defined ( __CC_ARM )
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#include "cmsis_armcc.h"
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/*
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* ARM Compiler 6 (armclang)
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*/
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#include "cmsis_armclang.h"
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/*
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* GNU Compiler
|
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*/
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#elif defined ( __GNUC__ )
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#include "cmsis_gcc.h"
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/*
|
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* IAR Compiler
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*/
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#elif defined ( __ICCARM__ )
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#ifndef __ASM
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#define __ASM __asm
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||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static inline
|
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#endif
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#include <cmsis_iar.h>
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|
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/* CMSIS compiler control architecture macros */
|
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#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
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#ifndef __ARM_ARCH_6M__
|
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#define __ARM_ARCH_6M__ 1
|
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#endif
|
||||
#elif (__CORE__ == __ARM7M__)
|
||||
#ifndef __ARM_ARCH_7M__
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#elif (__CORE__ == __ARM7EM__)
|
||||
#ifndef __ARM_ARCH_7EM__
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __noreturn
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __root
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
__packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
//#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
//#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
// Workaround for missing __CLZ intrinsic in
|
||||
// various versions of the IAR compilers.
|
||||
// __IAR_FEATURE_CLZ__ should be defined by
|
||||
// the compiler that supports __CLZ internally.
|
||||
#if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
|
||||
__STATIC_INLINE uint32_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0u) { return 32u; }
|
||||
|
||||
uint32_t count = 0;
|
||||
uint32_t mask = 0x80000000;
|
||||
|
||||
while ((data & mask) == 0)
|
||||
{
|
||||
count += 1u;
|
||||
mask = mask >> 1u;
|
||||
}
|
||||
|
||||
return (count);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TI ARM Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
+1979
File diff suppressed because it is too large
Load Diff
+39
@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
+1878
File diff suppressed because it is too large
Load Diff
+2902
File diff suppressed because it is too large
Load Diff
+888
File diff suppressed because it is too large
Load Diff
+1021
File diff suppressed because it is too large
Load Diff
+1878
File diff suppressed because it is too large
Load Diff
+1928
File diff suppressed because it is too large
Load Diff
+2898
File diff suppressed because it is too large
Load Diff
+2113
File diff suppressed because it is too large
Load Diff
+2655
File diff suppressed because it is too large
Load Diff
+1016
File diff suppressed because it is too large
Load Diff
+1903
File diff suppressed because it is too large
Load Diff
+182
@@ -0,0 +1,182 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for ARMv7 MPU
|
||||
* @version V5.0.2
|
||||
* @date 09. June 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
|
||||
|
||||
#define ARM_MPU_AP_NONE 0u
|
||||
#define ARM_MPU_AP_PRIV 1u
|
||||
#define ARM_MPU_AP_URO 2u
|
||||
#define ARM_MPU_AP_FULL 3u
|
||||
#define ARM_MPU_AP_PRO 5u
|
||||
#define ARM_MPU_AP_RO 6u
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos))
|
||||
|
||||
/**
|
||||
* MPU Region Attribut and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
((DisableExec << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
((AccessPermission << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
((TypeExtField << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
((IsShareable << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
((IsCacheable << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
((IsBufferable << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
|
||||
((SubRegionDisable << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
((Size << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
((1UL << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct _ARM_MPU_Region_t {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable()
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0u;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0u; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u);
|
||||
}
|
||||
|
||||
#endif
|
||||
+69
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 21. September 2016
|
||||
* $Revision: V1.0
|
||||
*
|
||||
* Project: TrustZone for ARMv8-M
|
||||
* Title: Context Management for ARMv8-M TrustZone
|
||||
*
|
||||
* Version 1.0
|
||||
* Initial Release
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
+678
File diff suppressed because it is too large
Load Diff
+16
@@ -0,0 +1,16 @@
|
||||
/**************************************************************************//**
|
||||
* @file NuMicro.h
|
||||
* @version V1.00
|
||||
* @brief NuMicro peripheral access layer header file.
|
||||
*
|
||||
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NUMICRO_H__
|
||||
#define __NUMICRO_H__
|
||||
|
||||
#include "M2351.h"
|
||||
|
||||
#endif /* __NUMICRO_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
||||
|
||||
+263
@@ -0,0 +1,263 @@
|
||||
/**************************************************************************//**
|
||||
* @file acmp_reg.h
|
||||
* @version V1.00
|
||||
* @brief ACMP register definition header file
|
||||
*
|
||||
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __ACMP_REG_H__
|
||||
#define __ACMP_REG_H__
|
||||
|
||||
/** @addtogroup REGISTER Control Register
|
||||
|
||||
@{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------- Analog Comparator Controller -------------------------*/
|
||||
/**
|
||||
@addtogroup ACMP Analog Comparator Controller(ACMP)
|
||||
Memory Mapped Structure for ACMP Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var ACMP_T::CTL
|
||||
* Offset: 0x00 Analog Comparator 0 Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ACMPEN |Comparator Enable Bit
|
||||
* | | |0 = Comparator 0 Disabled.
|
||||
* | | |1 = Comparator 0 Enabled.
|
||||
* | | |
|
||||
* |[1] |ACMPIE |Comparator Interrupt Enable Bit
|
||||
* | | |0 = Comparator 0 interrupt Disabled.
|
||||
* | | |1 = Comparator 0 interrupt Enabled
|
||||
* | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
|
||||
* | | |
|
||||
* |[2] |HYSEN |Comparator Hysteresis Enable Bit
|
||||
* | | |0 = Comparator 0 hysteresis Disabled.
|
||||
* | | |1 = Comparator 0 hysteresis Enabled.
|
||||
* | | |Note: If HYSEN = 0, user can adjust HYS by HYSSEL.
|
||||
* | | |Note: If HYSEN = 1, HYSSEL is invalid. The Hysteresis is fixed to 30mV.
|
||||
* |[3] |ACMPOINV |Comparator Output Inverse
|
||||
* | | |0 = Comparator 0 output inverse Disabled.
|
||||
* | | |1 = Comparator 0 output inverse Enabled.
|
||||
* | | |
|
||||
* |[5:4] |NEGSEL |Comparator Negative Input Selection
|
||||
* | | |00 = ACMP0_N pin.
|
||||
* | | |01 = Internal comparator reference voltage (CRV).
|
||||
* | | |10 = Band-gap voltage.
|
||||
* | | |11 = DAC output.
|
||||
* | | |
|
||||
* |[7:6] |POSSEL |Comparator Positive Input Selection
|
||||
* | | |00 = Input from ACMP0_P0.
|
||||
* | | |01 = Input from ACMP0_P1.
|
||||
* | | |10 = Input from ACMP0_P2.
|
||||
* | | |11 = Input from ACMP0_P3.
|
||||
* | | |
|
||||
* |[9:8] |INTPOL |Interrupt Condition Polarity Selection
|
||||
* | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
|
||||
* | | |00 = Rising edge or falling edge.
|
||||
* | | |01 = Rising edge.
|
||||
* | | |10 = Falling edge.
|
||||
* | | |11 = Reserved.
|
||||
* | | |
|
||||
* |[12] |OUTSEL |Comparator Output Select
|
||||
* | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
|
||||
* | | |1 = Comparator 0 output to ACMP0_O pin is from filter output.
|
||||
* | | |
|
||||
* |[15:13] |FILTSEL |Comparator Output Filter Count Selection
|
||||
* | | |000 = Filter function is Disabled.
|
||||
* | | |001 = ACMP0 output is sampled 1 consecutive PCLK.
|
||||
* | | |010 = ACMP0 output is sampled 2 consecutive PCLKs.
|
||||
* | | |011 = ACMP0 output is sampled 4 consecutive PCLKs.
|
||||
* | | |100 = ACMP0 output is sampled 8 consecutive PCLKs.
|
||||
* | | |101 = ACMP0 output is sampled 16 consecutive PCLKs.
|
||||
* | | |110 = ACMP0 output is sampled 32 consecutive PCLKs.
|
||||
* | | |111 = ACMP0 output is sampled 64 consecutive PCLKs.
|
||||
* | | |
|
||||
* |[16] |WKEN |Power-down Wake-up Enable Bit
|
||||
* | | |0 = Wake-up function Disabled.
|
||||
* | | |1 = Wake-up function Enabled.
|
||||
* | | |
|
||||
* |[17] |WLATEN |Window Latch Mode Enable Bit
|
||||
* | | |0 = Window Latch Mode Disabled.
|
||||
* | | |1 = Window Latch Mode Enabled.
|
||||
* | | |
|
||||
* |[18] |WCMPSEL |Window Compare Mode Selection
|
||||
* | | |0 = Window Compare Mode Disabled.
|
||||
* | | |1 = Window Compare Mode is Selected.
|
||||
* | | |
|
||||
* |[25:24] |HYSSEL |Hysteresis Mode Selection
|
||||
* | | |00 = Hysteresis is 0mV.
|
||||
* | | |01 = Hysteresis is 10mV.
|
||||
* | | |10 = Hysteresis is 20mV.
|
||||
* | | |11 = Hysteresis is 30mV.
|
||||
* | | |
|
||||
* |[29:28] |MODESEL |Propagation Delay Mode Selection
|
||||
* | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA.
|
||||
* | | |01 = Max propagation delay is 2uS, operation current is 3uA.
|
||||
* | | |10 = Max propagation delay is 600nS, operation current is 10uA.
|
||||
* | | |11 = Max propagation delay is 200nS, operation current is 75uA.
|
||||
* | | |
|
||||
|
||||
* @var ACMP_T::STATUS
|
||||
* Offset: 0x08 Analog Comparator Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
|
||||
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output
|
||||
* | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
|
||||
* | | |Note: Write 1 to clear this bit to 0.
|
||||
* | | |
|
||||
* |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
|
||||
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output
|
||||
* | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
|
||||
* | | |Note: Write 1 to clear this bit to 0.
|
||||
* | | |
|
||||
* |[4] |ACMPO0 |Comparator 0 Output
|
||||
* | | |Synchronized to the PCLK to allow reading by software
|
||||
* | | |Cleared when the comparator 0 is disabled, i.e
|
||||
* | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
|
||||
* | | |
|
||||
* |[5] |ACMPO1 |Comparator 1 Output
|
||||
* | | |Synchronized to the PCLK to allow reading by software
|
||||
* | | |Cleared when the comparator 1 is disabled, i.e
|
||||
* | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
|
||||
* | | |
|
||||
* |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag
|
||||
* | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
|
||||
* | | |0 = No power-down wake-up occurred.
|
||||
* | | |1 = Power-down wake-up occurred.
|
||||
* | | |Note: Write 1 to clear this bit to 0.
|
||||
* | | |
|
||||
* |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag
|
||||
* | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
|
||||
* | | |0 = No power-down wake-up occurred.
|
||||
* | | |1 = Power-down wake-up occurred.
|
||||
* | | |Note: Write 1 to clear this bit to 0.
|
||||
* | | |
|
||||
* |[12] |ACMPS0 |Comparator 0 Status
|
||||
* | | |Synchronized to the PCLK to allow reading by software
|
||||
* | | |Cleared when the comparator 0 is disabled, i.e
|
||||
* | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
|
||||
* |[13] |ACMPS1 |Comparator 1 Status
|
||||
* | | |Synchronized to the PCLK to allow reading by software
|
||||
* | | |Cleared when the comparator 1 is disabled, i.e
|
||||
* | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
|
||||
* |[16] |ACMPWO |Comparator Window Output
|
||||
* | | |This bit shows the output status of window compare mode
|
||||
* | | |0 = The positive input voltage is outside the window.
|
||||
* | | |1 = The positive input voltage is in the window.
|
||||
* | | |
|
||||
* @var ACMP_T::VREF
|
||||
* Offset: 0x0C Analog Comparator Reference Voltage Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |CRVCTL |Comparator Reference Voltage Setting
|
||||
* | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
|
||||
* | | |
|
||||
* |[6] |CRVSSEL |CRV Source Voltage Selection
|
||||
* | | |0 = VDDA is selected as CRV source voltage.
|
||||
* | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
|
||||
* | | |
|
||||
*/
|
||||
__IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0~1 Control Register */
|
||||
__IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */
|
||||
__IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */
|
||||
|
||||
} ACMP_T;
|
||||
|
||||
/**
|
||||
@addtogroup ACMP_CONST ACMP Bit Field Definition
|
||||
Constant Definitions for ACMP Controller
|
||||
@{ */
|
||||
|
||||
#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
|
||||
#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
|
||||
|
||||
#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
|
||||
#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
|
||||
|
||||
#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */
|
||||
#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */
|
||||
|
||||
#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
|
||||
#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
|
||||
|
||||
#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
|
||||
#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
|
||||
|
||||
#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
|
||||
#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
|
||||
|
||||
#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
|
||||
#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
|
||||
|
||||
#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
|
||||
#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
|
||||
|
||||
#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
|
||||
#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
|
||||
|
||||
#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
|
||||
#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
|
||||
|
||||
#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */
|
||||
#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */
|
||||
|
||||
#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */
|
||||
#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */
|
||||
|
||||
#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */
|
||||
#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */
|
||||
|
||||
#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */
|
||||
#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
|
||||
#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
|
||||
#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
|
||||
#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
|
||||
#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
|
||||
|
||||
#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
|
||||
#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
|
||||
|
||||
#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
|
||||
#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */
|
||||
#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */
|
||||
#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */
|
||||
#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */
|
||||
|
||||
#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
|
||||
#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
|
||||
|
||||
#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
|
||||
#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
|
||||
|
||||
/**@}*/ /* ACMP_CONST */
|
||||
/**@}*/ /* end of ACMP register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#endif /* __ACMP_REG_H__ */
|
||||
+1797
File diff suppressed because it is too large
Load Diff
+787
File diff suppressed because it is too large
Load Diff
+1542
File diff suppressed because it is too large
Load Diff
+150
@@ -0,0 +1,150 @@
|
||||
/**************************************************************************//**
|
||||
* @file crc_reg.h
|
||||
* @version V1.00
|
||||
* @brief CRC register definition header file
|
||||
*
|
||||
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __CRC_REG_H__
|
||||
#define __CRC_REG_H__
|
||||
|
||||
/** @addtogroup REGISTER Control Register
|
||||
|
||||
@{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
|
||||
/**
|
||||
@addtogroup CRC Cyclic Redundancy Check Controller(CRC)
|
||||
Memory Mapped Structure for CRC Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var CRC_T::CTL
|
||||
* Offset: 0x00 CRC Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CRCEN |CRC Channel Generator Enable Bit
|
||||
* | | |Set this bit 1 to enable CRC generator for CRC operation.
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = CRC operation generator is active.
|
||||
* |[1] |CHKSINIT |Checksum Initialization
|
||||
* | | |Set this bit will auto reload SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value.
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reload SEED value to CHECKSUM register as CRC operation initial checksum value.
|
||||
* | | |The others contents of CRC_CTL register will not be cleared.
|
||||
* | | |Note1: This bit will be cleared automatically
|
||||
* | | |Note2: Setting this bit will reload the seed value from CRC_SEED register as checksum initial value.
|
||||
* |[24] |DATREV |Write Data Bit Order Reverse Enable Bit
|
||||
* | | |This bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]) in CRC_DAT register.
|
||||
* | | |0 = Bit order reversed for CRC_DATA write data in Disabled.
|
||||
* | | |1 = Bit order reversed for CRC_DATA write data in Enabled (per byte).
|
||||
* | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
|
||||
* |[25] |CHKSREV |Checksum Bit Order Reverse Enable Bit
|
||||
* | | |This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).
|
||||
* | | |0 = Bit order reverse for CRC CHECKSUMCRC checksum Disabled.
|
||||
* | | |1 = Bit order reverse for CRC CHECKSUMCRC checksum Enabled.
|
||||
* | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB.
|
||||
* |[26] |DATFMT |Write Data 1's Complement Enable Bit
|
||||
* | | |This bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0]).
|
||||
* | | |0 = 1's complement for CRC_DATA writes data in Disabled.
|
||||
* | | |1 = 1's complement for CRC_DATA writes data in Enabled.
|
||||
* |[27] |CHKSFMT |Checksum 1's Complement Enable Bit
|
||||
* | | |This bit is used to enable the 1's complement function for checksum result in CHECKSUM (CRC_CHECKSUM[31:0]) register.
|
||||
* | | |0 = 1's complement for CRC CHECKSUM Disabled.
|
||||
* | | |1 = 1's complement for CRC CHECKSUMCRC Enabled.
|
||||
* |[29:28] |DATLEN |CPU Write Data Length
|
||||
* | | |This field indicates the valid write data length of DATA (CRC_DAT[31:0]).
|
||||
* | | |00 = Data length is 8-bit mode.
|
||||
* | | |01 = Data length is 16-bit mode.
|
||||
* | | |1x = Data length is 32-bit mode.
|
||||
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
|
||||
* |[31:30] |CRCMODE |CRC Polynomial Mode
|
||||
* | | |This field indicates the CRC operation polynomial mode.
|
||||
* | | |00 = CRC-CCITT Polynomial mode.
|
||||
* | | |01 = CRC-8 Polynomial mode.
|
||||
* | | |10 = CRC-16 Polynomial mode.
|
||||
* | | |11 = CRC-32 Polynomial mode.
|
||||
* @var CRC_T::DAT
|
||||
* Offset: 0x04 CRC Write Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |DATA |CRC Write Data Bits
|
||||
* | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
|
||||
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
|
||||
* @var CRC_T::SEED
|
||||
* Offset: 0x08 CRC Seed Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |SEED |CRC Seed Value
|
||||
* | | |This field indicates the CRC seed value.
|
||||
* | | |Note1: This field SEED value will be reloaded to as checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) register) after perform CRC engine reset, CHKSINIT (CRC_CTL[1]) to 1.
|
||||
* | | |Note2: The valid bits of CRC_SEED[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
|
||||
* @var CRC_T::CHECKSUM
|
||||
* Offset: 0x0C CRC Checksum Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |CHECKSUM |CRC Checksum Results
|
||||
* | | |This field indicates the CRC checksum result.
|
||||
* | | |Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] CRC Control Register */
|
||||
__IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */
|
||||
__IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */
|
||||
__I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */
|
||||
|
||||
} CRC_T;
|
||||
|
||||
/**
|
||||
@addtogroup CRC_CONST CRC Bit Field Definition
|
||||
Constant Definitions for CRC Controller
|
||||
@{ */
|
||||
|
||||
#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
|
||||
#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
|
||||
|
||||
#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */
|
||||
#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */
|
||||
|
||||
#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
|
||||
#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
|
||||
|
||||
#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
|
||||
#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
|
||||
|
||||
#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
|
||||
#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
|
||||
|
||||
#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
|
||||
#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
|
||||
|
||||
#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
|
||||
#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
|
||||
|
||||
#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
|
||||
#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
|
||||
|
||||
#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
|
||||
#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
|
||||
|
||||
#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
|
||||
#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
|
||||
|
||||
#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
|
||||
#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
|
||||
|
||||
/**@}*/ /* CRC_CONST */
|
||||
/**@}*/ /* end of CRC register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#endif /* __CLK_REG_H__ */
|
||||
+2188
File diff suppressed because it is too large
Load Diff
+205
@@ -0,0 +1,205 @@
|
||||
/**************************************************************************//**
|
||||
* @file dac_reg.h
|
||||
* @version V1.00
|
||||
* @brief DAC register definition header file
|
||||
*
|
||||
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __DAC_REG_H__
|
||||
#define __DAC_REG_H__
|
||||
|
||||
|
||||
/** @addtogroup REGISTER Control Register
|
||||
|
||||
@{
|
||||
|
||||
*/
|
||||
|
||||
/*---------------------- Digital to Analog Converter -------------------------*/
|
||||
/**
|
||||
@addtogroup DAC Digital to Analog Converter(DAC)
|
||||
Memory Mapped Structure for DAC Controller
|
||||
@{ */
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @var DAC_T::CTL
|
||||
* Offset: 0x00 DAC Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |DACEN |DAC Enable Bit
|
||||
* | | |0 = DAC is Disabled.
|
||||
* | | |1 = DAC is Enabled.
|
||||
* |[1] |DACIEN |DAC Interrupt Enable Bit
|
||||
* | | |0 = Interrupt is Disabled.
|
||||
* | | |1 = Interrupt is Enabled.
|
||||
* |[2] |DMAEN |DMA Mode Enable Bit
|
||||
* | | |0 = DMA mode Disabled.
|
||||
* | | |1 = DMA mode Enabled.
|
||||
* |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit
|
||||
* | | |0 = DMA under-run interrupt Disabled.
|
||||
* | | |1 = DMA under-run interrupt Enabled.
|
||||
* |[4] |TRGEN |Trigger Mode Enable Bit
|
||||
* | | |0 = DAC event trigger mode Disabled.
|
||||
* | | |1 = DAC event trigger mode Enabled.
|
||||
* |[7:5] |TRGSEL |Trigger Source Selection
|
||||
* | | |000 = Software trigger.
|
||||
* | | |001 = External pin DAC0_ST trigger.
|
||||
* | | |010 = Timer 0 trigger.
|
||||
* | | |011 = Timer 1 trigger.
|
||||
* | | |100 = Timer 2 trigger.
|
||||
* | | |101 = Timer 3 trigger.
|
||||
* | | |110 = EPWM0 trigger.
|
||||
* | | |111 = EPWM1 trigger.
|
||||
* |[8] |BYPASS |Bypass Buffer Mode
|
||||
* | | |0 = Output voltage buffer Enabled.
|
||||
* | | |1 = Output voltage buffer Disabled.
|
||||
* |[10] |LALIGN |DAC Data Left-aligned Enabled Control
|
||||
* | | |0 = Right alignment.
|
||||
* | | |1 = Left alignment.
|
||||
* |[13:12] |ETRGSEL |External Pin Trigger Selection
|
||||
* | | |00 = Low level trigger.
|
||||
* | | |01 = High level trigger.
|
||||
* | | |10 = Falling edge trigger.
|
||||
* | | |11 = Rising edge trigger.
|
||||
* |[15:14] |BWSEL |DAC Data Bit-width Selection
|
||||
* | | |00 = data is 12 bits.
|
||||
* | | |01 = data is 8 bits.
|
||||
* | | |Others = reserved.
|
||||
* |[16] |GRPEN |DAC Group Mode Enable Bit
|
||||
* | | |0 = DAC0 and DAC1 are not grouped.
|
||||
* | | |1 = DAC0 and DAC1 are grouped.
|
||||
* @var DAC_T::SWTRG
|
||||
* Offset: 0x04 DAC Software Trigger Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SWTRG |Software Trigger
|
||||
* | | |0 = Software trigger Disabled.
|
||||
* | | |1 = Software trigger Enabled.
|
||||
* | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
|
||||
* @var DAC_T::DAT
|
||||
* Offset: 0x08 DAC Data Holding Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |DACDAT |DAC 12-bit Holding Data
|
||||
* | | |These bits are written by user software which specifies 12-bit conversion data for DAC output.
|
||||
* | | |The unused bits (DACDAT[3:0] in left-alignment mode and DACDAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
|
||||
* | | |12 bit left alignment: user has to load data into DACDAT[15:4] bits.
|
||||
* | | |12 bit right alignment: user has to load data into DACDAT[11:0] bits.
|
||||
* @var DAC_T::DATOUT
|
||||
* Offset: 0x0C DAC Data Output Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[11:0] |DATOUT |DAC 12-bit Output Data
|
||||
* | | |These bits are current digital data for DAC output conversion.
|
||||
* | | |It is loaded from DAC_DAT register and user cannot write it directly.
|
||||
* @var DAC_T::STATUS
|
||||
* Offset: 0x10 DAC Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |FINISH |DAC Conversion Complete Finish Flag
|
||||
* | | |0 = DAC is in conversion state.
|
||||
* | | |1 = DAC conversion finish.
|
||||
* | | |This bit set to 1 when conversion time counter counts to SETTLET.
|
||||
* | | |It is cleared to 0 when DAC starts a new conversion.
|
||||
* | | |User writes 1 to clear this bit to 0.
|
||||
* |[1] |DMAUDR |DMA Under-run Interrupt Flag
|
||||
* | | |0 = No DMA under-run error condition occurred.
|
||||
* | | |1 = DMA under-run error condition occurred.
|
||||
* | | |User writes 1 to clear this bit.
|
||||
* |[8] |BUSY |DAC Busy Flag (Read Only)
|
||||
* | | |0 = DAC is ready for next conversion.
|
||||
* | | |1 = DAC is busy in conversion.
|
||||
* | | |This is read only bit.
|
||||
* @var DAC_T::TCTL
|
||||
* Offset: 0x14 DAC Timing Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[9:0] |SETTLET |DAC Output Settling Time
|
||||
* | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
|
||||
* | | |For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x40.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] DAC Control Register */
|
||||
__IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */
|
||||
__IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */
|
||||
__I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */
|
||||
__IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */
|
||||
__IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */
|
||||
|
||||
} DAC_T;
|
||||
|
||||
/**
|
||||
@addtogroup DAC_CONST DAC Bit Field Definition
|
||||
Constant Definitions for DAC Controller
|
||||
@{ */
|
||||
|
||||
#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
|
||||
#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
|
||||
|
||||
#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
|
||||
#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
|
||||
|
||||
#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
|
||||
#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
|
||||
|
||||
#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
|
||||
#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
|
||||
|
||||
#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
|
||||
#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
|
||||
|
||||
#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
|
||||
#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
|
||||
|
||||
#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
|
||||
#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
|
||||
|
||||
#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
|
||||
#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
|
||||
|
||||
#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
|
||||
#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
|
||||
|
||||
#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */
|
||||
#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */
|
||||
|
||||
#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */
|
||||
#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */
|
||||
|
||||
#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
|
||||
#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
|
||||
|
||||
#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */
|
||||
#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */
|
||||
|
||||
#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
|
||||
#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
|
||||
|
||||
#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
|
||||
#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
|
||||
|
||||
#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
|
||||
#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
|
||||
|
||||
#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
|
||||
#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
|
||||
|
||||
#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
|
||||
#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
|
||||
|
||||
/**@}*/ /* DAC_CONST */
|
||||
/**@}*/ /* end of DAC register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#endif /* __DAC_REG_H__ */
|
||||
+1704
File diff suppressed because it is too large
Load Diff
+153
@@ -0,0 +1,153 @@
|
||||
/**************************************************************************//**
|
||||
* @file ebi_reg.h
|
||||
* @version V1.00
|
||||
* @brief EBI register definition header file
|
||||
*
|
||||
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __EBI_REG_H__
|
||||
#define __EBI_REG_H__
|
||||
|
||||
/** @addtogroup REGISTER Control Register
|
||||
|
||||
@{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------- External Bus Interface Controller -------------------------*/
|
||||
/**
|
||||
@addtogroup EBI External Bus Interface Controller(EBI)
|
||||
Memory Mapped Structure for EBI Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var EBI_T::CTL0
|
||||
* Offset: 0x00 External Bus Interface Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |EN |EBI Enable Bit
|
||||
* | | |This bit is the functional enable bit for EBI.
|
||||
* | | |0 = EBI function Disabled.
|
||||
* | | |1 = EBI function Enabled.
|
||||
* |[1] |DW16 |EBI Data Width 16-bit Select
|
||||
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
|
||||
* | | |0 = EBI data width is 8-bit.
|
||||
* | | |1 = EBI data width is 16-bit.
|
||||
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
|
||||
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
|
||||
* | | |0 = Chip select pin (EBI_nCS) is active low.
|
||||
* | | |1 = Chip select pin (EBI_nCS) is active high.
|
||||
* |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
|
||||
* | | |0 = Address/Data Bus Separating Mode Disabled.
|
||||
* | | |1 = Address/Data Bus Separating Mode Enabled.
|
||||
* |[4] |CACCESS |Continuous Data Access Mode
|
||||
* | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
|
||||
* | | |0 = Continuous data access mode Disabled.
|
||||
* | | |1 = Continuous data access mode Enabled.
|
||||
* |[10:8] |MCLKDIV |External Output Clock Divider
|
||||
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
|
||||
* | | |000 = HCLK/1.
|
||||
* | | |001 = HCLK/2.
|
||||
* | | |010 = HCLK/4.
|
||||
* | | |011 = HCLK/8.
|
||||
* | | |100 = HCLK/16.
|
||||
* | | |101 = HCLK/32.
|
||||
* | | |110 = HCLK/64.
|
||||
* | | |111 = HCLK/128.
|
||||
* |[18:16] |TALE |Extend Time of ALE
|
||||
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
|
||||
* | | |tALE = (TALE+1)*EBI_MCLK.
|
||||
* | | |Note: This field only available in EBI_CTL0 register
|
||||
* @var EBI_T::TCTL0
|
||||
* Offset: 0x04 External Bus Interface Timing Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:3] |TACC |EBI Data Access Time
|
||||
* | | |TACC define data access time (tACC).
|
||||
* | | |tACC = (TACC+1) * EBI_MCLK.
|
||||
* |[10:8] |TAHD |EBI Data Access Hold Time
|
||||
* | | |TAHD define data access hold time (tAHD).
|
||||
* | | |tAHD = (TAHD+1) * EBI_MCLK.
|
||||
* |[15:12] |W2X |Idle Cycle After Write
|
||||
* | | |This field defines the number of W2X idle cycle.
|
||||
* | | |W2X idle cycle = (W2X * EBI_MCLK).
|
||||
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
|
||||
* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
|
||||
* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
|
||||
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
|
||||
* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
|
||||
* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
|
||||
* |[27:24] |R2R |Idle Cycle Between Read-to-read
|
||||
* | | |This field defines the number of R2R idle cycle.
|
||||
* | | |R2R idle cycle = (R2R * EBI_MCLK).
|
||||
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
|
||||
*/
|
||||
__IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
|
||||
__IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
|
||||
__I uint32_t RESERVE0[2];
|
||||
__IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
|
||||
__IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
|
||||
__I uint32_t RESERVE1[2];
|
||||
__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */
|
||||
__IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */
|
||||
|
||||
} EBI_T;
|
||||
|
||||
/**
|
||||
@addtogroup EBI_CONST EBI Bit Field Definition
|
||||
Constant Definitions for EBI Controller
|
||||
@{ */
|
||||
|
||||
#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
|
||||
#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
|
||||
|
||||
#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
|
||||
#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
|
||||
|
||||
#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
|
||||
#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
|
||||
|
||||
#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */
|
||||
#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */
|
||||
|
||||
#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */
|
||||
#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */
|
||||
|
||||
#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
|
||||
#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
|
||||
|
||||
#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
|
||||
#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
|
||||
|
||||
#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
|
||||
#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
|
||||
|
||||
#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
|
||||
#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
|
||||
|
||||
#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
|
||||
#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
|
||||
|
||||
#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
|
||||
#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
|
||||
|
||||
#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
|
||||
#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
|
||||
|
||||
#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
|
||||
#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
|
||||
|
||||
/**@}*/ /* EBI_CONST */
|
||||
/**@}*/ /* end of EBI register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
|
||||
#endif /* __EBI_REG_H__ */
|
||||
+384
@@ -0,0 +1,384 @@
|
||||
/**************************************************************************//**
|
||||
* @file ecap_reg.h
|
||||
* @version V1.00
|
||||
* @brief ECAP register definition header file
|
||||
*
|
||||
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __ECAP_REG_H__
|
||||
#define __ECAP_REG_H__
|
||||
|
||||
/** @addtogroup REGISTER Control Register
|
||||
|
||||
@{
|
||||
|
||||
*/
|
||||
|
||||
/*---------------------- Enhanced Input Capture Timer -------------------------*/
|
||||
/**
|
||||
@addtogroup ECAP Enhanced Input Capture Timer(ECAP)
|
||||
Memory Mapped Structure for ECAP Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @var ECAP_T::CNT
|
||||
* Offset: 0x00 Input Capture Counter (24-bit up counter)
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[23:0] |CNT |Input Capture Timer/Counter
|
||||
* | | |The input Capture Timer/Counter is a 24-bit up-counting counter
|
||||
* | | |The clock source for the counter is from the clock divider
|
||||
* @var ECAP_T::HLD0
|
||||
* Offset: 0x04 Input Capture Hold Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[23:0] |HOLD |Input Capture Counter Hold Register
|
||||
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
|
||||
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
|
||||
* @var ECAP_T::HLD1
|
||||
* Offset: 0x08 Input Capture Hold Register 1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[23:0] |HOLD |Input Capture Counter Hold Register
|
||||
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
|
||||
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
|
||||
* @var ECAP_T::HLD2
|
||||
* Offset: 0x0C Input Capture Hold Register 2
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[23:0] |HOLD |Input Capture Counter Hold Register
|
||||
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
|
||||
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
|
||||
* @var ECAP_T::CNTCMP
|
||||
* Offset: 0x10 Input Capture Compare Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[23:0] |CNTCMP |Input Capture Counter Compare Register
|
||||
* | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).
|
||||
* | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.
|
||||
* @var ECAP_T::CTL0
|
||||
* Offset: 0x14 Input Capture Control Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
|
||||
* | | |To determine the sampling frequency of the Noise Filter clock
|
||||
* | | |000 = CAP_CLK.
|
||||
* | | |001 = CAP_CLK/2.
|
||||
* | | |010 = CAP_CLK/4.
|
||||
* | | |011 = CAP_CLK/16.
|
||||
* | | |100 = CAP_CLK/32.
|
||||
* | | |101 = CAP_CLK/64.
|
||||
* |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control
|
||||
* | | |0 = Noise filter of Input Capture Enabled.
|
||||
* | | |1 = Noise filter of Input Capture Disabled (Bypass).
|
||||
* |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control
|
||||
* | | |0 = IC0 input to Input Capture Unit Disabled.
|
||||
* | | |1 = IC0 input to Input Capture Unit Enabled.
|
||||
* |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control
|
||||
* | | |0 = IC1 input to Input Capture Unit Disabled.
|
||||
* | | |1 = IC1 input to Input Capture Unit Enabled.
|
||||
* |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control
|
||||
* | | |0 = IC2 input to Input Capture Unit Disabled.
|
||||
* | | |1 = IC2 input to Input Capture Unit Enabled.
|
||||
* |[9:8] |CAPSEL0 |CAP0 Input Source Selection
|
||||
* | | |00 = CAP0 input is from port pin ICAP0.
|
||||
* | | |01 = Reserved.
|
||||
* | | |10 = CAP0 input is from signal CHA of QEI controller unit n.
|
||||
* | | |11 = Reserved.
|
||||
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
|
||||
* |[11:10] |CAPSEL1 |CAP1 Input Source Selection
|
||||
* | | |00 = CAP1 input is from port pin ICAP1.
|
||||
* | | |01 = Reserved.
|
||||
* | | |10 = CAP1 input is from signal CHB of QEI controller unit n.
|
||||
* | | |11 = Reserved.
|
||||
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
|
||||
* |[13:12] |CAPSEL2 |CAP2 Input Source Selection
|
||||
* | | |00 = CAP2 input is from port pin ICAP2.
|
||||
* | | |01 = Reserved.
|
||||
* | | |10 = CAP2 input is from signal CHX of QEI controller unit n.
|
||||
* | | |11 = Reserved.
|
||||
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
|
||||
* |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control
|
||||
* | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.
|
||||
* | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.
|
||||
* |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control
|
||||
* | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.
|
||||
* | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.
|
||||
* |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control
|
||||
* | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.
|
||||
* | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.
|
||||
* |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control
|
||||
* | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.
|
||||
* | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.
|
||||
* |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control
|
||||
* | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.
|
||||
* | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.
|
||||
* |[24] |CNTEN |Input Capture Counter Start Counting Control
|
||||
* | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
|
||||
* | | |0 = ECAP_CNT stop counting.
|
||||
* | | |1 = ECAP_CNT starts up-counting.
|
||||
* |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control
|
||||
* | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.
|
||||
* | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.
|
||||
* | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
|
||||
* |[28] |CMPEN |Compare Function Enable Control
|
||||
* | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
|
||||
* | | |0 = The compare function Disabled.
|
||||
* | | |1 = The compare function Enabled.
|
||||
* |[29] |CAPEN |Input Capture Timer/Counter Enable Control
|
||||
* | | |0 = Input Capture function Disabled.
|
||||
* | | |1 = Input Capture function Enabled.
|
||||
* @var ECAP_T::CTL1
|
||||
* Offset: 0x18 Input Capture Control Register 1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection
|
||||
* | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change
|
||||
* | | |00 = Detect rising edge only.
|
||||
* | | |01 = Detect falling edge only.
|
||||
* | | |1x = Detect both rising and falling edge.
|
||||
* |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection
|
||||
* | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change
|
||||
* | | |00 = Detect rising edge only.
|
||||
* | | |01 = Detect falling edge only.
|
||||
* | | |1x = Detect both rising and falling edge.
|
||||
* |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection
|
||||
* | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes
|
||||
* | | |00 = Detect rising edge only.
|
||||
* | | |01 = Detect falling edge only.
|
||||
* | | |1x = Detect both rising and falling edge.
|
||||
* |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit
|
||||
* | | |0 = The reload triggered by Event CAPTE0 Disabled.
|
||||
* | | |1 = The reload triggered by Event CAPTE0 Enabled.
|
||||
* |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit
|
||||
* | | |0 = The reload triggered by Event CAPTE1 Disabled.
|
||||
* | | |1 = The reload triggered by Event CAPTE1 Enabled.
|
||||
* |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit
|
||||
* | | |0 = The reload triggered by Event CAPTE2 Disabled.
|
||||
* | | |1 = The reload triggered by Event CAPTE2 Enabled.
|
||||
* |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit
|
||||
* | | |0 = The reload triggered by CAPOV Disabled.
|
||||
* | | |1 = The reload triggered by CAPOV Enabled.
|
||||
* |[14:12] |CLKSEL |Capture Timer Clock Divide Selection
|
||||
* | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
|
||||
* | | |000 = CAP_CLK/1.
|
||||
* | | |001 = CAP_CLK/4.
|
||||
* | | |010 = CAP_CLK/16.
|
||||
* | | |011 = CAP_CLK/32.
|
||||
* | | |100 = CAP_CLK/64.
|
||||
* | | |101 = CAP_CLK/96.
|
||||
* | | |110 = CAP_CLK/112.
|
||||
* | | |111 = CAP_CLK/128.
|
||||
* |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection
|
||||
* | | |Select the capture timer/counter clock source.
|
||||
* | | |00 = CAP_CLK (default).
|
||||
* | | |01 = CAP0.
|
||||
* | | |10 = CAP1.
|
||||
* | | |11 = CAP2.
|
||||
* |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control
|
||||
* | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.
|
||||
* | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.
|
||||
* |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control
|
||||
* | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.
|
||||
* | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.
|
||||
* |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control
|
||||
* | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.
|
||||
* | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.
|
||||
* @var ECAP_T::STATUS
|
||||
* Offset: 0x1C Input Capture Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag
|
||||
* | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.
|
||||
* | | |0 = No valid edge change has been detected at CAP0 input since last clear.
|
||||
* | | |1 = At least a valid edge change has been detected at CAP0 input since last clear.
|
||||
* | | |Note: This bit is only cleared by writing 1 to it.
|
||||
* |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag
|
||||
* | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.
|
||||
* | | |0 = No valid edge change has been detected at CAP1 input since last clear.
|
||||
* | | |1 = At least a valid edge change has been detected at CAP1 input since last clear.
|
||||
* | | |Note: This bit is only cleared by writing 1 to it.
|
||||
* |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag
|
||||
* | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.
|
||||
* | | |0 = No valid edge change has been detected at CAP2 input since last clear.
|
||||
* | | |1 = At least a valid edge change has been detected at CAP2 input since last clear.
|
||||
* | | |Note: This bit is only cleared by writing 1 to it.
|
||||
* |[4] |CAPCMPF |Input Capture Compare-match Flag
|
||||
* | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.
|
||||
* | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.
|
||||
* | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.
|
||||
* | | |Note: This bit is only cleared by writing 1 to it.
|
||||
* |[5] |CAPOVF |Input Capture Counter Overflow Flag
|
||||
* | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
|
||||
* | | |0 = No overflow event has occurred since last clear.
|
||||
* | | |1 = Overflow event(s) has/have occurred since last clear.
|
||||
* | | |Note: This bit is only cleared by writing 1 to it.
|
||||
* |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only)
|
||||
* | | |Reflecting the value of input channel 0, CAP0
|
||||
* | | |(The bit is read only and write is ignored)
|
||||
* |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only)
|
||||
* | | |Reflecting the value of input channel 1, CAP1
|
||||
* | | |(The bit is read only and write is ignored)
|
||||
* |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only)
|
||||
* | | |Reflecting the value of input channel 2, CAP2.
|
||||
* | | |(The bit is read only and write is ignored)
|
||||
*/
|
||||
__IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */
|
||||
__IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */
|
||||
__IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */
|
||||
__IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */
|
||||
__IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */
|
||||
__IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */
|
||||
__IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */
|
||||
__IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */
|
||||
|
||||
} ECAP_T;
|
||||
|
||||
/**
|
||||
@addtogroup ECAP_CONST ECAP Bit Field Definition
|
||||
Constant Definitions for ECAP Controller
|
||||
@{ */
|
||||
|
||||
#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */
|
||||
#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */
|
||||
|
||||
#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */
|
||||
#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */
|
||||
|
||||
#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */
|
||||
#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */
|
||||
|
||||
#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */
|
||||
#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */
|
||||
|
||||
#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */
|
||||
#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */
|
||||
|
||||
#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */
|
||||
#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */
|
||||
|
||||
#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */
|
||||
#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */
|
||||
|
||||
#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */
|
||||
#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */
|
||||
|
||||
#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */
|
||||
#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */
|
||||
|
||||
#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */
|
||||
#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */
|
||||
|
||||
#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */
|
||||
#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */
|
||||
|
||||
#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */
|
||||
#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */
|
||||
|
||||
#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */
|
||||
#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */
|
||||
|
||||
#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */
|
||||
#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */
|
||||
|
||||
#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */
|
||||
#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */
|
||||
|
||||
#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */
|
||||
#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */
|
||||
|
||||
#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */
|
||||
#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */
|
||||
|
||||
#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */
|
||||
#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */
|
||||
|
||||
#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */
|
||||
#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */
|
||||
|
||||
#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */
|
||||
#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */
|
||||
|
||||
#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */
|
||||
#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */
|
||||
|
||||
#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */
|
||||
#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */
|
||||
|
||||
#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */
|
||||
#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */
|
||||
|
||||
#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */
|
||||
#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */
|
||||
|
||||
#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */
|
||||
#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */
|
||||
|
||||
#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */
|
||||
#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */
|
||||
|
||||
#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */
|
||||
#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */
|
||||
|
||||
#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */
|
||||
#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */
|
||||
|
||||
#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */
|
||||
#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */
|
||||
|
||||
#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */
|
||||
#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */
|
||||
|
||||
#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */
|
||||
#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */
|
||||
|
||||
#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */
|
||||
#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */
|
||||
|
||||
#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */
|
||||
#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */
|
||||
|
||||
#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */
|
||||
#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */
|
||||
|
||||
#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */
|
||||
#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */
|
||||
|
||||
#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */
|
||||
#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */
|
||||
|
||||
#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */
|
||||
#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */
|
||||
|
||||
#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */
|
||||
#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */
|
||||
|
||||
#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */
|
||||
#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */
|
||||
|
||||
#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */
|
||||
#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */
|
||||
|
||||
#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */
|
||||
#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */
|
||||
|
||||
#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */
|
||||
#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */
|
||||
|
||||
/**@}*/ /* ECAP_CONST */
|
||||
/**@}*/ /* end of ECAP register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
|
||||
#endif /* __ECAP_REG_H__ */
|
||||
+3732
File diff suppressed because it is too large
Load Diff
+728
File diff suppressed because it is too large
Load Diff
+962
File diff suppressed because it is too large
Load Diff
+111
@@ -0,0 +1,111 @@
|
||||
/**************************************************************************//**
|
||||
* @file hdiv_reg.h
|
||||
* @version V1.00
|
||||
* @brief HDIV register definition header file
|
||||
*
|
||||
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __HDIV_REG_H__
|
||||
#define __HDIV_REG_H__
|
||||
|
||||
/** @addtogroup REGISTER Control Register
|
||||
|
||||
@{
|
||||
|
||||
*/
|
||||
|
||||
/*---------------------- Hardware Divider --------------------------------*/
|
||||
/**
|
||||
@addtogroup HDIV Hardware Divider(HDIV)
|
||||
Memory Mapped Structure for HDIV Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var HDIV_T::DIVIDEND
|
||||
* Offset: 0x00 Dividend Source Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |DIVIDEND |Dividend Source
|
||||
* | | |This register is given the dividend of divider before calculation starting.
|
||||
* @var HDIV_T::DIVISOR
|
||||
* Offset: 0x04 Divisor Source Resister
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |DIVISOR |Divisor Source
|
||||
* | | |This register is given the divisor of divider before calculation starts.
|
||||
* | | |Note: When this register is written, hardware divider will start calculate.
|
||||
* @var HDIV_T::DIVQUO
|
||||
* Offset: 0x08 Quotient Result Resister
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |QUOTIENT |Quotient Result
|
||||
* | | |This register holds the quotient result of divider after calculation complete.
|
||||
* @var HDIV_T::DIVREM
|
||||
* Offset: 0x0C Remainder Result Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |REMAINDER |Remainder Result
|
||||
* | | |The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete.
|
||||
* | | |The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer.
|
||||
* | | |This register holds the remainder result of divider after calculation complete.
|
||||
* @var HDIV_T::DIVSTS
|
||||
* Offset: 0x10 Divider Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |FINISH |Division Finish Flag
|
||||
* | | |0 = Under Calculation.
|
||||
* | | |1 = Calculation finished.
|
||||
* | | |The flag will become low when the divider is in calculation.
|
||||
* | | |The flag will go back to high once the calculation finished.
|
||||
* |[1] |DIV0 |Divisor Zero Warning
|
||||
* | | |0 = The divisor is not 0.
|
||||
* | | |1 = The divisor is 0.
|
||||
* | | |Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written
|
||||
* | | |This register is read only.
|
||||
*/
|
||||
__IO uint32_t DIVIDEND; /*!< [0x0000] Dividend Source Register */
|
||||
__IO uint32_t DIVISOR; /*!< [0x0004] Divisor Source Resister */
|
||||
__IO uint32_t DIVQUO; /*!< [0x0008] Quotient Result Resister */
|
||||
__IO uint32_t DIVREM; /*!< [0x000c] Remainder Result Register */
|
||||
__I uint32_t DIVSTS; /*!< [0x0010] Divider Status Register */
|
||||
|
||||
} HDIV_T;
|
||||
|
||||
/**
|
||||
@addtogroup HDIV_CONST HDIV Bit Field Definition
|
||||
Constant Definitions for HDIV Controller
|
||||
@{ */
|
||||
|
||||
#define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */
|
||||
#define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */
|
||||
|
||||
#define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */
|
||||
#define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */
|
||||
|
||||
#define HDIV_DIVQUO_QUOTIENT_Pos (0) /*!< HDIV_T::DIVQUO: QUOTIENT Position */
|
||||
#define HDIV_DIVQUO_QUOTIENT_Msk (0xfffffffful << HDIV_DIVQUO_QUOTIENT_Pos) /*!< HDIV_T::DIVQUO: QUOTIENT Mask */
|
||||
|
||||
#define HDIV_DIVREM_REMAINDER_Pos (0) /*!< HDIV_T::DIVREM: REMAINDER Position */
|
||||
#define HDIV_DIVREM_REMAINDER_Msk (0xfffffffful << HDIV_DIVREM_REMAINDER_Pos) /*!< HDIV_T::DIVREM: REMAINDER Mask */
|
||||
|
||||
#define HDIV_DIVSTS_FINISH_Pos (0) /*!< HDIV_T::DIVSTS: FINISH Position */
|
||||
#define HDIV_DIVSTS_FINISH_Msk (0x1ul << HDIV_DIVSTS_FINISH_Pos) /*!< HDIV_T::DIVSTS: FINISH Mask */
|
||||
|
||||
#define HDIV_DIVSTS_DIV0_Pos (1) /*!< HDIV_T::DIVSTS: DIV0 Position */
|
||||
#define HDIV_DIVSTS_DIV0_Msk (0x1ul << HDIV_DIVSTS_DIV0_Pos) /*!< HDIV_T::DIVSTS: DIV0 Mask */
|
||||
|
||||
/**@}*/ /* HDIV_CONST */
|
||||
/**@}*/ /* end of HDIV register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
|
||||
#endif /* __HDIV_REG_H__ */
|
||||
+714
File diff suppressed because it is too large
Load Diff
+700
File diff suppressed because it is too large
Load Diff
+394
@@ -0,0 +1,394 @@
|
||||
/**************************************************************************//**
|
||||
* @file otg_reg.h
|
||||
* @version V1.00
|
||||
* @brief OTG register definition header file
|
||||
*
|
||||
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __OTG_REG_H__
|
||||
#define __OTG_REG_H__
|
||||
|
||||
/** @addtogroup REGISTER Control Register
|
||||
|
||||
@{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------- USB On-The-Go Controller -------------------------*/
|
||||
/**
|
||||
@addtogroup OTG USB On-The-Go Controller(OTG)
|
||||
Memory Mapped Structure for OTG Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var OTG_T::CTL
|
||||
* Offset: 0x00 OTG Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |VBUSDROP |Drop VBUS Control
|
||||
* | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
|
||||
* | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
|
||||
* | | |0 = Not drop the VBUS.
|
||||
* | | |1 = Drop the VBUS.
|
||||
* |[1] |BUSREQ |OTG Bus Request
|
||||
* | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
|
||||
* | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power
|
||||
* | | |This bit will be cleared when A-device goes to A_wait_vfall state
|
||||
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
|
||||
* | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
|
||||
* | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues SRP in specified interval, defined in OTG specification)
|
||||
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
|
||||
* | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
|
||||
* | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
|
||||
* |[2] |HNPREQEN |OTG HNP Request Enable Bit
|
||||
* | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
|
||||
* | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
|
||||
* | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
|
||||
* | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
|
||||
* | | |0 = HNP request Disabled.
|
||||
* | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
|
||||
* | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
|
||||
* |[4] |OTGEN |OTG Function Enable Bit
|
||||
* | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device
|
||||
* | | |When USB frame not configured as OTG device, this bit is must be low.
|
||||
* | | |0= OTG function Disabled.
|
||||
* | | |1 = OTG function Enabled.
|
||||
* |[5] |WKEN |OTG ID Pin Wake-up Enable Bit
|
||||
* | | |0 = OTG ID pin status change wake-up function Disabled.
|
||||
* | | |1 = OTG ID pin status change wake-up function Enabled.
|
||||
* @var OTG_T::PHYCTL
|
||||
* Offset: 0x04 OTG PHY Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |OTGPHYEN |OTG PHY Enable Bit
|
||||
* | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function
|
||||
* | | |If device is not configured as OTG-device nor ID-dependent , this bit is "don't care".
|
||||
* | | |0 = OTG PHY Disabled.
|
||||
* | | |1 = OTG PHY Enabled.
|
||||
* |[1] |IDDETEN |ID Detection Enable Bit
|
||||
* | | |0 = Detect ID pin status Disabled.
|
||||
* | | |1 = Detect ID pin status Enabled.
|
||||
* |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity
|
||||
* | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
|
||||
* | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
|
||||
* | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
|
||||
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
|
||||
* | | |0 = The off-chip USB VBUS power switch enable is active high.
|
||||
* | | |1 = The off-chip USB VBUS power switch enable is active low.
|
||||
* |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity
|
||||
* | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
|
||||
* | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
|
||||
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
|
||||
* | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
|
||||
* | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
|
||||
* @var OTG_T::INTEN
|
||||
* Offset: 0x08 OTG Interrupt Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG specification.
|
||||
* |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* | | |Note: Going to idle state means going to a_idle or b_idle state
|
||||
* | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
|
||||
* |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
|
||||
* | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, an interrupt will be asserted.
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
|
||||
* | | |If this bit is set to 1 and the device is changed as a peripheral, an interrupt will be asserted.
|
||||
* | | |0 = This device as a peripheral interrupt Disabled.
|
||||
* | | |1 = This device as a peripheral interrupt Enabled.
|
||||
* |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
|
||||
* | | |If this bit is set to 1 and the device is changed as a host, an interrupt will be asserted.
|
||||
* | | |0 = This device as a host interrupt Disabled.
|
||||
* | | |1 = This device as a host interrupt Enabled.
|
||||
* |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
|
||||
* | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, an interrupt will be asserted.
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
|
||||
* | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, an interrupt will be asserted.
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit
|
||||
* | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, an interrupt will be asserted.
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
|
||||
* | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, an interrupt will be asserted.
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* @var OTG_T::INTSTS
|
||||
* Offset: 0x0C OTG Interrupt Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ROLECHGIF |OTG Role Change Interrupt Status
|
||||
* | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
|
||||
* | | |0 = OTG device role not changed.
|
||||
* | | |1 = OTG device role changed.
|
||||
* | | |Note: Write 1 to clear this flag.
|
||||
* |[1] |VBEIF |VBUS Error Interrupt Status
|
||||
* | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
|
||||
* | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
|
||||
* | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
|
||||
* | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
|
||||
* |[2] |SRPFIF |SRP Fail Interrupt Status
|
||||
* | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
|
||||
* | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
|
||||
* | | |0 = OTG B-device gets VBUS high before this interval.
|
||||
* | | |1 = OTG B-device does not get VBUS high before this interval.
|
||||
* | | |Note: Write 1 to clear this flag.
|
||||
* |[3] |HNPFIF |HNP Fail Interrupt Status
|
||||
* | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
|
||||
* | | |0 = A-device connects to B-device before specified interval expires.
|
||||
* | | |1 = A-device does not connect to B-device before specified interval expires.
|
||||
* | | |Note: Write 1 to clear this flag.
|
||||
* |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
|
||||
* | | |Flag is set if the OTG device transfers from non-idle state to idle state
|
||||
* | | |The OTG device will be neither a host nor a peripheral.
|
||||
* | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
|
||||
* | | |1 = OTG device goes back to idle state(a_idle or b_idle).
|
||||
* | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
|
||||
* | | |Note 2: Write 1 to clear this flag.
|
||||
* |[5] |IDCHGIF |ID State Change Interrupt Status
|
||||
* | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
|
||||
* | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
|
||||
* | | |Note: Write 1 to clear this flag.
|
||||
* |[6] |PDEVIF |Act As Peripheral Interrupt Status
|
||||
* | | |0= This device does not act as a peripheral.
|
||||
* | | |1 = This device acts as a peripheral.
|
||||
* | | |Note: Write 1 to clear this flag.
|
||||
* |[7] |HOSTIF |Act As Host Interrupt Status
|
||||
* | | |0= This device does not act as a host.
|
||||
* | | |1 = This device acts as a host.
|
||||
* | | |Note: Write 1 to clear this flag.
|
||||
* |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
|
||||
* | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
|
||||
* | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
|
||||
* | | |Note: Write 1 to clear this status.
|
||||
* |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
|
||||
* | | |0 = AVLD (OTG_STATUS[4]) not toggled.
|
||||
* | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
|
||||
* | | |Note: Write 1 to clear this status.
|
||||
* |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
|
||||
* | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
|
||||
* | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
|
||||
* | | |Note: Write 1 to clear this status.
|
||||
* |[11] |SECHGIF |SESSEND State Change Interrupt Status
|
||||
* | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
|
||||
* | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
|
||||
* | | |Note: Write 1 to clear this flag.
|
||||
* |[13] |SRPDETIF |SRP Detected Interrupt Status
|
||||
* | | |0 = SRP not detected.
|
||||
* | | |1 = SRP detected.
|
||||
* | | |Note: Write 1 to clear this status.
|
||||
* @var OTG_T::STATUS
|
||||
* Offset: 0x10 OTG Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |OVERCUR |Over Current Condition
|
||||
* | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
|
||||
* | | |0 = OTG A-device drives VBUS successfully.
|
||||
* | | |1 = OTG A-device cannot drives VBUS high in this interval.
|
||||
* |[1] |IDSTS |USB_ID Pin State of Mini-/Micro- Plug
|
||||
* | | |0 = Mini-A/Micro-A plug is attached.
|
||||
* | | |1 = Mini-B/Micro-B plug is attached.
|
||||
* |[2] |SESSEND |Session End Status
|
||||
* | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1
|
||||
* | | |Session end means no meaningful power on VBUS.
|
||||
* | | |0 = Session is not end.
|
||||
* | | |1 = Session is end.
|
||||
* |[3] |BVLD |B-device Session Valid Status
|
||||
* | | |0 = B-device session is not valid.
|
||||
* | | |1 = B-device session is valid.
|
||||
* |[4] |AVLD |A-device Session Valid Status
|
||||
* | | |0 = A-device session is not valid.
|
||||
* | | |1 = A-device session is valid.
|
||||
* |[5] |VBUSVLD |VBUS Valid Status
|
||||
* | | |When VBUS is larger than 4.7V, this bit will be set to 1.
|
||||
* | | |0 = VBUS is not valid.
|
||||
* | | |1 = VBUS is valid.
|
||||
* |[6] |ASPERI |As Peripheral Status
|
||||
* | | |When OTG as peripheral, this bit is set.
|
||||
* | | |0: OTG not as peripheral
|
||||
* | | |1: OTG as peripheral
|
||||
* |[7] |ASHOST |As Host Status
|
||||
* | | |When OTG as Host, this bit is set.
|
||||
* | | |0: OTG not as Host
|
||||
* | | |1: OTG as Host
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] OTG Control Register */
|
||||
__IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */
|
||||
__IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */
|
||||
__IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */
|
||||
__I uint32_t STATUS; /*!< [0x0010] OTG Status Register */
|
||||
|
||||
} OTG_T;
|
||||
|
||||
/**
|
||||
@addtogroup OTG_CONST OTG Bit Field Definition
|
||||
Constant Definitions for OTG Controller
|
||||
@{ */
|
||||
|
||||
#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */
|
||||
#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */
|
||||
|
||||
#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */
|
||||
#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */
|
||||
|
||||
#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */
|
||||
#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */
|
||||
|
||||
#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */
|
||||
#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */
|
||||
|
||||
#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */
|
||||
#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */
|
||||
|
||||
#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */
|
||||
#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */
|
||||
|
||||
#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */
|
||||
#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */
|
||||
|
||||
#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */
|
||||
#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */
|
||||
|
||||
#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */
|
||||
#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */
|
||||
|
||||
#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */
|
||||
#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */
|
||||
|
||||
#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */
|
||||
#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */
|
||||
|
||||
#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */
|
||||
#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */
|
||||
|
||||
#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */
|
||||
#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */
|
||||
|
||||
#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */
|
||||
#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */
|
||||
|
||||
#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */
|
||||
#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */
|
||||
|
||||
#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */
|
||||
#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */
|
||||
|
||||
#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */
|
||||
#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */
|
||||
|
||||
#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */
|
||||
#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */
|
||||
|
||||
#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */
|
||||
#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */
|
||||
|
||||
#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */
|
||||
#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */
|
||||
|
||||
#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */
|
||||
#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */
|
||||
|
||||
#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */
|
||||
#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */
|
||||
|
||||
#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */
|
||||
#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */
|
||||
|
||||
#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */
|
||||
#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */
|
||||
|
||||
#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */
|
||||
#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */
|
||||
|
||||
#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */
|
||||
#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */
|
||||
|
||||
#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */
|
||||
#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */
|
||||
|
||||
#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */
|
||||
#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */
|
||||
|
||||
#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */
|
||||
#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */
|
||||
|
||||
#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */
|
||||
#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */
|
||||
|
||||
#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */
|
||||
#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */
|
||||
|
||||
#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */
|
||||
#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */
|
||||
|
||||
#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */
|
||||
#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */
|
||||
|
||||
#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */
|
||||
#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */
|
||||
|
||||
#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */
|
||||
#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */
|
||||
|
||||
#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */
|
||||
#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */
|
||||
|
||||
#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */
|
||||
#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */
|
||||
|
||||
#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */
|
||||
#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */
|
||||
|
||||
#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */
|
||||
#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */
|
||||
|
||||
#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */
|
||||
#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */
|
||||
|
||||
#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */
|
||||
#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */
|
||||
|
||||
#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */
|
||||
#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */
|
||||
|
||||
#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */
|
||||
#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */
|
||||
|
||||
/**@}*/ /* OTG_CONST */
|
||||
/**@}*/ /* end of OTG register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
|
||||
|
||||
#endif /* __OTG_REG_H__ */
|
||||
+775
File diff suppressed because it is too large
Load Diff
+305
@@ -0,0 +1,305 @@
|
||||
/**************************************************************************//**
|
||||
* @file qei_reg.h
|
||||
* @version V1.00
|
||||
* @brief QEI register definition header file
|
||||
*
|
||||
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __QEI_REG_H__
|
||||
#define __QEI_REG_H__
|
||||
|
||||
/** @addtogroup REGISTER Control Register
|
||||
|
||||
@{
|
||||
|
||||
*/
|
||||
|
||||
/*---------------------- Quadrature Encoder Interface -------------------------*/
|
||||
/**
|
||||
@addtogroup QEI Quadrature Encoder Interface(QEI)
|
||||
Memory Mapped Structure for QEI Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var QEI_T::CNT
|
||||
* Offset: 0x00 QEI Counter Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |CNT |Quadrature Encoder Interface Counter
|
||||
* | | |A 32-bit up/down counter
|
||||
* | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF is zero
|
||||
* | | |This register performs an integrator which count value is proportional to the encoder position
|
||||
* | | |The pulse counter may be initialized to a predetermined value by one of three events occurs:
|
||||
* | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0.
|
||||
* | | |2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode.
|
||||
* | | |3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTL[27])=1.
|
||||
* @var QEI_T::CNTHOLD
|
||||
* Offset: 0x04 QEI Counter Hold Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold
|
||||
* | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register.
|
||||
* @var QEI_T::CNTLATCH
|
||||
* Offset: 0x08 QEI Counter Index Latch Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch
|
||||
* | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register.
|
||||
* @var QEI_T::CNTCMP
|
||||
* Offset: 0x0C QEI Counter Compare Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare
|
||||
* | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set
|
||||
* | | |This register is software writable.
|
||||
* @var QEI_T::CNTMAX
|
||||
* Offset: 0x14 QEI Pre-set Maximum Count Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count
|
||||
* | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode
|
||||
* @var QEI_T::CTL
|
||||
* Offset: 0x18 QEI Controller Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
|
||||
* | | |To determine the sampling frequency of the Noise Filter clock .
|
||||
* | | |000 = QEI_CLK.
|
||||
* | | |001 = QEI_CLK/2.
|
||||
* | | |010 = QEI_CLK/4.
|
||||
* | | |011 = QEI_CLK/16.
|
||||
* | | |100 = QEI_CLK/32.
|
||||
* | | |101 = QEI_CLK/64.
|
||||
* |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit
|
||||
* | | |0 = The noise filter of QEI controller Enabled.
|
||||
* | | |1 = The noise filter of QEI controller Disabled.
|
||||
* |[4] |CHAEN |QEA Input to QEI Controller Enable Bit
|
||||
* | | |0 = QEA input to QEI Controller Disabled.
|
||||
* | | |1 = QEA input to QEI Controller Enabled.
|
||||
* |[5] |CHBEN |QEB Input to QEI Controller Enable Bit
|
||||
* | | |0 = QEB input to QEI Controller Disabled.
|
||||
* | | |1 = QEB input to QEI Controller Enabled.
|
||||
* |[6] |IDXEN |IDX Input to QEI Controller Enable Bit
|
||||
* | | |0 = IDX input to QEI Controller Disabled.
|
||||
* | | |1 = IDX input to QEI Controller Enabled.
|
||||
* |[9:8] |MODE |QEI Counting Mode Selection
|
||||
* | | |There are four quadrature encoder pulse counter operation modes.
|
||||
* | | |00 = X4 Free-counting Mode.
|
||||
* | | |01 = X2 Free-counting Mode.
|
||||
* | | |10 = X4 Compare-counting Mode.
|
||||
* | | |11 = X2 Compare-counting Mode.
|
||||
* |[12] |CHAINV |Inverse QEA Input Polarity
|
||||
* | | |0 = Not inverse QEA input polarity.
|
||||
* | | |1 = QEA input polarity is inverse to QEI controller.
|
||||
* |[13] |CHBINV |Inverse QEB Input Polarity
|
||||
* | | |0 = Not inverse QEB input polarity.
|
||||
* | | |1 = QEB input polarity is inverse to QEI controller.
|
||||
* |[14] |IDXINV |Inverse IDX Input Polarity
|
||||
* | | |0 = Not inverse IDX input polarity.
|
||||
* | | |1 = IDX input polarity is inverse to QEI controller.
|
||||
* |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit
|
||||
* | | |0 = OVUNF can trigger QEI controller interrupt Disabled.
|
||||
* | | |1 = OVUNF can trigger QEI controller interrupt Enabled.
|
||||
* |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit
|
||||
* | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled.
|
||||
* | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled.
|
||||
* |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit
|
||||
* | | |0 = CMPF can trigger QEI controller interrupt Disabled.
|
||||
* | | |1 = CMPF can trigger QEI controller interrupt Enabled.
|
||||
* |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit
|
||||
* | | |0 = The IDXF can trigger QEI interrupt Disabled.
|
||||
* | | |1 = The IDXF can trigger QEI interrupt Enabled.
|
||||
* |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0
|
||||
* | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT.
|
||||
* | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1.
|
||||
* |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1
|
||||
* | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT.
|
||||
* | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1.
|
||||
* |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2
|
||||
* | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT.
|
||||
* | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1.
|
||||
* |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3
|
||||
* | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT.
|
||||
* | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1.
|
||||
* |[24] |HOLDCNT |Hold QEI_CNT Control
|
||||
* | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into QEI_CNTHOLD
|
||||
* | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
|
||||
* | | |0 = No operation.
|
||||
* | | |1 = QEI_CNT content is captured and stored in QEI_CNTHOLD.
|
||||
* | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
|
||||
* |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit
|
||||
* | | |If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX.
|
||||
* | | |0 = The index signal latch QEI counter function Disabled.
|
||||
* | | |1 = The index signal latch QEI counter function Enabled.
|
||||
* |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit
|
||||
* | | |When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF = 0).
|
||||
* | | |0 = Reload function Disabled.
|
||||
* | | |1 = QEI_CNT re-initialized by Index signal Enabled.
|
||||
* |[28] |CMPEN |the Compare Function Enable Bit
|
||||
* | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set.
|
||||
* | | |0 = Compare function Disabled.
|
||||
* | | |1 = Compare function Enabled.
|
||||
* |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit
|
||||
* | | |0 = QEI controller function Disabled.
|
||||
* | | |1 = QEI controller function Enabled.
|
||||
* @var QEI_T::STATUS
|
||||
* Offset: 0x2C QEI Controller Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |IDXF |IDX Detected Flag
|
||||
* | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
|
||||
* | | |0 = No rising edge detected on signal CHX.
|
||||
* | | |1 = A rising edge occurs on signal CHX.
|
||||
* | | |Note: This bit is only cleared by writing 1 to it.
|
||||
* |[1] |CMPF |Compare-match Flag
|
||||
* | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).
|
||||
* | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]).
|
||||
* | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]).
|
||||
* | | |Note: This bit is only cleared by writing 1 to it.
|
||||
* |[2] |OVUNF |QEI Counter Overflow or Underflow Flag
|
||||
* | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode
|
||||
* | | |Similarly, the flag is set wile QEI counter underflow from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).
|
||||
* | | |0 = No overflow or underflow occurs in QEI counter.
|
||||
* | | |1 = QEI counter occurs counting overflow or underflow.
|
||||
* | | |Note: This bit is only cleared by writing 1 to it.
|
||||
* |[3] |DIRCHGF |Direction Change Flag
|
||||
* | | |Flag is set by hardware while QEI counter counting direction is changed
|
||||
* | | |Software can clear this bit by writing 1 to it.
|
||||
* | | |0 = No change in QEI counter counting direction.
|
||||
* | | |1 = QEI counter counting direction is changed.
|
||||
* | | |Note: This bit is only cleared by writing 1 to it.
|
||||
* |[8] |DIRF |QEI Counter Counting Direction Indication
|
||||
* | | |0 = QEI Counter is in down-counting.
|
||||
* | | |1 = QEI Counter is in up-counting.
|
||||
* | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
|
||||
*/
|
||||
__IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */
|
||||
__IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */
|
||||
__IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */
|
||||
__IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */
|
||||
__I uint32_t RESERVE0[1];
|
||||
__IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */
|
||||
__IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */
|
||||
__I uint32_t RESERVE1[4];
|
||||
__IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */
|
||||
|
||||
} QEI_T;
|
||||
|
||||
/**
|
||||
@addtogroup QEI_CONST QEI Bit Field Definition
|
||||
Constant Definitions for QEI Controller
|
||||
@{ */
|
||||
|
||||
#define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */
|
||||
#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */
|
||||
|
||||
#define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */
|
||||
#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */
|
||||
|
||||
#define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */
|
||||
#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */
|
||||
|
||||
#define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */
|
||||
#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */
|
||||
|
||||
#define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */
|
||||
#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */
|
||||
|
||||
#define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */
|
||||
#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */
|
||||
|
||||
#define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */
|
||||
#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */
|
||||
|
||||
#define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */
|
||||
#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */
|
||||
|
||||
#define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */
|
||||
#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */
|
||||
|
||||
#define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */
|
||||
#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */
|
||||
|
||||
#define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */
|
||||
#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */
|
||||
|
||||
#define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */
|
||||
#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */
|
||||
|
||||
#define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */
|
||||
#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */
|
||||
|
||||
#define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */
|
||||
#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */
|
||||
|
||||
#define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */
|
||||
#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */
|
||||
|
||||
#define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */
|
||||
#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */
|
||||
|
||||
#define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */
|
||||
#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */
|
||||
|
||||
#define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */
|
||||
#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */
|
||||
|
||||
#define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */
|
||||
#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */
|
||||
|
||||
#define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */
|
||||
#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */
|
||||
|
||||
#define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */
|
||||
#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */
|
||||
|
||||
#define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */
|
||||
#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */
|
||||
|
||||
#define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */
|
||||
#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */
|
||||
|
||||
#define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */
|
||||
#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */
|
||||
|
||||
#define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */
|
||||
#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */
|
||||
|
||||
#define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */
|
||||
#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */
|
||||
|
||||
#define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */
|
||||
#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */
|
||||
|
||||
#define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */
|
||||
#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */
|
||||
|
||||
#define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */
|
||||
#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */
|
||||
|
||||
#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */
|
||||
#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */
|
||||
|
||||
#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */
|
||||
#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */
|
||||
|
||||
#define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */
|
||||
#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */
|
||||
|
||||
/**@}*/ /* QEI_CONST */
|
||||
/**@}*/ /* end of QEI register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
|
||||
#endif /* __QEI_REG_H__ */
|
||||
+585
File diff suppressed because it is too large
Load Diff
+1325
File diff suppressed because it is too large
Load Diff
+977
File diff suppressed because it is too large
Load Diff
+1245
File diff suppressed because it is too large
Load Diff
+525
File diff suppressed because it is too large
Load Diff
+788
File diff suppressed because it is too large
Load Diff
+2368
File diff suppressed because it is too large
Load Diff
+148
@@ -0,0 +1,148 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_M2351.h
|
||||
* @version V3.00
|
||||
* @brief System Setting Header File
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __SYSTEM_M2351_H__
|
||||
#define __SYSTEM_M2351_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Macro Definition */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#ifndef DEBUG_PORT
|
||||
# define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
|
||||
#endif
|
||||
|
||||
|
||||
/* Init ETM Interface Multi-function Pins */
|
||||
#define ETM_INIT() { \
|
||||
SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC0MFP_ETM_TRACE_Msk | SYS_GPC_MFPL_PC1MFP_ETM_TRACE_Msk | \
|
||||
SYS_GPC_MFPL_PC2MFP_ETM_TRACE_Msk | SYS_GPC_MFPL_PC3MFP_ETM_TRACE_Msk | \
|
||||
SYS_GPC_MFPL_PC4MFP_ETM_TRACE_Msk); \
|
||||
SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_ETM_TRACE_CLK | SYS_GPC_MFPL_PC1MFP_ETM_TRACE_DATA0 | \
|
||||
SYS_GPC_MFPL_PC2MFP_ETM_TRACE_DATA1 | SYS_GPC_MFPL_PC3MFP_ETM_TRACE_DATA2 | \
|
||||
SYS_GPC_MFPL_PC4MFP_ETM_TRACE_DATA3;}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
*
|
||||
* @details This is used to enable PLL to speed up booting at startup. Remove it will cause system using
|
||||
* default clock source (External crystal or internal 22.1184MHz IRC).
|
||||
* Enable this option will cause system booting in 72MHz(By XTAL) or 71.8848MHz(By IRC22M) according to
|
||||
* user configuration setting in CONFIG0
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
#define INIT_SYSCLK_AT_BOOTING
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define SYSCLK
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
|
||||
#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */
|
||||
#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */
|
||||
#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
|
||||
#define __HSI (48000000UL) /*!< PLL Output Clock Frequency */
|
||||
#define __HIRC48 (48000000UL) /*!< Internal 48M RC Oscillator Frequency */
|
||||
#define __LIRC32 (32000UL) /*!< Internal 32K RC Oscillator Frequency */
|
||||
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L)
|
||||
# if defined (__ICCARM__)
|
||||
# define __NONSECURE_ENTRY __cmse_nonsecure_entry
|
||||
# define __NONSECURE_ENTRY_WEAK __cmse_nonsecure_entry //__weak
|
||||
# define __NONSECURE_CALL __cmse_nonsecure_call
|
||||
# else
|
||||
# define __NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry))
|
||||
# define __NONSECURE_ENTRY_WEAK __attribute__((cmse_nonsecure_entry,weak))
|
||||
# define __NONSECURE_CALL __attribute__((cmse_nonsecure_call))
|
||||
# endif
|
||||
#else
|
||||
# define __NONSECURE_ENTRY
|
||||
# define __NONSECURE_ENTRY_WEAK
|
||||
# define __NONSECURE_CALL
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
|
||||
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
|
||||
extern uint32_t __PC(void); /*!< Return the current program counter value */
|
||||
|
||||
#if USE_ASSERT
|
||||
/**
|
||||
* @brief Assert Function
|
||||
*
|
||||
* @param[in] expr Expression to be evaluated
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details If the expression is false, an error message will be printed out
|
||||
* from debug port (UART0 or UART1).
|
||||
*/
|
||||
#define ASSERT_PARAM(expr) { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } }
|
||||
|
||||
void AssertError(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define ASSERT_PARAM(expr)
|
||||
#endif
|
||||
|
||||
#define assert_param(expr) ASSERT_PARAM(expr)
|
||||
|
||||
|
||||
/**
|
||||
* @brief System Initialization
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The necessary initialization of system.
|
||||
*/
|
||||
extern void SystemInit(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update the Variable SystemCoreClock
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to update the variable SystemCoreClock
|
||||
* and must be called whenever the core clock is changed.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
|
||||
|
||||
|
||||
#if (defined(__ICCARM__) && (__VER__ >= 7080000) && (__VER__ < 8020000))
|
||||
uint32_t __TZ_get_PSP_NS(void);
|
||||
void __TZ_set_PSP_NS(uint32_t topOfProcStack);
|
||||
int32_t __TZ_get_MSP_NS(void);
|
||||
void __TZ_set_MSP_NS(uint32_t topOfMainStack);
|
||||
uint32_t __TZ_get_PRIMASK_NS(void);
|
||||
void __TZ_set_PRIMASK_NS(uint32_t priMask);
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_M2351_H__ */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user