Mirrors_Framework/FreeRTOS
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS.git synced 2026-09-21 02:23:53 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

Core kernel files:

Browse Source 
+ Change how queues are allocated and deleted so only one pvPortMalloc() or vPortFree() is required in place of the previous 2.
+ Where the TCB is allocated in relation to the stack is now dependent on the stack growth direction.  The stack will not grow into the TCB.
+ Introduce the configAPPLICATION_ALLOCATED_HEAP constant to allow the application to provide the array used by heap_4.c as its heap.  This allows the application writer to use qualifiers on the array to, for example, force the memory into faster RAM.

Demo application:
+ Add demo for SAMA5D4 using IAR.
This commit is contained in:
Richard Barry
2014-10-08 20:31:14 +00:00
parent ee541a347d
commit 9e66637bec
196 changed files with 70548 additions and 72 deletions
Download Patch File Download Diff File Expand all files Collapse all files
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/board.h
+736
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/ads7843.h
+55
View File
@@ -0,0 +1,55 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for ADS7843 driver.
*/
#ifndef _ADS7843_
#define _ADS7843_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void ADS7843_Initialize( void ) ;
extern void ADS7843_Reset( void ) ;
extern void ADS7843_GetPosition( uint32_t *px_pos, uint32_t *py_pos ) ;
#endif /* #ifndef _ADS7843_H */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/bmp.h
+250
View File
@@ -0,0 +1,250 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
* \section Purpose
*
* Utility for BMP
*
*/
#ifndef BMP_H
#define BMP_H
/** BMP magic number ('BM'). */
#define BMP_TYPE 0x4D42
/** headerSize must be set to 40 */
#define BITMAPINFOHEADER 40
/*------------------------------------------------------------------------------
* Exported types
*------------------------------------------------------------------------------*/
/*
* In case of IAR EWARM use, we define an empty macro to turn useless GCC and MDK __attribute__ keyword
*/
#if defined __ICCARM__ || defined __CC_ARM || defined __GNUC__
# pragma pack( 1 )
#endif
/** BMP (Windows) File Header Format */
typedef struct _BMPFileHeader
{
/** signature, must be 4D42 hex */
uint16_t type;
/** size of BMP file in bytes (unreliable) */
uint32_t fileSize;
/** reserved, must be zero */
uint16_t reserved1;
/** reserved, must be zero */
uint16_t reserved2;
/** offset to start of image data in bytes */
uint32_t offset;
} BMPFileHeader;
/** BMP (Windows 2.x) Header */
typedef struct _BMP2XHeader
{
/** size of this header in bytes */
uint32_t size;
/** image width in pixels */
uint16_t width;
/** image height in pixels */
uint16_t height;
/** number of color planes */
uint16_t planes;
/** number of bits per pixel */
uint16_t bitsPerPixel;
} BMP2XHeader;
/** BMP (Windows 3.x) Header, 40 bytes */
typedef struct _BMP3XHeader
{
/** size of this header in bytes */
uint32_t size;
/** image width in pixels */
int32_t width;
/** image height in pixels */
int32_t height;
/** number of color planes */
uint16_t planes;
/** number of bits per pixel */
uint16_t bitsPerPixel;
/** Compression methods used */
uint32_t compression;
/** Size of bitmap in bytes */
uint32_t sizeOfBitmap;
/** horizontal resolution in pixels per meter */
int32_t xResolution;
/** vertical resolution in pixels per meter */
int32_t yResolution;
/** number of colors in the image */
uint32_t colorsUsed;
/** minimum number of important colors */
uint32_t colorsImportant;
} BMP3XHeader;
/** BMP (Windows 95, V4) Header, 108 bytes */
typedef struct _BMP4Header
{
/** size of this header in bytes */
uint32_t size;
/** image width in pixels */
int32_t width;
/** image height in pixels */
int32_t height;
/** number of color planes */
uint16_t planes;
/** number of bits per pixel */
uint16_t bitsPerPixel;
/** Compression methods used */
uint32_t compression;
/** Size of bitmap in bytes */
uint32_t sizeOfBitmap;
/** horizontal resolution in pixels per meter */
int32_t xResolution;
/** vertical resolution in pixels per meter */
int32_t yResolution;
/** number of colors in the image */
uint32_t colorsUsed;
/** minimum number of important colors */
uint32_t colorsImportant;
/** Mask identifying bits of red component */
uint32_t redMask;
/** Mask identifying bits of green component */
uint32_t greenMask;
/** Mask identifying bits of blue component */
uint32_t blueMask;
/** Mask identifying bits of alpha component */
uint32_t alphaMask;
/** Color space type */
uint32_t csType;
/** X coordinate of red endpoint */
int32_t redX;
/** Y coordinate of red endpoint */
int32_t redY;
/** Z coordinate of red endpoint */
int32_t redZ;
/** X coordinate of green endpoint */
int32_t greenX;
/** Y coordinate of green endpoint */
int32_t greenY;
/** Z coordinate of green endpoint */
int32_t greenZ;
/** X coordinate of blue endpoint */
int32_t blueX;
/** Y coordinate of blue endpoint */
int32_t blueY;
/** Z coordinate of blue endpoint */
int32_t blueZ;
/** Gamma red coordinate scale value */
uint32_t gammaRed;
/** Gamma green coordinate scale value */
uint32_t gammaGreen;
/** Gamma blue coordinate scale value */
uint32_t gammaBlue;
} BMP4Header;
/** BMP (Windows) Header Format */
typedef struct _BMPHeader
{
/* signature, must be 4D42 hex */
uint16_t type;
/* size of BMP file in bytes (unreliable) */
uint32_t fileSize;
/* reserved, must be zero */
uint16_t reserved1;
/* reserved, must be zero */
uint16_t reserved2;
/* offset to start of image data in bytes */
uint32_t offset;
/* size of BITMAPINFOHEADER structure, must be 40 */
uint32_t headerSize;
/* image width in pixels */
uint32_t width;
/* image height in pixels */
uint32_t height;
/* number of planes in the image, must be 1 */
uint16_t planes;
/* number of bits per pixel (1, 4, 8, 16, 24, 32) */
uint16_t bits;
/* compression type (0=none, 1=RLE-8, 2=RLE-4) */
uint32_t compression;
/* size of image data in bytes (including padding) */
uint32_t imageSize;
/* horizontal resolution in pixels per meter (unreliable) */
uint32_t xresolution;
/* vertical resolution in pixels per meter (unreliable) */
uint32_t yresolution;
/* number of colors in image, or zero */
uint32_t ncolours;
/* number of important colors, or zero */
uint32_t importantcolours;
} BMPHeader ; // GCC
#if defined __ICCARM__ || defined __CC_ARM || defined __GNUC__
# pragma pack()
#endif
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
extern uint8_t BMP_IsValid(void *file);
extern uint32_t BMP_GetFileSize(void *file);
extern uint8_t BMP_Decode(
void *file,
uint8_t*buffer,
uint32_t width,
uint32_t height,
unsigned char bpp);
extern void WriteBMPheader(uint32_t* pAddressHeader,
uint32_t bmpHSize,
uint32_t bmpVSize,
uint8_t bmpRgb,
uint8_t nbByte_Pixels);
extern void BMP_displayHeader(uint32_t* pAddressHeader);
extern void RGB565toBGR555(
uint8_t *fileSource,
uint8_t *fileDestination,
uint32_t width,
uint32_t height,
uint8_t bpp);
#endif //#ifndef BMP_H
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/board_lowlevel.h
+124
View File
@@ -0,0 +1,124 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for the low-level initialization function.
*
*/
#ifndef BOARD_LOWLEVEL_H
#define BOARD_LOWLEVEL_H
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void defaultSpuriousHandler( void );
extern void defaultFiqHandler( void );
extern void defaultIrqHandler( void );
/* Cortex-A5 core handlers */
/*
*/
extern void SYS_IrqHandler( void ) ;
extern void Spurious_handler( void ) ;
/* Peripherals handlers */
extern void SAIC0_Handler(void);
extern void ARM_IrqHandler(void);
extern void PIT_IrqHandler(void);
extern void WDT_IrqHandler(void);
extern void PIOD_IrqHandler(void);
extern void USART0_IrqHandler(void);
extern void USART1_IrqHandler(void);
extern void XDMAC0_IrqHandler(void);
extern void ICM_IrqHandler(void);
extern void PKCC_IrqHandler(void);
extern void SCI_IrqHandler(void);
extern void AES_IrqHandler(void);
extern void AESB_IrqHandler(void);
extern void TDES_IrqHandler(void);
extern void SHA_IrqHandler(void);
extern void MPDDRC_IrqHandler(void);
extern void H32MX_IrqHandler(void);
extern void H64MX_IrqHandler(void);
extern void VDEC_IrqHandler(void);
extern void SECUMOD_IrqHandler(void);
extern void MSADCC_IrqHandler(void);
extern void HSMC_IrqHandler(void);
extern void PIOA_IrqHandler(void);
extern void PIOB_IrqHandler(void);
extern void PIOC_IrqHandler(void);
extern void PIOE_IrqHandler(void);
extern void UART0_IrqHandler(void);
extern void UART1_IrqHandler(void);
extern void USART2_IrqHandler(void);
extern void USART3_IrqHandler(void);
extern void USART4_IrqHandler(void);
extern void TWI0_IrqHandler(void);
extern void TWI1_IrqHandler(void);
extern void TWI2_IrqHandler(void);
extern void HSMCI0_IrqHandler(void);
extern void HSMCI1_IrqHandler(void);
extern void SPI0_IrqHandler(void);
extern void SPI1_IrqHandler(void);
extern void SPI2_IrqHandler(void);
extern void TC0_IrqHandler(void);
extern void TC1_IrqHandler(void);
extern void TC2_IrqHandler(void);
extern void PWM_IrqHandler(void);
extern void ADC_IrqHandler(void);
extern void DBGU_IrqHandler(void);
extern void UHPHS_IrqHandler(void);
extern void UDPHS_IrqHandler(void);
extern void SSC0_IrqHandler(void);
extern void SSC1_IrqHandler(void);
extern void XDMAC1_IrqHandler(void);
extern void LCDC_IrqHandler(void);
extern void ISI_IrqHandler(void);
extern void TRNG_IrqHandler(void);
extern void GMAC0_IrqHandler(void);
extern void GMAC1_IrqHandler(void);
extern void AIC0_IrqHandler(void);
extern void SFC_IrqHandler(void);
extern void SECURAM_IrqHandler(void);
extern void CTB_IrqHandler(void);
extern void SMD_IrqHandler(void);
extern void TWI3_IrqHandler(void);
extern void CATB_IrqHandler(void);
extern void SFR_IrqHandler(void);
extern void AIC1_IrqHandler(void);
extern void SAIC1_IrqHandler(void);
extern void L2CC_IrqHandler(void);
extern void LowLevelInit( void ) ;
#endif /* BOARD_LOWLEVEL_H */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/board_memories.h
+53
View File
@@ -0,0 +1,53 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for memories configuration on board.
*
*/
#ifndef BOARD_MEMORIES_H
#define BOARD_MEMORIES_H
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void BOARD_RemapRom( void );
extern void BOARD_RemapRam( void );
extern void BOARD_ConfigureVddMemSel(uint8_t VddMemSel) ;
extern void BOARD_ConfigureDdram( void );
extern void BOARD_ConfigureSdram( void );
extern void BOARD_ConfigureNandFlash( uint8_t busWidth ) ;
extern void BOARD_ConfigureNorFlash( uint8_t busWidth ) ;
extern void BOARD_ConfigureLpDdram(void);
#endif /* #ifndef BOARD_MEMORIES_H */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/dbg_util.h
+66
View File
@@ -0,0 +1,66 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \section Purpose
*
* Implements DBG utility that uses DBGU and System tick to get byte or binary
* stream from DBGU console.
*/
#ifndef _DBG_UTIL_
#define _DBG_UTIL_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern uint8_t DbgReceiveByte(uint8_t * pByte,uint32_t timeOut);
extern uint32_t DbgReceiveBinary(uint8_t start,
uint32_t address,
uint32_t maxSize);
extern uint32_t DbgReceive1KXModem(uint8_t * pktBuffer,
uint32_t address,
uint32_t maxSize);
#endif /* _DBG_UTIL_ */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/dbgu_console.h
+56
View File
@@ -0,0 +1,56 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _DBGU_CONSOLE_
#define _DBGU_CONSOLE_
#include <stdint.h>
/** Console baudrate always using 115200. */
#define CONSOLE_BAUDRATE 115200
extern void DBGU_ConsoleUseDBGU(void);
extern void DBGU_ConsoleUseUSART0(void);
extern void DBGU_ConsoleUseUSART1(void);
extern void DBGU_ConsoleUseUSART3(void);
extern void DBGU_Configure( uint32_t dwBaudrate, uint32_t dwMasterClock ) ;
extern void DBGU_PutChar( uint8_t uc ) ;
extern uint32_t DBGU_GetChar( void ) ;
extern uint32_t DBGU_IsRxReady( void ) ;
extern void DBGU_DumpFrame( uint8_t* pucFrame, uint32_t dwSize ) ;
extern void DBGU_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, uint32_t dwAddress ) ;
extern uint32_t DBGU_GetInteger( uint32_t* pdwValue ) ;
extern uint32_t DBGU_GetIntegerMinMax( uint32_t* pdwValue, uint32_t dwMin, uint32_t dwMax ) ;
extern uint32_t DBGU_GetHexa32( uint32_t* pdwValue ) ;
#endif /* _DBGU_CONSOLE_ */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/gmacb.h
+112
View File
@@ -0,0 +1,112 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup gmacb_module Ethernet GMACB Driver
*@{
* Implement GEMAC PHY driver, that initialize the PHY to prepare for
* ethernet transfer.
*
* \section Usage
* -# EMAC related pins and Driver should be initialized at first.
* -# Initialize GMACB Driver instance by invoking GMACB_Init().
* -# Initialize PHY connected via GMACB_InitPhy(), PHY address is
* automatically adjusted by attempt to read.
* -# Perform PHY auto negotiate through GMACB_AutoNegotiate(), so
* connection established.
*
*
* Related files:\n
* \ref gmacb.h\n
* \ref gmacb.c\n
* \ref gmii.h.\n
*
*/
/**@}*/
#ifndef _GMACB_H
#define _GMACB_H
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Definitions
*---------------------------------------------------------------------------*/
/** The reset length setting for external reset configuration */
#define GMACB_RESET_LENGTH 0xD
/*---------------------------------------------------------------------------
* Types
*---------------------------------------------------------------------------*/
/** The DM9161 instance */
typedef struct _GMacb {
sGmacd *pGmacd; /**< Driver */
/** The retry & timeout settings */
uint32_t retryMax;
/** PHY address ( pre-defined by pins on reset ) */
uint8_t phyAddress;
} GMacb;
/*---------------------------------------------------------------------------
* Exported functions
*---------------------------------------------------------------------------*/
extern void GMACB_SetupTimeout(GMacb *pMacb, uint32_t toMax);
extern void GMACB_Init(GMacb *pMacb, sGmacd *pGmacd, uint8_t phyAddress);
extern uint8_t GMACB_InitPhy(GMacb *pMacb,
uint32_t mck,
const Pin *pResetPins,
uint32_t nbResetPins,
const Pin *pEmacPins,
uint32_t nbEmacPins);
extern uint8_t GMACB_AutoNegotiate(GMacb *pMacb);
extern uint8_t GMACB_GetLinkSpeed(GMacb *pMacb, uint8_t applySettings);
extern uint8_t GMACB_Send(GMacb *pMacb, void *pBuffer, uint32_t size);
extern uint32_t GMACB_Poll(GMacb *pMacb, uint8_t *pBuffer, uint32_t size);
extern void GMACB_DumpRegisters(GMacb *pMacb);
extern uint8_t GMACB_ResetPhy(GMacb *pMacb);
#endif // #ifndef _GMACB_H
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/gmacd.h
+198
View File
@@ -0,0 +1,198 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup gmacd_module
* @{
* Implement GMAC data transfer and PHY management functions.
*
* \section Usage
* -# Implement GMAC interrupt handler, which must invoke GMACD_Handler()
* to handle GMAC interrupt events.
* -# Implement sGmacd instance in application.
* -# Initialize the instance with GMACD_Init() and GMACD_InitTransfer(),
* so that GMAC data can be transmitted/received.
* -# Some management callbacks can be set by GMACD_SetRxCallback()
* and GMACD_SetTxWakeupCallback().
* -# Send ethernet packets using GMACD_Send(), GMACD_TxLoad() is used
* to check the free space in TX queue.
* -# Check and obtain received ethernet packets via GMACD_Poll().
*
* \sa \ref gmacb_module, \ref gmac_module
*
* Related files:\n
* \ref gmacd.c\n
* \ref gmacd.h.\n
*
* \defgroup gmacd_defines GMAC Driver Defines
* \defgroup gmacd_types GMAC Driver Types
* \defgroup gmacd_functions GMAC Driver Functions
*/
/**@}*/
#ifndef _GMACD_H_
#define _GMACD_H_
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Definitions
*---------------------------------------------------------------------------*/
/** \addtogroup gmacd_defines
@{*/
/** \addtogroup gmacd_buf_size GMACD Default Buffer Size
@{*/
#define GMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */
#define GMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */
/** @}*/
/** \addtogroup gmacd_rc GMACD Return Codes
@{*/
#define GMACD_OK 0 /**< Operation OK */
#define GMACD_TX_BUSY 1 /**< TX in progress */
#define GMACD_RX_NULL 1 /**< No data received */
/** Buffer size not enough */
#define GMACD_SIZE_TOO_SMALL 2
/** Parameter error, TX packet invalid or RX size too small */
#define GMACD_PARAM 3
/** Transter is not initialized */
#define GMACD_NOT_INITIALIZED 4
/** @}*/
/** @}*/
/*---------------------------------------------------------------------------
* Types
*---------------------------------------------------------------------------*/
/** \addtogroup gmacd_types
@{*/
/** RX callback */
typedef void (*fGmacdTransferCallback)(uint32_t status);
/** Wakeup callback */
typedef void (*fGmacdWakeupCallback)(void);
/**
* GMAC driver struct.
*/
typedef struct _GmacDriver {
/** Pointer to HW register base */
Gmac *pHw;
uint8_t *pTxBuffer;
/** Pointer to allocated RX buffer */
uint8_t *pRxBuffer;
/** Pointer to Rx TDs (must be 8-byte aligned) */
sGmacRxDescriptor *pRxD;
/** Pointer to Tx TDs (must be 8-byte aligned) */
sGmacTxDescriptor *pTxD;
/** Optional callback to be invoked once a frame has been received */
fGmacdTransferCallback fRxCb;
/** Optional callback to be invoked once several TD have been released */
fGmacdWakeupCallback fWakupCb;
/** Optional callback list to be invoked once TD has been processed */
fGmacdTransferCallback *fTxCbList;
/** RX TD list size */
uint16_t wRxListSize;
/** RX index for current processing TD */
uint16_t wRxI;
/** TX TD list size */
uint16_t wTxListSize;
/** Circular buffer head pointer by upper layer (buffer to be sent) */
uint16_t wTxHead;
/** Circular buffer tail pointer incremented by handlers (buffer sent) */
uint16_t wTxTail;
/** Number of free TD before wakeup callback is invoked */
uint8_t bWakeupThreshold;
/** HW ID */
uint8_t bId;
} sGmacd;
/** @}*/
/** \addtogroup gmacd_functions
@{*/
/*---------------------------------------------------------------------------
* GMAC Exported functions
*---------------------------------------------------------------------------*/
extern void GMACD_Handler(sGmacd *pGmacd );
extern void GMACD_Init(sGmacd *pGmacd,
Gmac *pHw,
uint8_t bID,
uint8_t enableCAF,
uint8_t enableNBC );
extern uint8_t GMACD_InitTransfer( sGmacd *pGmacd,
uint8_t *pRxBuffer,
sGmacRxDescriptor *pRxD,
uint16_t wRxSize,
uint8_t *pTxBuffer,
sGmacTxDescriptor *pTxD,
fGmacdTransferCallback *pTxCb,
uint16_t wTxSize);
extern void GMACD_Reset(sGmacd *pGmacd);
extern uint8_t GMACD_Send(sGmacd *pGmacd,
void *pBuffer,
uint32_t size,
fGmacdTransferCallback fTxCb );
extern uint32_t GMACD_TxLoad(sGmacd *pGmacd);
extern uint8_t GMACD_Poll(sGmacd * pGmacd,
uint8_t *pFrame,
uint32_t frameSize,
uint32_t *pRcvSize);
extern void GMACD_SetRxCallback(sGmacd * pGmacd, fGmacdTransferCallback fRxCb);
extern uint8_t GMACD_SetTxWakeupCallback(sGmacd * pGmacd,
fGmacdWakeupCallback fWakeup,
uint8_t bThreshold);
/** @}*/
#endif // #ifndef _GMACD_H_
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/gmii.h
+122
View File
@@ -0,0 +1,122 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _GMII_DEFINE_H
#define _GMII_DEFINE_H
//-----------------------------------------------------------------------------
/// Definitions
//-----------------------------------------------------------------------------
//IEEE defined Registers
#define GMII_BMCR 0x0 // Basic Mode Control Register
#define GMII_BMSR 0x1 // Basic Mode Status Register
#define GMII_PHYID1R 0x2 // PHY Idendifier Register 1
#define GMII_PHYID2R 0x3 // PHY Idendifier Register 2
#define GMII_ANAR 0x4 // Auto_Negotiation Advertisement Register
#define GMII_ANLPAR 0x5 // Auto_negotiation Link Partner Ability Register
#define GMII_ANER 0x6 // Auto-negotiation Expansion Register
#define GMII_ANNPR 0x7 // Auto-negotiation Next Page Register
#define GMII_ANLPNPAR 0x8 // Auto_negotiation Link Partner Next Page Ability Register
#define GMII_DRCR 0x10 // Digital Reserved Control Register
#define GMII_AFEC1R 0x11 // AFE Control 1 Register
#define GMII_RXERCR 0x15 // RXER Couter Register
#define GMII_OMSOR 0x16 // Operation Mode Strap Override Register
#define GMII_OMSSR 0x17 // Operation Mode Strap Status Register
#define GMII_ECR 0x18 // Expanded Control Register
#define GMII_ICSR 0x1B // Interrupt Control/Status Register
#define GMII_LCSR 0x1D // LinkMD® Control/Status Register
#define GMII_PC1R 0x1E // PHY Control 1 Register
#define GMII_PC2R 0x1F // PHY Control 2 Register
// PHY ID Identifier Register
#define GMII_LSB_MASK 0xF
// definitions: MII_PHYID1
#define GMII_OUI_MSB 0x0022
// definitions: MII_PHYID2
#define GMII_OUI_LSB 0x1560
// Basic Mode Control Register (BMCR)
// Bit definitions: MII_BMCR
#define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
#define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
#define GMII_SPEED_SELECT_LSB (1 << 13) // 1,0=1000Mbps 0,1=100Mbps; 0,0=10Mbps
#define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable
#define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation
#define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation
#define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation
#define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation
// Reserved 7 // Read as 0, ignore on write
#define GMII_SPEED_SELECT_MSB (1 << 6) //
// Reserved 5 to 0 // Read as 0, ignore on write
// Basic Mode Status Register (BMSR)
// Bit definitions: MII_BMSR
#define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable
#define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable
#define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable
#define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable
#define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable
// Reserved 10 to 9 // Read as 0, ignore on write
#define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15
// Reserved 7
#define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression
#define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete
#define GMII_REMOTE_FAULT (1 << 4) // Remote Fault
#define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability
#define GMII_LINK_STATUS (1 << 2) // Link Status
#define GMII_JABBER_DETECT (1 << 1) // Jabber Detect
#define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability
// Auto-negotiation Advertisement Register (ANAR)
// Auto-negotiation Link Partner Ability Register (ANLPAR)
// Bit definitions: MII_ANAR, MII_ANLPAR
#define GMII_NP (1 << 15) // Next page Indication
// Reserved 7
#define GMII_RF (1 << 13) // Remote Fault
// Reserved 12 // Write as 0, ignore on read
#define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner)
// 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device)
#define GMII_T4 (1 << 9) // 100BASE-T4 Support
#define GMII_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support
#define GMII_TX_HDX (1 << 7) // 100BASE-TX Support
#define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support
#define GMII_10_HDX (1 << 5) // 10BASE-T Support
// Selector 4 to 0 // Protocol Selection Bits
#define GMII_AN_IEEE_802_3 0x0001
#endif // #ifndef _MII_DEFINE_H
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/hamming.h
+64
View File
@@ -0,0 +1,64 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _HAMMING_
#define _HAMMING_
/*------------------------------------------------------------------------------
* Defines
*------------------------------------------------------------------------------*/
/**
* These are the possible errors when trying to verify a block of data encoded
* using a Hamming code:
*
* \section Errors
* - Hamming_ERROR_SINGLEBIT
* - Hamming_ERROR_ECC
* - Hamming_ERROR_MULTIPLEBITS
*/
/** A single bit was incorrect but has been recovered. */
#define Hamming_ERROR_SINGLEBIT 1
/** The original code has been corrupted. */
#define Hamming_ERROR_ECC 2
/** Multiple bits are incorrect in the data and they cannot be corrected. */
#define Hamming_ERROR_MULTIPLEBITS 3
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
extern void Hamming_Compute256x( const uint8_t* pucData, uint32_t dwSize, uint8_t* pucCode ) ;
extern uint8_t Hamming_Verify256x( uint8_t* pucData, uint32_t dwSize, const uint8_t* pucCode ) ;
#endif /* _HAMMING_ */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/iso7816_4.h
+87
View File
@@ -0,0 +1,87 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
/** \page
*
* \section Purpose
*
* Definition of methods for ISO7816 driver.
*
* \section Usage
*
* -# ISO7816_Init
* -# ISO7816_IccPowerOff
* -# ISO7816_XfrBlockTPDU_T0
* -# ISO7816_Escape
* -# ISO7816_RestartClock
* -# ISO7816_StopClock
* -# ISO7816_toAPDU
* -# ISO7816_Datablock_ATR
* -# ISO7816_SetDataRateandClockFrequency
* -# ISO7816_StatusReset
* -# ISO7816_cold_reset
* -# ISO7816_warm_reset
* -# ISO7816_Decode_ATR
*----------------------------------------------------------------------------*/
#ifndef ISO7816_4_H
#define ISO7816_4_H
/*------------------------------------------------------------------------------
* Constants Definition
*----------------------------------------------------------------------------*/
/** Size max of Answer To Reset */
#define ATR_SIZE_MAX 55
/** NULL byte to restart byte procedure */
#define ISO_NULL_VAL 0x60
/*------------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void ISO7816_Init( const Pin pPinIso7816RstMC );
extern void ISO7816_IccPowerOff(void);
extern uint16_t ISO7816_XfrBlockTPDU_T0(const uint8_t *pAPDU,
uint8_t *pMessage,
uint16_t wLength );
extern void ISO7816_Escape( void );
extern void ISO7816_RestartClock(void);
extern void ISO7816_StopClock( void );
extern void ISO7816_toAPDU( void );
extern void ISO7816_Datablock_ATR( uint8_t* pAtr, uint8_t* pLength );
extern void ISO7816_SetDataRateandClockFrequency( uint32_t dwClockFrequency, uint32_t dwDataRate );
extern uint8_t ISO7816_StatusReset( void );
extern void ISO7816_cold_reset( void );
extern void ISO7816_warm_reset( void );
extern void ISO7816_Decode_ATR( uint8_t* pAtr );
#endif /* ISO7816_4_H */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/lcd_color.h
+85
View File
@@ -0,0 +1,85 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef COLOR_H
#define COLOR_H
/**
* \file
*
* RGB 24-bits color table definition.
*
*/
/*
* RGB 24 Bpp
* RGB 888
* R7R6R5R4 R3R2R1R0 G7G6G5G4 G3G2G1G0 B7B6B5B4 B3B2B1B0
*/
#define COLOR_BLACK 0x000000
#define COLOR_WHITE 0xFFFFFF
#define COLOR_BLUE 0x0000FF
#define COLOR_GREEN 0x00FF00
#define COLOR_RED 0xFF0000
#define COLOR_NAVY 0x000080
#define COLOR_DARKBLUE 0x00008B
#define COLOR_DARKGREEN 0x006400
#define COLOR_DARKCYAN 0x008B8B
#define COLOR_CYAN 0x00FFFF
#define COLOR_TURQUOISE 0x40E0D0
#define COLOR_INDIGO 0x4B0082
#define COLOR_DARKRED 0x800000
#define COLOR_OLIVE 0x808000
#define COLOR_GRAY 0x808080
#define COLOR_SKYBLUE 0x87CEEB
#define COLOR_BLUEVIOLET 0x8A2BE2
#define COLOR_LIGHTGREEN 0x90EE90
#define COLOR_DARKVIOLET 0x9400D3
#define COLOR_YELLOWGREEN 0x9ACD32
#define COLOR_BROWN 0xA52A2A
#define COLOR_DARKGRAY 0xA9A9A9
#define COLOR_SIENNA 0xA0522D
#define COLOR_LIGHTBLUE 0xADD8E6
#define COLOR_GREENYELLOW 0xADFF2F
#define COLOR_SILVER 0xC0C0C0
#define COLOR_LIGHTGREY 0xD3D3D3
#define COLOR_LIGHTCYAN 0xE0FFFF
#define COLOR_VIOLET 0xEE82EE
#define COLOR_AZUR 0xF0FFFF
#define COLOR_BEIGE 0xF5F5DC
#define COLOR_MAGENTA 0xFF00FF
#define COLOR_TOMATO 0xFF6347
#define COLOR_GOLD 0xFFD700
#define COLOR_ORANGE 0xFFA500
#define COLOR_SNOW 0xFFFAFA
#define COLOR_YELLOW 0xFFFF00
#endif /* #define COLOR_H */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/lcd_draw.h
+108
View File
@@ -0,0 +1,108 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup lcdd_draw Drawing On LCD
*
* Interface for drawing function on LCD.
*
* \note Before drawing, <b>canvas</b> should be selected via
* LCDD_SelectCanvas(), or created by LCDD_CreateCanvas().
*
* Following functions can use:
* - Simple drawing:
* - LCDD_Fill()
* - LCDD_DrawPixel()
* - LCDD_ReadPixel()
* - LCDD_DrawLine()
* - LCDD_DrawRectangle(), LCDD_DrawFilledRectangle()
* - LCDD_DrawCircle(), LCDD_DrawFilledCircle()
* - LCDD_DrawImage()
* - String related:
* - LCDD_DrawString()
* - LCDD_GetStringSize()
*
* \sa \ref lcdd_module, \ref lcdd_font
*/
#ifndef DRAW_H
#define DRAW_H
/** \addtogroup lcdd_draw
*@{
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
#include "lcd_gimp_image.h"
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup lcdd_draw_func LCD Drawing Functions */
/** @{*/
extern void LCDD_Fill0( void ) ;
extern void LCDD_Fill( uint32_t color ) ;
extern void LCDD_DrawPixel( uint32_t x, uint32_t y, uint32_t c ) ;
extern uint32_t LCDD_ReadPixel( uint32_t x, uint32_t y ) ;
extern void LCDD_DrawLine( uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2, uint32_t color ) ;
extern void LCDD_DrawRectangle( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor ) ;
extern void LCDD_DrawFilledRectangle( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2, uint32_t dwColor ) ;
extern void LCDD_DrawCircle( uint32_t x, uint32_t y, uint32_t r, uint32_t color ) ;
extern void LCDD_DrawFilledCircle(uint32_t dwX,uint32_t dwY,uint32_t dwR,uint32_t dwColor);
extern void LCDD_DrawString( uint32_t x, uint32_t y, const char *pString, uint32_t color ) ;
extern void LCDD_DrawStringWithBGColor( uint32_t x, uint32_t y, const char *pString, uint32_t fontColor, uint32_t bgColor ) ;
extern void LCDD_GetStringSize( const char *pString, uint32_t *pWidth, uint32_t *pHeight ) ;
extern void LCDD_DrawImage( uint32_t x, uint32_t y, const uint8_t *pImage, uint32_t width, uint32_t height ) ;
void LCDD_DrawGIMPImage( uint32_t dwX, uint32_t dwY, const SGIMPImage* pGIMPImage, uint32_t dwWidth, uint32_t dwHeight ) ;
extern void LCDD_ClearWindow( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor ) ;
/** @}*/
/**@}*/
#endif /* #ifndef DRAW_H */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/lcd_font.h
+108
View File
@@ -0,0 +1,108 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for draw font on LCD.
*
*/
/**
* \addtogroup lcdd_font LCD Font Drawing
*
* \section Purpose
*
* The lcd_font.h files declares a font structure and a LCDD_DrawChar() function
* that must be implemented by a font definition file to be used with the
* LCDD_DrawString() method of draw.h.
*
* The font10x14.c implements the necessary variable and function for a 10x14
* font.
*
* \note Before drawing fonts, <b>canvas</b> should be selected via
* LCDD_SelectCanvas(), or created by LCDD_CreateCanvas().
*
* \section Usage
*
* -# Declare a gFont global variable with the necessary Font information.
* -# Implement an LCDD_DrawChar() function which displays the specified
* character on the LCD.
* -# Select or create canvas via LCDD_SelectCanvas() or LCDD_CreateCanvas().
* -# Use the LCDD_DrawString() method defined in draw.h to display a complete
* string.
*
* \sa \ref lcdd_module, \ref lcdd_draw.
*/
#ifndef _LCD_FONT_
#define _LCD_FONT_
/** \addtogroup lcdd_font
*@{
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \brief Describes the font (width, height, supported characters, etc.) used by
* the LCD driver draw API.
*/
typedef struct _Font {
/* Font width in pixels. */
uint8_t width;
/* Font height in pixels. */
uint8_t height;
} Font;
/*----------------------------------------------------------------------------
* Variables
*----------------------------------------------------------------------------*/
extern const Font gFont;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup lcdd_font_func Font Functions */
/** @{*/
extern void LCDD_DrawChar( uint32_t x, uint32_t y, uint8_t c, uint32_t color ) ;
extern void LCDD_DrawCharWithBGColor( uint32_t x, uint32_t y, uint8_t c, uint32_t fontColor, uint32_t bgColor );
/** @}*/
/**@}*/
#endif /* #ifndef LCD_FONT_ */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/lcd_font10x14.h
+50
View File
@@ -0,0 +1,50 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup lcdd_font
* @{
* \addtogroup font_10x14 Font 10x14
*/
/**@}*/
#ifndef _LCD_FONT_10x14_
#define _LCD_FONT_10x14_
/** \addtogroup font_10x14
* @{
*/
#include <stdint.h>
extern const uint8_t pCharset10x14[] ;
/** @}*/
#endif /* #ifdef _LCD_FONT_10x14_ */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/lcd_gimp_image.h
+43
View File
@@ -0,0 +1,43 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _GIMP_IMAGE_
#define _GIMP_IMAGE_
#include <stdint.h>
typedef struct _SGIMPImage
{
uint32_t dwWidth;
uint32_t dwHeight;
uint32_t dwBytes_per_pixel; /* 3:RGB, 4:RGBA */
uint8_t* pucPixel_data ;
} SGIMPImage ;
#endif // _GIMP_IMAGE_
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/lcdd.h
+194
View File
@@ -0,0 +1,194 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \ingroup lib_board
* \addtogroup lcdd_module LCD Driver
*
* \section Purpose
*
* Implement driver functions for LCD control and image display.
* - Implement basic LCD controler configuration.
* - Implement display functions for LCD layers.
* - Implement simple drawing functions.
* - Implement string display functions.
*
* \section lcdd_base_usage Usage
*
* Uses following functions for LCD basic configuration and displaying:
* -# Uses LCDD_Initialize() to initialize the controller and LCD.
* -# LCDD_On() and LCDD_Off() is used to turn LCD ON/OFF.
* -# LCDD_SetBacklight() is used to change LCD backlight level.
* -# To display a image (BMP format) on LCD, LCDD_ShowBMPRotated()
* LCDD_ShowBMPScaled() and LCDD_ShowBMP() can be used.
* -# To change configuration for an overlay layer, the following functions
* can use:
* -# LCDD_EnableLayer(), LCDD_IsLayerOn(): Turn ON/OFF layer, check status.
* -# LCDD_SetPosition(), LCDD_SetPrioty(), LCDD_EnableAlpha(),
* LCDD_SetAlpha(), LCDD_SetColorKeying(): Change display options.
* -# Shortcuts for layer display are as following:
* -# LCDD_ShowBase(), LCDD_StopBase()
* -# LCDD_ShowOvr1(), LCDD_StopOvr1()
* -# LCDD_ShowHeo(), LCDD_StopHeo()
* -# LCDD_ShowHcr(), LCDD_StopHcr()
* -# Drawing supporting fucntions, for drawing canvas:
* -# LCDD_CreateCanvas(): Create blank canvas on specified layer for
* drawing on
* -# LCDD_SelectCanvas(): Select a displayer as canvas to drawing on
* -# LCDD_GetCanvas(): Get current selected canvas layer
*
* For LCD drawing functions, refer to \ref lcdd_draw.
*
* For LCD string display, refer to \ref lcdd_font.
*
* @{
* \defgroup lcdd_base LCD Driver General Operations
* @{
* Implementation of LCD driver, Include LCD initialization,
* LCD on/off and LCD backlight control.
*
* \sa \ref lcdd_base_usage "LCD Driver General Usage"
* @}
* \defgroup lcdd_draw LCD Driver Simple Drawing
* @{
* @}
* \defgroup lcdd_font LCD Driver Font Display
* @{
* @}
* @}
*/
#ifndef LCDD_H
#define LCDD_H
/** \addtogroup lcdd_base
* @{
*/
/*----------------------------------------------------------------------------
* Defines
*----------------------------------------------------------------------------*/
/** \addtogroup lcdd_disp_id LCD display layers IDs
* @{
*/
/** LCD controller ID, no display, configuration ONLY */
#define LCDD_CONTROLLER 0
/** LCD base layer, display fixed size image */
#define LCDD_BASE 1
/** LCD Overlay 1 */
#define LCDD_OVR1 2
/** LCD Overlay 2 */
#define LCDD_OVR2 4
/** LCD HighEndOverlay, support resize */
#define LCDD_HEO 3
/** LCD Cursor, max size 128x128 */
#define LCDD_CUR 6
/** @}*/
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** LCD display layer information */
typedef struct _LcddLayer {
void* pBuffer; /**< Display image buffer */
uint16_t wImgW; /**< Display image width */
uint16_t wImgH; /**< Display image height */
uint8_t bMode; /**< Image bpp (16,24,32) for RGB mode */
uint8_t bLayer; /**< Layer ID */
} sLCDDLayer;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void LCDD_Initialize(void);
extern void LCDD_On(void);
extern void LCDD_Off(void);
extern void LCDD_SetBacklight (uint32_t step);
extern void LCDD_EnableLayer(uint8_t bLayer,uint8_t bEnDis);
extern uint8_t LCDD_IsLayerOn(uint8_t bLayer);
extern void LCDD_SetPosition(uint8_t bLayer,uint32_t x,uint32_t y);
extern void LCDD_SetPrioty(uint8_t bLayer,uint8_t bPri);
extern uint8_t LCDD_GetPrioty(uint8_t bLayer);
extern void LCDD_EnableAlpha(uint8_t bLayer,uint8_t bEnDisLA,uint8_t bEnDisGA);
extern void LCDD_SetAlpha(uint8_t bLayer, uint8_t bReverse, uint8_t bAlpha);
extern uint8_t LCDD_GetAlpha(uint8_t bLayer);
extern void LCDD_SetColorKeying(uint8_t bLayer,
uint8_t bDstSrc,
uint32_t dwColor,uint32_t dwMask);
extern void LCDD_DisableColorKeying(uint8_t bLayer);
extern void LCDD_SetCLUT(uint8_t bLayer,
uint32_t * pCLUT,
uint8_t bpp,uint8_t nbColors);
extern void LCDD_Refresh(uint8_t bLayer);
extern void *LCDD_ShowBMPRotated(uint8_t bLayer,
void * pBuffer,uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h,
uint32_t imgW,uint32_t imgH,
int16_t wRotate);
extern void *LCDD_ShowBMPScaled(uint8_t bLayer,
void * pBuffer,uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h,
uint32_t imgW,uint32_t imgH);
extern void *LCDD_ShowBMP(uint8_t bLayer,
void * pBuffer,uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h);
extern void *LCDD_ShowBase(void * pBuffer, uint8_t bpp, uint8_t bScanBottomUp);
extern void LCDD_StopBase(void);
extern void *LCDD_ShowOvr1(void * pBuffer, uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h);
extern void LCDD_StopOvr1(void);
extern void *LCDD_ShowHeo(void * pBuffer, uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h,
uint32_t memW,uint32_t memH);
extern void LCDD_StopHeo(void);
extern void *LCDD_ShowHcr(void * pBuffer, uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h);
extern void LCDD_StopHcr(void);
extern sLCDDLayer *LCDD_GetCanvas(void);
extern uint8_t LCDD_SelectCanvas(uint8_t bLayer);
extern void *LCDD_CreateCanvas(uint8_t bLayer,
void * pBuffer,uint8_t bBPP,
uint16_t wX,uint16_t wY,uint16_t wW,uint16_t wH);
extern void LCDD_Flush_CurrentCanvas(void);
/** @}*/
#endif /* #ifndef LCDD_H */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/led.h
+72
View File
@@ -0,0 +1,72 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \section Purpose
*
* Small set of functions for simple and portable LED usage.
*
* \section Usage
*
* -# Configure one or more LEDs using LED_Configure and
* LED_ConfigureAll.
* -# Set, clear and toggle LEDs using LED_Set, LED_Clear and
* LED_Toggle.
*
* LEDs are numbered starting from 0; the number of LEDs depend on the
* board being used. All the functions defined here will compile properly
* regardless of whether the LED is defined or not; they will simply
* return 0 when a LED which does not exist is given as an argument.
* Also, these functions take into account how each LED is connected on to
* board; thus, \ref LED_Set might change the level on the corresponding pin
* to 0 or 1, but it will always light the LED on; same thing for the other
* methods.
*/
#ifndef _LED_
#define _LED_
#include <stdint.h>
//------------------------------------------------------------------------------
// Global Functions
//------------------------------------------------------------------------------
extern uint32_t LED_Configure( uint32_t dwLed ) ;
extern uint32_t LED_Set( uint32_t dwLed ) ;
extern uint32_t LED_Clear( uint32_t dwLed ) ;
extern uint32_t LED_Toggle( uint32_t dwLed ) ;
#endif /* #ifndef LED_H */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/math.h
+43
View File
@@ -0,0 +1,43 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _MATH_
#define _MATH_
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
extern uint32_t min( uint32_t dwA, uint32_t dwB ) ;
extern uint32_t absv( int32_t lValue ) ;
extern uint32_t power( uint32_t dwX, uint32_t dwY ) ;
#endif /* #ifndef _MATH_ */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/mcid.h
+172
View File
@@ -0,0 +1,172 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \ingroup sdmmc_hal
* \addtogroup mcid_module MCI Driver (HAL for SD/MMC Lib)
*
* \section Purpose
*
* This driver implements SD(IO)/MMC command operations and MCI configuration
* routines to perform SD(IO)/MMC access. It's used for upper layer
* (\ref libsdmmc_module "SD/MMC driver") to perform SD/MMC operations.
*
* \section Usage
*
* -# MCID_Init(): Initializes a MCI driver instance and the underlying
* peripheral.
* -# MCID_SendCmd(): Starts a MCI transfer which described by
* \ref sSdmmcCommand.
* -# MCID_CancelCmd(): Cancel a pending command.
* -# MCID_IsCmdCompleted(): Check if MCI transfer is finished.
* -# MCID_Handler(): Interrupt handler which is called by ISR handler.
* -# MCID_IOCtrl(): IO control function to report HW attributes to upper
* layer driver and modify HW settings (such as clock
* frequency, High-speed support, etc. See
* \ref sdmmc_ioctrls).
*
* \sa \ref dmad_module "DMA Driver", \ref hsmci_module "HSMCI",
* \ref libsdmmc_module "SD/MMC Library"
*
* Related files:\n
* \ref mcid.h\n
* \ref mcid_dma.c.\n
*/
#ifndef MCID_H
#define MCID_H
/** \addtogroup mcid_module
*@{
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include <stdint.h>
#include <stdio.h>
/** \addtogroup mcid_defines MCI Driver Defines
* @{*/
/*----------------------------------------------------------------------------
* Constants
*----------------------------------------------------------------------------*/
/** MCI States */
#define MCID_IDLE 0 /**< Idle */
#define MCID_LOCKED 1 /**< Locked for specific slot */
#define MCID_CMD 2 /**< Processing the command */
#define MCID_ERROR 3 /**< Command error */
/** MCI Initialize clock 400K Hz */
#define MCI_INITIAL_SPEED 400000
/** @}*/
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \addtogroup mcid_structs MCI Driver Data Structs
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief MCI Driver
*/
typedef struct _Mcid
{
/** Pointer to a MCI peripheral. */
Hsmci *pMciHw;
/** Pointer to a DMA driver */
sXdmad *pXdmad;
/** Pointer to currently executing command. */
void *pCmd;
/** MCK source, Hz */
uint32_t dwMck;
/** DMA transfer channel */
uint32_t dwDmaCh;
/** DMA transferred data index (bytes) */
uint32_t dwXfrNdx;
/** DMA transfer size (bytes) */
uint32_t dwXSize;
/** MCI peripheral identifier. */
uint8_t bID;
/** Polling mode */
uint8_t bPolling;
/** Reserved */
uint8_t reserved;
/** state. */
volatile uint8_t bState;
} sMcid;
/** @}*/
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup mcid_functions MCI Driver Functions
@{*/
extern void MCID_Init(sMcid * pMcid,
Hsmci * pMci, uint8_t bID, uint32_t dwMck,
sXdmad * pXdmad,
uint8_t bPolling);
extern void MCID_Reset(sMcid * pMcid);
extern void MCID_SetSlot(Hsmci *pMci, uint8_t slot);
extern uint32_t MCID_Lock(sMcid * pMcid, uint8_t bSlot);
extern uint32_t MCID_Release(sMcid * pMcid);
extern void MCID_Handler(sMcid * pMcid);
extern uint32_t MCID_SendCmd(sMcid * pMcid, void * pCmd);
extern uint32_t MCID_CancelCmd(sMcid * pMcid);
extern uint32_t MCID_IsCmdCompleted(sMcid * pMcid);
extern uint32_t MCID_IOCtrl(sMcid * pMcid,uint32_t bCtl,uint32_t param);
#ifdef __cplusplus
}
#endif
/** @}*/
/**@}*/
#endif //#ifndef HSMCID_H
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/omnivision.h
+74
View File
@@ -0,0 +1,74 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef OMNIVISION_H
#define OMNIVISION_H
/*---------------------------------------------------------------------------
* TYPE
*---------------------------------------------------------------------------*/
/** define a structure for ovxxxx register initialization values */
struct ov_reg
{
/* Register to be written */
uint16_t reg;
/* Value to be written in the register */
uint8_t val;
};
/*---------------------------------------------------------------------------
* DEFINITAION
*---------------------------------------------------------------------------*/
#define OV_2640 0x00
#define OV_2643 0x01
#define OV_5640 0x02
#define OV_7740 0x03
#define OV_9740 0x04
#define OV_UNKNOWN 0xFF
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint8_t ov_init(Twid *pTwid);
extern void ov_DumpRegisters8(Twid *pTwid);
extern void ov_DumpRegisters16(Twid *pTwid);
extern uint32_t ov_write_regs8(Twid *pTwid, const struct ov_reg* pReglist);
extern uint32_t ov_write_regs16(Twid *pTwid, const struct ov_reg* pReglist);
extern uint8_t ov_read_reg8(Twid *pTwid, uint8_t reg, uint8_t *pData);
extern uint8_t ov_read_reg16(Twid *pTwid, uint16_t reg, uint8_t *pData);
extern uint8_t ov_write_reg8(Twid *pTwid, uint8_t reg, uint8_t val);
extern uint8_t ov_write_reg16(Twid *pTwid, uint16_t reg, uint8_t val);
extern void isOV5640_AF_InitDone(Twid *pTwid);
extern uint32_t ov_5640_AF_single(Twid *pTwid);
extern uint32_t ov_5640_AF_continue(Twid *pTwid);
extern uint32_t ov_5640_AFPause(Twid *pTwid);
extern uint32_t ov_5640_AFrelease(Twid *pTwid);
#endif
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/ov.h
+50
View File
@@ -0,0 +1,50 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef OV_H
#define OV_H
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** Captor capture size */
struct capture_size {
uint32_t width;
uint32_t height;
};
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void ov_configure(Twid *pTwid, uint8_t type, uint32_t width, uint32_t heigth);
extern void ov_5640Afc_Firmware(Twid *pTwid);
#endif
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/ovyuv.h
+58
View File
@@ -0,0 +1,58 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _YUV_H_
#define _YUV_H_
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Exported variable
*---------------------------------------------------------------------------*/
extern const struct ov_reg ov2640_yuv_vga[];
extern const struct ov_reg ov2640_yuv_qvga[];
extern const struct ov_reg ov2643_yuv_vga[];
extern const struct ov_reg ov2643_yuv_swvga[];
extern const struct ov_reg ov2643_yuv_uxga[];
extern const struct ov_reg ov5640_yuv_vga[];
extern const struct ov_reg ov5640_yuv_sxga[];
extern const struct ov_reg ov5640_afc[];
extern const struct ov_reg ov7740_yuv_vga[];
extern const struct ov_reg ov9740_yuv_sxga[];
extern const struct ov_reg ov9740_yuv_vga[];
#endif // #ifndef _YUV_H_
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/qt1070.h
+155
View File
@@ -0,0 +1,155 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implementation QT1070 driver.
*
*/
#ifndef QT1070_H
#define QT1070_H
#include "board.h"
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/** Slave address */
#define QT1070_SLAVE_ADDRESS 0x1B
/** Internal Register Address Allocation */
/** Chip ID register*/
#define QT1070_CHIP_ID 0
/** Firmware version register*/
#define QT1070_REG_FIRMWARE_VERSION 1
/** Detection status*/
#define QT1070_REG_DETECTION_STATUS 2
/** Key status*/
#define QT1070_REG_KEY_STATUS 3
/** Key signal */
#define QT1070_REG_KEY0_SIGNAL_MSB 4
#define QT1070_REG_KEY0_SIGNAL_LSB 5
#define QT1070_REG_KEY1_SIGNAL_MSB 6
#define QT1070_REG_KEY1_SIGNAL_LSB 7
#define QT1070_REG_KEY2_SIGNAL_MSB 8
#define QT1070_REG_KEY2_SIGNAL_LSB 9
#define QT1070_REG_KEY3_SIGNAL_MSB 10
#define QT1070_REG_KEY3_SIGNAL_LSB 11
#define QT1070_REG_KEY4_SIGNAL_MSB 12
#define QT1070_REG_KEY4_SIGNAL_LSB 13
#define QT1070_REG_KEY5_SIGNAL_MSB 14
#define QT1070_REG_KEY5_SIGNAL_LSB 15
#define QT1070_REG_KEY6_SIGNAL_MSB 16
#define QT1070_REG_KEY6_SIGNAL_LSB 17
/** Reference date */
#define QT1070_REG_REFDATA0_MSB 18
#define QT1070_REG_REFDATA0_LSB 19
#define QT1070_REG_REFDATA1_MSB 20
#define QT1070_REG_REFDATA1_LSB 21
#define QT1070_REG_REFDATA2_MSB 22
#define QT1070_REG_REG_REFDATA2_LSB 23
#define QT1070_REG_REFDATA3_MSB 24
#define QT1070_REG_REG_REFDATA3_LSB 25
#define QT1070_REG_REFDATA4_MSB 26
#define QT1070_REG_REFDATA4_LSB 27
#define QT1070_REG_REFDATA5_MSB 28
#define QT1070_REG_REFDATA5_LSB 29
#define QT1070_REG_REFDATA6_MSB 30
#define QT1070_REG_REFDATA6_LSB 31
/** Negative threshold level */
#define QT1070_REG_NTHR_KEY0 32
#define QT1070_REG_NTHR_KEY1 33
#define QT1070_REG_NTHR_KEY2 34
#define QT1070_REG_NTHR_KEY3 35
#define QT1070_REG_NTHR_KEY4 36
#define QT1070_REG_NTHR_KEY5 37
#define QT1070_REG_NTHR_KEY6 38
/** Adjacent key suppression level */
#define QT1070_REG_AVEAKS_KEY0 39
#define QT1070_REG_AVEAKS_KEY1 40
#define QT1070_REG_AVEAKS_KEY2 41
#define QT1070_REG_AVEAKS_KEY3 42
#define QT1070_REG_AVEAKS_KEY4 43
#define QT1070_REG_AVEAKS_KEY5 44
#define QT1070_REG_AVEAKS_KEY6 45
/** Detection interator conter for key*/
#define QT1070_REG_DI_KEY0 46
#define QT1070_REG_DI_KEY1 47
#define QT1070_REG_DI_KEY2 48
#define QT1070_REG_DI_KEY3 49
#define QT1070_REG_DI_KEY4 50
#define QT1070_REG_DI_KEY5 51
#define QT1070_REG_DI_KEY6 52
/** Low power mode */
#define QT1070_REG_LOWPOWER_MODE 54
/** Maximum on duration */
#define QT1070_REG_MAX_DURATION 55
/** Calibrate */
#define QT1070_REG_CALIRATE 56
/** Reset */
#define QT1070_REG_RESET 57
/** Detection Status. */
/** This bit is set during a calibration sequence.*/
#define QT_CALIBRATE_BIT 7
/** This bit is set if the time to acquire all key signals exceeds 8 ms*/
#define QT_OVERFLOW_BIT 6
/** This bit is set if Comms mode is enabled. */
#define QT_COMMSENABLED_BIT 5
/** This bit is set if any keys are in detect. */
#define QT_TOUCH_BIT 0
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint8_t QT1070_GetChipId(Twid *pTwid);
extern uint8_t QT1070_GetFirmwareVersion(Twid *pTwid);
extern uint8_t QT1070_GetDetection_Status(Twid *pTwid);
extern uint8_t QT1070_GetKey_Status(Twid *pTwid);
extern uint16_t QT1070_GetKey_Signal(Twid *pTwid, uint8_t key);
extern uint16_t QT1070_GetKey_Reference(Twid *pTwid, uint8_t key);
extern void QT1070_SetThreshold(Twid *pTwid, uint8_t key, uint8_t threshold);
extern void QT1070_SetAveAks(Twid *pTwid, uint8_t key, uint8_t Ave, uint8_t Aks);
extern void QT1070_SetDetectionIntegrator(Twid *pTwid, uint8_t key, uint8_t di);
extern void QT1070_StartCalibrate(Twid *pTwid);
extern void QT1070_StartReset(Twid *pTwid);
#endif // QT1070_H
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/rand.h
+48
View File
@@ -0,0 +1,48 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* \file
*
* \section Purpose
* Small function for gererating random number.
*
*------------------------------------------------------------------------------*/
#ifndef _RAND_
#define _RAND_
/*------------------------------------------------------------------------------
* Global Functions
*------------------------------------------------------------------------------*/
extern void srand( uint32_t dwSeed ) ;
extern uint32_t rand( void ) ;
#endif /* #ifndef _RAND_ */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/rtc_calib.h
+50
View File
@@ -0,0 +1,50 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for Real Time Clock calibration (RTC) .
*
*/
/** RTC crystal **/
typedef struct
{
int8_t Tempr;
int16_t PPM;
uint8_t NEGPPM;
uint8_t HIGHPPM;
uint16_t CORRECTION;
}RTC_PPMLookup;
extern void RTC_ClockCalibration( Rtc* pRtc, int32_t CurrentTempr);
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/syscalls.h
+65
View File
@@ -0,0 +1,65 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file syscalls.h
*
* Implementation of newlib syscall.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdio.h>
#include <stdarg.h>
#include <sys/types.h>
#include <sys/stat.h>
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern caddr_t _sbrk ( int incr ) ;
extern int link( char *old, char *new ) ;
extern int _close( int file ) ;
extern int _fstat( int file, struct stat *st ) ;
extern int _isatty( int file ) ;
extern int _lseek( int file, int ptr, int dir ) ;
extern int _read(int file, char *ptr, int len) ;
extern int _write( int file, char *ptr, int len ) ;
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/timetick.h
+80
View File
@@ -0,0 +1,80 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \par Purpose
*
* Methods and definitions for Global time tick and wait functions.
*
* Defines a common and simpliest use of Time Tick, to increase tickCount
* every 1ms, the application can get this value through GetTickCount().
*
* \par Usage
*
* -# Configure the System Tick with TimeTick_Configure() when MCK changed
* \note
* Must be done before any invoke of GetTickCount(), Wait() or Sleep().
* -# Uses GetTickCount to get current tick value.
* -# Uses Wait to wait several ms.
* -# Uses Sleep to enter wait for interrupt mode to wait several ms.
*
*/
#ifndef _TIMETICK_
#define _TIMETICK_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern uint32_t TimeTick_Configure( uint32_t dwNew_MCK ) ;
extern void TimeTick_Increment( uint32_t dwInc ) ;
extern uint32_t GetDelayInTicks(uint32_t startTick,uint32_t endTick);
extern uint32_t GetTickCount( void ) ;
extern void Wait( volatile uint32_t dwMs ) ;
extern void Sleep( volatile uint32_t dwMs ) ;
#endif /* _TIMETICK_ */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/tsd.h
+86
View File
@@ -0,0 +1,86 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \addtogroup tsd_module TouchScreen Driver
*
* \section Purpose
*
* This unit provides a very powerful touchscreen driver which handles all the
* complexity. This includes touchscreen calibration, retrieving measurements,
* configuring the TSADC, etc.
*
* \section Usage
*
* -# Implement ADC interrupt handler in application, to invoke TSD_Handler()
* to handle ADC sampling events for touchscreen monitor.
* -# Call TSD_Initialize() to initialize ADC used for touchscreen.
* -# Call TSD_Calibrate() to do touchscreen calibration with LCD, and enable
* touchscreen monitor if calibration success.
* -# Call TSD_Enable() to enable or disable touchscreen monitoring.
* -# Declare a global TSD_PenPressed() function anywhere in your code. This
* function will get called every time the pen is pressed on the screen.
* -# Declare a global TSD_PenMoved() function, which will get called whenever
* the pen stays in contact with the screen but changes position.
* -# Declare a global TSD_PenReleased() function, which will be invoked as the
* pen is lifted from the screen.
*/
#ifndef TSD_H
#define TSD_H
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern void TSD_Handler(uint32_t dwAdcStatus);
extern void TSD_Initialize(void);
extern void TSD_DeInitialize(void);
extern void TSD_Enable(uint8_t bEnDis);
extern uint8_t TSD_Calibrate(void);
/* calibration used functions */
extern void TSD_GetRawMeasurement(uint32_t * pData);
extern void TSD_WaitPenPressed(void);
extern void TSD_WaitPenReleased(void);
/* callbacks */
extern void TSD_PenPressed(uint32_t x, uint32_t y, uint32_t pressure);
extern void TSD_PenMoved(uint32_t x, uint32_t y, uint32_t pressure);
extern void TSD_PenReleased(uint32_t x, uint32_t y);
#endif //#ifndef TSD_H
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/tsd_com.h
+50
View File
@@ -0,0 +1,50 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
#ifndef TSD_COM_H
#define TSD_COM_H
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern void TSDCom_InterpolateMeasurement(
const uint32_t *pData,
uint32_t *pPoint);
uint8_t TSDCom_Calibrate(void);
uint8_t TSDCom_IsCalibrationOk(void);
void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size);
void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size);
#endif /* #ifndef TSD_COM_H */
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/twid.h
+114
View File
@@ -0,0 +1,114 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _TWID_
#define _TWID_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definition
*----------------------------------------------------------------------------*/
/** TWI driver is currently busy. */
#define TWID_ERROR_BUSY 1
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \brief TWI driver structure. Holds the internal state of the driver.*/
typedef struct _Twid
{
/** Pointer to the underlying TWI peripheral.*/
Twi *pTwi ;
/** Current asynchronous transfer being processed.*/
Async *pTransfer ;
} Twid;
/*----------------------------------------------------------------------------
* Export functions
*----------------------------------------------------------------------------*/
extern void TWID_Initialize( Twid *pTwid, Twi *pTwi ) ;
extern void TWID_Handler( Twid *pTwid ) ;
extern uint8_t TWID_Read(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync);
extern uint8_t TWID_DmaRead(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync,
uint8_t TWI_ID);
extern uint8_t TWID_Write(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync);
extern uint8_t TWID_DmaWrite(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync,
uint8_t TWI_ID);
#ifdef __cplusplus
}
#endif
#endif //#ifndef TWID_H
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/wav.h
+78
View File
@@ -0,0 +1,78 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef WAV_H
#define WAV_H
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
/* Standard WAV file header information. */
typedef struct _WavHeader
{
/* Contains the letters "RIFF" in ASCII form. */
unsigned int chunkID;
/* Size of the rest of the chunk following this number.*/
unsigned int chunkSize;
/* Contains the letters "WAVE".*/
unsigned int format;
/* Contains the letters "fmt ".*/
unsigned int subchunk1ID;
/* 16 for PCM. This is the size of the rest of the Subchunk which follows this number.*/
unsigned int subchunk1Size;
/* PCM = 1 (i.e. Linear quantization). Values other than 1 indicate some form of compression.*/
unsigned short audioFormat;
/* Mono = 1, Stereo = 2, etc.*/
unsigned short numChannels;
/* 8000, 44100, etc.*/
unsigned int sampleRate;
/* SampleRate * NumChannels * BitsPerSample/8*/
unsigned int byteRate;
/* NumChannels * BitsPerSample/8*/
unsigned short blockAlign;
/* 8 bits = 8, 16 bits = 16, etc.*/
unsigned short bitsPerSample;
/* Contains the letters "data".*/
unsigned int subchunk2ID;
/* Number of bytes in the data.*/
unsigned int subchunk2Size;
} WavHeader;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern unsigned char WAV_IsValid(const WavHeader *header);
extern void WAV_DisplayInfo(const WavHeader *header);
#endif //#ifndef WAV_H
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/wm8904.h
+158
View File
@@ -0,0 +1,158 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implementation WM8904 driver.
*
*/
#ifndef WM8904_H
#define WM8904_H
#include "board.h"
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
#define WM8904_CSB_STATE (0x0 << 0)
/** Slave address */
#define WM8904_SLAVE_ADDRESS 0x1a | WM8904_CSB_STATE
/** Reset register*/
#define WM8904_REG_RESET 0x00
/** Bias control 0 register*/
#define WM8904_REG_BIAS_CTRL0 0x04
/** VMID control 0 register*/
#define WM8904_REG_VMID_CTRL0 0x05
/** MIC Bias control 0 register*/
#define WM8904_REG_MICBIAS_CTRL0 0x06
/** Bias control 1 register*/
#define WM8904_REG_BIAS_CTRL1 0x07
/** Power management control 0 register*/
#define WM8904_REG_POWER_MANG0 0x0C
/** Power management control 2 register*/
#define WM8904_REG_POWER_MANG2 0x0E
/** Power management control 3 register*/
#define WM8904_REG_POWER_MANG3 0x0F
/** Power management control 6 register*/
#define WM8904_REG_POWER_MANG6 0x12
/** Clock rate0 register*/
#define WM8904_REG_CLOCK_RATE0 0x14
/** Clock rate1 register*/
#define WM8904_REG_CLOCK_RATE1 0x15
/** Clock rate2 register*/
#define WM8904_REG_CLOCK_RATE2 0x16
/** Audio interface0 register*/
#define WM8904_REG_AUD_INF0 0x18
/** Audio interface1 register*/
#define WM8904_REG_AUD_INF1 0x19
/** Audio interface2 register*/
#define WM8904_REG_AUD_INF2 0x1A
/** Audio interface3 register*/
#define WM8904_REG_AUD_INF3 0x1B
/** ADC digital 0 register*/
#define WM8904_REG_ADC_DIG0 0x20
/** ADC digital 1 register*/
#define WM8904_REG_ADC_DIG1 0x21
/** Analogue left input 0 register*/
#define WM8904_REG_ANALOGUE_LIN0 0x2C
/** Analogue right input 0 register*/
#define WM8904_REG_ANALOGUE_RIN0 0x2D
/** Analogue left input 1 register*/
#define WM8904_REG_ANALOGUE_LIN1 0x2E
/** Analogue right input 1 register*/
#define WM8904_REG_ANALOGUE_RIN1 0x2F
/** Analogue left output 1 register*/
#define WM8904_REG_ANALOGUE_LOUT1 0x39
/** Analogue right output 1 register*/
#define WM8904_REG_ANALOGUE_ROUT1 0x3A
/** Analogue left output 2 register*/
#define WM8904_REG_ANALOGUE_LOUT2 0x3B
/** Analogue right output 2 register*/
#define WM8904_REG_ANALOGUE_ROUT2 0x3C
/** Analogue output 12 ZC register*/
#define WM8904_REG_ANALOGUE_OUT12ZC 0x3D
/** DC servo 0 register*/
#define WM8904_REG_DC_SERVO0 0x43
/** Analogue HP 0 register*/
#define WM8904_REG_ANALOGUE_HP0 0x5A
/** Charge pump 0 register*/
#define WM8904_REG_CHARGE_PUMP0 0x62
/** Class W 0 register*/
#define WM8904_REG_CLASS0 0x68
/** FLL control 1 register*/
#define WM8904_REG_FLL_CRTL1 0x74
/** FLL control 2 register*/
#define WM8904_REG_FLL_CRTL2 0x75
/** FLL control 3 register*/
#define WM8904_REG_FLL_CRTL3 0x76
/** FLL control 4 register*/
#define WM8904_REG_FLL_CRTL4 0x77
/** FLL control 5 register*/
#define WM8904_REG_FLL_CRTL5 0x78
/** DUMMY register*/
#define WM8904_REG_END 0xFF
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint16_t WM8904_Read(Twid *pTwid, uint32_t device, uint32_t regAddr);
extern void WM8904_Write(Twid *pTwid, uint32_t device, uint32_t regAddr, uint16_t data);
extern uint8_t WM8904_Init(Twid *pTwid, uint32_t device, uint32_t PCK);
extern uint8_t WM8904_VolumeSet(Twid *pTwid, uint32_t device, uint16_t value);
extern void WM8904_IN2R_IN1L(Twid *pTwid, uint32_t device);
#endif // WM8904_H
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/xdma_hardware_interface.h
+58
View File
@@ -0,0 +1,58 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _XDMAD_IF_H
#define _XDMAD_IF_H
/*----------------------------------------------------------------------------
* Includes
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** DMA hardware interface */
typedef struct _XdmaHardwareInterface {
uint8_t bXdmac; /**< DMA Controller number */
uint32_t bPeriphID; /**< Peripheral ID */
uint8_t bTransfer; /**< Transfer type 0: Tx, 1 :Rx*/
uint8_t bIfID; /**< DMA Interface ID */
} XdmaHardwareInterface;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint8_t XDMAIF_IsValidatedPeripherOnDma( uint8_t bXdmac, uint8_t bPeriphID);
extern uint8_t XDMAIF_Get_ChannelNumber (uint8_t bXdmac, uint8_t bPeriphID, uint8_t bTransfer);
#endif //#ifndef _XDMAD_IF_H
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/xdmad.h
+250
View File
@@ -0,0 +1,250 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _XDMAD_H
#define _XDMAD_H
/*----------------------------------------------------------------------------
* Includes
*----------------------------------------------------------------------------*/
#include "board.h"
#include <assert.h>
/** \addtogroup dmad_defines DMA Driver Defines
@{*/
/*----------------------------------------------------------------------------
* Consts
*----------------------------------------------------------------------------*/
#define XDMAD_TRANSFER_MEMORY 0xFF /**< DMA transfer from or to memory */
#define XDMAD_ALLOC_FAILED 0xFFFF /**< Channel allocate failed */
#define XDMAD_TRANSFER_TX 0
#define XDMAD_TRANSFER_RX 1
/* XDMA_MBR_UBC */
#define XDMA_UBC_NDE (0x1u << 24)
#define XDMA_UBC_NDE_FETCH_DIS (0x0u << 24)
#define XDMA_UBC_NDE_FETCH_EN (0x1u << 24)
#define XDMA_UBC_NSEN (0x1u << 25)
#define XDMA_UBC_NSEN_UNCHANGED (0x0u << 25)
#define XDMA_UBC_NSEN_UPDATED (0x1u << 25)
#define XDMA_UBC_NDEN (0x1u << 26)
#define XDMA_UBC_NDEN_UNCHANGED (0x0u << 26)
#define XDMA_UBC_NDEN_UPDATED (0x1u << 26)
#define XDMA_UBC_NVIEW_Pos 27
#define XDMA_UBC_NVIEW_Msk (0x3u << XDMA_UBC_NVIEW_Pos)
#define XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_Pos)
#define XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_Pos)
#define XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_Pos)
#define XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_Pos)
/*----------------------------------------------------------------------------
* MACRO
*----------------------------------------------------------------------------*/
/** @}*/
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \addtogroup dmad_structs DMA Driver Structs
@{*/
/** DMA status or return code */
typedef enum _XdmadStatus {
XDMAD_OK = 0, /**< Operation is sucessful */
XDMAD_PARTIAL_DONE,
XDMAD_DONE,
XDMAD_BUSY, /**< Channel occupied or transfer not finished */
XDMAD_ERROR, /**< Operation failed */
XDMAD_CANCELED /**< Operation canceled */
} eXdmadStatus, eXdmadRC;
/** DMA state for channel */
typedef enum _XdmadState {
XDMAD_STATE_FREE = 0, /**< Free channel */
XDMAD_STATE_ALLOCATED, /**< Allocated to some peripheral */
XDMAD_STATE_START, /**< DMA started */
XDMAD_STATE_IN_XFR, /**< DMA in trasfering */
XDMAD_STATE_DONE, /**< DMA transfer done */
} eXdmadState;
/** DMA transfer callback */
typedef void (*XdmadTransferCallback)(uint32_t status, void* pArg);
/** DMA driver channel */
typedef struct _XdmadChannel {
XdmadTransferCallback fCallback; /**< Callback */
void* pArg; /**< Callback argument */
uint8_t bIrqOwner; /**< Uses DMA handler or external one */
uint8_t bSrcPeriphID; /**< HW ID for source */
uint8_t bDstPeriphID; /**< HW ID for destination */
uint8_t bSrcTxIfID; /**< DMA Tx Interface ID for source */
uint8_t bSrcRxIfID; /**< DMA Rx Interface ID for source */
uint8_t bDstTxIfID; /**< DMA Tx Interface ID for destination */
uint8_t bDstRxIfID; /**< DMA Rx Interface ID for destination */
volatile uint8_t state; /**< DMA channel state */
} sXdmadChannel;
/** DMA driver instance */
typedef struct _Xdmad {
Xdmac *pXdmacs[2];
sXdmadChannel XdmaChannels[2][16];
uint8_t numControllers;
uint8_t numChannels;
uint8_t pollingMode;
uint8_t pollingTimeout;
} sXdmad;
typedef struct _XdmadCfg {
/** Microblock Control Member. */
uint32_t mbr_ubc;
/** Source Address Member. */
uint32_t mbr_sa;
/** Destination Address Member. */
uint32_t mbr_da;
/** Configuration Register. */
uint32_t mbr_cfg;
/** Block Control Member. */
uint32_t mbr_bc;
/** Data Stride Member. */
uint32_t mbr_ds;
/** Source Microblock Stride Member. */
uint32_t mbr_sus;
/** Destination Microblock Stride Member. */
uint32_t mbr_dus;
} sXdmadCfg;
/** \brief Structure for storing parameters for DMA view0 that can be
* performed by the DMA Master transfer.*/
typedef struct _LinkedListDescriporView0
{
/** Next Descriptor Address number. */
uint32_t mbr_nda;
/** Microblock Control Member. */
uint32_t mbr_ubc;
/** Transfer Address Member. */
uint32_t mbr_ta;
}LinkedListDescriporView0;
/** \brief Structure for storing parameters for DMA view1 that can be
* performed by the DMA Master transfer.*/
typedef struct _LinkedListDescriporView1
{
/** Next Descriptor Address number. */
uint32_t mbr_nda;
/** Microblock Control Member. */
uint32_t mbr_ubc;
/** Source Address Member. */
uint32_t mbr_sa;
/** Destination Address Member. */
uint32_t mbr_da;
}LinkedListDescriporView1;
/** \brief Structure for storing parameters for DMA view2 that can be
* performed by the DMA Master transfer.*/
typedef struct _LinkedListDescriporView2
{
/** Next Descriptor Address number. */
uint32_t mbr_nda;
/** Microblock Control Member. */
uint32_t mbr_ubc;
/** Source Address Member. */
uint32_t mbr_sa;
/** Destination Address Member. */
uint32_t mbr_da;
/** Configuration Register. */
uint32_t mbr_cfg;
}LinkedListDescriporView2;
/** \brief Structure for storing parameters for DMA view3 that can be
* performed by the DMA Master transfer.*/
typedef struct _LinkedListDescriporView3
{
/** Next Descriptor Address number. */
uint32_t mbr_nda;
/** Microblock Control Member. */
uint32_t mbr_ubc;
/** Source Address Member. */
uint32_t mbr_sa;
/** Destination Address Member. */
uint32_t mbr_da;
/** Configuration Register. */
uint32_t mbr_cfg;
/** Block Control Member. */
uint32_t mbr_bc;
/** Data Stride Member. */
uint32_t mbr_ds;
/** Source Microblock Stride Member. */
uint32_t mbr_sus;
/** Destination Microblock Stride Member. */
uint32_t mbr_dus;
}LinkedListDescriporView3;
/** @}*/
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup dmad_functions DMA Driver Functionos
@{*/
extern void XDMAD_Initialize( sXdmad *pXdmad,
uint8_t bPollingMode );
extern void XDMAD_Handler( sXdmad *pDmad);
extern uint32_t XDMAD_AllocateChannel( sXdmad *pXdmad,
uint8_t bSrcID, uint8_t bDstID);
extern eXdmadRC XDMAD_FreeChannel( sXdmad *pXdmad, uint32_t dwChannel );
extern eXdmadRC XDMAD_ConfigureTransfer( sXdmad *pXdmad,
uint32_t dwChannel,
sXdmadCfg *pXdmaParam,
uint32_t dwXdmaDescCfg,
uint32_t dwXdmaDescAddr);
extern eXdmadRC XDMAD_PrepareChannel( sXdmad *pXdmad, uint32_t dwChannel);
extern eXdmadRC XDMAD_IsTransferDone( sXdmad *pXdmad, uint32_t dwChannel );
extern eXdmadRC XDMAD_StartTransfer( sXdmad *pXdmad, uint32_t dwChannel );
extern eXdmadRC XDMAD_SetCallback( sXdmad *pXdmad,
uint32_t dwChannel,
XdmadTransferCallback fCallback,
void* pArg );
extern eXdmadRC XDMAD_StopTransfer( sXdmad *pXdmad, uint32_t dwChannel );
/** @}*/
/**@}*/
#endif //#ifndef _XDMAD_H
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/resources/ewarm/sama5d4x-ek-ddram.mac
+488
View File
@@ -0,0 +1,488 @@
// ---------------------------------------------------------
// ATMEL Microcontroller Software Support
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: sama5d4-ek-ddram.mac
// User setup file for CSPY debugger.
//
// ---------------------------------------------------------
__var __tempo_var;
__var __dummy_read;
__var __data_test;
__var __mac_i;
__var REG_CKGR_MOR;
__var CKGR_MOR_MOSCXTEN;
__var CKGR_MOR_MOSCXTBY;
__var CKGR_MOR_MOSCRCEN;
__var CKGR_MOR_MOSCSEL;
__var REG_CKGR_MCFR;
__var CKGR_MCFR_MAINFRDY;
__var REG_PMC_SR;
__var PMC_SR_MCKRDY;
__var PMC_SR_LOCKA;
__var PMC_PCK_CSS_MAIN_CLK;
__var REG_CKGR_PLLAR;
__var REG_PMC_PLLICPR;
__var REG_PMC_MCKR;
__var PMC_MCKR_PLLADIV2_DIV2;
__var PMC_MCKR_PRES_Msk;
__var PMC_MCKR_PRES_CLOCK;
__var PMC_MCKR_MDIV_Msk;
__var PMC_MCKR_MDIV_PCK_DIV3;
__var PMC_MCKR_CSS_PLLA_CLK;
__var PMC_SR_MOSCSELS;
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
__message "------------------------------ execUserReset ---------------------------------";
ini();
__message "-------------------------------Set PC Reset ----------------------------------";
__writeMemory32(0x1D3,0x98,"Register"); //* Set CPSR
}
/*********************************************************************
*
* execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
__message "------------------------------ execUserPreload ---------------------------------";
//__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
__tempo_var = __readMemory32(0xF0018028,"Memory"); // PLL A reg addr is 0xF0018028
if (__tempo_var == 0x215C3F01)
{
__message " ----------- PLL A is already set to 1056 MHz - Skip DDR2 init -----------";
__tempo_var = __readMemory32(0xF001000C,"Memory");
if (__tempo_var == 0x2223A338)
{
__message " ----------- DDR2 is already Up - skip initialization -----------";
}
else
{
__initDDR2(); //* Init DDR2 memory
__message "------------ DDR2 is initialized ------------";
}
}
else
{
__writeMemory32(0x00FFFFFF,0xF001C210,"Memory"); // SLAVE 4
__writeMemory32(0x0000000F,0xF001C290,"Memory");
__writeMemory32(0x0000FFFF,0xF001C250,"Memory");
__writeMemory32(0x00FFFFFF,0xF001C214,"Memory"); // SLAVE 5
__writeMemory32(0x0000000F,0xF001C294,"Memory");
__writeMemory32(0x0000FFFF,0xF001C254,"Memory");
__writeMemory32(0x00FFFFFF,0xF001C218,"Memory"); // SLAVE 6
__writeMemory32(0x0000000F,0xF001C298,"Memory");
__writeMemory32(0x0000FFFF,0xF001C258,"Memory");
__writeMemory32(0x00FFFFFF,0xF001C21C,"Memory"); // SLAVE 7
__writeMemory32(0x0000000F,0xF001C29C,"Memory");
__writeMemory32(0x0000FFFF,0xF001C25C,"Memory");
__writeMemory32(0x00FFFFFF,0xF001C220,"Memory"); // SLAVE 8
__writeMemory32(0x0000000F,0xF001C2A0,"Memory");
__writeMemory32(0x0000FFFF,0xF001C260,"Memory");
__writeMemory32(0x00FFFFFF,0xF001C224,"Memory"); // SLAVE 9
__writeMemory32(0x0000000F,0xF001C2A4,"Memory");
__writeMemory32(0x0000FFFF,0xF001C264,"Memory");
__writeMemory32(0x00FFFFFF,0xF001C228,"Memory"); // SLAVE 10
__writeMemory32(0x0000000F,0xF001C2A8,"Memory");
__writeMemory32(0x0000FFFF,0xF001C268,"Memory");
PMC_SelectExt12M_Osc();
PMC_SwitchMck2Main();
PMC_SetPllA(87);
PMC_SetMckPllaDiv();
PMC_SetMckPrescaler();
PMC_SetMckDivider();
PMC_SwitchMck2Pll();
__message "------------ PLL set to 1056 MHz, MCK set to 176 MHz ------------";
__initDDR2(1); //* Init DDR2 memory
__message "------------ DDR2 is initialized ------------";
}
Watchdog(); //* Watchdog Disable
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
__mac_i=__readMemory32(0xFC069040,"Memory");
__message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
}
/*********************************************************************
*
* ini() :
* Function description
* Write ARM9 core regsiter to Reset value
*/
ini()
{
__writeMemory32(0x0,0x00,"Register");
__writeMemory32(0x0,0x04,"Register");
__writeMemory32(0x0,0x08,"Register");
__writeMemory32(0x0,0x0C,"Register");
__writeMemory32(0x0,0x10,"Register");
__writeMemory32(0x0,0x14,"Register");
__writeMemory32(0x0,0x18,"Register");
__writeMemory32(0x0,0x1C,"Register");
__writeMemory32(0x0,0x20,"Register");
__writeMemory32(0x0,0x24,"Register");
__writeMemory32(0x0,0x28,"Register");
__writeMemory32(0x0,0x2C,"Register");
__writeMemory32(0x0,0x30,"Register");
__writeMemory32(0x0,0x34,"Register");
__writeMemory32(0x0,0x38,"Register");
// Set CPSR
__writeMemory32(0x0D3,0x98,"Register");
}
/*********************************************************************
*
* _Watchdog()
*
* Function description
* Clear Watchdog
*/
Watchdog()
{
// Watchdog Disable
__writeMemory32(0x00008000,0xFC068644,"Memory");
__message " ------------------------ Watchdog Disable ------------------------";
}
/*********************************************************************
*
* PMC_SelectExt12M_Osc()
*
* Function description
* Select external 12MHz oscillator
*/
PMC_SelectExt12M_Osc()
{
// --------- Select_ext_Crystal_32k ---------------
REG_CKGR_MOR = 0xF0018020;
CKGR_MOR_MOSCXTEN = (0x1 << 0); /*(CKGR_MOR) Main Crystal Oscillator Enable */
CKGR_MOR_MOSCXTBY = (0x1 << 1); /*(CKGR_MOR) Main Crystal Oscillator Bypass */
CKGR_MOR_MOSCRCEN = (0x1 << 3); /*(CKGR_MOR) Main On-Chip RC Oscillator Enable */
CKGR_MOR_MOSCSEL = (0x1 << 24); /*(CKGR_MOR) Main Oscillator Selection */
REG_CKGR_MCFR = 0xF0018024; /*(PMC) Main Clock Frequency Register */
CKGR_MCFR_MAINFRDY = (0x1 << 16); /*(CKGR_MCFR) Main Clock Ready */
REG_PMC_SR = 0xF0018068; /*(PMC) Status Register */
PMC_SR_MOSCSELS = (0x1 << 16); /*(PMC_SR) Main Oscillator Selection Status */
PMC_SR_MCKRDY = (0x1 << 3); /*(PMC_SR) Master Clock Status */
/* enable external OSC 12 MHz */
__tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");
__tempo_var |= CKGR_MOR_MOSCXTEN | (0x37 << 16);
__writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");
/* wait Main CLK Ready */
while(!((__readMemory32(REG_CKGR_MCFR,"Memory")) & CKGR_MCFR_MAINFRDY));
/* disable external OSC 12 MHz bypass */
__tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");
__tempo_var = (__tempo_var & ~CKGR_MOR_MOSCXTBY) | (0x37 << 16);
__writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");
/* switch MAIN clock to external OSC 12 MHz*/
__tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");
__tempo_var |= CKGR_MOR_MOSCSEL | (0x37 << 16);
__writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");
/* wait MAIN clock status change for external OSC 12 MHz selection*/
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MOSCSELS));
/* in case when MCK is running on MAIN CLK */
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__message " -------- PMC_SelectExt12M_Osc ---------- REG_CKGR_MOR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SwitchMck2Main()
*
* Function description
* Switch PMC from MCK to main clock.
*/
PMC_SwitchMck2Main()
{
REG_PMC_MCKR = 0xF0018030; /*(PMC) Master Clock Register */
PMC_PCK_CSS_MAIN_CLK = (0x1 << 0); /*(PMC_PCK[3]) Main Clock is selected */
PMC_SR_MCKRDY = (0x1 << 3); /*(PMC_SR) Master Clock Status */
REG_PMC_SR = 0xF0018068; /*(PMC) Status Register */
/* Select Main Oscillator as input clock for PCK and MCK */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
__tempo_var = (__tempo_var & ~0x03)| PMC_PCK_CSS_MAIN_CLK ;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__mac_i=__readMemory32(REG_PMC_MCKR,"Memory");
__message " --------- PMC_SwitchMck2Main ----------- REG_PMC_MCKR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SetPllA()
*
* Function description
* Configure PLLA Registe.
*/
PMC_SetPllA(pllmul)
{
REG_CKGR_PLLAR = 0xF0018028; /*(PMC) PLLA Register */
REG_PMC_PLLICPR = 0xF0018080; /*(PMC) PLL Charge Pump Current Register */
REG_PMC_SR = 0xF0018068; /*(PMC) Status Register */
PMC_SR_LOCKA = (0x1 << 1); /*(PMC_SR) PLLA Lock Status */
__writeMemory32(((0x1 << 29) | (0x3F << 8) | ( 0 << 14) | ((pllmul) << 18) | 1 ), REG_CKGR_PLLAR,"Memory");
//__writeMemory32((0x03<<8), REG_PMC_PLLICPR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_LOCKA));
__mac_i=__readMemory32(REG_CKGR_PLLAR,"Memory");
__message " --------- PMC_SetPllA ---------------- REG_CKGR_PLLAR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SetMckPllaDiv()
*
* Function description
* Configure MCK PLLA divider.
*/
PMC_SetMckPllaDiv()
{
REG_PMC_MCKR = 0xF0018030; /*(PMC) Master Clock Register */
PMC_MCKR_PLLADIV2_DIV2 = (0x1 << 12); /*(PMC_MCKR) PLLA clock frequency is divided by 2. */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
if ((__tempo_var & PMC_MCKR_PLLADIV2_DIV2) != PMC_MCKR_PLLADIV2_DIV2)
{
__tempo_var |= PMC_MCKR_PLLADIV2_DIV2;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
}
}
/*********************************************************************
*
* PMC_SetMckPrescaler()
*
* Function description
* Configure MCK Prescaler.
*/
PMC_SetMckPrescaler()
{
REG_PMC_MCKR = 0xF0018030; /*(PMC) Master Clock Register */
PMC_MCKR_PRES_Msk = (0x7 << 4); /*(PMC_MCKR) Master/Processor Clock Prescaler */
PMC_MCKR_PRES_CLOCK = (0x0 << 4); /*(PMC_MCKR) Selected clock */
/* Change MCK Prescaler divider in PMC_MCKR register */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
__tempo_var = (__tempo_var & ~PMC_MCKR_PRES_Msk) | PMC_MCKR_PRES_CLOCK;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__mac_i=__readMemory32(REG_PMC_MCKR,"Memory");
__message " --------- PMC_SetMckPrescaler -------------- REG_PMC_MCKR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SetMckDivider()
*
* Function description
* Configure MCK Divider.
*/
PMC_SetMckDivider()
{
REG_PMC_MCKR = 0xF0018030; /*(PMC) Master Clock Register */
PMC_MCKR_MDIV_Msk = (0x3 << 8); /*(PMC_MCKR) Master Clock Division */
PMC_MCKR_MDIV_PCK_DIV3 = (0x3 << 8); /*(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */
/* change MCK Prescaler divider in PMC_MCKR register */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
__tempo_var = (__tempo_var & ~PMC_MCKR_MDIV_Msk) | PMC_MCKR_MDIV_PCK_DIV3;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__mac_i=__readMemory32(REG_PMC_MCKR,"Memory");
__message " --------- PMC_SetMckDivider -------------- REG_PMC_MCKR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SwitchMck2Pll()
*
* Function description
* Switch PMC from MCK to PLL clock.
*/
PMC_SwitchMck2Pll()
{
REG_PMC_MCKR = 0xF0018030; /*(PMC) Master Clock Register */
PMC_MCKR_CSS_PLLA_CLK = (0x2 << 0); /*(PMC_MCKR) PLLACK/PLLADIV2 is selected */
/* Select PLL as input clock for PCK and MCK */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
__tempo_var = (__tempo_var & ~0x03) | PMC_MCKR_CSS_PLLA_CLK;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__mac_i=__readMemory32(REG_PMC_MCKR,"Memory");
__message " --------- PMC_SwitchMck2Pll -------------- REG_PMC_MCKR 0x",__mac_i:%X;
}
// ---------------------------------------------------------------------------
// Function Name : __initDDR2
// Object : Set DDR2 memory for working at 176 Mhz
// ---------------------------------------------------------------------------
__initDDR2(type)
{
// ------------------ DDR Controller Registers --------------
// #define REG_MPDDRC_MR (0xF0010000U) /**< \brief (MPDDRC) MPDDRC Mode Register */
// #define REG_MPDDRC_RTR (0xF0010004U) /**< \brief (MPDDRC) MPDDRC Refresh Timer Register */
// #define REG_MPDDRC_CR (0xF0010008U) /**< \brief (MPDDRC) MPDDRC Configuration Register */
// #define REG_MPDDRC_TPR0 (0xF001000CU) /**< \brief (MPDDRC) MPDDRC Timing Parameter 0 Register */
// #define REG_MPDDRC_TPR1 (0xF0010010U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 1 Register */
// #define REG_MPDDRC_TPR2 (0xF0010014U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 2 Register */
// #define REG_MPDDRC_LPR (0xF001001CU) /**< \brief (MPDDRC) MPDDRC Low-power Register */
// #define REG_MPDDRC_MD (0xF0010020U) /**< \brief (MPDDRC) MPDDRC Memory Device Register */
// #define REG_MPDDRC_LPDDR2_LPR (0xF0010028U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Low-power Register */
// #define REG_MPDDRC_LPDDR2_CAL_MR4 (0xF001002CU) /**< \brief (MPDDRC) MPDDRC LPDDR2 Calibration and MR4 Register */
// #define REG_MPDDRC_LPDDR2_TIM_CAL (0xF0010030U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Timing Calibration Register */
// #define REG_MPDDRC_IO_CALIBR (0xF0010034U) /**< \brief (MPDDRC) MPDDRC IO Calibration */
// #define REG_MPDDRC_OCMS (0xF0010038U) /**< \brief (MPDDRC) MPDDRC OCMS Register */
// #define REG_MPDDRC_OCMS_KEY1 (0xF001003CU) /**< \brief (MPDDRC) MPDDRC OCMS KEY1 Register */
// #define REG_MPDDRC_OCMS_KEY2 (0xF0010040U) /**< \brief (MPDDRC) MPDDRC OCMS KEY2 Register */
// #define REG_MPDDRC_CONF_ARBITER (0xF0010044U) /**< \brief (MPDDRC) MPDDRC Configuration Arbiter */
// #define REG_MPDDRC_TIMEOUT (0xF0010048U) /**< \brief (MPDDRC) MPDDRC Time-out Port 0/1/2/3 */
// #define REG_MPDDRC_REQ_PORT_0123 (0xF001004CU) /**< \brief (MPDDRC) MPDDRC Time-out Request Port 0/1/2/3 */
// #define REG_MPDDRC_REQ_PORT_4567 (0xF0010050U) /**< \brief (MPDDRC) MPDDRC Time-out Request Port 4/5/6/7 */
// #define REG_MPDDRC_BDW_PORT_0123 (0xF0010054U) /**< \brief (MPDDRC) MPDDRC Bandwidth Port 0/1/2/3 */
// #define REG_MPDDRC_BDW_PORT_4567 (0xF0010058U) /**< \brief (MPDDRC) MPDDRC Bandwidth Port 4/5/6/7 */
// #define REG_MPDDRC_RD_DATA_PATH (0xF001005CU) /**< \brief (MPDDRC) MPDDRC_READ_DATA_PATH */
// #define REG_MPDDRC_SAW (0xF0010060U) /**< \brief (MPDDRC) MPDDRC Smart Adaptation Wrapper 0 Register */
// #define REG_MPDDRC_WPMR (0xF00100E4U) /**< \brief (MPDDRC) MPDDRC Write Protect Control Register */
// #define REG_MPDDRC_WPSR (0xF00100E8U) /**< \brief (MPDDRC) MPDDRC Write Protect Status Register */
// #define REG_MPDDRC_DLL_OS (0xF0010100U) /**< \brief (MPDDRC) MPDDRC DLL Offset Selection Register */
// #define REG_MPDDRC_DLL_MO (0xF0010104U) /**< \brief (MPDDRC) MPDDRC DLL MASTER Offset Register */
// #define REG_MPDDRC_DLL_SO0 (0xF0010108U) /**< \brief (MPDDRC) MPDDRC DLL SLAVE Offset 0 Register */
// #define REG_MPDDRC_DLL_SO1 (0xF001010CU) /**< \brief (MPDDRC) MPDDRC DLL SLAVE Offset 1 Register */
// #define REG_MPDDRC_DLL_WRO (0xF0010110U) /**< \brief (MPDDRC) MPDDRC DLL CLKWR Offset Register */
// #define REG_MPDDRC_DLL_ADO (0xF0010114U) /**< \brief (MPDDRC) MPDDRC DLL CLKAD Offset Register */
// #define REG_MPDDRC_DLL_SM (0xF0010118U) /**< \brief (MPDDRC) MPDDRC DLL Status MASTER0 Register */
// #define REG_MPDDRC_DLL_SSL (0xF0010128U) /**< \brief (MPDDRC) MPDDRC DLL Status SLAVE0 Register */
// #define REG_MPDDRC_DLL_SWR (0xF0010148U) /**< \brief (MPDDRC) MPDDRC DLL Status CLKWR0 Register */
// #define REG_MPDDRC_DLL_SAD (0xF0010158U) /**< \brief (MPDDRC) MPDDRC DLL Status CLKAD Register */
// -----------------------------------------------
__delay(2);
__writeMemory32(0x00008000,0xFC068644,"Memory"); // Disable Watchdog
__writeMemory32(0x00010000,0xF0018010,"Memory"); // Enable MPDDR controller clock
__writeMemory32(0x00000004,0xF0018000,"Memory"); // System Clock Enable Register : Enable DDR clock
__writeMemory32(0x00000001,0xF001005C,"Memory"); // Read Data Path register : Sampling point is shifted of one cycle
__writeMemory32(0x00870514,0xF0010034,"Memory"); // MPDDRC I/O Calibration Register : RZQ_60_RZQ_50 + enable permanent calibration + TZQIO = 5
__writeMemory32(0x00000006,0xF0010020,"Memory"); // Memory Device Register : 32bit mode - DDR2 mode
__writeMemory32(0x2223A338,0xF001000C,"Memory"); // Timing 0 Register : tras | trcd | twr | trc | trp | trrd | twtr | tmrd
__writeMemory32(0x0b206417,0xF0010010,"Memory"); // Timing 1 Register : trfc | txsnr | txsrd | txp
__writeMemory32(0x00072328,0xF0010014,"Memory"); // Timing 2 Register : txard | tards | trpa | trtp | tfaw
__writeMemory32(0x00B0003D,0xF0010008,"Memory"); // Configuration Register : row = 14, column(DDR) = 10, CAS 3, DLL reset disable, phase error correction is enabled / normal driver strength
__writeMemory32(0x00000001,0xF0010000,"Memory"); // Mode register : command NOP --> ENABLE CLOCK output
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1); // wait 1 ms
__writeMemory32(0x00000001,0xF0010000,"Memory"); // Mode register : command NOP --> ENABLE CLOCK output
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000002,0xF0010000,"Memory"); // Mode register : command All Banks Precharge
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000005,0xF0010000,"Memory"); // Mode register : command Extended Load Mode Register : Set EMR Ext Mode Reg EMSR2 BA0=0 BA1=1
__writeMemory32(0x00000000,0x28000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000005,0xF0010000,"Memory"); // Mode register : command Extended Load Mode Register : Set EMR Ext Mode Reg EMSR3 BA0=1 BA1=1
__writeMemory32(0x00000000,0x2C000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000005,0xF0010000,"Memory"); // Mode register : command Extended Load Mode Register : Set EMR Ext Mode Reg EMSR1 BA0=1 BA1=0 ENABLE DLL
__writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00B000BD,0xF0010008,"Memory"); // Configuration Register : Enable DLL reset
__writeMemory32(0x00000003,0xF0010000,"Memory"); // Mode register : command RESET DLL
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000002,0xF0010000,"Memory"); // Mode register : command All Banks Precharge
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000004,0xF0010000,"Memory"); // Mode register : 2 * command Auto-Refresh
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000004,0xF0010000,"Memory"); // Mode register :
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00B0003D,0xF0010008,"Memory"); // Configuration Register : disable DLL reset
__writeMemory32(0x00000003,0xF0010000,"Memory"); // Mode register : MRS initialize device operation (CAS latency, burst length and disable DLL reset)
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00B0703D,0xF0010008,"Memory"); // Configuration Register : OCD default value
__writeMemory32(0x00000005,0xF0010000,"Memory"); // Mode register : EMRS1 OCD Default values
__writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00B0003D,0xF0010008,"Memory"); // Configuration Register : OCD exit
__writeMemory32(0x00000005,0xF0010000,"Memory"); // Mode register : EMRS1 OCD exit
__writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000000,0xF0010000,"Memory"); // Mode register : command Normal mode
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x000002B0,0xF0010004,"Memory"); // Refresh Timer register
__message "------------------------------- DDR2 memory init for 176 MHz ----------------------------------";
}
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/resources/ewarm/sama5d4x-ek-sram.mac
+106
View File
@@ -0,0 +1,106 @@
// ---------------------------------------------------------
// ATMEL Microcontroller Software Support
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: sama5d3x-ek-sram.mac
// User setup file for CSPY debugger.
//
// ---------------------------------------------------------
__var __tempo_var;
__var __dummy_read;
__var __data_test;
__var __mac_i;
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
__message "------------------------------ execUserReset ---------------------------------";
//CheckNoRemap();
__message "-------------------------------Set PC Reset ----------------------------------";
__writeMemory32(0x1D3,0x98,"Register"); //* Set CPSR
}
/*********************************************************************
*
* execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
__message "------------------------------ execUserPreload ---------------------------------";
//__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
//__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
//CheckNoRemap(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
Watchdog(); //* Watchdog Disable
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
__mac_i=__readMemory32(0xFC069040,"Memory");
__message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
}
/*********************************************************************
*
* CheckRemap()
*
* Function description
* Check the Remap.
*/
CheckNoRemap()
{
__tempo_var = __readMemory32(0x00000000,"Memory");
if (__tempo_var == 0xAA55AA55)
{
__data_test = 0x55AA55AA;
}
else
{
__data_test = 0xAA55AA55;
}
__writeMemory32(__data_test,0x00000000,"Memory");
__dummy_read = __readMemory32(0x00000000,"Memory");
__writeMemory32(__tempo_var,0x00000000,"Memory");
if (__dummy_read == __data_test)
{
__message " ------------------------ The Remap is already done ------------------------";
}
else
{
__message " ------------------------ The Remap is not DONE ------------------------";
__writeMemory32(0x00000001,0x00700000,"Memory");
__delay(50);
__message "------------ The Remap was executed ------------";
}
}
/*********************************************************************
*
* _Watchdog()
*
* Function description
* Clear Watchdog
*/
Watchdog()
{
// Watchdog Disable
__writeMemory32(0x00008000,0xFC068644,"Memory");
__message " ------------------------ Watchdog Disable ------------------------";
}
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/resources/ewarm/sama5d4x/ddram.icf
+59
View File
@@ -0,0 +1,59 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Memory Regions-*/
define symbol __ICFEDIT_region_DDRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_DDRAM_end__ = 0x23FFFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x200000;
define symbol __ICFEDIT_region_RAM_end__ = 0x21FFFF;
define symbol __ICFEDIT_region_DDRAM_BUF_start__ = 0x24000000;
define symbol __ICFEDIT_region_DDRAM_BUF_end__ = 0x24FFFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_startup__ = 0x200;
define symbol __ICFEDIT_size_vectors__ = 0x100;
define symbol __ICFEDIT_size_cstack__ = 0x4000;
define symbol __ICFEDIT_size_irqstack__ = 0x60;
define symbol __ICFEDIT_size_fiqstack__ = 0x60;
define symbol __ICFEDIT_size_abtstack__ = 0x60;
define symbol __ICFEDIT_size_undstack__ = 0x40;
define symbol __ICFEDIT_size_heap__ = 0x60;
/*-Exports-*/
export symbol __ICFEDIT_region_DDRAM_start__;
export symbol __ICFEDIT_region_DDRAM_end__;
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
export symbol __ICFEDIT_size_startup__;
export symbol __ICFEDIT_size_vectors__;
export symbol __ICFEDIT_size_cstack__;
export symbol __ICFEDIT_size_irqstack__;
export symbol __ICFEDIT_size_fiqstack__;
export symbol __ICFEDIT_size_heap__;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region STA_region = mem:[from __ICFEDIT_region_DDRAM_start__ size __ICFEDIT_size_startup__];
define region STACK_region = mem:[from __ICFEDIT_region_DDRAM_start__+__ICFEDIT_size_startup__ size __ICFEDIT_size_startup__+__ICFEDIT_size_cstack__+__ICFEDIT_size_irqstack__+__ICFEDIT_size_fiqstack__+__ICFEDIT_size_heap__];
define region DDRAM_region = mem:[from __ICFEDIT_region_DDRAM_start__+__ICFEDIT_size_startup__+__ICFEDIT_size_cstack__+__ICFEDIT_size_irqstack__+__ICFEDIT_size_fiqstack__+__ICFEDIT_size_heap__ to __ICFEDIT_region_DDRAM_end__];
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
define region DMA_BUF_region = mem:[from __ICFEDIT_region_DDRAM_BUF_start__ to __ICFEDIT_region_DDRAM_BUF_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { section .vectors };
do not initialize { section .noinit };
place in STA_region { section .cstartup };
place in VEC_region { section .vectors };
place in DDRAM_region { readonly };
place in DDRAM_region { readwrite };
place in DDRAM_region { zeroinit };
place in STACK_region { block IRQ_STACK, block FIQ_STACK, block ABT_STACK, block UND_STACK, block CSTACK, block HEAP };
place in DMA_BUF_region {section region_dma_nocache };
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/resources/ewarm/sama5d4x/sram.icf
+46
View File
@@ -0,0 +1,46 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Memory Regions-*/
define symbol __ICFEDIT_region_RAM_start__ = 0x200000;
define symbol __ICFEDIT_region_RAM_end__ = 0x21FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_vectors__ = 0x100;
define symbol __ICFEDIT_size_cstack__ = 0x4000;
define symbol __ICFEDIT_size_irqstack__ = 0x60;
define symbol __ICFEDIT_size_fiqstack__ = 0x60;
define symbol __ICFEDIT_size_abtstack__ = 0x60;
define symbol __ICFEDIT_size_undstack__ = 0x40;
define symbol __ICFEDIT_size_heap__ = 0x400;
/*-Exports-*/
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
export symbol __ICFEDIT_size_vectors__;
export symbol __ICFEDIT_size_cstack__;
export symbol __ICFEDIT_size_irqstack__;
export symbol __ICFEDIT_size_fiqstack__;
export symbol __ICFEDIT_size_heap__;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy with packing=none { readwrite };
do not initialize { readonly section .noinit };
place in VEC_region { section .vectors };
place in RAM_region { readonly };
place in RAM_region { section .cstartup };
place in RAM_region { readwrite, block IRQ_STACK, block FIQ_STACK, block ABT_STACK, block UND_STACK, block CSTACK, block HEAP };
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/bmp.c
+315
View File
@@ -0,0 +1,315 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <string.h>
/*----------------------------------------------------------------------------
* Definition
*----------------------------------------------------------------------------*/
/// BMP offset for header
#define IMAGE_OFFSET 0x100
/*----------------------------------------------------------------------------
* Internal types
*----------------------------------------------------------------------------*/
/** Describe the BMP palette */
typedef struct _BMPPaletteEntry
{
/** Blue value */
uint8_t b;
/** Green value */
uint8_t g;
/** Red value */
uint8_t r;
/** Filler character value */
uint8_t filler;
} BMPPaletteEntry ;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Test if BMP is valid.
* \param file Buffer holding the file to examinate.
* \return 1 if the header of a BMP file is valid; otherwise returns 0.
*/
uint8_t BMP_IsValid( void *file )
{
return ((BMPHeader*) file)->type == BMP_TYPE ;
}
/**
* \brief Returns the size of a BMP image given at least its header (the file does
* not have to be complete).
* \param file Pointer to the buffer which holds the BMP file.
* \return size of BMP image
*/
uint32_t BMP_GetFileSize( void *file )
{
return ((BMPHeader *) file)->fileSize ;
}
/**
* \brief Write a BMP header
* \param pAddressHeader Begin address of the BMP
* \param bmpHSize BMP heigth size
* \param bmpVSize BMP width size
* \param bmpRgb Type of BMP (YUV or RGB)
* \param nbByte_Pixels Number of byte per pixels
*/
void WriteBMPheader( uint32_t* pAddressHeader, uint32_t bmpHSize, uint32_t bmpVSize, uint8_t bmpRgb, uint8_t nbByte_Pixels )
{
uint32_t i;
uint32_t* fill;
BMPHeader *Header;
bmpRgb = bmpRgb;
fill = pAddressHeader;
for ( i=0 ; i < IMAGE_OFFSET ; i+=4 )
{
*fill++ = 0;
}
Header = (BMPHeader*) pAddressHeader;
Header->type = BMP_TYPE;
Header->fileSize = (bmpHSize * bmpVSize * nbByte_Pixels) + IMAGE_OFFSET;
Header->reserved1 = 0;
Header->reserved2 = 0;
Header->offset = IMAGE_OFFSET;
Header->headerSize = BITMAPINFOHEADER;
Header->width = bmpHSize;
Header->height = bmpVSize;
Header->planes = 1;
Header->bits = nbByte_Pixels * 8;
Header->compression = 0;
Header->imageSize = bmpHSize * bmpVSize * nbByte_Pixels;
Header->xresolution = 0;
Header->yresolution = 0;
Header->ncolours = 0;
Header->importantcolours = 0;
}
/**
* \brief Debug function, dislay BMP header
* \param pAddressHeader Address of the BMP
*/
void BMP_displayHeader( uint32_t* pAddressHeader )
{
#if (TRACE_LEVEL >= TRACE_LEVEL_INFO)
BMPHeader *header;
header = (BMPHeader*) pAddressHeader;
TRACE_INFO("BMP\n\r");
TRACE_INFO("type 0x%X \n\r", header->type);
TRACE_INFO("fileSize %ld \n\r", header->fileSize);
TRACE_INFO("reserved1 %d \n\r", header->reserved1);
TRACE_INFO("reserved2 %d \n\r", header->reserved2);
TRACE_INFO("offset %ld \n\r", header->offset);
TRACE_INFO("headerSize %ld \n\r", header->headerSize);
TRACE_INFO("width %ld \n\r", header->width);
TRACE_INFO("height %ld \n\r", header->height);
TRACE_INFO("planes %d \n\r", header->planes);
TRACE_INFO("bits %d \n\r", header->bits);
TRACE_INFO("compression %ld \n\r", header->compression);
TRACE_INFO("imageSize %ld \n\r", header->imageSize);
TRACE_INFO("xresolution %ld \n\r", header->xresolution);
TRACE_INFO("yresolution %ld \n\r", header->yresolution);
TRACE_INFO("ncolours %ld \n\r", header->ncolours);
TRACE_INFO("importantcolours %ld\n\r", header->importantcolours);
#else
pAddressHeader = pAddressHeader;
#endif
}
/**
* \brief Loads a BMP image located at the given address, decodes it and stores the
* resulting image inside the provided buffer. Image must have the specified
* width & height.
* If no buffer is provided, this function simply checks if it is able to
* decode the image.
* \param file Buffer which holds the BMP file.
* \param buffer Buffer in which to store the decoded image.
* \param width Buffer width in pixels.
* \param height Buffer height in pixels.
* \param bpp Number of bits per pixels that the buffer stores.
* \return 0 if the image has been loaded; otherwise returns an error code.
*/
uint8_t BMP_Decode( void *file, uint8_t *buffer, uint32_t width, uint32_t height, uint8_t bpp )
{
BMPHeader *header;
uint32_t i, j;
uint8_t r, g, b;
uint8_t *image;
// Read header information
header = (BMPHeader*) file;
// Verify that the file is valid
if ( !BMP_IsValid( file ) )
{
TRACE_ERROR("BMP_Decode: File type is not 'BM' (0x%04X).\n\r",header->type);
return 1;
}
// Check that parameters match
if ( (header->compression != 0) || (header->width != width) || (header->height != height))
{
TRACE_ERROR("BMP_Decode: File format not supported\n\r");
TRACE_ERROR(" -> .compression = %u\n\r", (unsigned int)header->compression);
TRACE_ERROR(" -> .width = %u\n\r", (unsigned int)header->width);
TRACE_ERROR(" -> .height = %u\n\r", (unsigned int)header->height);
TRACE_ERROR(" -> .bits = %d\n\r", header->bits);
return 2;
}
// Get image data
image = (uint8_t *) ((uint32_t) file + header->offset);
// Check that the bpp resolution is supported
// Only a 24-bit output & 24- or 8-bit input are supported
if ( bpp != 24 )
{
TRACE_ERROR("BMP_Decode: Output resolution not supported\n\r");
return 3;
}
else
{
if (header->bits == 24)
{
// Decoding is ok
if (!buffer) return 0;
// Get image data (swapping red & blue)
for ( i=0 ; i < height ; i++ )
{
for ( j=0 ; j < width; j++ )
{
r = image[((height - i - 1) * width + j) * 3 + 2];
g = image[((height - i - 1) * width + j) * 3 + 1];
b = image[((height - i - 1) * width + j) * 3];
#if defined(BOARD_LCD_RGB565)
// Interlacing
r = ((r << 1) & 0xF0) | ((g & 0x80) >> 4) | ((r & 0x80) >> 5);
g = (g << 1) & 0xF8;
b = b & 0xF8;
buffer[(i * width + j) * 3] = b;
buffer[(i * width + j) * 3 + 1] = g;
buffer[(i * width + j) * 3 + 2] = r;
#else
buffer[(i * width + j) * 3] = r;
buffer[(i * width + j) * 3 + 1] = g;
buffer[(i * width + j) * 3 + 2] = b;
#endif //#if defined(BOARD_LCD_RGB565)
}
}
}
else
{
if ( header->bits == 8 )
{
// Decoding is ok
if (!buffer) return 0;
// Retrieve palette
BMPPaletteEntry palette[256];
memcpy( palette, (uint8_t *) ((uint32_t) file + sizeof( BMPHeader )), header->offset - sizeof( BMPHeader ) ) ;
// Decode image (reversing row order)
for ( i=0 ; i < height ; i++ )
{
for (j=0; j < width; j++)
{
r = palette[image[(height - i - 1) * width + j]].r;
g = palette[image[(height - i - 1) * width + j]].g;
b = palette[image[(height - i - 1) * width + j]].b;
buffer[(i * width + j) * 3] = r;
buffer[(i * width + j) * 3 + 1] = g;
buffer[(i * width + j) * 3 + 2] = b;
}
}
}
else
{
TRACE_ERROR("BMP_Decode: Input resolution not supported\n\r");
TRACE_INFO("header->bits 0x%X \n\r", header->bits);
return 4 ;
}
}
}
return 0 ;
}
/**
* \brief Convert RGB 565 to RGB 555 (RGB 555 is adapted to LCD)
*
* \param fileSource Buffer which holds the RGB file
* \param fileDestination Buffer in which to store the decoded image
* \param width Buffer width in pixels.
* \param height Buffer height in pixels.
* \param bpp Number of bits per pixels that the buffer stores.
*/
void RGB565toBGR555( uint8_t *fileSource, uint8_t *fileDestination, uint32_t width, uint32_t height, uint8_t bpp )
{
uint32_t i;
uint32_t j;
uint32_t row;
for (i=0; i < height*(bpp/8); i++)
{
row = (i*width*(bpp/8));
for (j=0; j <= width*(bpp/8); j+=2)
{
fileDestination[row+j] = ((fileSource[row+j+1]>>3)&0x1F)
| (fileSource[row+j]&0xE0);
fileDestination[row+j+1] = (fileSource[row+j+1]&0x03)
| ((fileSource[row+j]&0x1F)<<2);
}
}
}
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/board_cstartup_gnu.S
+283
View File
@@ -0,0 +1,283 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
#define AIC 0xFC06E000
#define AIC_IVR 0x10
#define AIC_EOICR 0x38
#define SAIC 0xFC068400
#define AIC_FVR 0x14
#define IRQ_STACK_SIZE 8*3*4
#define FIQ_STACK_SIZE 8*3*4
#define MODE_MSK 0x1F
#define ARM_MODE_ABT 0x17
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define ARM_MODE_SYS 0x1F
#define I_BIT 0x80
#define F_BIT 0x40
#define REG_SFR_AICREDIR 0xF8028054
#define REG_SFR_UID 0xF8028050
#define AICREDIR_KEY 0x5F67B102
//------------------------------------------------------------------------------
// Startup routine
//------------------------------------------------------------------------------
.align 4
.arm
/* Exception vectors
*******************/
.section .vectors, "a", %progbits
resetVector:
ldr pc, =resetHandler /* Reset */
undefVector:
b undefVector /* Undefined instruction */
swiVector:
b swiVector /* Software interrupt */
prefetchAbortVector:
b prefetchAbortVector /* Prefetch abort */
dataAbortVector:
b dataAbortVector /* Data abort */
reservedVector:
b reservedVector /* Reserved for future use */
irqVector:
b irqHandler /* Interrupt */
fiqVector:
b fiqHandler /* Fast interrupt */
//------------------------------------------------------------------------------
/// Handles a fast interrupt request by branching to the address defined in the
/// AIC.
//------------------------------------------------------------------------------
fiqHandler:
SUB lr, lr, #4
STMFD sp!, {lr}
/* MRS lr, SPSR */
STMFD sp!, {r0}
/* Write in the IVR to support Protect Mode */
LDR lr, =SAIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]
/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SVC
STMFD sp!, {r1-r3, r4, r12, lr}
MOV r14, pc
BX r0
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
/* Acknowledge interrupt */
LDR lr, =SAIC
STR lr, [r14, #AIC_EOICR]
/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0}
/* MSR SPSR_cxsf, lr*/
LDMIA sp!, {pc}^
//------------------------------------------------------------------------------
/// Handles incoming interrupt requests by branching to the corresponding
/// handler, as defined in the AIC. Supports interrupt nesting.
//------------------------------------------------------------------------------
irqHandler:
/* Save interrupt context on the stack to allow nesting */
/* Save interrupt context on the stack to allow nesting */
SUB lr, lr, #4
STMFD sp!, {lr}
MRS lr, SPSR
STMFD sp!, {r0, lr}
/* Write in the IVR to support Protect Mode */
LDR lr, =AIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]
/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SVC
STMFD sp!, {r1-r3, r4, r12, lr}
/* Check for 8-byte alignment and save lr plus a */
/* word to indicate the stack adjustment used (0 or 4) */
AND r1, sp, #4
SUB sp, sp, r1
STMFD sp!, {r1, lr}
BLX r0
LDMIA sp!, {r1, lr}
ADD sp, sp, r1
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
/* Acknowledge interrupt */
LDR lr, =AIC
STR lr, [r14, #AIC_EOICR]
/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0, lr}
MSR SPSR_cxsf, lr
LDMIA sp!, {pc}^
//------------------------------------------------------------------------------
/// Initializes the chip and branches to the main() function.
//------------------------------------------------------------------------------
.section .textEntry
.global entry
entry:
resetHandler:
CPSIE A
/* Enable VFP */
/* - Enable access to CP10 and CP11 in CP15.CACR */
//mrc p15, 0, r0, c1, c0, 2
//orr r0, r0, #0xf00000
//mcr p15, 0, r0, c1, c0, 2
/* - Enable access to CP10 and CP11 in CP15.NSACR */
/* - Set FPEXC.EN (B30) */
//fmrx r0, fpexc
//orr r0, r0, #0x40000000
//fmxr fpexc, r0
/* Useless instruction for referencing the .vectors section */
ldr r0, =resetVector
/* Set pc to actual code location (i.e. not in remap zone) */
ldr pc, =1f
/* Initialize the prerelocate segment */
1:
ldr r0, =_efixed
ldr r1, =_sprerelocate
ldr r2, =_eprerelocate
1:
cmp r1, r2
ldrcc r3, [r0], #4
strcc r3, [r1], #4
bcc 1b
/* Perform low-level initialization of the chip using LowLevelInit() */
ldr sp, =_cstack
stmfd sp!, {r0}
ldr r0, =LowLevelInit
blx r0
/* Initialize the postrelocate segment */
ldmfd sp!, {r0}
ldr r1, =_spostrelocate
ldr r2, =_epostrelocate
1:
cmp r1, r2
ldrcc r3, [r0], #4
strcc r3, [r1], #4
bcc 1b
/* Clear the zero segment */
ldr r0, =_szero
ldr r1, =_ezero
mov r2, #0
1:
cmp r0, r1
strcc r2, [r0], #4
bcc 1b
MRS r0, cpsr
/* Set up the fast interrupt stack pointer.*/
bic r0, r0, #MODE_MSK
orr r0, r0, #ARM_MODE_FIQ
msr cpsr_c, r0
ldr sp, =_fiqstack
bic sp,sp,#0x7
/* Set up the normal interrupt stack pointer.*/
bic r0, r0, #MODE_MSK
orr r0, r0, #ARM_MODE_IRQ
msr cpsr_c, r0
ldr sp, =_irqstack
bic sp,sp,#0x7
/* Set up the stack pointer.*/
bic r0 ,r0, #MODE_MSK
orr r0 ,r0, #ARM_MODE_SYS
msr cpsr_c, r0
ldr sp, =_sysstack
bic sp,sp,#0x7
bic r0 ,r0, #MODE_MSK
orr r0 ,r0, #ARM_MODE_SVC
msr cpsr_c, r0
ldr sp, =_cstack
bic sp,sp,#0x7
// Redirect FIQ to IRQ
LDR r0, =AICREDIR_KEY
LDR r1, = REG_SFR_UID
LDR r2, = REG_SFR_AICREDIR
LDR r3,[r1]
EORS r0, r0, r3
ORRS r0, r0, #0x01
STR r0, [r2]
/*Initialize the C library */
ldr r3, =__libc_init_array
mov lr, pc
bx r3
/* Branch to main()
******************/
ldr r0, =main
blx r0
/* Loop indefinitely when program is finished */
1:
b 1b
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/board_cstartup_iar.s
+313
View File
@@ -0,0 +1,313 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*
IAR startup file for SAMA5D4X microcontrollers.
*/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION IRQ_STACK:DATA:NOROOT(2)
SECTION FIQ_STACK:DATA:NOROOT(2)
SECTION UND_STACK:DATA:NOROOT(2)
SECTION ABT_STACK:DATA:NOROOT(2)
SECTION CSTACK:DATA:NOROOT(3)
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#define __ASSEMBLY__
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
#define AIC 0xFC06E000
#define AIC_IVR 0x10
#define AIC_EOICR 0x38
#define L2CC_CR 0x00A00100
#define REG_SFR_AICREDIR 0xF8028054
#define REG_SFR_UID 0xF8028050
#define AICREDIR_KEY 0x5F67B102
MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
#define ARM_MODE_ABT 0x17
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define ARM_MODE_SYS 0x1F
#define ARM_MODE_UND 0x1B
#define I_BIT 0x80
#define F_BIT 0x40
//------------------------------------------------------------------------------
// Startup routine
//------------------------------------------------------------------------------
/*
Exception vectors
*/
SECTION .vectors:CODE:NOROOT(2)
PUBLIC resetVector
PUBLIC IRQ_Handler
PUBLIC FIQ_Handler
EXTERN Undefined_C_Handler
EXTERN SWI_Handler
EXTERN Prefetch_C_Handler
EXTERN Abort_C_Handler
ARM
__iar_init$$done: ; The interrupt vector is not needed
; until after copy initialization is done
resetVector:
; All default exception handlers (except reset) are
; defined as weak symbol definitions.
; If a handler is defined by the application it will take precedence.
LDR pc, =resetHandler ; Reset
LDR pc, Undefined_Addr ; Undefined instructions
LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)
LDR pc, Prefetch_Addr ; Prefetch abort
LDR pc, Abort_Addr ; Data abort
B . ; RESERVED
LDR PC,IRQ_Addr ; 0x18 IRQ
LDR PC,FIQ_Addr ; 0x1c FIQ
Undefined_Addr: DCD Undefined_C_Handler
SWI_Addr: DCD SWI_Handler
Abort_Addr: DCD Abort_C_Handler
Prefetch_Addr: DCD Prefetch_C_Handler
IRQ_Addr: DCD IRQ_Handler
FIQ_Addr: DCD FIQ_Handler
/*
Handles incoming interrupt requests by branching to the corresponding
handler, as defined in the AIC. Supports interrupt nesting.
*/
IRQ_Handler:
/* Save interrupt context on the stack to allow nesting */
SUB lr, lr, #4
STMFD sp!, {lr}
MRS lr, SPSR
STMFD sp!, {r0, lr}
/* Write in the IVR to support Protect Mode */
LDR lr, =AIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]
/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SVC
STMFD sp!, {r1-r3, r4, r12, lr}
/* Check for 8-byte alignment and save lr plus a */
/* word to indicate the stack adjustment used (0 or 4) */
AND r1, sp, #4
SUB sp, sp, r1
STMFD sp!, {r1, lr}
BLX r0
LDMIA sp!, {r1, lr}
ADD sp, sp, r1
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
/* Acknowledge interrupt */
LDR lr, =AIC
STR lr, [r14, #AIC_EOICR]
/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0, lr}
MSR SPSR_cxsf, lr
LDMIA sp!, {pc}^
/*
After a reset, execution starts here, the mode is ARM, supervisor
with interrupts disabled.
Initializes the chip and branches to the main() function.
*/
SECTION .cstartup:CODE:NOROOT(2)
PUBLIC resetHandler
EXTERN LowLevelInit
EXTERN ?main
REQUIRE resetVector
EXTERN CP15_InvalidateBTB
EXTERN CP15_InvalidateTranslationTable
EXTERN CP15_InvalidateIcache
EXTERN CP15_InvalidateDcacheBySetWay
ARM
resetHandler:
LDR r4, =SFE(CSTACK) ; End of SVC stack
BIC r4,r4,#0x7 ; Make sure SP is 8 aligned
MOV sp, r4
;; Set up the normal interrupt stack pointer.
MSR CPSR_c, #(ARM_MODE_IRQ | F_BIT | I_BIT)
LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
;; Set up the fast interrupt stack pointer.
MSR CPSR_c, #(ARM_MODE_FIQ | F_BIT | I_BIT)
LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
MSR CPSR_c, #(ARM_MODE_ABT | F_BIT | I_BIT)
LDR sp, =SFE(ABT_STACK) ; End of ABT_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
MSR CPSR_c, #(ARM_MODE_UND | F_BIT | I_BIT)
LDR sp, =SFE(UND_STACK) ; End of UND_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
MSR CPSR_c, #(ARM_MODE_SYS | F_BIT | I_BIT)
LDR sp, =SFE(CSTACK-0x3000) ; 0x1000 bytes of SYS stack
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
MSR CPSR_c, #(ARM_MODE_SVC | F_BIT | I_BIT)
CPSIE A
/* Enable VFP */
/* - Enable access to CP10 and CP11 in CP15.CACR */
MRC p15, 0, r0, c1, c0, 2
ORR r0, r0, #0xf00000
MCR p15, 0, r0, c1, c0, 2
/* - Enable access to CP10 and CP11 in CP15.NSACR */
/* - Set FPEXC.EN (B30) */
#ifdef __ARMVFP__
MOV r3, #0x40000000
VMSR FPEXC, r3
#endif
// Redirect FIQ to IRQ
LDR r0, =AICREDIR_KEY
LDR r1, = REG_SFR_UID
LDR r2, = REG_SFR_AICREDIR
LDR r3,[r1]
EORS r0, r0, r3
ORRS r0, r0, #0x01
STR r0, [r2]
/* Perform low-level initialization of the chip using LowLevelInit() */
LDR r0, =LowLevelInit
BLX r0
MRC p15, 0, r0, c1, c0, 0 ; Read CP15 Control Regsiter into r0
TST r0, #0x1 ; Is the MMU enabled?
BICNE r0, r0, #0x1 ; Clear bit 0
TST r0, #0x4 ; Is the Dcache enabled?
BICNE r0, r0, #0x4 ; Clear bit 2
MCRNE p15, 0, r0, c1, c0, 0 ; Write value back
// Disbale L2 cache
LDR r1,=L2CC_CR
MOV r2,#0
STR r2, [r1]
DMB
BL CP15_InvalidateTranslationTable
BL CP15_InvalidateBTB
BL CP15_InvalidateIcache
BL CP15_InvalidateDcacheBySetWay
DMB
ISB
/* Branch to main() */
LDR r0, =?main
BLX r0
/* Loop indefinitely when program is finished */
loop4:
B loop4
;------------------------------------------------------------------------------
;- Function : FIQ_Handler
;- Treatments : FIQ Controller Interrupt Handler.
;- Called Functions : AIC_IVR[interrupt]
;------------------------------------------------------------------------------
SAIC DEFINE 0xFC068400
AIC_FVR DEFINE 0x14
SECTION .text:CODE:NOROOT(2)
ARM
FIQ_Handler:
/* Save interrupt context on the stack to allow nesting */
SUB lr, lr, #4
STMFD sp!, {lr}
/* MRS lr, SPSR */
STMFD sp!, {r0}
/* Write in the IVR to support Protect Mode */
LDR lr, =SAIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]
/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SVC
STMFD sp!, {r1-r3, r4, r12, lr}
MOV r14, pc
BX r0
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
/* Acknowledge interrupt */
LDR lr, =SAIC
STR lr, [r14, #AIC_EOICR]
/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0}
/* MSR SPSR_cxsf, lr */
LDMIA sp!, {pc}^
END
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/board_lowlevel.c
+529
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/board_memories.c
+476
View File
@@ -0,0 +1,476 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 20143, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup ddrd_module
*
* The DDR/SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises
* four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved
* to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol.
*
* \section ddr2 Configures DDR2
*
* The DDR2-SDRAM devices are initialized by the following sequence:
* <ul>
* <li> EBI Chip Select 1 is assigned to the DDR2SDR Controller, Enable DDR2 clock x2 in PMC.</li>
* <li> Step 1: Program the memory device type</li>
* <li> Step 2:
* -# Program the features of DDR2-SDRAM device into the Configuration Register.
* -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T0PR.
* -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T1PR.
* -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T2PR. </li>
* <li> Step 3: An NOP command is issued to the DDR2-SDRAM to enable clock. </li>
* <li> Step 4: An NOP command is issued to the DDR2-SDRAM </li>
* <li> Step 5: An all banks precharge command is issued to the DDR2-SDRAM. </li>
* <li> Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose between commercialor high temperature operations.</li>
* <li> Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set all registers to 0. </li>
* <li> Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL.</li>
* <li> Step 9: Program DLL field into the Configuration Register.</li>
* <li> Step 10: A Mode Register set (MRS) cycle is issued to reset DLL.</li>
* <li> Step 11: An all banks precharge command is issued to the DDR2-SDRAM.</li>
* <li> Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register.</li>
* <li> Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset).</li>
* <li> Step 14: A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices.</li>
* <li> Step 15: Program OCD field into the Configuration Register to high (OCD calibration default). </li>
* <li> Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.</li>
* <li> Step 17: Program OCD field into the Configuration Register to low (OCD calibration mode exit).</li>
* <li> Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.</li>
* <li> Step 19,20: A mode Normal command is provided. Program the Normal mode into Mode Register.</li>
* <li> Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a refresh every 15.625 or 7.81. </li>
* </ul>
*/
/*@{*/
/*@}*/
/** \addtogroup sdram_module
*
* \section sdram Configures SDRAM
*
* The SDR-SDRAM devices are initialized by the following sequence:
* <ul>
* <li> EBI Chip Select 1 is assigned to the DDR2SDR Controller, Enable DDR2 clock x2 in PMC.</li>
* <li> Step 1. Program the memory device type into the Memory Device Register</li>
* <li> Step 2. Program the features of the SDR-SDRAM device into the Timing Register and into the Configuration Register.</li>
* <li> Step 3. For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low-power Register.</li>
* <li> Step 4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode Register, the application must
* set Mode to 1 in the Mode Register. Perform a write access to any SDR-SDRAM address to acknowledge this command.
* Now the clock which drives SDR-SDRAM device is enabled.</li>
* <li> Step 5. An all banks precharge command is issued to the SDR-SDRAM. Program all banks precharge command into Mode Register, the application must set Mode to 2 in the
* Mode Register . Perform a write access to any SDRSDRAM address to acknowledge this command.</li>
* <li> Step 6. Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into Mode Register, the application must set Mode to 4 in the Mode Register.
* Once in the idle state, two AUTO REFRESH cycles must be performed.</li>
* <li> Step 7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRSDRAM
* devices, in particular CAS latency and burst length. </li>
* <li> Step 8. For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). The write
* address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0 </li>
* <li> Step 9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and perform a write access at any location in the SDRAM to acknowledge this command.</li>
* <li> Step 10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register </li>
* </ul>
*/
/*@{*/
/*@}*/
/**
* \file
*
* Implementation of memories configuration on board.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Changes the mapping of the chip so that the remap area mirrors the
* internal ROM or the EBI CS0.
*/
void BOARD_RemapRom( void )
{
AXIMX->AXIMX_REMAP = 0;
}
/**
* \brief Changes the mapping of the chip so that the remap area mirrors the
* internal RAM.
*/
void BOARD_RemapRam( void )
{
AXIMX->AXIMX_REMAP = AXIMX_REMAP_REMAP0;
}
/**
* \brief Initialize Vdd EBI drive
* \param 0: 1.8V 1: 3.3V
*/
void BOARD_ConfigureVddMemSel( uint8_t VddMemSel )
{
}
#define DDR2_BA0(r) (1 << (26 + r))
#define DDR2_BA1(r) (1 << (27 + r))
#define H64MX_DDR_SLAVE_PORT0 3
static void matrix_configure_slave_ddr(void)
{
int ddr_port;
/* Disable write protection */
MATRIX0->MATRIX_WPMR = MPDDRC_WPMR_WPKEY_PASSWD;
/* Partition internal SRAM */
MATRIX0->MATRIX_SSR[11] = 0;
MATRIX0->MATRIX_SRTSR[11] = 0x05;
MATRIX0->MATRIX_SASSR[11] = 0x04;
ddr_port = 1;
/* Partition external DDR */
/* DDR port 0 not used from NWd */
for (ddr_port = 1 ; ddr_port < 8 ; ddr_port++) {
MATRIX0->MATRIX_SSR[H64MX_DDR_SLAVE_PORT0 + ddr_port] = 0x00FFFFFF;
MATRIX0->MATRIX_SRTSR[H64MX_DDR_SLAVE_PORT0 + ddr_port] = 0x0000000F;
MATRIX0->MATRIX_SASSR[H64MX_DDR_SLAVE_PORT0 + ddr_port] = 0x0000FFFF;
}
}
#define MATRIX_KEY_VAL (0x4D4154u)
static void matrix_configure_slave_nand(void)
{
/* Disable write protection */
MATRIX0->MATRIX_WPMR = MATRIX_WPMR_WPKEY(MATRIX_KEY_VAL);
MATRIX1->MATRIX_WPMR = MATRIX_WPMR_WPKEY(MATRIX_KEY_VAL);
/* Partition internal SRAM */
MATRIX0->MATRIX_SSR[11] = 0x00010101;
MATRIX0->MATRIX_SRTSR[11] = 0x05;
MATRIX0->MATRIX_SASSR[11] = 0x05;
MATRIX1->MATRIX_SRTSR[3] = 0xBBBBBBBB;
MATRIX1->MATRIX_SSR[3] = 0x00FFFFFF;
MATRIX1->MATRIX_SASSR[3] = 0xBBBBBBBB;
MATRIX1->MATRIX_SRTSR[4] = 0x01;
MATRIX1->MATRIX_SSR[4] = 0x00FFFFFF;
MATRIX1->MATRIX_SASSR[4] = 0x01;
MATRIX1->MATRIX_MEIER = 0x3FF;
}
/**
* \brief Configures DDR2 (MT47H128M16RT 128MB/ MT47H64M16HR)
MT47H64M16HR : 8 Meg x 16 x 8 banks
Refresh count: 8K
Row address: A[12:0] (8K)
Column address A[9:0] (1K)
Bank address BA[2:0] a(24,25) (8)
*/
void BOARD_ConfigureDdram( void )
{
volatile uint8_t *pDdr = (uint8_t *) DDR_CS_ADDR;
volatile uint32_t i;
volatile uint32_t dummy_value;
matrix_configure_slave_ddr();
/* Enable DDR2 clock x2 in PMC */
PMC->PMC_PCER0 = (1 << (ID_MPDDRC));
PMC->PMC_SCER |= PMC_SCER_DDRCK;
/* MPDDRC I/O Calibration Register */
dummy_value = MPDDRC->MPDDRC_IO_CALIBR;
dummy_value &= ~MPDDRC_IO_CALIBR_RDIV_Msk;
dummy_value &= ~MPDDRC_IO_CALIBR_TZQIO_Msk;
dummy_value |= MPDDRC_IO_CALIBR_CALCODEP(7);
dummy_value |= MPDDRC_IO_CALIBR_CALCODEN(8);
dummy_value |= MPDDRC_IO_CALIBR_RDIV_RZQ_60_RZQ_50;
dummy_value |= MPDDRC_IO_CALIBR_TZQIO(5);
dummy_value |= MPDDRC_IO_CALIBR_EN_CALIB_ENABLE_CALIBRATION;
MPDDRC->MPDDRC_IO_CALIBR = dummy_value;
/* Step 1: Program the memory device type */
/* DBW = 0 (32 bits bus wide); Memory Device = 6 = DDR2-SDRAM = 0x00000006*/
MPDDRC->MPDDRC_MD = MPDDRC_MD_MD_DDR2_SDRAM | MPDDRC_MD_DBW_DBW_32_BITS;
MPDDRC->MPDDRC_RD_DATA_PATH = MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT_ONE_CYCLE;
/* Step 2: Program the features of DDR2-SDRAM device into the Timing Register.*/
MPDDRC->MPDDRC_CR = MPDDRC_CR_NR_14_ROW_BITS |
MPDDRC_CR_NC_10_COL_BITS |
MPDDRC_CR_CAS_DDR_CAS3 |
MPDDRC_CR_DLL_RESET_DISABLED |
MPDDRC_CR_DQMS_NOT_SHARED |
MPDDRC_CR_ENRDM_OFF |
MPDDRC_CR_NB_8_BANKS |
MPDDRC_CR_NDQS_DISABLED |
MPDDRC_CR_UNAL_SUPPORTED |
MPDDRC_CR_OCD_DDR2_EXITCALIB;
MPDDRC->MPDDRC_TPR0 = MPDDRC_TPR0_TRAS(8) // 40 ns
| MPDDRC_TPR0_TRCD(3) // 12.5 ns
| MPDDRC_TPR0_TWR(3) // 15 ns
| MPDDRC_TPR0_TRC(10) // 55 ns
| MPDDRC_TPR0_TRP(3) // 12.5 ns
| MPDDRC_TPR0_TRRD(2) // 8 ns
| MPDDRC_TPR0_TWTR(2) // 2 clock cycle
| MPDDRC_TPR0_TMRD(2); // 2 clock cycles
MPDDRC->MPDDRC_TPR1 = MPDDRC_TPR1_TRFC(23)
| MPDDRC_TPR1_TXSNR(25)
| MPDDRC_TPR1_TXSRD(200)
| MPDDRC_TPR1_TXP(2);
MPDDRC->MPDDRC_TPR2 = MPDDRC_TPR2_TXARD(8)
| MPDDRC_TPR2_TXARDS(2)
| MPDDRC_TPR2_TRPA(3)
| MPDDRC_TPR2_TRTP(2)
| MPDDRC_TPR2_TFAW(7);
/* DDRSDRC Low-power Register */
for (i = 0; i < 13300; i++) {
asm("nop");
}
/* Step 3: An NOP command is issued to the DDR2-SDRAM. Program the NOP command into
the Mode Register, the application must set MODE to 1 in the Mode Register. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD;
/* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
*pDdr = 0; /* Now clocks which drive DDR2-SDRAM device are enabled.*/
/* A minimum pause of 200 ¦Ìs is provided to precede any signal toggle. (6 core cycles per iteration, core is at 396MHz: min 13200 loops) */
for (i = 0; i < 13300; i++) {
asm("nop");
}
/* Step 4: An NOP command is issued to the DDR2-SDRAM */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD;
/* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/
*pDdr = 0; /* Now CKE is driven high.*/
/* wait 400 ns min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 5: An all banks precharge command is issued to the DDR2-SDRAM. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD;
/* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/
*pDdr = 0;
/* wait 400 ns min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose between commercialor high temperature operations. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA1(0))) = 0; /* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set all registers to 0. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA1(0) + DDR2_BA0(0))) = 0; /* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1.*/
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA0(0))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. */
/* An additional 200 cycles of clock are required for locking DLL */
for (i = 0; i < 10000; i++) {
asm("nop");
}
/* Step 9: Program DLL field into the Configuration Register.*/
MPDDRC->MPDDRC_CR |= MPDDRC_CR_DLL_RESET_ENABLED;
/* Step 10: A Mode Register set (MRS) cycle is issued to reset DLL. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD;
*(pDdr) = 0; /* The write address must be chosen so that BA[1:0] bits are set to 0. */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 11: An all banks precharge command is issued to the DDR2-SDRAM. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD;
*(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_RFSH_CMD;
*(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Configure 2nd CBR. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_RFSH_CMD;
*(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset). */
MPDDRC->MPDDRC_CR &= ~MPDDRC_CR_DLL_RESET_ENABLED;
/* Step 14: A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD;
*(pDdr) = 0; /* The write address must be chosen so that BA[1:0] are set to 0. */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 15: Program OCD field into the Configuration Register to high (OCD calibration default). */
MPDDRC->MPDDRC_CR |= MPDDRC_CR_OCD_DDR2_DEFAULT_CALIB;
/* Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA0(0))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.*/
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 17: Program OCD field into the Configuration Register to low (OCD calibration mode exit). */
MPDDRC->MPDDRC_CR &= ~(MPDDRC_CR_OCD_DDR2_DEFAULT_CALIB);
/* Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.*/
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA0(0))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.*/
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 19,20: A mode Normal command is provided. Program the Normal mode into Mode Register. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NORMAL_CMD;
*(pDdr) = 0;
/* Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a refresh every 15.625 ¦Ìs or 7.81 ¦Ìs.
With a 100MHz frequency, the refresh timer count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100MHz) = 781 i.e. 0x030d. */
/* For MT47H64M16HR, The refresh period is 64ms (commercial), This equates to an average
refresh rate of 7.8125¦Ìs (commercial), To ensure all rows of all banks are properly
refreshed, 8192 REFRESH commands must be issued every 64ms (commercial) */
/* ((64 x 10(^-3))/8192) x133 x (10^6) */
MPDDRC->MPDDRC_RTR = MPDDRC_RTR_COUNT(0x2b0); /* Set Refresh timer 7.8125 us*/
/* OK now we are ready to work on the DDRSDR */
/* wait for end of calibration */
for (i = 0; i < 500; i++) {
asm(" nop");
}
}
/**
* \brief Configures the EBI for Sdram (LPSDR Micron MT48H8M16) access.
*/
void BOARD_ConfigureSdram( void )
{
}
/** \brief Configures the EBI for NandFlash access at 133Mhz.
*/
void BOARD_ConfigureNandFlash( uint8_t busWidth )
{
PMC_EnablePeripheral(ID_HSMC);
matrix_configure_slave_nand();
HSMC->HSMC_CS_NUMBER[3].HSMC_SETUP = 0
| HSMC_SETUP_NWE_SETUP(2)
| HSMC_SETUP_NCS_WR_SETUP(2)
| HSMC_SETUP_NRD_SETUP(2)
| HSMC_SETUP_NCS_RD_SETUP(2);
HSMC->HSMC_CS_NUMBER[3].HSMC_PULSE = 0
| HSMC_PULSE_NWE_PULSE(7)
| HSMC_PULSE_NCS_WR_PULSE(7)
| HSMC_PULSE_NRD_PULSE(7)
| HSMC_PULSE_NCS_RD_PULSE(7);
HSMC->HSMC_CS_NUMBER[3].HSMC_CYCLE = 0
| HSMC_CYCLE_NWE_CYCLE(13)
| HSMC_CYCLE_NRD_CYCLE(13);
HSMC->HSMC_CS_NUMBER[3].HSMC_TIMINGS = HSMC_TIMINGS_TCLR(3)
| HSMC_TIMINGS_TADL(27)
| HSMC_TIMINGS_TAR(3)
| HSMC_TIMINGS_TRR(6)
| HSMC_TIMINGS_TWB(5)
| HSMC_TIMINGS_RBNSEL(3)
|(HSMC_TIMINGS_NFSEL);
HSMC->HSMC_CS_NUMBER[3].HSMC_MODE = HSMC_MODE_READ_MODE |
HSMC_MODE_WRITE_MODE |
((busWidth == 8 )? HSMC_MODE_DBW_BIT_8 :HSMC_MODE_DBW_BIT_16) |
HSMC_MODE_TDF_CYCLES(1);
}
void BOARD_ConfigureNorFlash( uint8_t busWidth )
{
uint32_t dbw;
PMC_EnablePeripheral(ID_HSMC);
if (busWidth == 8)
{
dbw = HSMC_MODE_DBW_BIT_8;
}
else {
dbw = HSMC_MODE_DBW_BIT_16;
}
/* Configure SMC, NCS0 is assigned to a norflash */
HSMC->HSMC_CS_NUMBER[0].HSMC_SETUP = 0x00020001;
HSMC->HSMC_CS_NUMBER[0].HSMC_PULSE = 0x0B0B0A0A;
HSMC->HSMC_CS_NUMBER[0].HSMC_CYCLE = 0x000E000B;
HSMC->HSMC_CS_NUMBER[0].HSMC_TIMINGS = 0x00000000;
HSMC->HSMC_CS_NUMBER[0].HSMC_MODE = HSMC_MODE_WRITE_MODE
| HSMC_MODE_READ_MODE
| dbw
| HSMC_MODE_EXNW_MODE_DISABLED
| HSMC_MODE_TDF_CYCLES(1);
}
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/dbg_util.c
+315
View File
@@ -0,0 +1,315 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
* Implement simple DBGU usage as stream receiver.
*/
/*-------------------------------
* Headers
*-------------------------------*/
#include <board.h>
/*-------------------------------
* Defines
*-------------------------------*/
/** Data RX timeout in binary start up */
#define TIMEOUT_RX_START (1000*20)
/** Data RX timeout default value */
#define TIMEOUT_RX (200)
/* ASCII Character Codes */
#define SOH 0x01
#define STX 0x02
#define EOT 0x04
#define CTRL_D 0x04 /**< Transfer Done */
#define ACK 0x06
#define NAK 0x15
#define CAN 0x18 /**< Cancel transfer */
#define CTRL_X 0x24
/* 1K XMODEM Parameters */
#define SOH_LENGTH 128
#define STX_LENGTH 1024
#define SOH_TIMEOUT 1000
/*-------------------------------
* Local functions
*-------------------------------*/
/**
* \brief Compute the CRC
*/
static uint16_t _GetCRC(uint8_t bByte, uint16_t wCrc)
{
int32_t cnt;
uint8_t newBit;
for (cnt = 7; cnt >= 0; cnt --)
{
newBit = ((wCrc >> 15) & 0x1) ^ ((bByte >> cnt) & 0x1);
wCrc <<= 1;
if (newBit) wCrc ^= (0x1021);
}
return wCrc;
}
/*-------------------------------
* Exported functions
*-------------------------------*/
/**
* \brief Receives byte with timeout.
* \param pByte pointer to locate received byte, can be NULL
* to discard data.
* \param timeOut timeout setting, in number of ticks.
*/
uint8_t DbgReceiveByte(uint8_t* pByte, uint32_t timeOut)
{
uint32_t tick;
uint32_t delay;
tick = GetTickCount();
while(1)
{
if (DBGU_IsRxReady())
{
uint8_t tmp = DBGU_GetChar();
if (pByte) *pByte = tmp;
return 1;
}
if (timeOut == 0)
{ /* Never timeout */
}
else
{
delay = GetDelayInTicks(tick, GetTickCount());
if (delay > timeOut)
{
return 0;
}
}
}
}
/**
* \brief Receives raw binary file through DBGU.
* \param bStart 1 to start a new data stream.
* \param address receiving data address
* \param maxSize max receive data size in bytes
* \return number of received bytes
*/
uint32_t DbgReceiveBinary(uint8_t bStart, uint32_t address, uint32_t maxSize)
{
volatile uint32_t tick0;
uint32_t delay;
uint8_t *pBuffer = (uint8_t*)address;
uint8_t xSign = 0;
uint32_t rxCnt = 0;
if (maxSize == 0) return 0;
if (bStart)
{
printf("\n\r-- Please start binary data in %d seconds:\n\r",
TIMEOUT_RX_START / 1000);
tick0 = GetTickCount();
while(1)
{
if (DBGU_IsRxReady())
{
pBuffer[rxCnt ++] = DBGU_GetChar();
DBGU_PutChar(' ');
break;
}
else
{
delay = GetDelayInTicks(tick0, GetTickCount());
if ((delay % 1000) == 0)
{
if (xSign == 0)
{
DBGU_PutChar('*');
xSign = 1;
}
}
else if (xSign)
{
xSign = 0;
}
if (delay > TIMEOUT_RX_START)
{
printf("\n\rRX timeout!\n\r");
return rxCnt;
}
}
}
}
/* Get data */
while(1)
{
tick0 = GetTickCount();
while(1)
{
if (DBGU_IsRxReady())
{
pBuffer[rxCnt ++] = DBGU_GetChar();
if ((rxCnt % (10*1024)) == 0)
{
DBGU_PutChar('.');
}
if (rxCnt >= maxSize)
{
/* Wait until file transfer finished */
return rxCnt;
}
break;
}
delay = GetDelayInTicks(tick0, GetTickCount());
if (delay > TIMEOUT_RX)
{
return rxCnt;
}
}
}
}
/**
* \brief Receives raw binary file through DBGU.
*
* \note When "CCC..", uses Ctrl + D to exit.
*
* \param pktBuffer 1K size packet buffer
* \param address receiving data address
* \param maxSize max receive data size in bytes
* \return number of received bytes
*/
uint32_t DbgReceive1KXModem(uint8_t* pktBuffer,
uint32_t address,
uint32_t maxSize)
{
uint8_t inChar;
uint32_t i, index = 0, pktLen = 0;
uint8_t pktNum = 0, prevPktNum = 0;
uint32_t error = 0;
uint16_t inCrc, myCrc;
uint8_t inCheckSum = 0xFF, checkSum = 0;
uint8_t *pBuffer = (uint8_t*)address;
uint32_t totalLen = 0;
DBGU_PutChar('C');
while (1)
{
if (!DbgReceiveByte(&inChar, SOH_TIMEOUT))
{
DBGU_PutChar('C');
continue;
}
/* Done */
if (EOT == inChar)
{
error = 0;
DBGU_PutChar(ACK);
break;
}
else if (CAN == inChar)
{
error = 2;
}
else if (CTRL_X == inChar)
{
error = 3;
}
else if (SOH == inChar)
{
pktLen = SOH_LENGTH;
}
else if (STX == inChar)
{
pktLen = STX_LENGTH;
}
else continue;
/* Get Packet Number */
if (!DbgReceiveByte(&pktNum, SOH_TIMEOUT)) error = 4;
/* Get 1's complement of packet number */
if (!DbgReceiveByte(&inChar, SOH_TIMEOUT)) error = 5;
/* Get 1 packet of information. */
checkSum = 0; myCrc = 0; index = 0;
for (i = 0; i < pktLen; i ++)
{
if (!DbgReceiveByte(&inChar, SOH_TIMEOUT)) error = 6;
checkSum += inChar;
myCrc = _GetCRC(inChar, myCrc);
if (pktNum != prevPktNum)
{
pktBuffer[index ++] = inChar;
}
}
/* Get CRC bytes */
if (!DbgReceiveByte(&inCheckSum, SOH_TIMEOUT)) error = 7;
inCrc = inCheckSum << 8;
if (!DbgReceiveByte(&inCheckSum, SOH_TIMEOUT)) error = 7;
inCrc += inCheckSum;
/* If CRC error, NAK */
if (error || (inCrc != myCrc))
{
DBGU_PutChar(NAK);
error = 0;
}
/* Save packet, ACK and next */
else
{
prevPktNum = pktNum;
/* Buffer full? */
if (totalLen + pktLen > maxSize)
{
/* Copy until buffer full? */
/* Stop transfer */
DBGU_PutChar(CAN);
return totalLen;
}
/* Copy the packet */
for (i = 0; i < pktLen; i ++)
{
pBuffer[totalLen + i] = pktBuffer[i];
}
totalLen += pktLen;
DBGU_PutChar(ACK);
}
}
return totalLen;
}
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/dbgu_console.c
+475
View File
@@ -0,0 +1,475 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implements DBGU console.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <stdio.h>
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/** The Pheripheral has no HW ID */
#define ID_NOTUSED 0xFF
/** Usart Hw ID (ID_USART0) */
#define CONSOLE_ID (pDbgPort->bID)
/** Usart Hw interface used by the console (USART0). */
#define CONSOLE_DBGU ((Dbgu*)pDbgPort->pHw)
/** Pins description list */
#define CONSOLE_PINLIST (pDbgPort->pPioList)
/** Pins description list size */
#define CONSOLE_PINLISTSIZE (pDbgPort->bPioListSize)
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/**
* Debug port struct
*/
typedef struct _DbgPort {
const void* pHw;
const Pin* pPioList;
const uint8_t bPioListSize;
const uint8_t bID;
} sDbgPort;
/*----------------------------------------------------------------------------
* Variables
*----------------------------------------------------------------------------*/
/** Pins for DBGU */
static const Pin pinsDbgu[] = {PINS_DBGU};
/** Pins for USART0 */
static const Pin pinsUs0[] = {PIN_USART0_TXD, PIN_USART0_RXD};
/** Pins for USART1 */
static const Pin pinsUs1[] = {PIN_USART1_TXD, PIN_USART1_RXD};
/** Pins for USART3 */
static const Pin pinsUs3[] = {PIN_USART3_TXD, PIN_USART3_RXD};
/** Uses DBGU as debug port */
static sDbgPort dbgpDbgu =
{
DBGU,
pinsDbgu, PIO_LISTSIZE(pinsDbgu),
ID_DBGU
};
/** Uses USART0 as debug port */
static sDbgPort dbgpUs0 =
{
USART0,
pinsUs0, PIO_LISTSIZE(pinsUs0),
ID_USART0
};
/** Uses USART0 as debug port */
static sDbgPort dbgpUs1 =
{
USART1,
pinsUs1, PIO_LISTSIZE(pinsUs1),
ID_USART1
};
/** Uses USART0 as debug port */
static sDbgPort dbgpUs3 =
{
USART3,
pinsUs3, PIO_LISTSIZE(pinsUs3),
ID_USART3
};
/** Current used debug port */
static sDbgPort *pDbgPort = &dbgpUs3;
/** Console initialize status */
uint8_t _bConsoleIsInitialized = 0;
/**
* \brief Select USART0 as DBGU port.
*/
void DBGU_ConsoleUseUSART0(void)
{
pDbgPort = &dbgpUs0;
_bConsoleIsInitialized = 0;
}
/**
* \brief Select USART1 as DBGU port.
*/
void DBGU_ConsoleUseUSART1(void)
{
pDbgPort = &dbgpUs1;
_bConsoleIsInitialized = 0;
}
/**
* \brief Select USART3 as DBGU port.
*/
void DBGU_ConsoleUseUSART3(void)
{
pDbgPort = &dbgpUs3;
_bConsoleIsInitialized = 0;
}
/**
* \brief Select DBGU as DBGU port.
*/
void DBGU_ConsoleUseDBGU(void)
{
pDbgPort = &dbgpDbgu;
_bConsoleIsInitialized = 0;
}
/**
* \brief Configures an DBGU peripheral with the specified parameters.
*
* \param baudrate Baudrate at which the DBGU should operate (in Hz).
* \param masterClock Frequency of the system master clock (in Hz).
*/
extern void DBGU_Configure( uint32_t baudrate, uint32_t masterClock)
{
/* Configure PIO */
PIO_Configure(CONSOLE_PINLIST, CONSOLE_PINLISTSIZE);
if ( ID_NOTUSED != CONSOLE_ID )
{
//PMC_SetPeriMaxClock(CONSOLE_ID, BOARD_MCK);
PMC_EnablePeripheral(CONSOLE_ID);
}
/* Configure mode register */
if (CONSOLE_DBGU!= DBGU ) {
CONSOLE_DBGU->DBGU_MR = DBGU_MR_CHMODE_NORM | DBGU_MR_PAR_NONE | US_MR_CHRL_8_BIT;
}
else {
CONSOLE_DBGU->DBGU_MR = DBGU_MR_CHMODE_NORM | DBGU_MR_PAR_NONE;
}
/* Reset and disable receiver & transmitter */
CONSOLE_DBGU->DBGU_CR = DBGU_CR_RSTRX | DBGU_CR_RSTTX;
CONSOLE_DBGU->DBGU_IDR = 0xFFFFFFFF;
CONSOLE_DBGU->DBGU_CR = DBGU_CR_RXDIS | DBGU_CR_TXDIS;
/* Configure baudrate */
CONSOLE_DBGU->DBGU_BRGR = (masterClock/2 / baudrate) / 16;
/* Enable receiver and transmitter */
CONSOLE_DBGU->DBGU_CR = DBGU_CR_RXEN | DBGU_CR_TXEN;
_bConsoleIsInitialized = 1 ;
#if defined(__GNUC__)
setvbuf(stdout, (char*)NULL, _IONBF, 0);
#endif
}
/**
* \brief Outputs a character on the DBGU line.
*
* \note This function is synchronous (i.e. uses polling).
* \param c Character to send.
*/
extern void DBGU_PutChar( uint8_t c )
{
if ( !_bConsoleIsInitialized )
{
DBGU_Configure(CONSOLE_BAUDRATE, BOARD_MCK);
}
/* Wait for the transmitter to be ready */
while ( (CONSOLE_DBGU->DBGU_SR & DBGU_SR_TXEMPTY) == 0 ) ;
/* Send character */
CONSOLE_DBGU->DBGU_THR=c ;
}
/**
* \brief Input a character from the DBGU line.
*
* \note This function is synchronous
* \return character received.
*/
extern uint32_t DBGU_GetChar( void )
{
if ( !_bConsoleIsInitialized )
{
DBGU_Configure(CONSOLE_BAUDRATE, BOARD_MCK);
}
while ( (CONSOLE_DBGU->DBGU_SR & DBGU_SR_RXRDY) == 0 ) ;
return CONSOLE_DBGU->DBGU_RHR ;
}
/**
* \brief Check if there is Input from DBGU line.
*
* \return true if there is Input.
*/
extern uint32_t DBGU_IsRxReady( void )
{
if ( !_bConsoleIsInitialized )
{
//DBGU_Configure( CONSOLE_BAUDRATE, BOARD_MCK ) ;
}
return (CONSOLE_DBGU->DBGU_SR & DBGU_SR_RXRDY) > 0 ;
}
/**
* Displays the content of the given frame on the DBGU.
*
* \param pucFrame Pointer to the frame to dump.
* \param dwSize Buffer size in bytes.
*/
extern void DBGU_DumpFrame( uint8_t* pucFrame, uint32_t dwSize )
{
uint32_t dw ;
for ( dw=0 ; dw < dwSize ; dw++ )
{
printf( "%02X ", pucFrame[dw] ) ;
}
printf( "\n\r" ) ;
}
/**
* Displays the content of the given buffer on the DBGU.
*
* \param pucBuffer Pointer to the buffer to dump.
* \param dwSize Buffer size in bytes.
* \param dwAddress Start address to display
*/
extern void DBGU_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, uint32_t dwAddress )
{
uint32_t i ;
uint32_t j ;
uint32_t dwLastLineStart ;
uint8_t* pucTmp ;
for ( i=0 ; i < (dwSize / 16) ; i++ )
{
printf( "0x%08X: ", (unsigned int )(dwAddress + ( i * 16) )) ;
pucTmp = (uint8_t*)&pucBuffer[i*16] ;
for ( j=0 ; j < 4 ; j++ )
{
printf( "%02X%02X%02X%02X ", pucTmp[0], pucTmp[1], pucTmp[2], pucTmp[3] ) ;
pucTmp += 4 ;
}
pucTmp=(uint8_t*)&pucBuffer[i*16] ;
for ( j=0 ; j < 16 ; j++ )
{
DBGU_PutChar( *pucTmp++ ) ;
}
printf( "\n\r" ) ;
}
if ( (dwSize%16) != 0 )
{
dwLastLineStart=dwSize - (dwSize%16) ;
printf( "0x%08X: ", (unsigned int ) (dwAddress + dwLastLineStart )) ;
for ( j=dwLastLineStart ; j < dwLastLineStart+16 ; j++ )
{
if ( (j!=dwLastLineStart) && (j%4 == 0) )
{
printf( " " ) ;
}
if ( j < dwSize )
{
printf( "%02X", pucBuffer[j] ) ;
}
else
{
printf(" ") ;
}
}
printf( " " ) ;
for ( j=dwLastLineStart ; j < dwSize ; j++ )
{
DBGU_PutChar( pucBuffer[j] ) ;
}
printf( "\n\r" ) ;
}
}
/**
* Reads an integer
*
* \param pdwValue Pointer to the uint32_t variable to contain the input value.
*/
extern uint32_t DBGU_GetInteger( uint32_t* pdwValue )
{
uint8_t ucKey ;
uint8_t ucNbNb=0 ;
uint32_t dwValue=0 ;
while ( 1 )
{
ucKey=DBGU_GetChar() ;
DBGU_PutChar( ucKey ) ;
if ( ucKey >= '0' && ucKey <= '9' )
{
dwValue = (dwValue * 10) + (ucKey - '0');
ucNbNb++ ;
}
else
{
if ( ucKey == 0x0D || ucKey == ' ' )
{
if ( ucNbNb == 0 )
{
printf( "\n\rWrite a number and press ENTER or SPACE!\n\r" ) ;
return 0 ;
}
else
{
printf( "\n\r" ) ;
*pdwValue=dwValue ;
return 1 ;
}
}
else
{
printf( "\n\r'%c' not a number!\n\r", ucKey ) ;
return 0 ;
}
}
}
}
/**
* Reads an integer and check the value
*
* \param pdwValue Pointer to the uint32_t variable to contain the input value.
* \param dwMin Minimum value
* \param dwMax Maximum value
*/
extern uint32_t DBGU_GetIntegerMinMax( uint32_t* pdwValue, uint32_t dwMin, uint32_t dwMax )
{
uint32_t dwValue=0 ;
if ( DBGU_GetInteger( &dwValue ) == 0 )
{
return 0 ;
}
if ( dwValue < dwMin || dwValue > dwMax )
{
printf( "\n\rThe number have to be between %u and %u\n\r", (unsigned int)dwMin, (unsigned int)dwMax ) ;
return 0 ;
}
printf( "\n\r" ) ;
*pdwValue = dwValue ;
return 1 ;
}
/**
* Reads an hexadecimal number
*
* \param pdwValue Pointer to the uint32_t variable to contain the input value.
*/
extern uint32_t DBGU_GetHexa32( uint32_t* pdwValue )
{
uint8_t ucKey ;
uint32_t dw = 0 ;
uint32_t dwValue = 0 ;
for ( dw=0 ; dw < 8 ; dw++ )
{
ucKey = DBGU_GetChar() ;
DBGU_PutChar( ucKey ) ;
if ( ucKey >= '0' && ucKey <= '9' )
{
dwValue = (dwValue * 16) + (ucKey - '0') ;
}
else
{
if ( ucKey >= 'A' && ucKey <= 'F' )
{
dwValue = (dwValue * 16) + (ucKey - 'A' + 10) ;
}
else
{
if ( ucKey >= 'a' && ucKey <= 'f' )
{
dwValue = (dwValue * 16) + (ucKey - 'a' + 10) ;
}
else
{
printf( "\n\rIt is not a hexa character!\n\r" ) ;
return 0 ;
}
}
}
}
printf("\n\r" ) ;
*pdwValue = dwValue ;
return 1 ;
}
#if defined __ICCARM__ /* IAR Ewarm 5.41+ */
/**
* \brief Outputs a character on the DBGU.
*
* \param c Character to output.
*
* \return The character that was output.
*/
extern WEAK signed int putchar( signed int c )
{
DBGU_PutChar( c ) ;
return c ;
}
#endif // defined __ICCARM__
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/gmacb.c
+516
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/gmacd.c
+711
View File
File diff suppressed because it is too large Load Diff
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/hamming.c
+338
View File
@@ -0,0 +1,338 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Internal function
*----------------------------------------------------------------------------*/
/**
* Counts and return the number of bits set to '1' in the given byte.
* \param byte Byte to count.
*/
static uint8_t CountBitsInByte(uint8_t byte)
{
uint8_t count = 0;
while (byte > 0)
{
if (byte & 1)
{
count++;
}
byte >>= 1;
}
return count;
}
/**
* Counts and return the number of bits set to '1' in the given hamming code.
* \param code Hamming code.
*/
static uint8_t CountBitsInCode256(uint8_t *code)
{
return CountBitsInByte(code[0]) + CountBitsInByte(code[1]) + CountBitsInByte(code[2]);
}
/**
* Calculates the 22-bit hamming code for a 256-bytes block of data.
* \param data Data buffer to calculate code for.
* \param code Pointer to a buffer where the code should be stored.
*/
static void Compute256(const uint8_t *data, uint8_t *code)
{
uint32_t i;
uint8_t columnSum = 0;
uint8_t evenLineCode = 0;
uint8_t oddLineCode = 0;
uint8_t evenColumnCode = 0;
uint8_t oddColumnCode = 0;
// Xor all bytes together to get the column sum;
// At the same time, calculate the even and odd line codes
for (i=0; i < 256; i++)
{
columnSum ^= data[i];
// If the xor sum of the byte is 0, then this byte has no incidence on
// the computed code; so check if the sum is 1.
if ((CountBitsInByte(data[i]) & 1) == 1)
{
// Parity groups are formed by forcing a particular index bit to 0
// (even) or 1 (odd).
// Example on one byte:
//
// bits (dec) 7 6 5 4 3 2 1 0
// (bin) 111 110 101 100 011 010 001 000
// '---'---'---'----------.
// |
// groups P4' ooooooooooooooo eeeeeeeeeeeeeee P4 |
// P2' ooooooo eeeeeee ooooooo eeeeeee P2 |
// P1' ooo eee ooo eee ooo eee ooo eee P1 |
// |
// We can see that: |
// - P4 -> bit 2 of index is 0 --------------------'
// - P4' -> bit 2 of index is 1.
// - P2 -> bit 1 of index if 0.
// - etc...
// We deduce that a bit position has an impact on all even Px if
// the log2(x)nth bit of its index is 0
// ex: log2(4) = 2, bit2 of the index must be 0 (-> 0 1 2 3)
// and on all odd Px' if the log2(x)nth bit of its index is 1
// ex: log2(2) = 1, bit1 of the index must be 1 (-> 0 1 4 5)
//
// As such, we calculate all the possible Px and Px' values at the
// same time in two variables, evenLineCode and oddLineCode, such as
// evenLineCode bits: P128 P64 P32 P16 P8 P4 P2 P1
// oddLineCode bits: P128' P64' P32' P16' P8' P4' P2' P1'
//
evenLineCode ^= (255 - i);
oddLineCode ^= i;
}
}
// At this point, we have the line parities, and the column sum. First, We
// must caculate the parity group values on the column sum.
for (i=0; i < 8; i++)
{
if (columnSum & 1)
{
evenColumnCode ^= (7 - i);
oddColumnCode ^= i;
}
columnSum >>= 1;
}
// Now, we must interleave the parity values, to obtain the following layout:
// Code[0] = Line1
// Code[1] = Line2
// Code[2] = Column
// Line = Px' Px P(x-1)- P(x-1) ...
// Column = P4' P4 P2' P2 P1' P1 PadBit PadBit
code[0] = 0;
code[1] = 0;
code[2] = 0;
for (i=0; i < 4; i++)
{
code[0] <<= 2;
code[1] <<= 2;
code[2] <<= 2;
// Line 1
if ((oddLineCode & 0x80) != 0)
{
code[0] |= 2;
}
if ((evenLineCode & 0x80) != 0)
{
code[0] |= 1;
}
// Line 2
if ((oddLineCode & 0x08) != 0)
{
code[1] |= 2;
}
if ((evenLineCode & 0x08) != 0)
{
code[1] |= 1;
}
// Column
if ((oddColumnCode & 0x04) != 0)
{
code[2] |= 2;
}
if ((evenColumnCode & 0x04) != 0)
{
code[2] |= 1;
}
oddLineCode <<= 1;
evenLineCode <<= 1;
oddColumnCode <<= 1;
evenColumnCode <<= 1;
}
// Invert codes (linux compatibility)
code[0] = (~(uint32_t)code[0]);
code[1] = (~(uint32_t)code[1]);
code[2] = (~(uint32_t)code[2]);
TRACE_DEBUG("Computed code = %02X %02X %02X\n\r",
code[0], code[1], code[2]);
}
/**
* Verifies and corrects a 256-bytes block of data using the given 22-bits
* hamming code.
*
* \param data Data buffer to check.
* \param originalCode Hamming code to use for verifying the data.
*
* \return 0 if there is no error, otherwise returns a HAMMING_ERROR code.
*/
static uint8_t Verify256( uint8_t* pucData, const uint8_t* pucOriginalCode )
{
/* Calculate new code */
uint8_t computedCode[3] ;
uint8_t correctionCode[3] ;
Compute256( pucData, computedCode ) ;
/* Xor both codes together */
correctionCode[0] = computedCode[0] ^ pucOriginalCode[0] ;
correctionCode[1] = computedCode[1] ^ pucOriginalCode[1] ;
correctionCode[2] = computedCode[2] ^ pucOriginalCode[2] ;
TRACE_DEBUG( "Correction code = %02X %02X %02X\n\r", correctionCode[0], correctionCode[1], correctionCode[2] ) ;
// If all bytes are 0, there is no error
if ( (correctionCode[0] == 0) && (correctionCode[1] == 0) && (correctionCode[2] == 0) )
{
return 0 ;
}
/* If there is a single bit error, there are 11 bits set to 1 */
if ( CountBitsInCode256( correctionCode ) == 11 )
{
// Get byte and bit indexes
uint8_t byte = correctionCode[0] & 0x80;
byte |= (correctionCode[0] << 1) & 0x40;
byte |= (correctionCode[0] << 2) & 0x20;
byte |= (correctionCode[0] << 3) & 0x10;
byte |= (correctionCode[1] >> 4) & 0x08;
byte |= (correctionCode[1] >> 3) & 0x04;
byte |= (correctionCode[1] >> 2) & 0x02;
byte |= (correctionCode[1] >> 1) & 0x01;
uint8_t bit = (correctionCode[2] >> 5) & 0x04;
bit |= (correctionCode[2] >> 4) & 0x02;
bit |= (correctionCode[2] >> 3) & 0x01;
/* Correct bit */
printf("Correcting byte #%d at bit %d\n\r", byte, bit ) ;
pucData[byte] ^= (1 << bit) ;
return Hamming_ERROR_SINGLEBIT ;
}
/* Check if ECC has been corrupted */
if ( CountBitsInCode256( correctionCode ) == 1 )
{
return Hamming_ERROR_ECC ;
}
/* Otherwise, this is a multi-bit error */
else
{
return Hamming_ERROR_MULTIPLEBITS ;
}
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* Computes 3-bytes hamming codes for a data block whose size is multiple of
* 256 bytes. Each 256 bytes block gets its own code.
* \param data Data to compute code for.
* \param size Data size in bytes.
* \param code Codes buffer.
*/
void Hamming_Compute256x( const uint8_t *pucData, uint32_t dwSize, uint8_t* puCode )
{
TRACE_DEBUG("Hamming_Compute256x()\n\r");
while ( dwSize > 0 )
{
Compute256( pucData, puCode ) ;
pucData += 256;
puCode += 3;
dwSize -= 256;
}
}
/**
* Verifies 3-bytes hamming codes for a data block whose size is multiple of
* 256 bytes. Each 256-bytes block is verified with its own code.
*
* \return 0 if the data is correct, Hamming_ERROR_SINGLEBIT if one or more
* block(s) have had a single bit corrected, or either Hamming_ERROR_ECC
* or Hamming_ERROR_MULTIPLEBITS.
*
* \param data Data buffer to verify.
* \param size Size of the data in bytes.
* \param code Original codes.
*/
uint8_t Hamming_Verify256x( uint8_t* pucData, uint32_t dwSize, const uint8_t* pucCode )
{
uint8_t error ;
uint8_t result = 0 ;
TRACE_DEBUG( "Hamming_Verify256x()\n\r" ) ;
while ( dwSize > 0 )
{
error = Verify256( pucData, pucCode ) ;
if ( error == Hamming_ERROR_SINGLEBIT )
{
result = Hamming_ERROR_SINGLEBIT ;
}
else
{
if ( error )
{
return error ;
}
}
pucData += 256;
pucCode += 3;
dwSize -= 256;
}
return result ;
}

Some files were not shown because too many files have changed in this diff Show More