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ARMv7-R No_GIC Port Demo (#1236)

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Add ARM_CRx_No_GIC_Demo
This commit is contained in:
Rahul Kar
2024-08-11 19:07:30 +05:30
committed by GitHub
parent d3d6893489
commit 8582188293
151 changed files with 72639 additions and 0 deletions
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.github/.cSpellWords.txt
+1
View File
@@ -724,6 +724,7 @@ CMock
CNBTR
CNDA
CNDTR
CNOT
CNTALOAD
CNTAMAX
CNTBLOAD
.github/scripts/core_checker.py
+1
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@@ -307,6 +307,7 @@ FREERTOS_IGNORED_PATTERNS = [
r'FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/.*',
r'FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/.*',
r'FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/.*',
r'FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/.*',
r'FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/.*',
r'FreeRTOS/Demo/AVR32_UC3/.*',
r'FreeRTOS/Demo/AVR_ATMega4809_IAR/.*',
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.ccsproject
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.clang-format
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.cproject
+180
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.gitignore
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[Bb]uild
[Dd]ebug
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.project
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.vscode/CORTEX_NO_GIC_R5F_TI_RM57_HERCULES_GCC.code-workspace
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.dil
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.hcg
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/RM57L8xx.ccxml
+43
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="configuration_0">
<instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe">
<instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
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<property Type="choicelist" Value="1" id="Debug Probe Selection">
<choice Name="Select by serial number" value="0">
<property Type="stringfield" Value="HLR57L00" id="-- Enter the serial number"/>
</choice>
</property>
<platform XML_version="1.2" id="platform_0">
<instance XML_version="1.2" desc="RM57L8xx" href="devices/rm57l8xx.xml" id="RM57L8xx" xml="rm57l8xx.xml" xmlpath="devices"/>
</platform>
</connection>
</configuration>
</configurations>
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_RM57.h
+114
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/**********************************************************************************************************************
* FILE DESCRIPTION
* -------------------------------------------------------------------------------------------------------------------
* File: Device_RM57.c
* Project: Tms570_TIFEEDriver
* Module: TIFEEDriver
* Generator: None
*
* Description: This file defines the number of sectors.
*---------------------------------------------------------------------------------------------------------------------
* Author: Vishwanath Reddy
*---------------------------------------------------------------------------------------------------------------------
* Revision History
*---------------------------------------------------------------------------------------------------------------------
* Version Date Author Change ID Description
*---------------------------------------------------------------------------------------------------------------------
* 01.15.00 06Jun2014 Vishwanath Reddy Initial Version.
*********************************************************************************************************************/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*********************************************************************************************************************
* INCLUDES
*********************************************************************************************************************/
#ifndef DEVICE_RM57_H
#define DEVICE_RM57_H
/** @def DEVICE_CONFIGURATION_VERSION
* @brief Device Configuration Version
*
* @note Indicates the current version of the device files
*/
#define DEVICE_CONFIGURATION_VERSION \
0U /* Indicates the current version of the device files */
/** @def DEVICE_NUMBER_OF_FLASH_BANKS
* @brief Number of Flash Banks
*
* @note Defines the number of Flash Banks on the device
*/
#define DEVICE_NUMBER_OF_FLASH_BANKS \
1U /* Defines the number of Flash Banks on the device */
/** @def DEVICE_BANK_MAX_NUMBER_OF_SECTORS
* @brief Maximum number of Sectors
*
* @note Defines the maxium number of sectors in all banks
*/
#define DEVICE_BANK_MAX_NUMBER_OF_SECTORS \
32U /* Defines the maxium number of sectors in all banks */
/** @def DEVICE_BANK1_NUMBER_OF_SECTORS
* @brief Number of Sectors
*
* @note Defines the number of sectors in bank1
*/
#define DEVICE_BANK1_NUMBER_OF_SECTORS \
32U /* Defines the number of sectors in bank1 */
/** @def DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS
* @brief Number of Sectors
*
* @note Defines the number of Read Cycle Thresholds
*/
#define DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS \
4U /* Defines the number of Read Cycle Thresholds */
/* Include Files */
#ifndef _PLATFORM_TYPES_H_
#define _PLATFORM_TYPES_H_
#endif
#ifndef _L2FMC
#define _L2FMC
#endif
#include "F021.h"
#include "hal_stdtypes.h"
#include "Device_types.h"
#endif /* DEVICE_RM57_H */
/* End of File */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_header.h
+65
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/**********************************************************************************************************************
* FILE DESCRIPTION
* -------------------------------------------------------------------------------------------------------------------
* File: Device_header.h
* Project: Tms570_TIFEEDriver
* Module: TIFEEDriver
* Generator: None
*
* Description: This file includes the header file.
*---------------------------------------------------------------------------------------------------------------------
* Author: Vishwanath Reddy
*---------------------------------------------------------------------------------------------------------------------
* Revision History
*---------------------------------------------------------------------------------------------------------------------
* Version Date Author Change ID Description
*---------------------------------------------------------------------------------------------------------------------
* 01.15.00 06Jun2014 Vishwanath Reddy Initial Version.
*********************************************************************************************************************/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*********************************************************************************************************************
* INCLUDES
*********************************************************************************************************************/
#ifndef TI_FEE_DEVICEHEADER_H
#define TI_FEE_DEVICEHEADER_H
/* Uncomment the appropriate include file depending on the device you are using */
#include "Device_RM57.h"
/* End of file */
#endif
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_types.h
+133
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@@ -0,0 +1,133 @@
/**********************************************************************************************************************
* FILE DESCRIPTION
* -------------------------------------------------------------------------------------------------------------------
* File: Device_types.h
* Project: Tms570_TIFEEDriver
* Module: TIFEEDriver
* Generator: None
*
* Description: This file defines the structures.
*---------------------------------------------------------------------------------------------------------------------
* Author: Vishwanath Reddy
*---------------------------------------------------------------------------------------------------------------------
* Revision History
*---------------------------------------------------------------------------------------------------------------------
* Version Date Author Change ID Description
*---------------------------------------------------------------------------------------------------------------------
* 01.15.00 06Jun2014 Vishwanath Reddy Initial Version.
*********************************************************************************************************************/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*********************************************************************************************************************
* INCLUDES
*********************************************************************************************************************/
#ifndef DEVICE_TYPES_H
#define DEVICE_TYPES_H
#include "hal_stdtypes.h"
/* Enum to describe the type of error handling on the device */
typedef enum
{
Device_ErrorHandlingNone, /* Device has no error handling */
Device_ErrorHandlingParity, /* Device has parity error handling */
Device_ErrorHandlingEcc /* Device has ECC error handling */
} Device_FlashErrorCorrectionProcessType;
/* Enum to describe the ARM core on the device*/
typedef enum
{
Device_CoreNone, /* To indicate that the device has a single core */
Device_Arm7, /* To indicate that the device has a ARM7 core */
Device_CortexR4, /* To indicate that the device has a CortexR4 core */
Device_CortexM3 /* To indicate that the device has a CortexM3 core */
} Device_ArmCoreType;
/* Structure defines an individual sector within a bank */
typedef struct
{
Fapi_FlashSectorType Device_Sector; /* Sector number */
uint32 Device_SectorStartAddress; /* Starting address of the sector */
uint32 Device_SectorLength; /* Length of the sector */
uint32 Device_MaxWriteCycles; /* Number of cycles the sector is rated for */
uint32 Device_EccAddress;
uint32 Device_EccLength;
} Device_SectorType;
/* Structure defines an individual bank */
typedef struct
{
Fapi_FmcRegistersType * Device_ControlRegister;
Fapi_FlashBankType Device_Core; /* Core number for this bank */
Device_SectorType Device_SectorInfo[ DEVICE_BANK_MAX_NUMBER_OF_SECTORS ]; /* Array of
the
Sectors
within a
bank */
} Device_BankType;
/* Structure defines the Flash structure of the device */
typedef struct
{
uint8 Device_DeviceName[ 12 ]; /* Device name */
uint32 Device_EngineeringId; /* Device Engineering ID */
Device_FlashErrorCorrectionProcessType
Device_FlashErrorHandlingProcessInfo; /* Indicates
which
type
of bit
Error
handling
is on
the
device
*/
Device_ArmCoreType Device_MasterCore; /* Indicates the Master core type on the device
*/
boolean Device_SupportsInterrupts; /* Indicates if the device supports Flash
interrupts for processing Flash */
uint32 Device_NominalWriteTime; /* Nominal time for one write command operation in uS
*/
uint32 Device_MaximumWriteTime; /* Maximum time for one write command operation in uS
*/
Device_BankType Device_BankInfo[ DEVICE_NUMBER_OF_FLASH_BANKS ]; /* Array of Banks on
the device */
} Device_FlashType;
#endif /* DEVICE_TYPES_H */
/* End of File */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/MemMap.h
+39
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@@ -0,0 +1,39 @@
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __MEM_MAP_H__
#define __MEM_MAP_H__
#endif /* __MEM_MAP_H__ */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/adc.h
+344
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@@ -0,0 +1,344 @@
/** @file adc.h
* @brief ADC Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the ADC driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __ADC_H__
#define __ADC_H__
#include "reg_adc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* ADC General Definitions */
/** @def adcGROUP0
* @brief Alias name for ADC event group
*
* @note This value should be used for API argument @a group
*/
#define adcGROUP0 0U
/** @def adcGROUP1
* @brief Alias name for ADC group 1
*
* @note This value should be used for API argument @a group
*/
#define adcGROUP1 1U
/** @def adcGROUP2
* @brief Alias name for ADC group 2
*
* @note This value should be used for API argument @a group
*/
#define adcGROUP2 2U
/** @def ADC_12_BIT_MODE
* @brief Alias name for ADC 12-bit mode of operation
*/
#define ADC_12_BIT_MODE 0x80000000U
/** @enum adcResolution
* @brief Alias names for data resolution
* This enumeration is used to provide alias names for the data resolution:
* - 12 bit resolution
* - 10 bit resolution
* - 8 bit resolution
*/
enum adcResolution
{
ADC_12_BIT = 0x00000000U, /**< Alias for 12 bit data resolution */
ADC_10_BIT = 0x00000100U, /**< Alias for 10 bit data resolution */
ADC_8_BIT = 0x00000200U /**< Alias for 8 bit data resolution */
};
/** @enum adcFiFoStatus
* @brief Alias names for FiFo status
* This enumeration is used to provide alias names for the current FiFo states:
* - FiFo is not full
* - FiFo is full
* - FiFo overflow occurred
*/
enum adcFiFoStatus
{
ADC_FIFO_IS_NOT_FULL = 0U, /**< Alias for FiFo is not full */
ADC_FIFO_IS_FULL = 1U, /**< Alias for FiFo is full */
ADC_FIFO_OVERFLOW = 3U /**< Alias for FiFo overflow occurred */
};
/** @enum adcConversionStatus
* @brief Alias names for conversion status
* This enumeration is used to provide alias names for the current conversion states:
* - Conversion is not finished
* - Conversion is finished
*/
enum adcConversionStatus
{
ADC_CONVERSION_IS_NOT_FINISHED = 0U, /**< Alias for current conversion is not finished
*/
ADC_CONVERSION_IS_FINISHED = 8U /**< Alias for current conversion is finished */
};
/** @enum adc1HwTriggerSource
* @brief Alias names for hardware trigger source
* This enumeration is used to provide alias names for the hardware trigger sources:
*/
enum adc1HwTriggerSource
{
ADC1_EVENT = 0U, /**< Alias for event pin */
ADC1_HET1_8 = 1U, /**< Alias for HET1 pin 8 */
ADC1_HET1_10 = 2U, /**< Alias for HET1 pin 10 */
ADC1_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */
ADC1_HET1_12 = 4U, /**< Alias for HET1 pin 12 */
ADC1_HET1_14 = 5U, /**< Alias for HET1 pin 14 */
ADC1_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */
ADC1_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */
ADC1_HET2_5 = 1U, /**< Alias for HET2 pin 5 */
ADC1_HET1_27 = 2U, /**< Alias for HET1 pin 27 */
ADC1_HET1_17 = 4U, /**< Alias for HET1 pin 17 */
ADC1_HET1_19 = 5U, /**< Alias for HET1 pin 19 */
ADC1_HET1_11 = 6U, /**< Alias for HET1 pin 11 */
ADC1_HET2_13 = 7U, /**< Alias for HET2 pin 13 */
ADC1_EPWM_B = 1U, /**< Alias for B Signal EPWM */
ADC1_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */
ADC1_HET2_1 = 5U, /**< Alias for HET2 pin 1 */
ADC1_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */
ADC1_EPWM_AB = 7U /**< Alias for AB Signal EPWM */
};
/** @enum adc2HwTriggerSource
* @brief Alias names for hardware trigger source
* This enumeration is used to provide alias names for the hardware trigger sources:
*/
enum adc2HwTriggerSource
{
ADC2_EVENT = 0U, /**< Alias for event pin */
ADC2_HET1_8 = 1U, /**< Alias for HET1 pin 8 */
ADC2_HET1_10 = 2U, /**< Alias for HET1 pin 10 */
ADC2_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */
ADC2_HET1_12 = 4U, /**< Alias for HET1 pin 12 */
ADC2_HET1_14 = 5U, /**< Alias for HET1 pin 14 */
ADC2_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */
ADC2_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */
ADC2_HET2_5 = 1U, /**< Alias for HET2 pin 5 */
ADC2_HET1_27 = 2U, /**< Alias for HET1 pin 27 */
ADC2_HET1_17 = 4U, /**< Alias for HET1 pin 17 */
ADC2_HET1_19 = 5U, /**< Alias for HET1 pin 19 */
ADC2_HET1_11 = 6U, /**< Alias for HET1 pin 11 */
ADC2_HET2_13 = 7U, /**< Alias for HET2 pin 13 */
ADC2_EPWM_B = 1U, /**< Alias for B Signal EPWM */
ADC2_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */
ADC2_HET2_1 = 5U, /**< Alias for HET2 pin 1 */
ADC2_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */
ADC2_EPWM_AB = 7U /**< Alias for AB Signal EPWM */
};
/* USER CODE BEGIN (1) */
/* USER CODE END */
/** @struct adcData
* @brief ADC Conversion data structure
*
* This type is used to pass adc conversion data.
*/
/** @typedef adcData_t
* @brief ADC Data Type Definition
*/
typedef struct adcData
{
uint32 id; /**< Channel/Pin Id */
uint16 value; /**< Conversion data value */
} adcData_t;
/* USER CODE BEGIN (2) */
/* USER CODE END */
typedef struct adc_config_reg
{
uint32 CONFIG_OPMODECR;
uint32 CONFIG_CLOCKCR;
uint32 CONFIG_GxMODECR[ 3U ];
uint32 CONFIG_G0SRC;
uint32 CONFIG_G1SRC;
uint32 CONFIG_G2SRC;
uint32 CONFIG_BNDCR;
uint32 CONFIG_BNDEND;
uint32 CONFIG_G0SAMP;
uint32 CONFIG_G1SAMP;
uint32 CONFIG_G2SAMP;
uint32 CONFIG_G0SAMPDISEN;
uint32 CONFIG_G1SAMPDISEN;
uint32 CONFIG_G2SAMPDISEN;
uint32 CONFIG_PARCR;
} adc_config_reg_t;
#define ADC1_OPMODECR_CONFIGVALUE 0x81140001U
#define ADC1_CLOCKCR_CONFIGVALUE ( 7U )
#define ADC1_G0MODECR_CONFIGVALUE \
( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define ADC1_G1MODECR_CONFIGVALUE \
( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U )
#define ADC1_G2MODECR_CONFIGVALUE \
( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U )
#define ADC1_G0SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT )
#define ADC1_G1SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT )
#define ADC1_G2SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT )
#define ADC1_BNDCR_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ) )
#define ADC1_BNDEND_CONFIGVALUE ( 2U )
#define ADC1_G0SAMP_CONFIGVALUE ( 1U )
#define ADC1_G1SAMP_CONFIGVALUE ( 1U )
#define ADC1_G2SAMP_CONFIGVALUE ( 1U )
#define ADC1_G0SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U )
#define ADC1_G1SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U )
#define ADC1_G2SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U )
#define ADC1_PARCR_CONFIGVALUE ( 0x00000005U )
#define ADC2_OPMODECR_CONFIGVALUE 0x81140001U
#define ADC2_CLOCKCR_CONFIGVALUE ( 7U )
#define ADC2_G0MODECR_CONFIGVALUE \
( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define ADC2_G1MODECR_CONFIGVALUE \
( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U )
#define ADC2_G2MODECR_CONFIGVALUE \
( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U )
#define ADC2_G0SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT )
#define ADC2_G1SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT )
#define ADC2_G2SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT )
#define ADC2_BNDCR_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ) )
#define ADC2_BNDEND_CONFIGVALUE ( 2U )
#define ADC2_G0SAMP_CONFIGVALUE ( 1U )
#define ADC2_G1SAMP_CONFIGVALUE ( 1U )
#define ADC2_G2SAMP_CONFIGVALUE ( 1U )
#define ADC2_G0SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U )
#define ADC2_G1SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U )
#define ADC2_G2SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U )
#define ADC2_PARCR_CONFIGVALUE ( 0x00000005U )
/**
* @defgroup ADC ADC
* @brief Analog To Digital Converter Module.
*
* The microcontroller includes two 12-bit ADC modules with selectable 10-bit or 12-bit
*resolution
*
* Related Files
* - reg_adc.h
* - adc.h
* - adc.c
* @addtogroup ADC
* @{
*/
/* ADC Interface Functions */
void adcInit( void );
void adcStartConversion( adcBASE_t * adc, uint32 group );
void adcStopConversion( adcBASE_t * adc, uint32 group );
void adcResetFiFo( adcBASE_t * adc, uint32 group );
uint32 adcGetData( adcBASE_t * adc, uint32 group, adcData_t * data );
uint32 adcIsFifoFull( adcBASE_t * adc, uint32 group );
uint32 adcIsConversionComplete( adcBASE_t * adc, uint32 group );
void adcEnableNotification( adcBASE_t * adc, uint32 group );
void adcDisableNotification( adcBASE_t * adc, uint32 group );
void adcCalibration( adcBASE_t * adc );
uint32 adcMidPointCalibration( adcBASE_t * adc );
void adcSetEVTPin( adcBASE_t * adc, uint32 value );
uint32 adcGetEVTPin( adcBASE_t * adc );
void adc1GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type );
void adc2GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type );
/** @fn void adcNotification(adcBASE_t *adc, uint32 group)
* @brief Group notification
* @param[in] adc Pointer to ADC node:
* - adcREG1: ADC1 module pointer
* - adcREG2: ADC2 module pointer
* @param[in] group number of ADC node:
* - adcGROUP0: ADC event group
* - adcGROUP1: ADC group 1
* - adcGROUP2: ADC group 2
*
* @note This function has to be provide by the user.
*/
void adcNotification( adcBASE_t * adc, uint32 group );
/* USER CODE BEGIN (3) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif
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/** @file crc.h
* @brief CRC Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the CRC driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __CRC_H__
#define __CRC_H__
#include "reg_crc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* CRC General Definitions */
/** @def CRCLEVEL_ACTIVE
* @brief Alias name for CRC error operation level active
*/
#define CRCLEVEL_ACTIVE 0x00U
/** @def CRC_AUTO
* @brief Alias name for CRC auto mode
*/
#define CRC_AUTO 0x00000001U
/** @def CRC_SEMI_CPU
* @brief Alias name for semi cpu mode setting
*/
#define CRC_SEMI_CPU 0x00000002U
/** @def CRC_FULL_CPU
* @brief Alias name for CRC cpu full mode
*/
#define CRC_FULL_CPU 0x00000003U
/** @def CRC_CH4_TO
* @brief Alias name for channel4 time out interrupt flag
*/
#define CRC_CH4_TO 0x10000000U
/** @def CRC_CH4_UR
* @brief Alias name for channel4 underrun interrupt flag
*/
#define CRC_CH4_UR 0x08000000U
/** @def CRC_CH4_OR
* @brief Alias name for channel4 overrun interrupt flag
*/
#define CRC_CH4_OR 0x04000000U
/** @def CRC_CH4_FAIL
* @brief Alias name for channel4 crc fail interrupt flag
*/
#define CRC_CH4_FAIL 0x02000000U
/** @def CRC_CH4_CC
* @brief Alias name for channel4 compression complete interrupt flag
*/
#define CRC_CH4_CC 0x01000000U
/** @def CRC_CH3_TO
* @brief Alias name for channel3 time out interrupt flag
*/
#define CRC_CH3_TO 0x00100000U
/** @def CRC_CH3_UR
* @brief Alias name for channel3 underrun interrupt flag
*/
#define CRC_CH3_UR 0x00080000U
/** @def CRC_CH3_OR
* @brief Alias name for channel3 overrun interrupt flag
*/
#define CRC_CH3_OR 0x00040000U
/** @def CRC_CH3_FAIL
* @brief Alias name for channel3 crc fail interrupt flag
*/
#define CRC_CH3_FAIL 0x00020000U
/** @def CRC_CH3_CC
* @brief Alias name for channel3 compression complete interrupt flag
*/
#define CRC_CH3_CC 0x00010000U
/** @def CRC_CH2_TO
* @brief Alias name for channel2 time out interrupt flag
*/
#define CRC_CH2_TO 0x00001000U
/** @def CRC_CH2_UR
* @brief Alias name for channel2 underrun interrupt flag
*/
#define CRC_CH2_UR 0x00000800U
/** @def CRC_CH2_OR
* @brief Alias name for channel2 overrun interrupt flag
*/
#define CRC_CH2_OR 0x00000400U
/** @def CRC_CH2_FAIL
* @brief Alias name for channel2 crc fail interrupt flag
*/
#define CRC_CH2_FAIL 0x00000200U
/** @def CRC_CH2_CC
* @brief Alias name for channel2 compression complete interrupt flag
*/
#define CRC_CH2_CC 0x00000100U
/** @def CRC_CH1_TO
* @brief Alias name for channel1 time out interrupt flag
*/
#define CRC_CH1_TO 0x00000010U
/** @def CRC_CH1_UR
* @brief Alias name for channel1 underrun interrupt flag
*/
#define CRC_CH1_UR 0x00000008U
/** @def CRC_CH1_OR
* @brief Alias name for channel1 overrun interrupt flag
*/
#define CRC_CH1_OR 0x00000004U
/** @def CRC_CH1_FAIL
* @brief Alias name for channel1 crc fail interrupt flag
*/
#define CRC_CH1_FAIL 0x00000002U
/** @def CRC_CH1_CC
* @brief Alias name for channel1 compression complete interrupt flag
*/
#define CRC_CH1_CC 0x00000001U
/** @def CRC_CH1
* @brief Alias name for channel1
*/
#define CRC_CH1 0x00000000U
/** @def CRC_CH1
* @brief Alias name for channel2
*/
#define CRC_CH2 0x00000001U
/** @def CRC_CH3
* @brief Alias name for channel3
*/
#define CRC_CH3 0x00000002U
/** @def CRC_CH4
* @brief Alias name for channel4
*/
#define CRC_CH4 0x00000003U
/** @struct crcModConfig
* @brief CRC mode specific parameters
*
* This type is used to pass crc mode specific parameters
*/
/** @typedef crcModConfig_t
* @brief CRC Data Type Definition
*/
typedef struct crcModConfig
{
uint32 mode; /**< Mode of operation */
uint32 crc_channel; /**< CRC channel-0,1 */
uint64 * src_data_pat; /**< Pattern data */
uint32 data_length; /**< Pattern data length.Number of 64 bit size word*/
} crcModConfig_t;
/** @struct crcConfig
* @brief CRC configuration for different modes
*
* This type is used to pass crc configuration
*/
/** @typedef crcConfig_t
* @brief CRC Data Type Definition
*/
typedef struct crcConfig
{
uint32 crc_channel; /**< CRC channel-0,1 */
uint32 mode; /**< Mode of operation */
uint32 pcount; /**< Pattern count*/
uint32 scount; /**< Sector count */
uint32 wdg_preload; /**< Watchdog period */
uint32 block_preload; /**< Block period*/
} crcConfig_t;
/* USER CODE BEGIN (1) */
/* USER CODE END */
typedef struct crc_config_reg
{
uint32 CONFIG_CTRL0;
uint32 CONFIG_CTRL1;
uint32 CONFIG_CTRL2;
uint32 CONFIG_INTS;
uint32 CONFIG_PCOUNT_REG1;
uint32 CONFIG_SCOUNT_REG1;
uint32 CONFIG_WDTOPLD1;
uint32 CONFIG_BCTOPLD1;
uint32 CONFIG_PCOUNT_REG2;
uint32 CONFIG_SCOUNT_REG2;
uint32 CONFIG_WDTOPLD2;
uint32 CONFIG_BCTOPLD2;
} crc_config_reg_t;
#define CRC1_CTRL0_CONFIGVALUE 0x00000000U
#define CRC1_CTRL1_CONFIGVALUE 0x00000000U
#define CRC1_CTRL2_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( CRC_FULL_CPU ) \
| ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ) )
#define CRC1_INTS_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U )
#define CRC1_PCOUNT_REG1_CONFIGVALUE ( 0x00000000U )
#define CRC1_SCOUNT_REG1_CONFIGVALUE ( 0x00000000U )
#define CRC1_WDTOPLD1_CONFIGVALUE ( 0x00000000U )
#define CRC1_BCTOPLD1_CONFIGVALUE ( 0x00000000U )
#define CRC1_PCOUNT_REG2_CONFIGVALUE ( 0x00000000U )
#define CRC1_SCOUNT_REG2_CONFIGVALUE ( 0x00000000U )
#define CRC1_WDTOPLD2_CONFIGVALUE ( 0x00000000U )
#define CRC1_BCTOPLD2_CONFIGVALUE ( 0x00000000U )
#define CRC2_CTRL0_CONFIGVALUE 0x00000000U
#define CRC2_CTRL1_CONFIGVALUE 0x00000000U
#define CRC2_CTRL2_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( CRC_FULL_CPU ) \
| ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ) )
#define CRC2_INTS_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U )
#define CRC2_PCOUNT_REG1_CONFIGVALUE ( 0U )
#define CRC2_SCOUNT_REG1_CONFIGVALUE ( 0U )
#define CRC2_WDTOPLD1_CONFIGVALUE ( 0U )
#define CRC2_BCTOPLD1_CONFIGVALUE ( 0U )
#define CRC2_PCOUNT_REG2_CONFIGVALUE ( 0U )
#define CRC2_SCOUNT_REG2_CONFIGVALUE ( 0U )
#define CRC2_WDTOPLD2_CONFIGVALUE ( 0U )
#define CRC2_BCTOPLD2_CONFIGVALUE ( 0U )
/**
* @defgroup CRC CRC
* @brief Cyclic Redundancy Check Controller Module.
*
* The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check)
* to verify the integrity of memory system. A signature representing the contents of the
* memory is obtained when the contents of the memory are read into CRC controller. The
* responsibility of CRC controller is to calculate the signature for a set of data and
* then compare the calculated signature value against a pre-determined good signature
* value. CRC controller supports two channels to perform CRC calculation on multiple
* memories in parallel and can be used on any memory system.
*
* Related Files
* - reg_crc.h
* - crc.h
* - crc.c
* @addtogroup CRC
* @{
*/
/* CRC Interface Functions */
void crcInit( void );
void crcSendPowerDown( crcBASE_t * crc );
void crcSignGen( crcBASE_t * crc, crcModConfig_t * param );
void crcSetConfig( crcBASE_t * crc, crcConfig_t * param );
uint64 crcGetPSASig( crcBASE_t * crc, uint32 channel );
uint64 crcGetSectorSig( crcBASE_t * crc, uint32 channel );
uint32 crcGetFailedSector( crcBASE_t * crc, uint32 channel );
uint32 crcGetIntrPend( crcBASE_t * crc, uint32 channel );
void crcChannelReset( crcBASE_t * crc, uint32 channel );
void crcEnableNotification( crcBASE_t * crc, uint32 flags );
void crcDisableNotification( crcBASE_t * crc, uint32 flags );
void crc1GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type );
void crc2GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type );
/** @fn void crcNotification(crcBASE_t *crc, uint32 flags)
* @brief Interrupt callback
* @param[in] crc - crc module base address
* @param[in] flags - copy of error interrupt flags
*
* This is a callback that is provided by the application and is called upon
* an interrupt. The parameter passed to the callback is a copy of the
* interrupt flag register.
*/
void crcNotification( crcBASE_t * crc, uint32 flags );
/* USER CODE BEGIN (2) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif
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/** @file dcc.h
* @brief DCC Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __DCC_H__
#define __DCC_H__
#include "reg_dcc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* DCC General Definitions */
/** @def dcc1CNT0_CLKSRC_HFLPO
* @brief Alias name for DCC1 Counter 0 Clock Source HFLPO
*
* This is an alias name for the Clock Source HFLPO for DCC1 Counter 0.
*
* @note This value should be used for API argument @a cnt0_Clock_Source
*/
#define dcc1CNT0_CLKSRC_HFLPO 0x00000005U
/** @def dcc1CNT0_CLKSRC_TCK
* @brief Alias name for DCC1 Counter 0 Clock Source TCK
*
* This is an alias name for the Clock Source TCK for DCC1 Counter 0.
*
* @note This value should be used for API argument @a cnt0_Clock_Source
*/
#define dcc1CNT0_CLKSRC_TCK 0x0000000AU
/** @def dcc1CNT0_CLKSRC_OSCIN
* @brief Alias name for DCC1 Counter 0 Clock Source OSCIN
*
* This is an alias name for the Clock Source OSCIN for DCC1 Counter 0.
*
* @note This value should be used for API argument @a cnt0_Clock_Source
*/
#define dcc1CNT0_CLKSRC_OSCIN 0x0000000FU
/** @def dcc1CNT1_CLKSRC_PLL1
* @brief Alias name for DCC1 Counter 1 Clock Source PLL1
*
* This is an alias name for the Clock Source PLL for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U
/** @def dcc1CNT1_CLKSRC_PLL2
* @brief Alias name for DCC1 Counter 1 Clock Source PLL2
*
* This is an alias name for the Clock Source OSCIN for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U
/** @def dcc1CNT1_CLKSRC_LFLPO
* @brief Alias name for DCC1 Counter 1 Clock Source LFLPO
*
* This is an alias name for the Clock Source LFLPO for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_LFLPO 0x0000A002U
/** @def dcc1CNT1_CLKSRC_HFLPO
* @brief Alias name for DCC1 Counter 1 Clock Source HFLPO
*
* This is an alias name for the Clock Source HFLPO for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_HFLPO 0x0000A003U
/** @def dcc1CNT1_CLKSRC_EXTCLKIN1
* @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN1
*
* This is an alias name for the Clock Source EXTCLKIN1 for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_EXTCLKIN1 0x0000A005U
/** @def dcc1CNT1_CLKSRC_EXTCLKIN2
* @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN2
*
* This is an alias name for the Clock Source EXTCLKIN2 for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_EXTCLKIN2 0x0000A006U
/** @def dcc1CNT1_CLKSRC_VCLK
* @brief Alias name for DCC1 Counter 1 Clock Source VCLK
*
* This is an alias name for the Clock Source VCLK for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_VCLK 0x0000A008U
/** @def dcc1CNT1_CLKSRC_N2HET1_31
* @brief Alias name for DCC1 Counter 1 Clock Source N2HET1_31
*
* This is an alias name for the Clock Source N2HET1_31 for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_N2HET1_31 0x0000500FU
/** @def dcc2CNT0_CLKSRC_TCK
* @brief Alias name for DCC2 Counter 0 Clock Source TCK
*
* This is an alias name for the Clock Source TCK for DCC2 Counter 0.
*
* @note This value should be used for API argument @a cnt0_Clock_Source
*/
#define dcc2CNT0_CLKSRC_TCK 0x0000000AU
/** @def dcc1CNT0_CLKSRC_OSCIN
* @brief Alias name for DCC1 Counter 0 Clock Source OSCIN
*
* This is an alias name for the Clock Source OSCIN for DCC2 Counter 0.
*
* @note This value should be used for API argument @a cnt0_Clock_Source
*/
#define dcc2CNT0_CLKSRC_OSCIN 0x0000000FU
/** @def dcc2CNT1_CLKSRC_VCLK
* @brief Alias name for DCC2 Counter 1 Clock Source VCLK
*
* This is an alias name for the Clock Source VCLK for DCC2 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc2CNT1_CLKSRC_VCLK 0x0000A008U
/** @def dcc2CNT1_CLKSRC_ODCLK8
* @brief Alias name for DCC2 Counter 1 Clock Source PLL2_post_ODCLK/8
*
* This is an alias name for the Clock Source PLL2_post_ODCLK/8 for DCC2 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc2CNT1_CLKSRC_ODCLK8 0x0000A001U
/** @def dcc2CNT1_CLKSRC_ODCLK16
* @brief Alias name for DCC2 Counter 1 Clock Source PLL2_post_ODCLK/16
*
* This is an alias name for the Clock Source PLL2_post_ODCLK/16 for DCC2 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc2CNT1_CLKSRC_ODCLK16 0x0000A002U
/** @def dcc2CNT1_CLKSRC_N2HET1_0
* @brief Alias name for DCC2 Counter 1 Clock Source N2HET2_0
*
* This is an alias name for the Clock Source N2HET2_0 for DCC2 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc2CNT1_CLKSRC_N2HET1_0 0x0000500FU
/** @def dccNOTIFICATION_DONE
* @brief Alias name for DCC Done notification
*
* This is an alias name for the DCC Done notification.
*
* @note This value should be used for API argument @a notification
*/
#define dccNOTIFICATION_DONE 0x0000A000U
/** @def dccNOTIFICATION_ERROR
* @brief Alias name for DCC Error notification
*
* This is an alias name for the DCC Error notification.
*
* @note This value should be used for API argument @a notification
*/
#define dccNOTIFICATION_ERROR 0x000000A0U
/** @enum dcc1clocksource
* @brief Alias names for dcc clock sources
*
* This enumeration is used to provide alias names for the clock sources:
*/
enum dcc1clocksource
{
DCC1_CNT0_HF_LPO = 0x5U, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
DCC1_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/
DCC1_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
DCC1_CNT1_PLL1 = 0x0U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/
DCC1_CNT1_PLL2 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/
DCC1_CNT1_LF_LPO = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/
DCC1_CNT1_HF_LPO = 0x3U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/
DCC1_CNT1_EXTCLKIN1 = 0x5U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/
DCC1_CNT1_EXTCLKIN2 = 0x6U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/
DCC1_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
DCC1_CNT1_N2HET1_31 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
};
/** @enum dcc2clocksource
* @brief Alias names for dcc clock sources
*
* This enumeration is used to provide alias names for the clock sources:
*/
enum dcc2clocksource
{
DCC2_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
DCC2_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
DCC2_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
DCC2_CNT1_ODCLK8 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/
DCC2_CNT1_ODCLK16 = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/
DCC2_CNT1_N2HET2_0 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
};
/* Configuration registers */
typedef struct dcc_config_reg
{
uint32 CONFIG_GCTRL;
uint32 CONFIG_CNT0SEED;
uint32 CONFIG_VALID0SEED;
uint32 CONFIG_CNT1SEED;
uint32 CONFIG_CNT1CLKSRC;
uint32 CONFIG_CNT0CLKSRC;
} dcc_config_reg_t;
/* Configuration registers initial value */
#define DCC1_GCTRL_CONFIGVALUE \
( ( uint32 ) 0xAU | ( uint32 ) ( ( uint32 ) 0xAU << 4U ) \
| ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | ( uint32 ) ( ( uint32 ) 0xAU << 12U ) )
#define DCC1_CNT0SEED_CONFIGVALUE 39204U
#define DCC1_VALID0SEED_CONFIGVALUE 792U
#define DCC1_CNT1SEED_CONFIGVALUE 742500U
#define DCC1_CNT1CLKSRC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 10U << 12U ) | ( uint32 ) DCC1_CNT1_PLL1 )
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Values come from GUI drop down option" */
#define DCC1_CNT0CLKSRC_CONFIGVALUE ( ( uint32 ) DCC1_CNT0_OSCIN )
#define DCC2_GCTRL_CONFIGVALUE \
( ( uint32 ) 0xAU | ( uint32 ) ( ( uint32 ) 0xAU << 4U ) \
| ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | ( uint32 ) ( ( uint32 ) 0xAU << 12U ) )
#define DCC2_CNT0SEED_CONFIGVALUE 0U
#define DCC2_VALID0SEED_CONFIGVALUE 0U
#define DCC2_CNT1SEED_CONFIGVALUE 0U
#define DCC2_CNT1CLKSRC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0xAU << 12U ) | ( uint32 ) DCC2_CNT1_VCLK )
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Values come from GUI drop down option" */
#define DCC2_CNT0CLKSRC_CONFIGVALUE ( ( uint32 ) DCC2_CNT0_OSCIN )
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**
* @defgroup DCC DCC
* @brief Dual-Clock Comparator Module
*
* The primary purpose of a DCC module is to measure the frequency of a clock signal
* using a second known clock signal as a reference. This capability can be used to ensure
* the correct frequency range for several different device clock sources, thereby
* enhancing the system safety metrics.
*
* Related Files
* - reg_dcc.h
* - dcc.h
* - dcc .c
* @addtogroup DCC
* @{
*/
/* DCC Interface Functions */
void dccInit( void );
void dccSetCounter0Seed( dccBASE_t * dcc, uint32 cnt0seed );
void dccSetTolerance( dccBASE_t * dcc, uint32 valid0seed );
void dccSetCounter1Seed( dccBASE_t * dcc, uint32 cnt1seed );
void dccSetSeed( dccBASE_t * dcc, uint32 cnt0seed, uint32 valid0seed, uint32 cnt1seed );
void dccSelectClockSource( dccBASE_t * dcc,
uint32 cnt0_Clock_Source,
uint32 cnt1_Clock_Source );
void dccEnable( dccBASE_t * dcc );
void dccDisable( dccBASE_t * dcc );
uint32 dccGetErrStatus( dccBASE_t * dcc );
void dccEnableNotification( dccBASE_t * dcc, uint32 notification );
void dccDisableNotification( dccBASE_t * dcc, uint32 notification );
void dcc1GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type );
void dcc2GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type );
/** @fn void dccNotification(dccBASE_t *dcc,uint32 flags)
* @brief Interrupt callback
* @param[in] dcc - dcc module base address
* @param[in] flags - status flags
*
* This is a callback function provided by the application. It is call when
* a dcc is complete or detected error.
*/
void dccNotification( dccBASE_t * dcc, uint32 flags );
/* USER CODE BEGIN (2) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dmm.h
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/** @file dmm.h
* @brief DMM Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __DMM_H__
#define __DMM_H__
#include "reg_dmm.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Configuration registers */
typedef struct dmm_config_reg
{
uint32 CONFIG_PC0;
uint32 CONFIG_PC1;
uint32 CONFIG_PC3;
uint32 CONFIG_PC6;
uint32 CONFIG_PC7;
uint32 CONFIG_PC8;
} dmm_config_reg_t;
#define DMM_PC3_CONFIGVALUE \
( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) )
#define DMM_PC1_CONFIGVALUE \
( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \
| ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \
| ( uint32 ) ( ( uint32 ) 1U << 18U ) )
#define DMM_PC6_CONFIGVALUE \
( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) )
#define DMM_PC8_CONFIGVALUE \
( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 1U << 7U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \
| ( uint32 ) ( ( uint32 ) 1U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \
| ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 1U << 15U ) \
| ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \
| ( uint32 ) ( ( uint32 ) 1U << 18U ) )
#define DMM_PC7_CONFIGVALUE \
( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) )
#define DMM_PC0_CONFIGVALUE \
( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 1U << 7U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \
| ( uint32 ) ( ( uint32 ) 1U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \
| ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 1U << 15U ) \
| ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \
| ( uint32 ) ( ( uint32 ) 1U << 18U ) )
/**
* @defgroup DMM DMM
* @brief Data Modification Module.
*
* The DMM module provides the capability to modify data in the entire 4 GB address space
*of the device from an external peripheral, with minimal interruption of the application.
*
* Related Files
* - reg_dmm.h
* - dmm.h
* - dmm.c
* @addtogroup DMM
* @{
*/
/* DMM Interface Functions */
void dmmInit( void );
void dmmGetConfigValue( dmm_config_reg_t * config_reg, config_value_type_t type );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ecap.h
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/** @file ecap.h
* @brief ECAP Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the ECAP driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __ECAP_H__
#define __ECAP_H__
#include "reg_ecap.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @brief Enumeration to define the capture (CAP) interrupts
*/
typedef enum
{
ecapInt_CTR_CMP = 0x0080U, /*< Denotes CTR = CMP interrupt */
ecapInt_CTR_PRD = 0x0040U, /*< Denotes CTR = PRD interrupt */
ecapInt_CTR_OVF = 0x0020U, /*< Denotes CTROVF interrupt */
ecapInt_CEVT4 = 0x0010U, /*< Denotes CEVT4 interrupt */
ecapInt_CEVT3 = 0x0008U, /*< Denotes CEVT3 interrupt */
ecapInt_CEVT2 = 0x0004U, /*< Denotes CEVT2 interrupt */
ecapInt_CEVT1 = 0x0002U, /*< Denotes CEVT1 interrupt */
ecapInt_Global = 0x0001U, /*< Denotes Capture global interrupt */
ecapInt_All = 0x00FFU /*< Denotes All interrupts */
} ecapInterrupt_t;
/** @brief Enumeration to define the capture (CAP) prescaler values
*/
typedef enum
{
ecapPrescale_By_1 = ( ( uint16 ) 0U << 9U ), /*< Divide by 1 */
ecapPrescale_By_2 = ( ( uint16 ) 1U << 9U ), /*< Divide by 2 */
ecapPrescale_By_4 = ( ( uint16 ) 2U << 9U ), /*< Divide by 4 */
ecapPrescale_By_6 = ( ( uint16 ) 3U << 9U ), /*< Divide by 6 */
ecapPrescale_By_8 = ( ( uint16 ) 4U << 9U ), /*< Divide by 8 */
ecapPrescale_By_10 = ( ( uint16 ) 5U << 9U ), /*< Divide by 10 */
ecapPrescale_By_12 = ( ( uint16 ) 6U << 9U ), /*< Divide by 12 */
ecapPrescale_By_14 = ( ( uint16 ) 7U << 9U ), /*< Divide by 14 */
ecapPrescale_By_16 = ( ( uint16 ) 8U << 9U ), /*< Divide by 16 */
ecapPrescale_By_18 = ( ( uint16 ) 9U << 9U ), /*< Divide by 18 */
ecapPrescale_By_20 = ( ( uint16 ) 10U << 9U ), /*< Divide by 20 */
ecapPrescale_By_22 = ( ( uint16 ) 11U << 9U ), /*< Divide by 22 */
ecapPrescale_By_24 = ( ( uint16 ) 12U << 9U ), /*< Divide by 24 */
ecapPrescale_By_26 = ( ( uint16 ) 13U << 9U ), /*< Divide by 26 */
ecapPrescale_By_28 = ( ( uint16 ) 14U << 9U ), /*< Divide by 28 */
ecapPrescale_By_30 = ( ( uint16 ) 15U << 9U ), /*< Divide by 30 */
ecapPrescale_By_32 = ( ( uint16 ) 16U << 9U ), /*< Divide by 32 */
ecapPrescale_By_34 = ( ( uint16 ) 17U << 9U ), /*< Divide by 34 */
ecapPrescale_By_36 = ( ( uint16 ) 18U << 9U ), /*< Divide by 36 */
ecapPrescale_By_38 = ( ( uint16 ) 19U << 9U ), /*< Divide by 38 */
ecapPrescale_By_40 = ( ( uint16 ) 20U << 9U ), /*< Divide by 40 */
ecapPrescale_By_42 = ( ( uint16 ) 21U << 9U ), /*< Divide by 42 */
ecapPrescale_By_44 = ( ( uint16 ) 22U << 9U ), /*< Divide by 44 */
ecapPrescale_By_46 = ( ( uint16 ) 23U << 9U ), /*< Divide by 46 */
ecapPrescale_By_48 = ( ( uint16 ) 24U << 9U ), /*< Divide by 48 */
ecapPrescale_By_50 = ( ( uint16 ) 25U << 9U ), /*< Divide by 50 */
ecapPrescale_By_52 = ( ( uint16 ) 26U << 9U ), /*< Divide by 52 */
ecapPrescale_By_54 = ( ( uint16 ) 27U << 9U ), /*< Divide by 54 */
ecapPrescale_By_56 = ( ( uint16 ) 28U << 9U ), /*< Divide by 56 */
ecapPrescale_By_58 = ( ( uint16 ) 29U << 9U ), /*< Divide by 58 */
ecapPrescale_By_60 = ( ( uint16 ) 30U << 9U ), /*< Divide by 60 */
ecapPrescale_By_62 = ( ( uint16 ) 31U << 9U ) /*< Divide by 62 */
} ecapPrescale_t;
/** @brief Enumeration to define the Sync Out options
*/
typedef enum
{
SyncOut_SyncIn = ( ( uint16 ) 0U << 6U ), /*< Sync In used for Sync Out */
SyncOut_CTRPRD = ( ( uint16 ) 1U << 6U ), /*< CTR = PRD used for Sync Out */
SyncOut_None = ( ( uint16 ) 2U << 6U ) /*< Disables Sync Out */
} ecapSyncOut_t;
/** @brief Enumeration to define the Polarity
*/
typedef enum
{
RISING_EDGE = 0U,
FALLING_EDGE = 1U
} ecapEdgePolarity_t;
typedef enum
{
ACTIVE_HIGH = 0U,
ACTIVE_LOW = 1U
} ecapAPWMPolarity_t;
/** @brief Enumeration to define the Mode of operation
*/
typedef enum
{
CONTINUOUS = 0U,
ONE_SHOT = 1U
} ecapMode_t;
/** @brief Enumeration to define the capture events
*/
typedef enum
{
CAPTURE_EVENT1 = 0U,
CAPTURE_EVENT2 = 1U,
CAPTURE_EVENT3 = 2U,
CAPTURE_EVENT4 = 3U
} ecapEvent_t;
typedef enum
{
RESET_ENABLE = 1U,
RESET_DISABLE = 0U
} ecapReset_t;
typedef struct ecap_config_reg
{
uint32 CONFIG_CTRPHS;
uint16 CONFIG_ECCTL1;
uint16 CONFIG_ECCTL2;
uint16 CONFIG_ECEINT;
} ecap_config_reg_t;
#define ECAP1_CTRPHS_CONFIGVALUE 0x00000000U
#define ECAP1_ECCTL1_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) )
#define ECAP1_ECCTL2_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \
| ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U )
#define ECAP1_ECEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ECAP2_CTRPHS_CONFIGVALUE 0x00000000U
#define ECAP2_ECCTL1_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) )
#define ECAP2_ECCTL2_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \
| ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U )
#define ECAP2_ECEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ECAP3_CTRPHS_CONFIGVALUE 0x00000000U
#define ECAP3_ECCTL1_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) )
#define ECAP3_ECCTL2_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \
| ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U )
#define ECAP3_ECEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ECAP4_CTRPHS_CONFIGVALUE 0x00000000U
#define ECAP4_ECCTL1_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) )
#define ECAP4_ECCTL2_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \
| ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U )
#define ECAP4_ECEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ECAP5_CTRPHS_CONFIGVALUE 0x00000000U
#define ECAP5_ECCTL1_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) )
#define ECAP5_ECCTL2_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \
| ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U )
#define ECAP5_ECEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ECAP6_CTRPHS_CONFIGVALUE 0x00000000U
#define ECAP6_ECCTL1_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) )
#define ECAP6_ECCTL2_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \
| ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U )
#define ECAP6_ECEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
/**
* @defgroup eCAP eCAP
* @brief Enhanced Capture Module.
*
* The enhanced Capture (eCAP) module is essential in systems where accurate timing of
*external events is important. This microcontroller implements 6 instances of the eCAP
*module.
*
* Related Files
* - reg_ecap.h
* - ecap.h
* - ecap.c
* @addtogroup eCAP
* @{
*/
void ecapInit( void );
void ecapSetCounter( ecapBASE_t * ecap, uint32 value );
void ecapEnableCounterLoadOnSync( ecapBASE_t * ecap, uint32 phase );
void ecapDisableCounterLoadOnSync( ecapBASE_t * ecap );
void ecapSetEventPrescaler( ecapBASE_t * ecap, ecapPrescale_t prescale );
void ecapSetCaptureEvent1( ecapBASE_t * ecap,
ecapEdgePolarity_t edgePolarity,
ecapReset_t resetenable );
void ecapSetCaptureEvent2( ecapBASE_t * ecap,
ecapEdgePolarity_t edgePolarity,
ecapReset_t resetenable );
void ecapSetCaptureEvent3( ecapBASE_t * ecap,
ecapEdgePolarity_t edgePolarity,
ecapReset_t resetenable );
void ecapSetCaptureEvent4( ecapBASE_t * ecap,
ecapEdgePolarity_t edgePolarity,
ecapReset_t resetenable );
void ecapSetCaptureMode( ecapBASE_t * ecap, ecapMode_t capMode, ecapEvent_t event );
void ecapEnableCapture( ecapBASE_t * ecap );
void ecapDisableCapture( ecapBASE_t * ecap );
void ecapStartCounter( ecapBASE_t * ecap );
void ecapStopCounter( ecapBASE_t * ecap );
void ecapSetSyncOut( ecapBASE_t * ecap, ecapSyncOut_t syncOutSrc );
void ecapEnableAPWMmode( ecapBASE_t * ecap,
ecapAPWMPolarity_t pwmPolarity,
uint32 period,
uint32 duty );
void ecapDisableAPWMMode( ecapBASE_t * ecap );
void ecapEnableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts );
void ecapDisableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts );
uint16 ecapGetEventStatus( ecapBASE_t * ecap, ecapInterrupt_t events );
void ecapClearFlag( ecapBASE_t * ecap, ecapInterrupt_t events );
uint32 ecapGetCAP1( ecapBASE_t * ecap );
uint32 ecapGetCAP2( ecapBASE_t * ecap );
uint32 ecapGetCAP3( ecapBASE_t * ecap );
uint32 ecapGetCAP4( ecapBASE_t * ecap );
void ecap1GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type );
void ecap2GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type );
void ecap3GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type );
void ecap4GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type );
void ecap5GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type );
void ecap6GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type );
/** @brief Interrupt callback
* @param[in] ecap Handle to CAP object
* @param[in] flags Copy of interrupt flags
*/
void ecapNotification( ecapBASE_t * ecap, uint16 flags );
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif /*end of _CAP_H_ definition */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac.h
+438
View File
@@ -0,0 +1,438 @@
/**
* \file emac.h
*
* \brief EMAC APIs and macros.
*
* This file contains the driver API prototypes and macro definitions.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __EMAC_H__
#define __EMAC_H__
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include "sys_common.h"
#include "hw_reg_access.h"
#include "hw_emac.h"
#include "hw_emac_ctrl.h"
#include "mdio.h"
#include "emac_phyConfig.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
/*****************************************************************************/
/*
** Macros which can be used as speed parameter to the API EMACRMIISpeedSet
*/
#define EMAC_RMIISPEED_10MBPS ( 0x00000000U )
#define EMAC_RMIISPEED_100MBPS ( 0x00008000U )
/* Macros for enabling taken as inputs from HALCoGen GUI. */
#define EMAC_TX_ENABLE ( 1U )
#define EMAC_RX_ENABLE ( 1U )
#define EMAC_MII_ENABLE ( 1U )
#define EMAC_FULL_DUPLEX_ENABLE ( 1U )
#define EMAC_LOOPBACK_ENABLE ( 0U )
#define EMAC_BROADCAST_ENABLE ( 1U )
#define EMAC_UNICAST_ENABLE ( 1U )
#define EMAC_CHANNELNUMBER ( 0U )
#define EMAC_PHYADDRESS ( 1U )
/*
* Macros to indicate EMAC Channel Numbers
*/
#define EMAC_CHANNEL_0 ( 0x00000000U )
#define EMAC_CHANNEL_1 ( 0x00000001U )
#define EMAC_CHANNEL_2 ( 0x00000002U )
#define EMAC_CHANNEL_3 ( 0x00000003U )
#define EMAC_CHANNEL_4 ( 0x00000004U )
#define EMAC_CHANNEL_5 ( 0x00000005U )
#define EMAC_CHANNEL_6 ( 0x00000006U )
#define EMAC_CHANNEL_7 ( 0x00000007U )
/* Macros which can be used as duplexMode parameter to the API
** EMACDuplexSet
*/
#define EMAC_DUPLEX_FULL ( 0x00000001U )
#define EMAC_DUPLEX_HALF ( 0x00000000U )
/*
** Macros which can be used as matchFilt parameters to the API
** EMACMACAddrSet
*/
/* Address not used to match/filter incoming packets */
#define EMAC_MACADDR_NO_MATCH_NO_FILTER ( 0x00000000U )
/* Address will be used to filter incoming packets */
#define EMAC_MACADDR_FILTER ( 0x00100000U )
/* Address will be used to match incoming packets */
#define EMAC_MACADDR_MATCH ( 0x00180000U )
/*
** Macros which can be passed as eoiFlag to EMACRxIntAckToClear API
*/
#define EMAC_INT_CORE0_RX ( 0x1U )
#define EMAC_INT_CORE1_RX ( 0x5U )
#define EMAC_INT_CORE2_RX ( 0x9U )
/*
** Macros which can be passed as eoiFlag to EMACTxIntAckToClear API
*/
#define EMAC_INT_CORE0_TX ( 0x2U )
#define EMAC_INT_CORE1_TX ( 0x6U )
#define EMAC_INT_CORE2_TX ( 0xAU )
/* Base Addresses */
#define EMAC_CTRL_RAM_0_BASE 0xFC520000U
#define EMAC_0_BASE 0xFCF78000U
#define EMAC_CTRL_0_BASE 0xFCF78800U
#define MDIO_0_BASE 0xFCF78900U
/*MAC address length*/
#define EMAC_HWADDR_LEN 6U
#define MAX_EMAC_INSTANCE 1U
#define SIZE_EMAC_CTRL_RAM 0x2000U
#define MAX_TRANSFER_UNIT 1514U
#define MAX_RX_PBUF_ALLOC ( 10U )
#define MIN_PKT_LEN 60U
#define MIN_PACKET_SIZE ( 46U )
#define EMAC_BUF_DESC_OWNER 0x20000000U
#define EMAC_BUF_DESC_SOP 0x80000000U
#define EMAC_BUF_DESC_EOP 0x40000000U
#define EMAC_BUF_DESC_EOQ 0x10000000U
#define EMAC_NETSTATREGS( n ) ( ( uint32 ) 0x200U + ( uint32 ) ( ( n ) * 4U ) )
/* Error Signalling Macros */
#define EMAC_ERR_CONNECT 0x2U /* Not connected. */
#define EMAC_ERR_OK 0x1U /* No error, everything OK. */
/* Macros for Configuration Value Registers */
#define EMAC_TXCONTROL_CONFIGVALUE 0x00000001U
#define EMAC_RXCONTROL_CONFIGVALUE 0x00000001U
#define EMAC_TXINTMASKSET_CONFIGVALUE 0x00000001U
#define EMAC_TXINTMASKCLEAR_CONFIGVALUE 0x00000001U
#define EMAC_RXINTMASKSET_CONFIGVALUE 0x00000001U
#define EMAC_RXINTMASKCLEAR_CONFIGVALUE 0x00000001U
#define EMAC_MACSRCADDRHI_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0xFFU << 24U ) | ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) \
| ( uint32 ) ( ( uint32 ) 0xFFU << 8U ) | ( uint32 ) ( ( uint32 ) 0xFFU ) )
#define EMAC_MACSRCADDRLO_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0xFFU << 8U ) | ( uint32 ) ( ( uint32 ) 0xFFU ) )
#define EMAC_MDIOCONTROL_CONFIGVALUE 0x4114001FU
#define EMAC_C0RXEN_CONFIGVALUE 0x00000001U
#define EMAC_C0TXEN_CONFIGVALUE 0x00000001U
/* Structure to store pending status from the Tx Interrupt Status Registers. */
typedef struct emac_tx_int_status
{
volatile uint32 intstatmasked; /* Pending interrupt status read from the Transmit
Interrupt Status (Masked) Register (TXINTSTATMASKED)
*/
volatile uint32 intstatraw; /* Pending interrupt status read from the Transmit
Interrupt Status (Unmasked) Register (TXINTSTATRAW) */
} emac_tx_int_status_t;
/* Structure to store pending status from the Rx Interrupt Status Registers. */
typedef struct emac_rx_int_status
{
volatile uint32 intstatmasked_pend; /* Reads RXnPEND value from the Receive Interrupt
Status (Unmasked) Register (RXINTSTATRAW) */
volatile uint32 intstatmasked_threshpend; /* Reads RXnTRHESHPEND value from the
Receive Interrupt Status (Unmasked)
Register (RXINTSTATRAW) */
volatile uint32 intstatraw_pend; /* Reads RXnPEND value from the Receive Interrupt
Status (Unmasked) Register (RXINTSTATRAW) */
volatile uint32 intstatraw_threshpend; /* Reads RXnTRHESHPEND value from the Receive
Interrupt Status (Unmasked) Register
(RXINTSTATRAW) */
} emac_rx_int_status_t;
/* EMAC TX Buffer descriptor data structure - Refer TRM for details about the buffer
* descriptor structure.*/
typedef struct emac_tx_bd
{
volatile struct emac_tx_bd * next;
volatile uint32 bufptr; /* Pointer to the actual Buffer storing the data to be
transmitted. */
volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each) */
volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/
} emac_tx_bd_t;
/* EMAC RX Buffer descriptor data structure - Refer TRM for details about the buffer
* descriptor structure. */
typedef struct emac_rx_bd
{
volatile struct emac_rx_bd * next; /*Used as a pointer for next element in the linked
list of descriptors.*/
volatile uint32 bufptr; /*Pointer to the actual Buffer which will store the received
data.*/
volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each)*/
volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/
} emac_rx_bd_t;
/**
* Helper struct to hold the data used to operate on a particular
* receive channel
*/
typedef struct rxch_struct
{
volatile emac_rx_bd_t * free_head; /*Used to point to the free buffer descriptor which
can receive new data.*/
volatile emac_rx_bd_t * active_head; /*Used to point to the active descriptor in the
chain which is receiving.*/
volatile emac_rx_bd_t * active_tail; /*Used to point to the last descriptor in the
chain.*/
} rxch_t;
/**
* Helper struct to hold the data used to operate on a particular
* transmit channel
*/
typedef struct txch_struct
{
volatile emac_tx_bd_t * free_head; /*Used to point to the free buffer descriptor which
can transmit new data.*/
volatile emac_tx_bd_t * active_tail; /*Used to point to the last descriptor in the
chain.*/
volatile emac_tx_bd_t * next_bd_to_process; /*Used to point to the next descriptor in
the chain to be processed.*/
} txch_t;
/**
* Helper struct to hold private data used to operate the ethernet interface.
*/
typedef struct hdkif_struct
{
/* MAC Address of the Module. */
uint8_t mac_addr[ 6 ];
/* emac base address */
uint32 emac_base;
/* emac controller base address */
volatile uint32 emac_ctrl_base;
volatile uint32 emac_ctrl_ram;
/* mdio base address */
volatile uint32 mdio_base;
/* phy parameters for this instance - for future use */
uint32 phy_addr;
boolean ( *phy_autoneg )( uint32 param1, uint32 param2, uint16 param3 );
boolean ( *phy_partnerability )( uint32 param4, uint32 param5, uint16 * param6 );
/* The tx/rx channels for the interface */
txch_t txchptr;
rxch_t rxchptr;
} hdkif_t;
/*Ethernet Frame Structure */
typedef struct ethernet_frame
{
uint8 dest_addr[ 6 ]; /* Destination MAC Address */
uint8 src_addr[ 6 ]; /*Source MAC Address. */
uint16 frame_length; /* Data Frame Length */
uint8 data[ 1500 ]; /* Data */
} ethernet_frame_t;
/* Struct used to take packet data input from the user for transmit APIs. */
typedef struct pbuf_struct
{
/** next pbuf in singly linked pbuf chain */
struct pbuf_struct * next;
/**
* Pointer to the actual ethernet packet/packet fragment to be transmitted.
* The packet needs to be in the following format:
* |Destination MAC Address (6 bytes)| Source MAC Address (6 bytes)| Length/Type (2
*bytes)| Data (46- 1500 bytes) The data can be split up over multiple pbufs which are
*linked as a linked list.
**/
uint8 * payload;
/**
* total length of this buffer and all next buffers in chain
* belonging to the same packet.
*
* For non-queue packet chains this is the invariant:
* p->tot_len == p->len + (p->next? p->next->tot_len: 0)
*/
uint16 tot_len;
/** length of this buffer */
uint16 len;
} pbuf_t;
/* Structure to hold the values of the EMAC Configuration Registers. */
typedef struct emac_config_reg_struct
{
/* EMAC Module Register Values */
uint32 TXCONTROL; /* Transmit Control Register. */
uint32 RXCONTROL; /* Receive Control Register */
uint32 TXINTMASKSET; /* Transmit Interrupt Mask Set Register */
uint32 TXINTMASKCLEAR; /* Transmit Interrupt Clear Register */
uint32 RXINTMASKSET; /* Receive Interrupt Mask Set Register */
uint32 RXINTMASKCLEAR; /*Receive Interrupt Mask Clear Register*/
uint32 MACSRCADDRHI; /*MAC Source Address High Bytes Register*/
uint32 MACSRCADDRLO; /*MAC Source Address Low Bytes Register*/
/*MDIO Module Registers */
uint32 MDIOCONTROL; /*MDIO Control Register. */
/* EMAC Control Module Registers */
uint32 C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/
uint32 C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/
} emac_config_reg_t;
/*****************************************************************************/
/**
* @defgroup EMACMDIO EMAC/MDIO
* @brief Ethernet Media Access Controller/Management Data Input/Output.
*
* The EMAC controls the flow of packet data from the system to the PHY. The MDIO module
*controls PHY configuration and status monitoring.
*
* Both the EMAC and the MDIO modules interface to the system core through a custom
*interface that allows efficient data transmission and reception. This custom interface
*is referred to as the EMAC control module and is considered integral to the EMAC/MDIO
*peripheral
*
* Related Files
* - emac.h
* - emac.c
* - hw_emac.h
* - hw_emac_ctrl.h
* - hw_mdio.h
* - hw_reg_access.h
* - mdio.h
* - mdio.c
* @addtogroup EMACMDIO
* @{
*/
/*
** Prototypes for the APIs
*/
extern uint32 EMACLinkSetup( hdkif_t * hdkif );
extern void EMACInstConfig( hdkif_t * hdkif );
extern void EMACTxIntPulseEnable( uint32 emacBase,
uint32 emacCtrlBase,
uint32 ctrlCore,
uint32 channel );
extern void EMACTxIntPulseDisable( uint32 emacBase,
uint32 emacCtrlBase,
uint32 ctrlCore,
uint32 channel );
extern void EMACRxIntPulseEnable( uint32 emacBase,
uint32 emacCtrlBase,
uint32 ctrlCore,
uint32 channel );
extern void EMACRxIntPulseDisable( uint32 emacBase,
uint32 emacCtrlBase,
uint32 ctrlCore,
uint32 channel );
extern void EMACRMIISpeedSet( uint32 emacBase, uint32 speed );
extern void EMACDuplexSet( uint32 emacBase, uint32 duplexMode );
extern void EMACTxEnable( uint32 emacBase );
extern void EMACTxDisable( uint32 emacBase );
extern void EMACRxEnable( uint32 emacBase );
extern void EMACRxDisable( uint32 emacBase );
uint32 EMACSwizzleData( uint32 word );
extern void EMACTxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel );
extern void EMACRxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel );
extern void EMACInit( uint32 emacCtrlBase, uint32 emacBase );
extern void EMACMACSrcAddrSet( uint32 emacBase, uint8 macAddr[ 6 ] );
extern void EMACMACAddrSet( uint32 emacBase,
uint32 channel,
uint8 macAddr[ 6 ],
uint32 matchFilt );
extern void EMACMIIEnable( uint32 emacBase );
extern void EMACMIIDisable( uint32 emacBase );
extern void EMACRxUnicastSet( uint32 emacBase, uint32 channel );
extern void EMACRxUnicastClear( uint32 emacBase, uint32 channel );
extern void EMACCoreIntAck( uint32 emacBase, uint32 eoiFlag );
extern void EMACTxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr );
extern void EMACRxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr );
extern void EMACRxBroadCastEnable( uint32 emacBase, uint32 channel );
extern void EMACRxBroadCastDisable( uint32 emacBase, uint32 channel );
extern void EMACRxMultiCastEnable( uint32 emacBase, uint32 channel );
extern void EMACRxMultiCastDisable( uint32 emacBase, uint32 channel );
extern void EMACNumFreeBufSet( uint32 emacBase, uint32 channel, uint32 nBuf );
extern uint32 EMACIntVectorGet( uint32 emacBase );
uint32 EMACHWInit( uint8_t macaddr[ 6U ] );
void EMACTxTeardown( uint32 emacBase, uint32 channel );
void EMACRxTeardown( uint32 emacBase, uint32 channel );
void EMACFrameSelect( uint32 emacBase, uint64 hashTable );
void EMACTxPrioritySelect( uint32 emacBase, uint32 txPType );
void EMACSoftReset( uint32 emacCtrlBase, uint32 emacBase );
void EMACEnableIdleState( uint32 emacBase );
void EMACDisableIdleState( uint32 emacBase );
void EMACEnableLoopback( uint32 emacBase );
void EMACDisableLoopback( uint32 emacBase );
void EMACTxFlowControlEnable( uint32 emacBase );
void EMACTxFlowControlDisable( uint32 emacBase );
void EMACRxFlowControlEnable( uint32 emacBase );
void EMACRxFlowControlDisable( uint32 emacBase );
void EMACRxSetFlowThreshold( uint32 emacBase, uint32 channel, uint32 threshold );
uint32 EMACReadNetStatRegisters( uint32 emacBase, uint32 statRegNo );
void EMACDMAInit( hdkif_t * hdkif );
boolean EMACTransmit( hdkif_t * hdkif, pbuf_t * pbuf );
void EMACTxIntHandler( hdkif_t * hdkif );
void EMACReceive( hdkif_t * hdkif );
/* Notification Function to which received packets are passed after processing */
void emacTxNotification( hdkif_t * hdkif );
void emacRxNotification( hdkif_t * hdkif );
void EMACTxIntStat( uint32 emacBase, uint32 channel, emac_tx_int_status_t * txintstat );
void EMACRxIntStat( uint32 emacBase, uint32 channel, emac_rx_int_status_t * rxintstat );
void EMACGetConfigValue( emac_config_reg_t * config_reg, config_value_type_t type );
/* USER CODE BEGIN (2) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* __EMAC_H__ */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac_phyConfig.h
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/**
* \file emac_phyConfig.h
*
* \brief PHY Configuration file for selecting and configuring the required PHY.
*
* This file contains the mappings of the PHY APIs so that the right one is chosen based
* on the user's preference.
*/
/* (c) Texas Instruments 2009-2014, All rights reserved. */
#ifndef _EMAC_PHYCONFIG_H_
#define _EMAC_PHYCONFIG_H_
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include "phy_dp83640.h"
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (2) */
/* USER CODE END */
#define PhyIDGet Dp83640IDGet
#define PhyLinkStatusGet Dp83640LinkStatusGet
#define PhyAutoNegotiate Dp83640AutoNegotiate
#define PhyPartnerAbilityGet Dp83640PartnerAbilityGet
#define PhyReset Dp83640Reset
#define PhyEnableLoopback Dp83640EnableLoopback
#define PhyDisableLoopback Dp83640DisableLoopback
#define PhyGetTimeStamp Dp83640GetTimeStamp
#define PhyPartnerSpdGet Dp83640PartnerSpdGet
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _EMAC_PHYCONFIG_H_ */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emif.h
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/** @file emif.h
* @brief emif Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _EMIF_H_
#define _EMIF_H_
#include "reg_emif.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @enum emif_pins
* @brief Alias for emif pins
*
*/
enum emif_pins
{
emif_wait_pin0 = 0U,
emif_wait_pin1 = 1U
};
/** @enum emif_size
* @brief Alias for emif page size
*
*/
enum emif_size
{
elements_256 = 0U,
elements_512 = 1U,
elements_1024 = 2U,
elements_2048 = 3U
};
/** @enum emif_port
* @brief Alias for emif port
*
*/
enum emif_port
{
emif_8_bit_port = 0U,
emif_16_bit_port = 1U
};
/** @enum emif_pagesize
* @brief Alias for emif pagesize
*
*/
enum emif_pagesize
{
emif_4_words = 0U,
emif_8_words = 1U
};
/** @enum emif_wait_polarity
* @brief Alias for emif wait polarity
*
*/
enum emif_wait_polarity
{
emif_pin_low = 0U,
emif_pin_high = 1U
};
#define PTR ( ( volatile uint32 * ) ( 0x80000000U ) )
/* Configuration registers */
typedef struct emif_config_reg
{
uint32 CONFIG_AWCC;
uint32 CONFIG_SDCR;
uint32 CONFIG_SDRCR;
uint32 CONFIG_CE2CFG;
uint32 CONFIG_CE3CFG;
uint32 CONFIG_CE4CFG;
uint32 CONFIG_CE5CFG;
uint32 CONFIG_SDTIMR;
uint32 CONFIG_SDSRETR;
uint32 CONFIG_INTMSK;
uint32 CONFIG_PMCR;
} emif_config_reg_t;
/* Configuration registers initial value for EMIF*/
#define EMIF_AWCC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) \
| ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) \
| ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 16U ) \
| ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 18U ) \
| ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 20U ) | ( uint32 ) ( ( uint32 ) 0U ) \
| ( uint32 ) 0xC0000000U )
#define EMIF_SDCR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 31U ) | ( uint32 ) ( ( uint32 ) 1U << 14U ) \
| ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \
| ( uint32 ) ( ( uint32 ) elements_256 ) )
#define EMIF_SDRCR_CONFIGVALUE 0U
#define EMIF_CE2CFG_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \
| ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \
| ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \
| ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) )
#define EMIF_CE3CFG_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \
| ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \
| ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \
| ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) )
#define EMIF_CE4CFG_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \
| ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \
| ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \
| ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) )
#define EMIF_CE5CFG_CONFIGVALUE 0x3FFFFFFDU
#define EMIF_SDTIMR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | 0x00000000U )
#define EMIF_SDSRETR_CONFIGVALUE 0U
#define EMIF_INTMSK_CONFIGVALUE 0x00000000U
#define EMIF_PMCR_CONFIGVALUE \
( 0xFC000000U | ( uint32 ) ( ( uint32 ) 0U << 2U ) \
| ( uint32 ) ( ( uint32 ) emif_4_words << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) \
| ( uint32 ) ( ( uint32 ) emif_4_words << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \
| ( uint32 ) ( ( uint32 ) emif_4_words << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) )
/**
* @defgroup EMIF EMIF
* @brief External Memory Interface.
*
* This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories
*utilizing a 16-bit data bus. The purpose of this EMIF is to provide a means for the CPU
*to connect to a variety of external devices including:
* - Single data rate (SDR) SDRAM
* - Asynchronous devices including NOR Flash and SRAM
* The most common use for the EMIF is to interface with both a flash device and an SDRAM
*device simultaneously. contains an example of operating the EMIF in this configuration.
*
* Related Files
* - reg_emif.h
* - emif.h
* - emif.c
* @addtogroup EMIF
* @{
*/
/* EMIF Interface Functions */
void emif_SDRAMInit( void );
void emif_SDRAM_StartupInit( void );
void emif_ASYNC1Init( void );
void emif_ASYNC2Init( void );
void emif_ASYNC3Init( void );
void emifGetConfigValue( emif_config_reg_t * config_reg, config_value_type_t type );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif /*EMIF_H_*/
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/epc.h
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/** @file epc.h
* @brief EPC Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the EPC driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef SYS_EPC_H_
#define SYS_EPC_H_
#include "reg_epc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
enum CAMIndex
{
CAMIndex_0 = 0U,
CAMIndex_1 = 1U,
CAMIndex_2 = 2U,
CAMIndex_3 = 3U,
CAMIndex_4 = 4U,
CAMIndex_5 = 5U,
CAMIndex_6 = 6U,
CAMIndex_7 = 7U,
CAMIndex_8 = 8U,
CAMIndex_9 = 9U,
CAMIndex_10 = 10U,
CAMIndex_11 = 11U,
CAMIndex_12 = 12U,
CAMIndex_13 = 13U,
CAMIndex_14 = 14U,
CAMIndex_15 = 15U,
CAMIndex_16 = 16U,
CAMIndex_17 = 17U,
CAMIndex_18 = 18U,
CAMIndex_19 = 19U,
CAMIndex_20 = 20U,
CAMIndex_21 = 21U,
CAMIndex_22 = 22U,
CAMIndex_23 = 23U,
CAMIndex_24 = 24U,
CAMIndex_25 = 25U,
CAMIndex_26 = 26U,
CAMIndex_27 = 27U,
CAMIndex_28 = 28U,
CAMIndex_29 = 29U,
CAMIndex_30 = 30U,
CAMIndex_31 = 31U
};
/**
* @defgroup EPC EPC
* @brief Error Profiling Controller
*
* Related files:
* - reg_epc.h
* - sys_epc.h
* - sys_epc.c
*
* @addtogroup EPC
* @{
*/
void epcEnableIP1ErrorGen( void );
void epcDisableIP1ErrorGen( void );
void epcEnableIP2ErrorGen( void );
void epcDisableIP2ErrorGen( void );
void epcEnableSERREvent( void );
void epcDisableSERREvent( void );
void epcEnableInterrupt( void );
void epcDisableInterrupt( void );
void epcCAMInit( void );
boolean epcDiagnosticTest( void );
boolean epcAddCAMEEntry( uint32 address );
boolean epcCheckCAMEntry( uint32 index );
void epcCAMFullNotification( void );
void epcFIFOFullNotification( uint32 epcFIFOStatus );
/**@}*/
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif /* SYS_EPC_H_ */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/eqep.h
+863
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/errata.h
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/** @file errata.c
* @brief Errata workaround Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Errata workaround API's
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __errata_H__
#define __errata_H__
#include "reg_pbist.h"
#include "reg_system.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
#define PBISTERRATA_FAIL1 1U
#define PBISTERRATA_FAIL2 2U
#define PBISTERRATA_FAIL3 3U
void errata_PBIST_4( void );
void errataFailNotification( uint32 flag );
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
#endif
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/errata_SSWF021_45.h
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/** @file errata_SSWF021_45.c
* @brief errata for PLLs
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef INCLUDE_ERRATA_SSWF021_45_H_
#define INCLUDE_ERRATA_SSWF021_45_H_
uint32 _errata_SSWF021_45_both_plls( uint32 count );
uint32 _errata_SSWF021_45_pll1( uint32 count );
uint32 _errata_SSWF021_45_pll2( uint32 count );
#endif /* INCLUDE_ERRATA_SSWF021_45_H_ */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/errata_SSWF021_45_defs.h
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/** @file errata_SSWF021_45.c
* @brief errata for PLLs
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef INCLUDE_ERRATA_SSWF021_45_DEFS_H_
#define INCLUDE_ERRATA_SSWF021_45_DEFS_H_
typedef unsigned int uint32_t;
typedef uint32_t uint32;
typedef volatile struct systemBase1
{
uint32 SYSPC1; /* 0x0000 */
uint32 SYSPC2; /* 0x0004 */
uint32 SYSPC3; /* 0x0008 */
uint32 SYSPC4; /* 0x000C */
uint32 SYSPC5; /* 0x0010 */
uint32 SYSPC6; /* 0x0014 */
uint32 SYSPC7; /* 0x0018 */
uint32 SYSPC8; /* 0x001C */
uint32 SYSPC9; /* 0x0020 */
uint32 SSWPLL1; /* 0x0024 */
uint32 SSWPLL2; /* 0x0028 */
uint32 SSWPLL3; /* 0x002C */
uint32 CSDIS; /* 0x0030 */
uint32 CSDISSET; /* 0x0034 */
uint32 CSDISCLR; /* 0x0038 */
uint32 CDDIS; /* 0x003C */
uint32 CDDISSET; /* 0x0040 */
uint32 CDDISCLR; /* 0x0044 */
uint32 GHVSRC; /* 0x0048 */
uint32 VCLKASRC; /* 0x004C */
uint32 RCLKSRC; /* 0x0050 */
uint32 CSVSTAT; /* 0x0054 */
uint32 MSTGCR; /* 0x0058 */
uint32 MINITGCR; /* 0x005C */
uint32 MSINENA; /* 0x0060 */
uint32 MSTFAIL; /* 0x0064 */
uint32 MSTCGSTAT; /* 0x0068 */
uint32 MINISTAT; /* 0x006C */
uint32 PLLCTL1; /* 0x0070 */
uint32 PLLCTL2; /* 0x0074 */
uint32 SYSPC10; /* 0x0078 */
uint32 DIEIDL; /* 0x007C */
uint32 DIEIDH; /* 0x0080 */
uint32 VRCTL; /* 0x0084 */
uint32 LPOMONCTL; /* 0x0088 */
uint32 CLKTEST; /* 0x008C */
uint32 DFTCTRLREG1; /* 0x0090 */
uint32 DFTCTRLREG2; /* 0x0094 */
uint32 rsvd1; /* 0x0098 */
uint32 rsvd2; /* 0x009C */
uint32 GPREG1; /* 0x00A0 */
uint32 BTRMSEL; /* 0x00A4 */
uint32 IMPFASTS; /* 0x00A8 */
uint32 IMPFTADD; /* 0x00AC */
uint32 SSISR1; /* 0x00B0 */
uint32 SSISR2; /* 0x00B4 */
uint32 SSISR3; /* 0x00B8 */
uint32 SSISR4; /* 0x00BC */
uint32 RAMGCR; /* 0x00C0 */
uint32 BMMCR1; /* 0x00C4 */
uint32 BMMCR2; /* 0x00C8 */
uint32 CPURSTCR; /* 0x00CC */
uint32 CLKCNTL; /* 0x00D0 */
uint32 ECPCNTL; /* 0x00D4 */
uint32 DSPGCR; /* 0x00D8 */
uint32 DEVCR1; /* 0x00DC */
uint32 SYSECR; /* 0x00E0 */
uint32 SYSESR; /* 0x00E4 */
uint32 SYSTASR; /* 0x00E8 */
uint32 GBLSTAT; /* 0x00EC */
uint32 DEV; /* 0x00F0 */
uint32 SSIVEC; /* 0x00F4 */
uint32 SSIF; /* 0x00F8 */
} systemBASE1_t;
typedef volatile struct systemBase2
{
uint32 PLLCTL3; /* 0x0000 */
uint32 rsvd1; /* 0x0004 */
uint32 STCCLKDIV; /* 0x0008 */
uint32 rsvd2[ 6U ]; /* 0x000C */
uint32 ECPCNTRL0; /* 0x0024 */
uint32 rsvd3[ 5U ]; /* 0x0028 */
uint32 CLK2CNTL; /* 0x003C */
uint32 VCLKACON1; /* 0x0040 */
uint32 rsvd4[ 11U ]; /* 0x0044 */
uint32 CLKSLIP; /* 0x0070 */
uint32 rsvd5[ 30U ]; /* 0x0074 */
uint32 EFC_CTLEN; /* 0x00EC */
uint32 DIEIDL_REG0; /* 0x00F0 */
uint32 DIEIDH_REG1; /* 0x00F4 */
uint32 DIEIDL_REG2; /* 0x00F8 */
uint32 DIEIDH_REG3; /* 0x00FC */
} systemBASE2_t;
typedef volatile struct esmBase
{
uint32 EEPAPR1; /* 0x0000 */
uint32 DEPAPR1; /* 0x0004 */
uint32 IESR1; /* 0x0008 */
uint32 IECR1; /* 0x000C */
uint32 ILSR1; /* 0x0010 */
uint32 ILCR1; /* 0x0014 */
uint32 SR1[ 3U ]; /* 0x0018, 0x001C, 0x0020 */
uint32 EPSR; /* 0x0024 */
uint32 IOFFHR; /* 0x0028 */
uint32 IOFFLR; /* 0x002C */
uint32 LTCR; /* 0x0030 */
uint32 LTCPR; /* 0x0034 */
uint32 EKR; /* 0x0038 */
uint32 SSR2; /* 0x003C */
uint32 IEPSR4; /* 0x0040 */
uint32 IEPCR4; /* 0x0044 */
uint32 IESR4; /* 0x0048 */
uint32 IECR4; /* 0x004C */
uint32 ILSR4; /* 0x0050 */
uint32 ILCR4; /* 0x0054 */
uint32 SR4[ 3U ]; /* 0x0058, 0x005C, 0x0060 */
} esmBASE_t;
typedef volatile struct dccBase
{
uint32 GCTRL; /**< 0x0000: DCC Control Register */
uint32 REV; /**< 0x0004: DCC Revision Id Register */
uint32 CNT0SEED; /**< 0x0008: DCC Counter0 Seed Register */
uint32 VALID0SEED; /**< 0x000C: DCC Valid0 Seed Register */
uint32 CNT1SEED; /**< 0x0010: DCC Counter1 Seed Register */
uint32 STAT; /**< 0x0014: DCC Status Register */
uint32 CNT0; /**< 0x0018: DCC Counter0 Value Register */
uint32 VALID0; /**< 0x001C: DCC Valid0 Value Register */
uint32 CNT1; /**< 0x0020: DCC Counter1 Value Register */
uint32 CNT1CLKSRC; /**< 0x0024: DCC Counter1 Clock Source Selection Register */
uint32 CNT0CLKSRC; /**< 0x0028: DCC Counter0 Clock Source Selection Register */
} dccBASE_t;
enum dcc1clocksource
{
DCC1_CNT0_HF_LPO = 0x5U, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
DCC1_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/
DCC1_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
DCC1_CNT1_PLL1 = 0x0U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/
DCC1_CNT1_PLL2 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/
DCC1_CNT1_LF_LPO = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/
DCC1_CNT1_HF_LPO = 0x3U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/
DCC1_CNT1_EXTCLKIN1 = 0x5U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/
DCC1_CNT1_EXTCLKIN2 = 0x6U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/
DCC1_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
DCC1_CNT1_N2HET1_31 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
};
#define SYS_CLKSRC_PLL1 0x00000002U
#define SYS_CLKSRC_PLL2 0x00000040U
#define SYS_CLKCNTRL_PENA 0x00000100U
#define ESM_SR1_PLL1SLIP 0x400U
#define ESM_SR4_PLL2SLIP 0x400U
#define PLL1 0x08
#define PLL2 0x80
#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U
#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U
#define systemREG1 ( ( systemBASE1_t * ) 0xFFFFFF00U )
#define systemREG2 ( ( systemBASE2_t * ) 0xFFFFE100U )
#define esmREG ( ( esmBASE_t * ) 0xFFFFF500U )
#define dccREG1 ( ( dccBASE_t * ) 0xFFFFEC00U )
#endif /* INCLUDE_ERRATA_SSWF021_45_DEFS_H_ */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/esm.h
+1178
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/etpwm.h
+909
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/fee_interface.h
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/**********************************************************************************************************************
* FILE DESCRIPTION
*
-------------------------------------------------------------------------------------------------------------------
* File: fee_interface.h
* Project: Tms570_TIFEEDriver
* Module: FEE Driver
* Generator: None
*
* Description: This file is interfce between Autosar FEE and TI FEE.
*---------------------------------------------------------------------------------------------------------------------
* Author: Vishwanath Reddy
*---------------------------------------------------------------------------------------------------------------------
* Revision History
*---------------------------------------------------------------------------------------------------------------------
* Version Date Author Change ID Description
*---------------------------------------------------------------------------------------------------------------------
* 00.01.00 07Sept2012 Vishwanath Reddy 0000000000000 Initial Version
* 00.01.01 14Sept2012 Vishwanath Reddy 0000000000000 Review changes
* 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 Misra Fixes, Memory
segmentation changes.
* 00.01.03 14Jan2013 Vishwanath Reddy SDOCM00098510 Changes as requested
by Vector.
* 00.01.06 11Mar2013 Vishwanath Reddy SDOCM00099152 Added feature :
copying of unconfigured blocks.
* 00.01.07 15Mar2013 Vishwanath Reddy SDOCM00099152 Added feature :
Number of 8 bytes writes, fixed issue with copy blocks.
* 00.01.08 05Apr2013 Vishwanath Reddy SDOCM00099152 Added feature :CRC
check for unconfigured blocks, Main function modified to complete writes as fast as
possible, Added Non polling mode support.
* 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 Traceability tags
added.
* MISRA C fixes.
* 01.21.00 15Oct2014 Vishwanath Reddy SDOCM00113379 RAM Optimization
changes. Added mew ,acro
* TI_FEE_TOTAL_BLOCKS_DATASETS
* 01.22.00 26Dec2014 Vishwanath Reddy SDOCM00114423 Following new macros
added.
* TI_FEE_VIRTUALSECTOR_SIZE,
* TI_FEE_PHYSICALSECTOR_SIZE,
* TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC.
* 01.23.00 12Oct2015 Vishwanath Reddy SDOCM00119455 Update version
history.
* 01.23.01 17Nov2015 Vishwanath Reddy SDOCM00120161 Updated version
history.
* 01.23.02 10Mar2016 Vishwanath Reddy SDOCM00121622 Updated version
history.
* 01.23.03 04Aug2016 Vishwanath Reddy SDOCM00122571 Update patch version
FEE_SW_PATCH_VERSION.
* 01.23.04 12Aug2016 Vishwanath Reddy SDOCM00122592
TI_FEE_CHECK_BANK7_ACCESS is always turned on.
* FEE_FLASH_CRC_ENABLE
is renamed to
* FEE_FLASH_CHECKSUM_ENABLE.
* New macro
FEE_USEPARTIALERASEDSECTOR added.
* 01.23.05 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version
history for AUTOSAR FEE
* (This corresponds to
TI FEE 1.19.04.)
*********************************************************************************************************************/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef FEE_INTERFACE_H
#define FEE_INTERFACE_H
#include "ti_fee_cfg.h"
#if( TI_FEE_DRIVER == 0U ) /* Include following macros only in Autosar Context */
#include "fee_cfg.h"
#include "nvm.h"
#define Fee_None \
0x00U /* Take no action on single bit errors, (respond with corrected data), \
*/
/* return error for uncorrectable error reads (multi bit errors for ECC or parity
* failures). */
/* For devices with no ECC (they may have parity or not) the only valid option is
* none. */
#define Fee_Fix \
0x01U /* single bit "zero" error will be fixed by reprogramming, single bit \
"one" error */
/* will be fixed by marking the current entry as invalid and copying the data to a new
* entry,*/
/* return error for uncorrectable error reads (multi bit errors for ECC or parity
* failures). */
#define TI_Fee_None \
0x00U /* Take no action on single bit errors, (respond with corrected data), \
*/
/* return error for uncorrectable error reads(multibit errors for ECC or parity
* failures)*/
/* For devices with no ECC (they may have parity or not) the only valid option is
* none. */
#define TI_Fee_Fix \
0x01U /* single bit "zero" error will be fixed by reprogramming, single bit \
"one" error */
/* will be fixed by marking the current entry as invalid and copying the data to a new
entry, */
/* return error for uncorrectable error reads (multi bit errors for ECC or parity
failures)*/
#if( FEE_FLASH_ERROR_CORRECTION_HANDLING == Fee_Fix )
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - TI_Fee_Fix is a symbolic
* constant."*/
#define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_Fix
#else
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - TI_Fee_None is a symbolic
* constant."*/
#define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_None
#endif
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_MAXIMUM_BLOCKING_TIME is a
* symbolic constant"*/
#define TI_FEE_MAXIMUM_BLOCKING_TIME FEE_MAXIMUM_BLOCKING_TIME
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_OPERATING_FREQUENCY is a
* symbolic constant."*/
#define TI_FEE_OPERATING_FREQUENCY FEE_OPERATING_FREQUENCY
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_FLASH_ERROR_CORRECTION_ENABLE
* is a symbolic constant."*/
#define TI_FEE_FLASH_ERROR_CORRECTION_ENABLE FEE_FLASH_ERROR_CORRECTION_ENABLE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_FLASH_CHECKSUM_ENABLE is a
* symbolic constant."*/
#define TI_FEE_FLASH_CHECKSUM_ENABLE FEE_FLASH_CHECKSUM_ENABLE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_FLASH_WRITECOUNTER_SAVE is a
* symbolic constant."*/
#define TI_FEE_FLASH_WRITECOUNTER_SAVE FEE_FLASH_WRITECOUNTER_SAVE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - NVM_DATASET_SELECTION_BITS is a
* symbolic constant."*/
#define TI_FEE_DATASELECT_BITS NVM_DATASET_SELECTION_BITS
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_EEPS is a symbolic
* constant."*/
#define TI_FEE_NUMBER_OF_EEPS FEE_NUMBER_OF_EEPS
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_INDEX is a symbolic
* constant."*/
#define TI_FEE_INDEX FEE_INDEX
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_PAGE_OVERHEAD is a symbolic
* constant."*/
#define TI_FEE_PAGE_OVERHEAD FEE_PAGE_OVERHEAD
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_BLOCK_OVERHEAD is a symbolic
* constant."*/
#define TI_FEE_BLOCK_OVERHEAD FEE_BLOCK_OVERHEAD
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_VIRTUAL_PAGE_SIZE is a
* symbolic constant."*/
#define TI_FEE_VIRTUAL_PAGE_SIZE FEE_VIRTUAL_PAGE_SIZE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_VIRTUAL_SECTOR_OVERHEAD is a
* symbolic constant."*/
#define TI_FEE_VIRTUAL_SECTOR_OVERHEAD FEE_VIRTUAL_SECTOR_OVERHEAD
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason -
* FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY is a symbolic constant."*/
#define TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY \
FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_EIGHTBYTEWRITES is a
* symbolic constant."*/
#define TI_FEE_NUMBER_OF_EIGHTBYTEWRITES FEE_NUMBER_OF_EIGHTBYTEWRITES
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NVM_JOB_END_NOTIFICATION is a
* symbolic constant."*/
#define TI_FEE_NVM_JOB_END_NOTIFICATION FEE_NVM_JOB_END_NOTIFICATION
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NVM_JOB_ERROR_NOTIFICATION is
* a symbolic constant."*/
#define TI_FEE_NVM_JOB_ERROR_NOTIFICATION FEE_NVM_JOB_ERROR_NOTIFICATION
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_POLLING_MODE is a symbolic
* constant."*/
#define TI_FEE_POLLING_MODE FEE_POLLING_MODE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_CHECK_BANK7_ACCESS is a
* symbolic constant."*/
#ifndef FEE_CHECK_BANK7_ACCESS
#define TI_FEE_CHECK_BANK7_ACCESS STD_ON
#else
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_CHECK_BANK7_ACCESS is a
* symbolic constant."*/
#define TI_FEE_CHECK_BANK7_ACCESS STD_ON
#endif
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_TOTAL_BLOCKS_DATASETS is a
* symbolic constant."*/
#define TI_FEE_TOTAL_BLOCKS_DATASETS FEE_TOTAL_BLOCKS_DATASETS
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_VIRTUALSECTOR_SIZE is a
* symbolic constant."*/
#define TI_FEE_VIRTUALSECTOR_SIZE FEE_VIRTUALSECTOR_SIZE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_PHYSICALSECTOR_SIZE is a
* symbolic constant."*/
#define TI_FEE_PHYSICALSECTOR_SIZE FEE_PHYSICALSECTOR_SIZE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason -
* FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC is a symbolic constant."*/
#define TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC \
FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_USEPARTIALERASEDSECTOR is a
* symbolic constant."*/
#define TI_FEE_USEPARTIALERASEDSECTOR FEE_USEPARTIALERASEDSECTOR
/*----------------------------------------------------------------------------*/
/* Virtual Sector Configuration */
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS is a
* symbolic constant."*/
/*SAFETYMCUSW 61 X MR:1.4,5.1 <APPROVED> "Reason - Similar Identifier name is
* required here."*/
#define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS FEE_NUMBER_OF_VIRTUAL_SECTORS
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1
* is a symbolic constant."*/
/*SAFETYMCUSW 384 S MR:1.4,5.1 <APPROVED> "Reason - Similar Identifier name is
* required here."*/
/*SAFETYMCUSW 61 X MR:1.4,5.1 <APPROVED> "Reason - Similar Identifier name is
* required here."*/
#define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1
/*----------------------------------------------------------------------------*/
/* Block Configuration */
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_BLOCKS is a symbolic
* constant."*/
#define TI_FEE_NUMBER_OF_BLOCKS FEE_NUMBER_OF_BLOCKS
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - TI_FEE_VARIABLE_DATASETS is a
* symbolic constant."*/
#define TI_FEE_VARIABLE_DATASETS STD_ON
#endif /* TI_FEE_DRIVER */
#endif /* FEE_INTERFACE_H */
/**********************************************************************************************************************
* END OF FILE: fee_interface.h
*********************************************************************************************************************/
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/gio.h
+182
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/** @file gio.h
* @brief GIO Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __GIO_H__
#define __GIO_H__
#include "reg_gio.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
typedef struct gio_config_reg
{
uint32 CONFIG_INTDET;
uint32 CONFIG_POL;
uint32 CONFIG_INTENASET;
uint32 CONFIG_LVLSET;
uint32 CONFIG_PORTADIR;
uint32 CONFIG_PORTAPDR;
uint32 CONFIG_PORTAPSL;
uint32 CONFIG_PORTAPULDIS;
uint32 CONFIG_PORTBDIR;
uint32 CONFIG_PORTBPDR;
uint32 CONFIG_PORTBPSL;
uint32 CONFIG_PORTBPULDIS;
} gio_config_reg_t;
#define GIO_INTDET_CONFIGVALUE 0U
#define GIO_POL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) )
#define GIO_INTENASET_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) )
#define GIO_LVLSET_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) )
#define GIO_PORTADIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTAPDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTAPSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTAPULDIS_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTBDIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTBPDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTBPSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTBPULDIS_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
/**
* @defgroup GIO GIO
* @brief General-Purpose Input/Output Module.
*
* The GIO module provides the family of devices with input/output (I/O) capability.
* The I/O pins are bidirectional and bit-programmable.
* The GIO module also supports external interrupt capability.
*
* Related Files
* - reg_gio.h
* - gio.h
* - gio.c
* @addtogroup GIO
* @{
*/
/* GIO Interface Functions */
void gioInit( void );
void gioSetDirection( gioPORT_t * port, uint32 dir );
void gioSetBit( gioPORT_t * port, uint32 bit, uint32 value );
void gioSetPort( gioPORT_t * port, uint32 value );
uint32 gioGetBit( gioPORT_t * port, uint32 bit );
uint32 gioGetPort( gioPORT_t * port );
void gioToggleBit( gioPORT_t * port, uint32 bit );
void gioEnableNotification( gioPORT_t * port, uint32 bit );
void gioDisableNotification( gioPORT_t * port, uint32 bit );
void gioNotification( gioPORT_t * port, uint32 bit );
void gioGetConfigValue( gio_config_reg_t * config_reg, config_value_type_t type );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h
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/** @file hal_stdtypes.h
* @brief HALCoGen standard types header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Type and Global definitions which are relevant for all drivers.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HAL_STDTYPES_H__
#define __HAL_STDTYPES_H__
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include <stdint.h>
#include <stdbool.h>
/* USER CODE BEGIN (1) */
/* USER CODE END */
/************************************************************/
/* Type Definitions */
/************************************************************/
#ifndef _UINT64_DECLARED
typedef uint64_t uint64;
#define _UINT64_DECLARED
#endif
#ifndef _UINT32_DECLARED
typedef uint32_t uint32;
#define _UINT32_DECLARED
#endif
#ifndef _UINT16_DECLARED
typedef uint16_t uint16;
#define _UINT16_DECLARED
#endif
#ifndef _UINT8_DECLARED
typedef uint8_t uint8;
#define _UINT8_DECLARED
#endif
#ifndef _BOOLEAN_DECLARED
#ifdef __cplusplus
typedef bool boolean;
#else
typedef _Bool boolean;
#endif
#define _BOOLEAN_DECLARED
#endif
#ifndef _SINT64_DECLARED
typedef int64_t sint64;
#define _SINT64_DECLARED
#endif
#ifndef _SINT32_DECLARED
typedef int32_t sint32;
#define _SINT32_DECLARED
#endif
#ifndef _SINT16_DECLARED
typedef int16_t sint16;
#define _SINT16_DECLARED
#endif
#ifndef _SINT8_DECLARED
typedef int8_t sint8;
#define _SINT8_DECLARED
#endif
#ifndef _FLOAT32_DECLARED
typedef float float32;
#define _FLOAT32_DECLARED
#endif
#ifndef _FLOAT64_DECLARED
typedef double float64;
#define _FLOAT64_DECLARED
#endif
typedef uint8 Std_ReturnType;
typedef struct
{
uint16 vendorID;
uint16 moduleID;
uint8 instanceID;
uint8 sw_major_version;
uint8 sw_minor_version;
uint8 sw_patch_version;
} Std_VersionInfoType;
/*****************************************************************************/
/* SYMBOL DEFINITIONS */
/*****************************************************************************/
#ifndef STATUSTYPEDEFINED
#define STATUSTYPEDEFINED
#define E_OK 0x00U
typedef unsigned char StatusType;
#endif
#ifndef E_NOT_OK
#define E_NOT_OK 0x01U
#endif
#ifndef STD_ON
#define STD_ON 0x01U
#endif
#ifndef STD_OFF
#define STD_OFF 0x00U
#endif
/************************************************************/
/* Global Definitions */
/************************************************************/
/** @def NULL
* @brief NULL definition
*/
#ifndef NULL
#define NULL ( ( void * ) 0U )
#endif
/** @def TRUE
* @brief definition for TRUE
*/
#ifndef TRUE
#define TRUE true
#endif
/** @def FALSE
* @brief BOOLEAN definition for FALSE
*/
#ifndef FALSE
#define FALSE false
#endif
/*****************************************************************************/
/* Define: NULL_PTR */
/* Description: Void pointer to 0 */
/*****************************************************************************/
#ifndef NULL_PTR
#define NULL_PTR ( ( void * ) 0x0U )
#endif
/* USER CODE BEGIN (2) */
/* USER CODE END */
#endif /* __HAL_STDTYPES_H__ */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/het.h
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/htu.h
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/** @file htu.h
* @brief HTU Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HTU_H__
#define __HTU_H__
#include "reg_htu.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* HTU General Definitions */
#define HTU1PARLOC ( *( volatile uint32 * ) 0xFF4E0200U )
#define HTU2PARLOC ( *( volatile uint32 * ) 0xFF4C0200U )
#define HTU1RAMLOC ( *( volatile uint32 * ) 0xFF4E0000U )
#define HTU2RAMLOC ( *( volatile uint32 * ) 0xFF4C0000U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac.h
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h
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/*
* hw_emac1.h
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _HW_EMAC_CTRL_H_
#define _HW_EMAC_CTRL_H_
/* USER CODE BEGIN (0) */
/* USER CODE END */
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
#define EMAC_CTRL_REVID ( 0x0U )
#define EMAC_CTRL_SOFTRESET ( 0x4U )
#define EMAC_CTRL_INTCONTROL ( 0xCU )
#define EMAC_CTRL_C0RXTHRESHEN ( 0x10U )
#define EMAC_CTRL_CnRXEN( n ) ( ( uint32 ) 0x14u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) )
#define EMAC_CTRL_CnTXEN( n ) ( ( uint32 ) 0x18u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) )
#define EMAC_CTRL_CnMISCEN( n ) \
( ( uint32 ) 0x1Cu + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) )
#define EMAC_CTRL_CnRXTHRESHEN( n ) \
( ( uint32 ) 0x20u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) )
#define EMAC_CTRL_C0RXTHRESHSTAT ( 0x40U )
#define EMAC_CTRL_C0RXSTAT ( 0x44U )
#define EMAC_CTRL_C0TXSTAT ( 0x48U )
#define EMAC_CTRL_C0MISCSTAT ( 0x4CU )
#define EMAC_CTRL_C1RXTHRESHSTAT ( 0x50U )
#define EMAC_CTRL_C1RXSTAT ( 0x54U )
#define EMAC_CTRL_C1TXSTAT ( 0x58U )
#define EMAC_CTRL_C1MISCSTAT ( 0x5CU )
#define EMAC_CTRL_C2RXTHRESHSTAT ( 0x60U )
#define EMAC_CTRL_C2RXSTAT ( 0x64U )
#define EMAC_CTRL_C2TXSTAT ( 0x68U )
#define EMAC_CTRL_C2MISCSTAT ( 0x6CU )
#define EMAC_CTRL_C0RXIMAX ( 0x70U )
#define EMAC_CTRL_C0TXIMAX ( 0x74U )
#define EMAC_CTRL_C1RXIMAX ( 0x78U )
#define EMAC_CTRL_C1TXIMAX ( 0x7CU )
#define EMAC_CTRL_C2RXIMAX ( 0x80U )
#define EMAC_CTRL_C2TXIMAX ( 0x84U )
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* USER CODE BEGIN (2) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
#endif
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_mdio.h
+235
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/*
* hw_mdio.h
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _HW_MDIO_H_
#define _HW_MDIO_H_
/* USER CODE BEGIN (0) */
/* USER CODE END */
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
#define MDIO_BASE ( 0xFCF78900U )
#define MDIO_REVID ( 0x0U )
#define MDIO_CONTROL ( 0x4U )
#define MDIO_ALIVE ( 0x8U )
#define MDIO_LINK ( 0xCU )
#define MDIO_LINKINTRAW ( 0x10U )
#define MDIO_LINKINTMASKED ( 0x14U )
#define MDIO_USERINTRAW ( 0x20U )
#define MDIO_USERINTMASKED ( 0x24U )
#define MDIO_USERINTMASKSET ( 0x28U )
#define MDIO_USERINTMASKCLEAR ( 0x2CU )
#define MDIO_USERACCESS0 ( 0x80U )
#define MDIO_USERPHYSEL0 ( 0x84U )
#define MDIO_USERACCESS1 ( 0x88U )
#define MDIO_USERPHYSEL1 ( 0x8CU )
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* REVID */
#define MDIO_REVID_REV ( 0xFFFFFFFFU )
#define MDIO_REVID_REV_SHIFT ( 0x00000000U )
/* CONTROL */
#define MDIO_CONTROL_IDLE ( 0x80000000U )
#define MDIO_CONTROL_IDLE_SHIFT ( 0x0000001FU )
/*----IDLE Tokens----*/
#define MDIO_CONTROL_IDLE_NO ( 0x00000000U )
#define MDIO_CONTROL_IDLE_YES ( 0x00000001U )
#define MDIO_CONTROL_ENABLE ( 0x40000000U )
#define MDIO_CONTROL_ENABLE_SHIFT ( 0x0000001EU )
#define MDIO_CONTROL_HIGHEST_USER_CHANNEL ( 0x1F000000U )
#define MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT ( 0x00000018U )
#define MDIO_CONTROL_PREAMBLE ( 0x00100000U )
#define MDIO_CONTROL_PREAMBLE_SHIFT ( 0x00000014U )
/*----PREAMBLE Tokens----*/
#define MDIO_CONTROL_FAULT ( 0x00080000U )
#define MDIO_CONTROL_FAULT_SHIFT ( 0x00000013U )
#define MDIO_CONTROL_FAULTENB ( 0x00040000U )
#define MDIO_CONTROL_FAULTENB_SHIFT ( 0x00000012U )
/*----FAULTENB Tokens----*/
#define MDIO_CONTROL_CLKDIV ( 0x0000FFFFU )
#define MDIO_CONTROL_CLKDIV_SHIFT ( 0x00000000U )
/*----CLKDIV Tokens----*/
/* ALIVE */
#define MDIO_ALIVE_REGVAL ( 0xFFFFFFFFU )
#define MDIO_ALIVE_REGVAL_SHIFT ( 0x00000000U )
/* LINK */
#define MDIO_LINK_REGVAL ( 0xFFFFFFFFU )
#define MDIO_LINK_REGVAL_SHIFT ( 0x00000000U )
/* LINKINTRAW */
#define MDIO_LINKINTRAW_USERPHY1 ( 0x00000002U )
#define MDIO_LINKINTRAW_USERPHY1_SHIFT ( 0x00000001U )
#define MDIO_LINKINTRAW_USERPHY0 ( 0x00000001U )
#define MDIO_LINKINTRAW_USERPHY0_SHIFT ( 0x00000000U )
/* LINKINTMASKED */
#define MDIO_LINKINTMASKED_USERPHY1 ( 0x00000002U )
#define MDIO_LINKINTMASKED_USERPHY1_SHIFT ( 0x00000001U )
#define MDIO_LINKINTMASKED_USERPHY0 ( 0x00000001U )
#define MDIO_LINKINTMASKED_USERPHY0_SHIFT ( 0x00000000U )
/* USERINTRAW */
#define MDIO_USERINTRAW_USERACCESS1 ( 0x00000002U )
#define MDIO_USERINTRAW_USERACCESS1_SHIFT ( 0x00000001U )
#define MDIO_USERINTRAW_USERACCESS0 ( 0x00000001U )
#define MDIO_USERINTRAW_USERACCESS0_SHIFT ( 0x00000000U )
/* USERINTMASKED */
#define MDIO_USERINTMASKED_USERACCESS1 ( 0x00000002U )
#define MDIO_USERINTMASKED_USERACCESS1_SHIFT ( 0x00000001U )
#define MDIO_USERINTMASKED_USERACCESS0 ( 0x00000001U )
#define MDIO_USERINTMASKED_USERACCESS0_SHIFT ( 0x00000000U )
/* USERINTMASKSET */
#define MDIO_USERINTMASKSET_USERACCESS1 ( 0x00000002U )
#define MDIO_USERINTMASKSET_USERACCESS1_SHIFT ( 0x00000001U )
#define MDIO_USERINTMASKSET_USERACCESS0 ( 0x00000001U )
#define MDIO_USERINTMASKSET_USERACCESS0_SHIFT ( 0x00000000U )
/* USERINTMASKCLEAR */
#define MDIO_USERINTMASKCLEAR_USERACCESS1 ( 0x00000002U )
#define MDIO_USERINTMASKCLEAR_USERACCESS1_SHIFT ( 0x00000001U )
#define MDIO_USERINTMASKCLEAR_USERACCESS0 ( 0x00000001U )
#define MDIO_USERINTMASKCLEAR_USERACCESS0_SHIFT ( 0x00000000U )
/* USERACCESS0 */
#define MDIO_USERACCESS0_GO ( 0x80000000U )
#define MDIO_USERACCESS0_GO_SHIFT ( 0x0000001FU )
#define MDIO_USERACCESS0_WRITE ( 0x40000000U )
#define MDIO_USERACCESS0_READ ( 0x00000000U )
#define MDIO_USERACCESS0_WRITE_SHIFT ( 0x0000001EU )
#define MDIO_USERACCESS0_ACK ( 0x20000000U )
#define MDIO_USERACCESS0_ACK_SHIFT ( 0x0000001DU )
#define MDIO_USERACCESS0_REGADR ( 0x03E00000U )
#define MDIO_USERACCESS0_REGADR_SHIFT ( 0x00000015U )
#define MDIO_USERACCESS0_PHYADR ( 0x001F0000U )
#define MDIO_USERACCESS0_PHYADR_SHIFT ( 0x00000010U )
#define MDIO_USERACCESS0_DATA ( 0x0000FFFFU )
#define MDIO_USERACCESS0_DATA_SHIFT ( 0x00000000U )
/* USERPHYSEL0 */
#define MDIO_USERPHYSEL0_LINKSEL ( 0x00000080U )
#define MDIO_USERPHYSEL0_LINKSEL_SHIFT ( 0x00000007U )
#define MDIO_USERPHYSEL0_LINKINTENB ( 0x00000040U )
#define MDIO_USERPHYSEL0_LINKINTENB_SHIFT ( 0x00000006U )
#define MDIO_USERPHYSEL0_PHYADRMON ( 0x0000001FU )
#define MDIO_USERPHYSEL0_PHYADRMON_SHIFT ( 0x00000000U )
/* USERACCESS1 */
#define MDIO_USERACCESS1_GO ( 0x80000000U )
#define MDIO_USERACCESS1_GO_SHIFT ( 0x0000001FU )
#define MDIO_USERACCESS1_WRITE ( 0x40000000U )
#define MDIO_USERACCESS1_WRITE_SHIFT ( 0x0000001EU )
#define MDIO_USERACCESS1_ACK ( 0x20000000U )
#define MDIO_USERACCESS1_ACK_SHIFT ( 0x0000001DU )
#define MDIO_USERACCESS1_REGADR ( 0x03E00000U )
#define MDIO_USERACCESS1_REGADR_SHIFT ( 0x00000015U )
#define MDIO_USERACCESS1_PHYADR ( 0x001F0000U )
#define MDIO_USERACCESS1_PHYADR_SHIFT ( 0x00000010U )
#define MDIO_USERACCESS1_DATA ( 0x0000FFFFU )
#define MDIO_USERACCESS1_DATA_SHIFT ( 0x00000000U )
/* USERPHYSEL1 */
#define MDIO_USERPHYSEL1_LINKSEL ( 0x00000080U )
#define MDIO_USERPHYSEL1_LINKSEL_SHIFT ( 0x00000007U )
#define MDIO_USERPHYSEL1_LINKINTENB ( 0x00000040U )
#define MDIO_USERPHYSEL1_LINKINTENB_SHIFT ( 0x00000006U )
#define MDIO_USERPHYSEL1_PHYADRMON ( 0x0000001FU )
#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT ( 0x00000000U )
/* USER CODE BEGIN (2) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
#endif
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_reg_access.h
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/*
* hw_reg_access.h
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _HW_REG_ACCESS_H_
#define _HW_REG_ACCESS_H_
/* USER CODE BEGIN (0) */
/* USER CODE END */
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
/*******************************************************************************
*
* Macros for hardware access, both direct and via the bit-band region.
*
*****************************************************************************/
#define HWREG( x ) ( *( ( volatile uint32 * ) ( x ) ) )
#define HWREGH( x ) ( *( ( volatile uint16 * ) ( x ) ) )
#define HWREGB( x ) ( *( ( volatile uint8 * ) ( x ) ) )
#define HWREGBITW( x, b ) \
( HWREG( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \
| ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \
| ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) )
#define HWREGBITH( x, b ) \
( HWREGH( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \
| ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \
| ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) )
#define HWREGBITB( x, b ) \
( HWREGB( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \
| ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \
| ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) )
/* USER CODE BEGIN (2) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
#endif /* __HW_TYPES_H__ */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/i2c.h
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/** @file I2C.h
* @brief I2C Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __I2C_H__
#define __I2C_H__
#include "reg_i2c.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @enum i2cMode
* @brief Alias names for i2c modes
* This enumeration is used to provide alias names for I2C modes:
*/
enum i2cMode
{
I2C_FD_FORMAT = 0x0008U, /* Free Data Format */
I2C_START_BYTE = 0x0010U,
I2C_RESET_OUT = 0x0020U,
I2C_RESET_IN = 0x0000U,
I2C_DLOOPBACK = 0x0040U,
I2C_REPEATMODE = 0x0080U, /* In Master Mode only */
I2C_10BIT_AMODE = 0x0100U,
I2C_7BIT_AMODE = 0x0000U,
I2C_TRANSMITTER = 0x0200U,
I2C_RECEIVER = 0x0000U,
I2C_MASTER = 0x0400U,
I2C_SLAVE = 0x0000U,
I2C_STOP_COND = 0x0800U, /* In Master Mode only */
I2C_START_COND = 0x2000U, /* In Master Mode only */
I2C_FREE_RUN = 0x4000U,
I2C_NACK_MODE = 0x8000U
};
/** @enum i2cBitCount
* @brief Alias names for i2c bit count
* This enumeration is used to provide alias names for I2C bit count:
*/
enum i2cBitCount
{
I2C_2_BIT = 0x2U,
I2C_3_BIT = 0x3U,
I2C_4_BIT = 0x4U,
I2C_5_BIT = 0x5U,
I2C_6_BIT = 0x6U,
I2C_7_BIT = 0x7U,
I2C_8_BIT = 0x0U
};
/** @enum i2cIntFlags
* @brief Interrupt Flag Definitions
*
* Used with I2CEnableNotification, I2CDisableNotification
*/
enum i2cIntFlags
{
I2C_AL_INT = 0x0001U, /* arbitration lost */
I2C_NACK_INT = 0x0002U, /* no acknowledgment */
I2C_ARDY_INT = 0x0004U, /* access ready */
I2C_RX_INT = 0x0008U, /* receive data ready */
I2C_TX_INT = 0x0010U, /* transmit data ready */
I2C_SCD_INT = 0x0020U, /* stop condition detect */
I2C_AAS_INT = 0x0040U /* address as slave */
};
/** @enum i2cStatFlags
* @brief Interrupt Status Definitions
*
*/
enum i2cStatFlags
{
I2C_AL = 0x0001U, /* arbitration lost */
I2C_NACK = 0x0002U, /* no acknowledgement */
I2C_ARDY = 0x0004U, /* access ready */
I2C_RX = 0x0008U, /* receive data ready */
I2C_TX = 0x0010U, /* transmit data ready */
I2C_SCD = 0x0020U, /* stop condition detect */
I2C_AD0 = 0x0100U, /* address Zero Status */
I2C_AAS = 0x0200U, /* address as slave */
I2C_XSMT = 0x0400U, /* Transmit shift empty not */
I2C_RXFULL = 0x0800U, /* receive full */
I2C_BUSBUSY = 0x1000U, /* bus busy */
I2C_NACKSNT = 0x2000U, /* No Ack Sent */
I2C_SDIR = 0x4000U /* Slave Direction */
};
/** @enum i2cDMA
* @brief I2C DMA definitions
*
* Used before i2c transfer
*/
enum i2cDMA
{
I2C_TXDMA = 0x20U,
I2C_RXDMA = 0x10U
};
/* Configuration registers */
typedef struct i2c_config_reg
{
uint32 CONFIG_OAR;
uint32 CONFIG_IMR;
uint32 CONFIG_CLKL;
uint32 CONFIG_CLKH;
uint32 CONFIG_CNT;
uint32 CONFIG_SAR;
uint32 CONFIG_MDR;
uint32 CONFIG_EMDR;
uint32 CONFIG_PSC;
uint32 CONFIG_DMAC;
uint32 CONFIG_FUN;
uint32 CONFIG_DIR;
uint32 CONFIG_ODR;
uint32 CONFIG_PD;
uint32 CONFIG_PSL;
} i2c_config_reg_t;
/* Configuration registers initial value for I2C*/
#define I2C1_OAR_CONFIGVALUE 0x00000000U
#define I2C1_IMR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( ( uint32 ) 0U ) )
#define I2C1_CLKL_CONFIGVALUE 37U
#define I2C1_CLKH_CONFIGVALUE 37U
#define I2C1_CNT_CONFIGVALUE 8U
#define I2C1_SAR_CONFIGVALUE 0x000003FFU
#define I2C1_MDR_CONFIGVALUE \
( 0x00000000U | ( uint32 ) ( ( uint32 ) 1U << 11U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( ( uint32 ) I2C_TRANSMITTER ) \
| ( ( uint32 ) I2C_7BIT_AMODE ) | ( uint32 ) ( ( uint32 ) 0 << 7U ) \
| ( ( uint32 ) 0U ) | ( ( uint32 ) I2C_8_BIT ) | ( uint32 ) I2C_RESET_OUT )
#define I2C1_EMDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C1_PSC_CONFIGVALUE 8U
#define I2C1_DMAC_CONFIGVALUE 0x00000000U
#define I2C1_FUN_CONFIGVALUE 0U
#define I2C1_DIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C1_ODR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C1_PD_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C1_PSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 1U ) )
/* Configuration registers initial value for I2C*/
#define I2C2_OAR_CONFIGVALUE 0x00000000U
#define I2C2_IMR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( ( uint32 ) 0U ) )
#define I2C2_CLKL_CONFIGVALUE 37U
#define I2C2_CLKH_CONFIGVALUE 37U
#define I2C2_CNT_CONFIGVALUE 8U
#define I2C2_SAR_CONFIGVALUE 0x000003FFU
#define I2C2_MDR_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) ( ( uint32 ) 1U << 11U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) I2C_TRANSMITTER ) \
| ( uint32 ) ( ( uint32 ) I2C_7BIT_AMODE ) | ( uint32 ) ( ( uint32 ) 0 << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U ) | ( uint32 ) ( ( uint32 ) I2C_2_BIT ) \
| ( uint32 ) I2C_RESET_OUT )
#define I2C2_EMDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C2_PSC_CONFIGVALUE 8U
#define I2C2_DMAC_CONFIGVALUE 0x00000000U
#define I2C2_FUN_CONFIGVALUE 0U
#define I2C2_DIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C2_ODR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C2_PD_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C2_PSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 1U ) )
/**
* @defgroup I2C I2C
* @brief Inter-Integrated Circuit Module.
*
* The I2C is a multi-master communication module providing an interface between the
* Texas Instruments (TI) microcontroller and devices compliant with Philips Semiconductor
* I2C-bus specification version 2.1 and connected by an I2Cbus. This module will support
* any slave or master I2C compatible device.
*
* Related Files
* - reg_i2c.h
* - i2c.h
* - i2c.c
* @addtogroup I2C
* @{
*/
/* I2C Interface Functions */
void i2cInit( void );
void i2cSetOwnAdd( i2cBASE_t * i2c, uint32 oadd );
void i2cSetSlaveAdd( i2cBASE_t * i2c, uint32 sadd );
void i2cSetBaudrate( i2cBASE_t * i2c, uint32 baud );
uint32 i2cIsTxReady( i2cBASE_t * i2c );
void i2cSendByte( i2cBASE_t * i2c, uint8 byte );
void i2cSend( i2cBASE_t * i2c, uint32 length, uint8 * data );
uint32 i2cIsRxReady( i2cBASE_t * i2c );
uint32 i2cIsStopDetected( i2cBASE_t * i2c );
void i2cClearSCD( i2cBASE_t * i2c );
uint32 i2cRxError( i2cBASE_t * i2c );
uint8 i2cReceiveByte( i2cBASE_t * i2c );
void i2cReceive( i2cBASE_t * i2c, uint32 length, uint8 * data );
void i2cEnableNotification( i2cBASE_t * i2c, uint32 flags );
void i2cDisableNotification( i2cBASE_t * i2c, uint32 flags );
void i2cSetStart( i2cBASE_t * i2c );
void i2cSetStop( i2cBASE_t * i2c );
void i2cSetCount( i2cBASE_t * i2c, uint32 cnt );
void i2cEnableLoopback( i2cBASE_t * i2c );
void i2cDisableLoopback( i2cBASE_t * i2c );
void i2cSetMode( i2cBASE_t * i2c, uint32 mode );
void i2cSetDirection( i2cBASE_t * i2c, uint32 dir );
bool i2cIsMasterReady( i2cBASE_t * i2c );
bool i2cIsBusBusy( i2cBASE_t * i2c );
void i2c1GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type );
void i2c2GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type );
/** @fn void i2cNotification(i2cBASE_t *i2c, uint32 flags)
* @brief Interrupt callback
* @param[in] i2c - I2C module base address
* @param[in] flags - copy of error interrupt flags
*
* This is a callback that is provided by the application and is called apon
* an interrupt. The parameter passed to the callback is a copy of the
* interrupt flag register.
*/
void i2cNotification( i2cBASE_t * i2c, uint32 flags );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/lin.h
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/** @file lin.h
* @brief LIN Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __LIN_H__
#define __LIN_H__
#include "reg_lin.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @def LIN_BREAK_INT
* @brief Alias for break detect interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_BREAK_INT 0x00000001U
/** @def LIN_WAKEUP_INT
* @brief Alias for wakeup interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_WAKEUP_INT 0x00000002U
/** @def LIN_TO_INT
* @brief Alias for time out interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_TO_INT 0x00000010U
/** @def LIN_TOAWUS_INT
* @brief Alias for time out after wakeup signal interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_TOAWUS_INT 0x00000040U
/** @def LIN_TOA3WUS_INT
* @brief Alias for time out after 3 wakeup signals interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_TOA3WUS_INT 0x00000080U
/** @def LIN_TX_READY
* @brief Alias for transmit buffer ready flag
*
* Used with linIsTxReady.
*/
#define LIN_TX_READY 0x00000100U
/** @def LIN_RX_INT
* @brief Alias for receive buffer ready interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_RX_INT 0x00000200U
/** @def LIN_ID_INT
* @brief Alias for received matching identifier interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_ID_INT 0x00002000U
/** @def LIN_PE_INT
* @brief Alias for parity error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_PE_INT 0x01000000U
/** @def LIN_OE_INT
* @brief Alias for overrun error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_OE_INT 0x02000000U
/** @def LIN_FE_INT
* @brief Alias for framing error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_FE_INT 0x04000000U
/** @def LIN_NRE_INT
* @brief Alias for no response error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_NRE_INT 0x08000000U
/** @def LIN_ISFE_INT
* @brief Alias for inconsistent sync field error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_ISFE_INT 0x10000000U
/** @def LIN_CE_INT
* @brief Alias for checksum error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_CE_INT 0x20000000U
/** @def LIN_PBE_INT
* @brief Alias for physical bus error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_PBE_INT 0x40000000U
/** @def LIN_BE_INT
* @brief Alias for bit error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_BE_INT 0x80000000U
/** @struct linBase
* @brief LIN Register Definition
*
* This structure is used to access the LIN module registers.
*/
/** @typedef linBASE_t
* @brief LIN Register Frame Type Definition
*
* This type is used to access the LIN Registers.
*/
enum linPinSelect
{
PIN_LIN_TX = 4U,
PIN_LIN_RX = 2U
};
/* Configuration registers */
typedef struct lin_config_reg
{
uint32 CONFIG_GCR0;
uint32 CONFIG_GCR1;
uint32 CONFIG_GCR2;
uint32 CONFIG_SETINT;
uint32 CONFIG_SETINTLVL;
uint32 CONFIG_FORMAT;
uint32 CONFIG_BRSR;
uint32 CONFIG_FUN;
uint32 CONFIG_DIR;
uint32 CONFIG_ODR;
uint32 CONFIG_PD;
uint32 CONFIG_PSL;
uint32 CONFIG_COMP;
uint32 CONFIG_MASK;
uint32 CONFIG_MBRSR;
} lin_config_reg_t;
/* Configuration registers initial value for LIN*/
#define LIN1_GCR0_CONFIGVALUE 0x00000001U
#define LIN1_GCR1_CONFIGVALUE \
( 0x03000CC0U | ( uint32 ) ( ( uint32 ) 1U << 12U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) )
#define LIN1_GCR2_CONFIGVALUE 0x00000000U
#define LIN1_SETINTLVL_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U )
#define LIN1_SETINT_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U )
#define LIN1_FORMAT_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) )
#define LIN1_BRSR_CONFIGVALUE ( 233U )
#define LIN1_COMP_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) | ( 13U - 13U ) )
#define LIN1_MASK_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | 0xFFU )
#define LIN1_MBRSR_CONFIGVALUE ( 3370U )
#define LIN1_FUN_CONFIGVALUE ( 4U | 2U | 0U )
#define LIN1_DIR_CONFIGVALUE ( 0U | 0U | 0U )
#define LIN1_ODR_CONFIGVALUE ( 0U | 0U | 0U )
#define LIN1_PD_CONFIGVALUE ( 0U | 0U | 0U )
#define LIN1_PSL_CONFIGVALUE ( 4U | 2U | 1U )
/* Configuration registers initial value for LIN*/
#define LIN2_GCR0_CONFIGVALUE 0x00000001U
#define LIN2_GCR1_CONFIGVALUE \
( 0x03000CC0U | ( uint32 ) ( ( uint32 ) 1U << 12U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) )
#define LIN2_GCR2_CONFIGVALUE 0x00000000U
#define LIN2_SETINTLVL_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U )
#define LIN2_SETINT_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U )
#define LIN2_FORMAT_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) )
#define LIN2_BRSR_CONFIGVALUE ( 233U )
#define LIN2_COMP_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) | ( 13U - 13U ) )
#define LIN2_MASK_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | 0xFFU )
#define LIN2_MBRSR_CONFIGVALUE ( 3370U )
#define LIN2_FUN_CONFIGVALUE ( 4U | 2U | 0U )
#define LIN2_DIR_CONFIGVALUE ( 0U | 0U | 0U )
#define LIN2_ODR_CONFIGVALUE ( 0U | 0U | 0U )
#define LIN2_PD_CONFIGVALUE ( 0U | 0U | 0U )
#define LIN2_PSL_CONFIGVALUE ( 4U | 2U | 1U )
/**
* @defgroup LIN LIN
* @brief Local Interconnect Network Module.
*
* The LIN standard is based on the SCI (UART) serial data link format. The communication
*concept is single-master/multiple-slave with a message identification for multi-cast
*transmission between any network nodes.
*
* Related Files
* - reg_lin.h
* - lin.h
* - lin.c
* @addtogroup LIN
* @{
*/
/* LIN Interface Functions */
void linInit( void );
void linSetFunctional( linBASE_t * lin, uint32 port );
void linSendHeader( linBASE_t * lin, uint8 identifier );
void linSendWakupSignal( linBASE_t * lin );
void linEnterSleep( linBASE_t * lin );
void linSoftwareReset( linBASE_t * lin );
uint32 linIsTxReady( linBASE_t * lin );
void linSetLength( linBASE_t * lin, uint32 length );
void linSend( linBASE_t * lin, uint8 * data );
uint32 linIsRxReady( linBASE_t * lin );
uint32 linTxRxError( linBASE_t * lin );
uint32 linGetIdentifier( linBASE_t * lin );
void linGetData( linBASE_t * lin, uint8 * const data );
void linEnableNotification( linBASE_t * lin, uint32 flags );
void linDisableNotification( linBASE_t * lin, uint32 flags );
void linEnableLoopback( linBASE_t * lin, loopBackType_t Loopbacktype );
void linDisableLoopback( linBASE_t * lin );
void lin1GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type );
void lin2GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type );
uint32 linGetStatusFlag( linBASE_t * lin );
void linClearStatusFlag( linBASE_t * lin, uint32 flags );
/** @fn void linNotification(linBASE_t *lin, uint32 flags)
* @brief Interrupt callback
* @param[in] lin - lin module base address
* @param[in] flags - copy of error interrupt flags
*
* This is a callback that is provided by the application and is called upon
* an interrupt. The parameter passed to the callback is a copy of the
* interrupt flag register.
*/
void linNotification( linBASE_t * lin, uint32 flags );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mdio.h
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/**
* \file mdio.h
*
* \brief MDIO APIs and macros.
*
* This file contains the driver API prototypes and macro definitions.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __MDIO_H__
#define __MDIO_H__
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include "sys_common.h"
#include "system.h"
#include "hw_mdio.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* MDIO input and output frequencies in Hz */
#define MDIO_FREQ_INPUT ( ( uint32 ) ( VCLK3_FREQ * 1000000.00F ) )
#define MDIO_FREQ_OUTPUT 1000000U
/*****************************************************************************/
/**
* @addtogroup EMACMDIO
* @{
*/
/*
** Prototypes for the APIs
*/
extern uint32 MDIOPhyAliveStatusGet( uint32 baseAddr );
extern uint32 MDIOPhyLinkStatusGet( uint32 baseAddr );
extern void MDIOInit( uint32 baseAddr, uint32 mdioInputFreq, uint32 mdioOutputFreq );
extern boolean MDIOPhyRegRead( uint32 baseAddr,
uint32 phyAddr,
uint32 regNum,
volatile uint16 * dataPtr );
extern void MDIOPhyRegWrite( uint32 baseAddr,
uint32 phyAddr,
uint32 regNum,
uint16 RegVal );
extern void MDIOEnable( uint32 baseAddr );
extern void MDIODisable( uint32 baseAddr );
/* USER CODE BEGIN (2) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* __MDIO_H__ */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mibspi.h
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/nmpu.h
+165
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/** @file nmpu.h
* @brief NMPU Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the NMPU driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NMPU_H_
#define NMPU_H_
#include "reg_nmpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
typedef enum nmpuRegion
{
NMPU_REGION0 = 0U,
NMPU_REGION1 = 1U,
NMPU_REGION2 = 2U,
NMPU_REGION3 = 3U,
NMPU_REGION4 = 4U,
NMPU_REGION5 = 5U,
NMPU_REGION6 = 6U,
NMPU_REGION7 = 7U
} nmpuReg_t;
typedef enum nmpuAccessPermission
{
NMPU_PRIV_NA_USER_NA = 0U,
NMPU_PRIV_RW_USER_NA = 1U,
NMPU_PRIV_RW_USER_RO = 2U,
NMPU_PRIV_RW_USER_RW = 3U,
NMPU_PRIV_RO_USER_NA = 5U,
NMPU_PRIV_RO_USER_RO = 6U
} nmpuAP_t;
typedef enum nmpuRegionSize
{
NMPU_SIZE_32_BYTES = 0x4U,
NMPU_SIZE_64_BYTES = 0x5U,
NMPU_SIZE_128_BYTES = 0x6U,
NMPU_SIZE_256_BYTES = 0x7U,
NMPU_SIZE_512_BYTES = 0x8U,
NMPU_SIZE_1_KB = 0x9U,
NMPU_SIZE_2_KB = 0xAU,
NMPU_SIZE_4_KB = 0xBU,
NMPU_SIZE_8_KB = 0xCU,
NMPU_SIZE_16_KB = 0xDU,
NMPU_SIZE_32_KB = 0xEU,
NMPU_SIZE_64_KB = 0xFU,
NMPU_SIZE_128_KB = 0x10U,
NMPU_SIZE_256_KB = 0x11U,
NMPU_SIZE_512_KB = 0x12U,
NMPU_SIZE_1_MB = 0x13U,
NMPU_SIZE_2_MB = 0x14U,
NMPU_SIZE_4_MB = 0x15U,
NMPU_SIZE_8_MB = 0x16U,
NMPU_SIZE_16_MB = 0x17U,
NMPU_SIZE_32_MB = 0x18U,
NMPU_SIZE_64_MB = 0x19U,
NMPU_SIZE_128_MB = 0x1AU,
NMPU_SIZE_256_MB = 0x1BU,
NMPU_SIZE_512_MB = 0x1CU,
NMPU_SIZE_1_GB = 0x1DU,
NMPU_SIZE_2_GB = 0x1EU,
NMPU_SIZE_4_GB = 0x1FU
} nmpuRegionSize_t;
typedef enum nmpuError
{
NMPU_ERROR_NONE,
NMPU_ERROR_AP_READ,
NMPU_ERROR_AP_WRITE,
NMPU_ERROR_BG_READ,
NMPU_ERROR_BG_WRITE
} nmpuErr_t;
typedef struct nmpuRegionAttributes
{
uint32 baseaddr;
nmpuReg_t regionsize;
nmpuAP_t accesspermission;
} nmpuRegionAttributes_t;
/**
* @defgroup NMPU NMPU
* @brief System Memory Protection Unit
*
* Related files:
* - reg_nmpu.h
* - sys_nmpu.h
* - sys_nmpu.c
*
* @addtogroup NMPU
* @{
*/
void nmpuEnable( nmpuBASE_t * nmpu );
void nmpuDisable( nmpuBASE_t * nmpu );
void nmpuEnableErrorGen( nmpuBASE_t * nmpu );
void nmpuDisableErrorGen( nmpuBASE_t * nmpu );
boolean nmpuEnableRegion( nmpuBASE_t * nmpu,
nmpuReg_t region,
nmpuRegionAttributes_t config );
boolean nmpuDisableRegion( nmpuBASE_t * nmpu, nmpuReg_t region );
nmpuErr_t nmpuGetErrorStatus( nmpuBASE_t * nmpu );
nmpuReg_t nmpuGetErrorRegion( nmpuBASE_t * nmpu );
uint32 nmpuGetErrorAddress( nmpuBASE_t * nmpu );
void nmpuClearErrorStatus( nmpuBASE_t * nmpu );
/**@}*/
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif /* NMPU_H_ */
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_dp83640.h
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/*
* DP83640.h
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _PHY_DP83640_H_
#define _PHY_DP83640_H_
/* USER CODE BEGIN (0) */
/* USER CODE END */
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
/** @enum PHY_timestamp
* @brief Alias names for transmit and receive timestamps
* This enumeration is used to provide alias names for getting the transmit and receive
* timestamps from the Dp83640GetTimeStamp API.
*/
typedef enum phyTimeStamp
{
Txtimestamp = 1, /*Transmit Timestamp*/
Rxtimestamp = 2 /*Receive Timestamp */
} phyTimeStamp_t;
/* PHY register offset definitions */
#define PHY_BCR ( 0u )
#define PHY_BSR ( 1u )
#define PHY_ID1 ( 2u )
#define PHY_ID2 ( 3u )
#define PHY_AUTONEG_ADV ( 4u )
#define PHY_LINK_PARTNER_ABLTY ( 5u )
#define PHY_LINK_PARTNER_SPD ( 16u )
#define PHY_TXTS ( 28u )
#define PHY_RXTS ( 29u )
/* PHY status definitions */
#define PHY_ID_SHIFT ( 16u )
#define PHY_SOFTRESET ( 0x8000U )
#define PHY_AUTONEG_ENABLE ( 0x1000u )
#define PHY_AUTONEG_RESTART ( 0x0200u )
#define PHY_AUTONEG_COMPLETE ( 0x0020u )
#define PHY_AUTONEG_INCOMPLETE ( 0x0000u )
#define PHY_AUTONEG_STATUS ( 0x0020u )
#define PHY_AUTONEG_ABLE ( 0x0008u )
#define PHY_LPBK_ENABLE ( 0x4000u )
#define PHY_LINK_STATUS ( 0x0004u )
#define PHY_INVALID_TYPE ( 0x0u )
/* PHY ID. The LSB nibble will vary between different phy revisions */
#define DP83640_PHY_ID ( 0x0007C0F0u )
#define DP83640_PHY_ID_REV_MASK ( 0x0000000Fu )
/* Pause operations */
#define DP83640_PAUSE_NIL ( 0x0000u )
#define DP83640_PAUSE_SYM ( 0x0400u )
#define DP83640_PAUSE_ASYM ( 0x0800u )
#define DP83640_PAUSE_BOTH_SYM_ASYM ( 0x0C00u )
/* 100 Base TX Full Duplex capablity */
#define DP83640_100BTX_HD ( 0x0000u )
#define DP83640_100BTX_FD ( 0x0100u )
/* 100 Base TX capability */
#define DP83640_NO_100BTX ( 0x0000u )
#define DP83640_100BTX ( 0x0080u )
/* 10 BaseT duplex capabilities */
#define DP83640_10BT_HD ( 0x0000u )
#define DP83640_10BT_FD ( 0x0040u )
/* 10 BaseT ability*/
#define DP83640_NO_10BT ( 0x0000u )
#define DP83640_10BT ( 0x0020u )
/**************************************************************************
API function Prototypes
***************************************************************************/
extern uint32 Dp83640IDGet( uint32 mdioBaseAddr, uint32 phyAddr );
extern void Dp83640Reset( uint32 mdioBaseAddr, uint32 phyAddr );
extern boolean Dp83640AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal );
extern boolean Dp83640PartnerAbilityGet( uint32 mdioBaseAddr,
uint32 phyAddr,
uint16 * ptnerAblty );
extern boolean Dp83640LinkStatusGet( uint32 mdioBaseAddr,
uint32 phyAddr,
volatile uint32 retries );
extern uint64 Dp83640GetTimeStamp( uint32 mdioBaseAddr,
uint32 phyAddr,
phyTimeStamp_t type );
extern void Dp83640EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr );
extern void Dp83640DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr );
extern boolean Dp83640PartnerSpdGet( uint32 mdioBaseAddr,
uint32 phyAddr,
uint16 * ptnerAblty );
/* USER CODE BEGIN (2) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
#endif
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_tlk111.h
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/*
* Tlk111.h
*/
/* Copyright (C) 2010 Texas Instruments Incorporated - www.ti.com
* ALL RIGHTS RESERVED
*/
#ifndef _PHY_TLK111_H_
#define _PHY_TLK111_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @enum PHY_timestamp
* @brief Alias names for transmit and receive timestamps
* This enumeration is used to provide alias names for getting the transmit and receive
* timestamps from the Tlk111GetTimeStamp API.
*/
typedef enum phyTimeStamp
{
Txtimestamp = 1, /*Transmit Timestamp*/
Rxtimestamp = 2 /*Receive Timestamp */
} phyTimeStamp_t;
/* PHY register offset definitions */
#define PHY_BCR ( 0u )
#define PHY_BSR ( 1u )
#define PHY_ID1 ( 2u )
#define PHY_ID2 ( 3u )
#define PHY_AUTONEG_ADV ( 4u )
#define PHY_LINK_PARTNER_ABLTY ( 5u )
#define PHY_LINK_PARTNER_SPD ( 16u )
#define PHY_SWSCR1 ( 9u )
#define PHY_SWSCR2 ( 10u )
#define PHY_SWSCR3 ( 11u )
#define PHY_TXTS ( 28u )
#define PHY_RXTS ( 29u )
/* PHY status definitions */
#define PHY_ID_SHIFT ( 16u )
#define PHY_SOFTRESET ( 0x8000U )
#define PHY_AUTONEG_ENABLE ( 0x1000u )
#define PHY_AUTONEG_RESTART ( 0x0200u )
#define PHY_AUTONEG_COMPLETE ( 0x0020u )
#define PHY_AUTONEG_INCOMPLETE ( 0x0000u )
#define PHY_AUTONEG_STATUS ( 0x0020u )
#define PHY_AUTONEG_ABLE ( 0x0008u )
#define PHY_LPBK_ENABLE ( 0x4000u )
#define PHY_LINK_STATUS ( 0x0004u )
#define PHY_INVALID_TYPE ( 0x0u )
/* PHY ID. The LSB nibble will vary between different phy revisions */
#define Tlk111_PHY_ID ( 0x2000A212 )
#define Tlk111_PHY_ID_REV_MASK ( 0x0000000Fu )
#define Tlk111_PHY_ID_OUI ( 0x2000A000 )
#define Tlk111_PHY_ID_OUI_MASK ( 0xFFFFFC00 )
/* Pause operations */
#define Tlk111_PAUSE_NIL ( 0x0000u )
#define Tlk111_PAUSE_SYM ( 0x0400u )
#define Tlk111_PAUSE_ASYM ( 0x0800u )
#define Tlk111_PAUSE_BOTH_SYM_ASYM ( 0x0C00u )
/* 100 Base TX Full Duplex capablity */
#define Tlk111_100BTX_HD ( 0x0000u )
#define Tlk111_100BTX_FD ( 0x0100u )
/* 100 Base TX capability */
#define Tlk111_NO_100BTX ( 0x0000u )
#define Tlk111_100BTX ( 0x0080u )
/* 10 BaseT duplex capabilities */
#define Tlk111_10BT_HD ( 0x0000u )
#define Tlk111_10BT_FD ( 0x0040u )
/* 10 BaseT ability*/
#define Tlk111_NO_10BT ( 0x0000u )
#define Tlk111_10BT ( 0x0020u )
/* Software Strap Register 1 */
#define Tlk111_SWStrapDone ( 1u << 15 )
#define Tlk111_Auto_MDIX_Ena ( 1u << 14 )
#define Tlk111_Auto_Neg_Ena ( 1u << 13 )
#define Tlk111_Auto_AnMode_10BT_HD ( 0u << 11 )
#define Tlk111_Auto_AnMode_10BT_FD ( 1u << 11 )
#define Tlk111_Auto_AnMode_100BT_HD ( 2u << 11 )
#define Tlk111_Auto_AnMode_100BT_FD ( 3u << 11 )
#define Tlk111_Force_LEDMode1 ( 1u << 10 )
#define Tlk111_RMII_Enhanced ( 1u << 9 )
#define Tlk111_TDR_AutoRun ( 1u << 8 )
#define Tlk111_LinkLoss_Recovery ( 1u << 8 )
#define Tlk111_FastAutoMdix ( 1u << 6 )
#define Tlk111_RobustAutoMdix ( 1u << 5 )
#define Tlk111_FastAnEn ( 1u << 4 )
#define Tlk111_FastAnSel0 ( 0u << 2 )
#define Tlk111_FastAnSel1 ( 1u << 2 )
#define Tlk111_FastAnSel2 ( 2u << 2 )
#define Tlk111_FastRxDvDetect ( 1u << 1 )
#define Tlk111_IntPdn_InterruptOut ( 1u << 0 )
/* Software Strap Register 2 */
#define Tlk111_100BT_Force_FE_LinkDrop ( 1u << 15 )
#define Tlk111_Rsv1 ( 2u << 7 )
#define Tlk111_FastLinkUpParallel ( 1u << 6 )
#define Tlk111_ExtendedFDAbility ( 1u << 5 )
#define Tlk111_ExtendedLEDLink ( 1u << 4 )
#define Tlk111_IsolateMII_100BT_HD ( 1u << 3 )
#define Tlk111_RXERR_DuringIdle ( 1u << 2 )
#define Tlk111_OddNibbleDetectDisable ( 1u << 1 )
#define Tlk111_RMII_Use_RXCLK ( 1u << 0 )
#define Tlk111_RMII_Use_XI ( 0u << 0 )
/* Software Strap Register 2 */
#define Tlk111_FastLinkDown ( 1u << 10 )
#define Tlk111_PolaritySwap ( 1u << 6 )
#define Tlk111_MDIXSwap ( 1u << 5 )
#define Tlk111_Bypass4B5B ( 1u << 4 )
#define Tlk111_FastLinkDownRxErrCnt ( 1u << 3 )
#define Tlk111_FastLinkDownMLT3ErrCnt ( 1u << 2 )
#define Tlk111_FastLinkDownLowSnr ( 1u << 1 )
#define Tlk111_FastLinkDownSigLoss ( 1u << 0 )
/* The Values for SWSCR Registers */
#define Tlk111_SWSCR1_Val \
( Tlk111_Auto_MDIX_Ena | Tlk111_Auto_Neg_Ena | Tlk111_Auto_AnMode_100BT_FD \
| Tlk111_Force_LEDMode1 | Tlk111_IntPdn_InterruptOut )
#define Tlk111_SWSCR2_Val ( Tlk111_Rsv1 | Tlk111_RXERR_DuringIdle )
#define Tlk111_SWSCR3_Val ( 0u )
/**************************************************************************
API function Prototypes
***************************************************************************/
extern uint32 Tlk111IDGet( uint32 mdioBaseAddr, uint32 phyAddr );
extern void Tlk111SwStrap( uint32 mdioBaseAddr, uint32 phyAddr );
extern void Tlk111Reset( uint32 mdioBaseAddr, uint32 phyAddr );
extern boolean Tlk111AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal );
extern boolean Tlk111PartnerAbilityGet( uint32 mdioBaseAddr,
uint32 phyAddr,
uint16 * ptnerAblty );
extern boolean Tlk111LinkStatusGet( uint32 mdioBaseAddr,
uint32 phyAddr,
volatile uint32 retries );
extern uint64 Tlk111GetTimeStamp( uint32 mdioBaseAddr,
uint32 phyAddr,
phyTimeStamp_t type );
extern void Tlk111EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr );
extern void Tlk111DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr );
extern boolean Tlk111PartnerSpdGet( uint32 mdioBaseAddr,
uint32 phyAddr,
uint16 * ptnerAblty );
#ifdef __cplusplus
}
#endif
#endif
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pinmux.h
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pom.h
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/** @file pom.h
* @brief POM Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __POM_H__
#define __POM_H__
#include "reg_pom.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @enum pom_region_size
* @brief Alias names for pom region size
* This enumeration is used to provide alias names for POM region size:
*/
enum pom_region_size
{
SIZE_32BYTES = 0U,
SIZE_64BYTES = 1U,
SIZE_128BYTES = 2U,
SIZE_256BYTES = 3U,
SIZE_512BYTES = 4U,
SIZE_1KB = 5U,
SIZE_2KB = 6U,
SIZE_4KB = 7U,
SIZE_8KB = 8U,
SIZE_16KB = 9U,
SIZE_32KB = 10U,
SIZE_64KB = 11U,
SIZE_128KB = 12U,
SIZE_256KB = 13U
};
/** @def INTERNAL_RAM
* @brief Alias name for Internal RAM
*/
#define INTERNAL_RAM 0x08000000U
/** @def SDRAM
* @brief Alias name for SD RAM
*/
#define SDRAM 0x80000000U
/** @def ASYNC_MEMORY
* @brief Alias name for Async RAM
*/
#define ASYNC_MEMORY 0x60000000U
typedef uint32 REGION_t;
/** @struct REGION_CONFIG_ST
* @brief POM region configuration
*/
typedef struct
{
uint32 Prog_Reg_Sta_Addr;
uint32 Ovly_Reg_Sta_Addr;
uint32 Reg_Size;
} REGION_CONFIG_t;
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* Configuration registers */
typedef struct pom_config_reg
{
uint32 CONFIG_POMGLBCTRL;
uint32 CONFIG_POMPROGSTART0;
uint32 CONFIG_POMOVLSTART0;
uint32 CONFIG_POMREGSIZE0;
uint32 CONFIG_POMPROGSTART1;
uint32 CONFIG_POMOVLSTART1;
uint32 CONFIG_POMREGSIZE1;
uint32 CONFIG_POMPROGSTART2;
uint32 CONFIG_POMOVLSTART2;
uint32 CONFIG_POMREGSIZE2;
uint32 CONFIG_POMPROGSTART3;
uint32 CONFIG_POMOVLSTART3;
uint32 CONFIG_POMREGSIZE3;
uint32 CONFIG_POMPROGSTART4;
uint32 CONFIG_POMOVLSTART4;
uint32 CONFIG_POMREGSIZE4;
uint32 CONFIG_POMPROGSTART5;
uint32 CONFIG_POMOVLSTART5;
uint32 CONFIG_POMREGSIZE5;
uint32 CONFIG_POMPROGSTART6;
uint32 CONFIG_POMOVLSTART6;
uint32 CONFIG_POMREGSIZE6;
uint32 CONFIG_POMPROGSTART7;
uint32 CONFIG_POMOVLSTART7;
uint32 CONFIG_POMREGSIZE7;
uint32 CONFIG_POMPROGSTART8;
uint32 CONFIG_POMOVLSTART8;
uint32 CONFIG_POMREGSIZE8;
uint32 CONFIG_POMPROGSTART9;
uint32 CONFIG_POMOVLSTART9;
uint32 CONFIG_POMREGSIZE9;
uint32 CONFIG_POMPROGSTART10;
uint32 CONFIG_POMOVLSTART10;
uint32 CONFIG_POMREGSIZE10;
uint32 CONFIG_POMPROGSTART11;
uint32 CONFIG_POMOVLSTART11;
uint32 CONFIG_POMREGSIZE11;
uint32 CONFIG_POMPROGSTART12;
uint32 CONFIG_POMOVLSTART12;
uint32 CONFIG_POMREGSIZE12;
uint32 CONFIG_POMPROGSTART13;
uint32 CONFIG_POMOVLSTART13;
uint32 CONFIG_POMREGSIZE13;
uint32 CONFIG_POMPROGSTART14;
uint32 CONFIG_POMOVLSTART14;
uint32 CONFIG_POMREGSIZE14;
uint32 CONFIG_POMPROGSTART15;
uint32 CONFIG_POMOVLSTART15;
uint32 CONFIG_POMREGSIZE15;
uint32 CONFIG_POMPROGSTART16;
uint32 CONFIG_POMOVLSTART16;
uint32 CONFIG_POMREGSIZE16;
uint32 CONFIG_POMPROGSTART17;
uint32 CONFIG_POMOVLSTART17;
uint32 CONFIG_POMREGSIZE17;
uint32 CONFIG_POMPROGSTART18;
uint32 CONFIG_POMOVLSTART18;
uint32 CONFIG_POMREGSIZE18;
uint32 CONFIG_POMPROGSTART19;
uint32 CONFIG_POMOVLSTART19;
uint32 CONFIG_POMREGSIZE19;
uint32 CONFIG_POMPROGSTART20;
uint32 CONFIG_POMOVLSTART20;
uint32 CONFIG_POMREGSIZE20;
uint32 CONFIG_POMPROGSTART21;
uint32 CONFIG_POMOVLSTART21;
uint32 CONFIG_POMREGSIZE21;
uint32 CONFIG_POMPROGSTART22;
uint32 CONFIG_POMOVLSTART22;
uint32 CONFIG_POMREGSIZE22;
uint32 CONFIG_POMPROGSTART23;
uint32 CONFIG_POMOVLSTART23;
uint32 CONFIG_POMREGSIZE23;
uint32 CONFIG_POMPROGSTART24;
uint32 CONFIG_POMOVLSTART24;
uint32 CONFIG_POMREGSIZE24;
uint32 CONFIG_POMPROGSTART25;
uint32 CONFIG_POMOVLSTART25;
uint32 CONFIG_POMREGSIZE25;
uint32 CONFIG_POMPROGSTART26;
uint32 CONFIG_POMOVLSTART26;
uint32 CONFIG_POMREGSIZE26;
uint32 CONFIG_POMPROGSTART27;
uint32 CONFIG_POMOVLSTART27;
uint32 CONFIG_POMREGSIZE27;
uint32 CONFIG_POMPROGSTART28;
uint32 CONFIG_POMOVLSTART28;
uint32 CONFIG_POMREGSIZE28;
uint32 CONFIG_POMPROGSTART29;
uint32 CONFIG_POMOVLSTART29;
uint32 CONFIG_POMREGSIZE29;
uint32 CONFIG_POMPROGSTART30;
uint32 CONFIG_POMOVLSTART30;
uint32 CONFIG_POMREGSIZE30;
uint32 CONFIG_POMPROGSTART31;
uint32 CONFIG_POMOVLSTART31;
uint32 CONFIG_POMREGSIZE31;
} pom_config_reg_t;
/* Configuration registers initial value for POM*/
#define POM_POMGLBCTRL_CONFIGVALUE ( ( uint32 ) INTERNAL_RAM | 0x00000005U )
#define POM_POMPROGSTART0_CONFIGVALUE ( 0x00000000U & 0x003FFFFFU )
#define POM_POMOVLSTART0_CONFIGVALUE ( 0x00000000U & 0x003FFFFFU )
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Values come from GUI drop down option" */
#define POM_POMREGSIZE0_CONFIGVALUE ( ( uint32 ) SIZE_64BYTES )
#define POM_POMPROGSTART1_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART1_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE1_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART2_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART2_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE2_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART3_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART3_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE3_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART4_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART4_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE4_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART5_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART5_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE5_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART6_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART6_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE6_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART7_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART7_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE7_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART8_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART8_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE8_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART9_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART9_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE9_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART10_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART10_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE10_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART11_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART11_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE11_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART12_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART12_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE12_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART13_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART13_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE13_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART14_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART14_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE14_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART15_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART15_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE15_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART16_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART16_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE16_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART17_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART17_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE17_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART18_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART18_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE18_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART19_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART19_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE19_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART20_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART20_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE20_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART21_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART21_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE21_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART22_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART22_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE22_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART23_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART23_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE23_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART24_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART24_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE24_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART25_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART25_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE25_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART26_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART26_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE26_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART27_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART27_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE27_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART28_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART28_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE28_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART29_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART29_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE29_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART30_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART30_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE30_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART31_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART31_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE31_CONFIGVALUE 0x00000000U
/**
* @defgroup POM POM
* @brief Parameter Overlay Module.
*
* The POM provides a mechanism to redirect accesses to non-volatile memory into a
* volatile memory internal or external to the device. The data requested by the CPU will
* be fetched from the overlay memory instead of the main non-volatile memory.
*
* Related Files
* - reg_pom.h
* - pom.h
* - pom.c
* @addtogroup POM
* @{
*/
/* POM Interface Functions */
void POM_Region_Config( REGION_CONFIG_t * Reg_Config_Ptr, REGION_t Region_Num );
void POM_Reset( void );
void POM_Init( void );
void POM_Enable( void );
void pomGetConfigValue( pom_config_reg_t * config_reg, config_value_type_t type );
/* USER CODE BEGIN (2) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif /* __POM_H_*/
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_adc.h
+252
View File
@@ -0,0 +1,252 @@
/** @file reg_adc.h
* @brief ADC Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the ADC driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_ADC_H__
#define __REG_ADC_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Adc Register Frame Definition */
/** @struct adcBase
* @brief ADC Register Frame Definition
*
* This type is used to access the ADC Registers.
*/
/** @typedef adcBASE_t
* @brief ADC Register Frame Type Definition
*
* This type is used to access the ADC Registers.
*/
typedef volatile struct adcBase
{
uint32 RSTCR; /**< 0x0000: Reset control register */
uint32 OPMODECR; /**< 0x0004: Operating mode control register */
uint32 CLOCKCR; /**< 0x0008: Clock control register */
uint32 CALCR; /**< 0x000C: Calibration control register */
uint32 GxMODECR[ 3U ]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */
uint32 EVSRC; /**< 0x001C: Group 0 trigger source control register */
uint32 G1SRC; /**< 0x0020: Group 1 trigger source control register */
uint32 G2SRC; /**< 0x0024: Group 2 trigger source control register */
uint32 GxINTENA[ 3U ]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register
*/
uint32 GxINTFLG[ 3U ]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */
uint32 GxINTCR[ 3U ]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */
uint32 EVDMACR; /**< 0x004C: Group 0 DMA control register */
uint32 G1DMACR; /**< 0x0050: Group 1 DMA control register */
uint32 G2DMACR; /**< 0x0054: Group 2 DMA control register */
uint32 BNDCR; /**< 0x0058: Buffer boundary control register */
uint32 BNDEND; /**< 0x005C: Buffer boundary end register */
uint32 EVSAMP; /**< 0x0060: Group 0 sample window register */
uint32 G1SAMP; /**< 0x0064: Group 1 sample window register */
uint32 G2SAMP; /**< 0x0068: Group 2 sample window register */
uint32 EVSR; /**< 0x006C: Group 0 status register */
uint32 G1SR; /**< 0x0070: Group 1 status register */
uint32 G2SR; /**< 0x0074: Group 2 status register */
uint32 GxSEL[ 3U ]; /**< 0x0078-0x007C: Group 0-2 channel select register */
uint32 CALR; /**< 0x0084: Calibration register */
uint32 SMSTATE; /**< 0x0088: State machine state register */
uint32 LASTCONV; /**< 0x008C: Last conversion register */
struct
{
uint32 BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */
uint32 BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */
uint32 BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */
uint32 BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */
uint32 BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */
uint32 BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */
uint32 BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */
uint32 BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */
} GxBUF[ 3U ];
uint32 EVEMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */
uint32 G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */
uint32 G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */
uint32 EVTDIR; /**< 0x00FC: Event pin direction register */
uint32 EVTOUT; /**< 0x0100: Event pin digital output register */
uint32 EVTIN; /**< 0x0104: Event pin digital input register */
uint32 EVTSET; /**< 0x0108: Event pin set register */
uint32 EVTCLR; /**< 0x010C: Event pin clear register */
uint32 EVTPDR; /**< 0x0110: Event pin open drain register */
uint32 EVTDIS; /**< 0x0114: Event pin pull disable register */
uint32 EVTPSEL; /**< 0x0118: Event pin pull select register */
uint32 EVSAMPDISEN; /**< 0x011C: Group 0 sample discharge register */
uint32 G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */
uint32 G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */
uint32 MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */
uint32 MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */
uint32 MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */
uint32 MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */
uint32 MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */
uint32 MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */
uint32 rsvd1; /**< 0x0140: Reserved */
uint32 rsvd2; /**< 0x0144: Reserved */
uint32 rsvd3; /**< 0x0148: Reserved */
uint32 rsvd4; /**< 0x014C: Reserved */
uint32 rsvd5; /**< 0x0150: Reserved */
uint32 rsvd6; /**< 0x0154: Reserved */
uint32 MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */
uint32 MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */
uint32 MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */
uint32 MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */
uint32 GxFIFORESETCR[ 3U ]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register
*/
uint32 EVRAMADDR; /**< 0x0174: Group 0 RAM pointer register */
uint32 G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */
uint32 G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */
uint32 PARCR; /**< 0x0180: Parity control register */
uint32 PARADDR; /**< 0x0184: Parity error address register */
uint32 PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */
uint32 rsvd7; /**< 0x018C: Reserved */
uint32 ADEVCHNSELMODECTRL; /**< 0x0190: Event Group Channel Selection Mode Control
Register */
uint32 ADG1CHNSELMODECTRL; /**< 0x0194: Group1 Channel Selection Mode Control Register
*/
uint32 ADG2CHNSELMODECTRL; /**< 0x0198: Group2 Channel Selection Mode Control Register
*/
uint32 ADEVCURRCOUNT; /**< 0x019C: Event Group Current Count Register */
uint32 ADEVMAXCOUNT; /**< 0x01A0: Event Group Max Count Register */
uint32 ADG1CURRCOUNT; /**< 0x01A4: Group1 Current Count Register */
uint32 ADG1MAXCOUNT; /**< 0x01A8: Group1 Max Count Register */
uint32 ADG2CURRCOUNT; /**< 0x01AC: Group2 Current Count Register */
uint32 ADG2MAXCOUNT; /**< 0x01B0: Group2 Max Count Register */
} adcBASE_t;
/** @struct adcLUTEntry
* @brief ADC Look-Up Table Entry
*
* This type is used to access ADC Look-Up Table Entry
*/
/** @typedef adcLUTEntry_t
* @brief ADC Look-Up Table Entry
*
* This type is used to access the Look-Up Table Entry.
*/
typedef struct adcLUTEntry
{
#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) )
uint8 EV_INT_CHN_MUX_SEL;
uint8 EV_EXT_CHN_MUX_SEL;
uint16 rsvd;
#else
uint16 rsvd;
uint8 EV_EXT_CHN_MUX_SEL;
uint8 EV_INT_CHN_MUX_SEL;
#endif
} adcLUTEntry_t;
/** @struct adcLUT
* @brief ADC Look-Up Table
*
* This type is used to access ADC Look-Up Table
*/
/** @typedef adcLUT_t
* @brief ADC Look-Up Table
*
* This type is used to access the ADC Look-Up Table.
*/
typedef volatile struct adcLUT
{
adcLUTEntry_t eventGroup[ 32 ];
adcLUTEntry_t Group1[ 32 ];
adcLUTEntry_t Group2[ 32 ];
} adcLUT_t;
/** @def adcREG1
* @brief ADC1 Register Frame Pointer
*
* This pointer is used by the ADC driver to access the ADC1 registers.
*/
#define adcREG1 ( ( adcBASE_t * ) 0xFFF7C000U )
/** @def adcREG2
* @brief ADC2 Register Frame Pointer
*
* This pointer is used by the ADC driver to access the ADC2 registers.
*/
#define adcREG2 ( ( adcBASE_t * ) 0xFFF7C200U )
/** @def adcRAM1
* @brief ADC1 RAM Pointer
*
* This pointer is used by the ADC driver to access the ADC1 RAM.
*/
#define adcRAM1 ( *( volatile uint32 * ) 0xFF3E0000U )
/** @def adcRAM2
* @brief ADC2 RAM Pointer
*
* This pointer is used by the ADC driver to access the ADC2 RAM.
*/
#define adcRAM2 ( *( volatile uint32 * ) 0xFF3A0000U )
/** @def adcPARRAM1
* @brief ADC1 Parity RAM Pointer
*
* This pointer is used by the ADC driver to access the ADC1 Parity RAM.
*/
#define adcPARRAM1 ( *( volatile uint32 * ) ( 0xFF3E0000U + 0x1000U ) )
/** @def adcPARRAM2
* @brief ADC2 Parity RAM Pointer
*
* This pointer is used by the ADC driver to access the ADC2 Parity RAM.
*/
#define adcPARRAM2 ( *( volatile uint32 * ) ( 0xFF3A0000U + 0x1000U ) )
/** @def adcLUT1
* @brief ADC1 Look-Up Table
*
* This pointer is used by the ADC driver to access the ADC1 Look-Up Table.
*/
#define adcLUT1 ( ( adcLUT_t * ) ( 0xFF3E0000U + 0x2000U ) )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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