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Start of a new ColdFire/CodeWarrior demo.

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This commit is contained in:
Richard Barry
2008-10-17 14:07:17 +00:00
parent 8e219f83f0
commit 709b7ee223
57 changed files with 8456 additions and 0 deletions
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Demo/ColdFire_MCF52221_CodeWarrior/RTOSDemo.mcp
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Demo/ColdFire_MCF52221_CodeWarrior/RTOSDemo_Data/CWSettingsWindows.stg
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Demo/ColdFire_MCF52221_CodeWarrior/RTOSDemo_Data/INTERNAL_FLASH/TargetDataWindows.tdt
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Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf
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Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf.S19
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Demo/ColdFire_MCF52221_CodeWarrior/bin/MCF52221_INTERNAL_FLASH.elf.xMAP
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Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_CONSOLE_INTERNAL_RAM.cfg
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ResetHalt
; Set VBR to the beginning of what will be SRAM
; VBR is an absolute CPU register
writecontrolreg 0x0801 0x20000000
; Set RAMBAR1 (SRAM)
writecontrolreg 0x0C05 0x20000021
; Set FLASHBAR (Flash)
writecontrolreg 0x0C04 0x00000061
; Enable PST[3:0] signals
writemem.b 0x40100074 0x0F
Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_CONSOLE_INTERNAL_RAM.mem
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// Memory Configuration File
//
// Description:
// A memory configuration file contains commands that define the legally accessible
// areas of memory for your specific board. Useful for example when the debugger
// tries to display the content of a "char *" variable, that has not yet been initialized.
// In this case the debugger may try to read from a bogus address, which could cause a
// bus error.
//
// Board:
// Freescale M52221DEMO
//
// Reference:
// Kirin2u_SoC_Guide.pdf - KIRIN2U_SG V0.7
// All reserved ranges read back 0xBABA...
reservedchar 0xBA
address IPSBAR_BASE 0x40000000
usederivative "MCF52221"
// Memory Map:
// ----------------------------------------------------------------------
range 0x00000000 0x0001FFFF 4 Read // 128 KByte Internal Flash Memory
reserved 0x00020000 0x1FFFFFFF
range 0x20000000 0x20003FFF 4 ReadWrite // 16 Kbytes Internal SRAM
reserved 0x20004000 0x40000007
// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers
reserved $IPSBAR_BASE + 0x001D004C 0xFFFFFFFF
Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_FLASH.cfg
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ResetHalt
; Set VBR to the beginning of what will be SRAM
; VBR is an absolute CPU register
writecontrolreg 0x0801 0x20000000
; Set RAMBAR1 (SRAM)
writecontrolreg 0x0C05 0x20000021
; Set FLASHBAR (Flash)
writecontrolreg 0x0C04 0x00000061
; Enable PST[3:0] signals
writemem.b 0x40100074 0x0F
Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_FLASH.mem
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// Memory Configuration File
//
// Description:
// A memory configuration file contains commands that define the legally accessible
// areas of memory for your specific board. Useful for example when the debugger
// tries to display the content of a "char *" variable, that has not yet been initialized.
// In this case the debugger may try to read from a bogus address, which could cause a
// bus error.
//
// Board:
// Freescale M52221DEMO
//
// Reference:
// Kirin2u_SoC_Guide.pdf - KIRIN2U_SG V0.7
// All reserved ranges read back 0xBABA...
reservedchar 0xBA
address IPSBAR_BASE 0x40000000
usederivative "MCF52221"
// Memory Map:
// ----------------------------------------------------------------------
range 0x00000000 0x0001FFFF 4 Read // 128 KByte Internal Flash Memory
reserved 0x00020000 0x1FFFFFFF
range 0x20000000 0x20003FFF 4 ReadWrite // 16 Kbytes Internal SRAM
reserved 0x20004000 0x40000007
// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers
reserved $IPSBAR_BASE + 0x001D004C 0xFFFFFFFF
Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_RAM.cfg
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ResetHalt
; Set VBR to the beginning of what will be SRAM
; VBR is an absolute CPU register
writecontrolreg 0x0801 0x20000000
; Set RAMBAR1 (SRAM)
writecontrolreg 0x0C05 0x20000021
; Set FLASHBAR (Flash)
writecontrolreg 0x0C04 0x00000061
; Enable PST[3:0] signals
writemem.b 0x40100074 0x0F
Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTERNAL_RAM.mem
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// Memory Configuration File
//
// Description:
// A memory configuration file contains commands that define the legally accessible
// areas of memory for your specific board. Useful for example when the debugger
// tries to display the content of a "char *" variable, that has not yet been initialized.
// In this case the debugger may try to read from a bogus address, which could cause a
// bus error.
//
// Board:
// Freescale M52221DEMO
//
// Reference:
// Kirin2u_SoC_Guide.pdf - KIRIN2U_SG V0.7
// All reserved ranges read back 0xBABA...
reservedchar 0xBA
address IPSBAR_BASE 0x40000000
usederivative "MCF52221"
// Memory Map:
// ----------------------------------------------------------------------
range 0x00000000 0x0001FFFF 4 Read // 128 KByte Internal Flash Memory
reserved 0x00020000 0x1FFFFFFF
range 0x20000000 0x20003FFF 4 ReadWrite // 16 Kbytes Internal SRAM
reserved 0x20004000 0x40000007
// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers
reserved $IPSBAR_BASE + 0x001D004C 0xFFFFFFFF
Demo/ColdFire_MCF52221_CodeWarrior/cfg/MCF52221_INTFLASH.xml
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<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>
<fpconfig xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="fp_config.xsd">
<targetconfwindow>
<usecustomsettings>false</usecustomsettings>
<targetprocessor>52221</targetprocessor>
<connection></connection>
<usetargetinit>true</usetargetinit>
<targetinitfile>{CodeWarrior}\ColdFire_Support\Initialization_Files\M52221DEMO.cfg</targetinitfile>
<targetmembuffaddr>0x20000000</targetmembuffaddr>
<targetmembuffsize>0x00004000</targetmembuffsize>
<enablelogging>true</enablelogging>
<verifywrites>false</verifywrites>
</targetconfwindow>
<flashconfwindow>
<membaseaddr>0x00000000</membaseaddr>
<device>CFM_MCF52221</device>
<organization>4Kx32x1</organization>
<flashstart>0x00000000</flashstart>
<flashend>0x0001FFFF</flashend>
</flashconfwindow>
<programverifywindow>
<useselectedfile>false</useselectedfile>
<projbuildtargetfile>nofile</projbuildtargetfile>
<fileiotype>Auto Detect</fileiotype>
<restrictaddrrange>false</restrictaddrrange>
<restrictaddrrangestart>0x00000000</restrictaddrrangestart>
<restrictaddrrangeend>0x0001FFFF</restrictaddrrangeend>
<applyaddroffset>false</applyaddroffset>
<addroffset>0x00000000</addroffset>
</programverifywindow>
<eraseblankcheckwindow>
<eraseallsectors>true</eraseallsectors>
<sector/>
<processsectorsindividually>false</processsectorsindividually>
</eraseblankcheckwindow>
<checksumwindow>
<computechecksumover>FileOnTarg</computechecksumover>
<addrstart>0x00000000</addrstart>
<addrsize>0x0000FFFF</addrsize>
</checksumwindow>
</fpconfig>
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_H__
#define __MCF52221_H__
/********************************************************************/
/*
* The basic data types
*/
typedef unsigned char uint8; /* 8 bits */
typedef unsigned short int uint16; /* 16 bits */
typedef unsigned long int uint32; /* 32 bits */
typedef signed char int8; /* 8 bits */
typedef signed short int int16; /* 16 bits */
typedef signed long int int32; /* 32 bits */
typedef volatile uint8 vuint8; /* 8 bits */
typedef volatile uint16 vuint16; /* 16 bits */
typedef volatile uint32 vuint32; /* 32 bits */
#ifdef __cplusplus
extern "C" {
#endif
#pragma define_section system ".system" far_absolute RW
/***
* MCF52221 Derivative Memory map definitions from linker command files:
* __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
* symbols must be defined in the linker command file.
*/
extern __declspec(system) uint8 __IPSBAR[];
extern __declspec(system) uint8 __RAMBAR[];
extern __declspec(system) uint8 __RAMBAR_SIZE[];
extern __declspec(system) uint8 __FLASHBAR[];
extern __declspec(system) uint8 __FLASHBAR_SIZE[];
#define IPSBAR_ADDRESS (uint32)__IPSBAR
#define RAMBAR_ADDRESS (uint32)__RAMBAR
#define RAMBAR_SIZE (uint32)__RAMBAR_SIZE
#define FLASHBAR_ADDRESS (uint32)__FLASHBAR
#define FLASHBAR_SIZE (uint32)__FLASHBAR_SIZE
#include "MCF52221_SCM.h"
#include "MCF52221_DMA.h"
#include "MCF52221_UART.h"
#include "MCF52221_I2C.h"
#include "MCF52221_QSPI.h"
#include "MCF52221_RTC.h"
#include "MCF52221_DTIM.h"
#include "MCF52221_INTC.h"
#include "MCF52221_GPIO.h"
#include "MCF52221_PAD.h"
#include "MCF52221_RCM.h"
#include "MCF52221_CCM.h"
#include "MCF52221_PMM.h"
#include "MCF52221_CLOCK.h"
#include "MCF52221_EPORT.h"
#include "MCF52221_PIT.h"
#include "MCF52221_ADC.h"
#include "MCF52221_GPTA.h"
#include "MCF52221_PWM.h"
#include "MCF52221_USB_OTG.h"
#include "MCF52221_CFM.h"
#ifdef __cplusplus
}
#endif
#endif /* __MCF52221_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_ADC.h
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Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CCM.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_CCM_H__
#define __MCF52221_CCM_H__
/*********************************************************************
*
* Chip Configuration Module (CCM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CCM_CCR (*(vuint16*)(0x40110004))
#define MCF_CCM_RCON (*(vuint16*)(0x40110008))
#define MCF_CCM_CIR (*(vuint16*)(0x4011000A))
/* Bit definitions and macros for MCF_CCM_CCR */
#define MCF_CCM_CCR_Mode(x) (((x)&0x7)<<0x8)
#define MCF_CCM_CCR_MODE_SINGLECHIP (0x600)
#define MCF_CCM_CCR_MODE_EZPORT (0x500)
/* Bit definitions and macros for MCF_CCM_RCON */
#define MCF_CCM_RCON_MODE (0x1)
#define MCF_CCM_RCON_RLOAD (0x20)
/* Bit definitions and macros for MCF_CCM_CIR */
#define MCF_CCM_CIR_PRN(x) (((x)&0x3F)<<0)
#define MCF_CCM_CIR_PIN(x) (((x)&0x3FF)<<0x6)
#endif /* __MCF52221_CCM_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CFM.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_CFM_H__
#define __MCF52221_CFM_H__
/*********************************************************************
*
* ColdFire Flash Module (CFM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CFM_CFMMCR (*(vuint16*)(0x401D0000))
#define MCF_CFM_CFMCLKD (*(vuint8 *)(0x401D0002))
#define MCF_CFM_CFMSEC (*(vuint32*)(0x401D0008))
#define MCF_CFM_CFMPROT (*(vuint32*)(0x401D0010))
#define MCF_CFM_CFMSACC (*(vuint32*)(0x401D0014))
#define MCF_CFM_CFMDACC (*(vuint32*)(0x401D0018))
#define MCF_CFM_CFMUSTAT (*(vuint8 *)(0x401D0020))
#define MCF_CFM_CFMCMD (*(vuint8 *)(0x401D0024))
#define MCF_CFM_CFMCLKSEL (*(vuint16*)(0x401D004A))
/* Bit definitions and macros for MCF_CFM_CFMMCR */
#define MCF_CFM_CFMMCR_KEYACC (0x20)
#define MCF_CFM_CFMMCR_CCIE (0x40)
#define MCF_CFM_CFMMCR_CBEIE (0x80)
#define MCF_CFM_CFMMCR_AEIE (0x100)
#define MCF_CFM_CFMMCR_PVIE (0x200)
#define MCF_CFM_CFMMCR_LOCK (0x400)
/* Bit definitions and macros for MCF_CFM_CFMCLKD */
#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0)
#define MCF_CFM_CFMCLKD_PRDIV8 (0x40)
#define MCF_CFM_CFMCLKD_DIVLD (0x80)
/* Bit definitions and macros for MCF_CFM_CFMSEC */
#define MCF_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)<<0)
#define MCF_CFM_CFMSEC_SECSTAT (0x40000000)
#define MCF_CFM_CFMSEC_KEYEN (0x80000000)
/* Bit definitions and macros for MCF_CFM_CFMPROT */
#define MCF_CFM_CFMPROT_PROTECT(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_CFM_CFMSACC */
#define MCF_CFM_CFMSACC_SUPV(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_CFM_CFMDACC */
#define MCF_CFM_CFMDACC_DACC(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_CFM_CFMUSTAT */
#define MCF_CFM_CFMUSTAT_BLANK (0x4)
#define MCF_CFM_CFMUSTAT_ACCERR (0x10)
#define MCF_CFM_CFMUSTAT_PVIOL (0x20)
#define MCF_CFM_CFMUSTAT_CCIF (0x40)
#define MCF_CFM_CFMUSTAT_CBEIF (0x80)
/* Bit definitions and macros for MCF_CFM_CFMCMD */
#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0)
#define MCF_CFM_CFMCMD_BLANK_CHECK (0x5)
#define MCF_CFM_CFMCMD_PAGE_ERASE_VERIFY (0x6)
#define MCF_CFM_CFMCMD_WORD_PROGRAM (0x20)
#define MCF_CFM_CFMCMD_PAGE_ERASE (0x40)
#define MCF_CFM_CFMCMD_MASS_ERASE (0x41)
/* Bit definitions and macros for MCF_CFM_CFMCLKSEL */
#define MCF_CFM_CFMCLKSEL_CLKSEL(x) (((x)&0x3)<<0)
#endif /* __MCF52221_CFM_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CLOCK.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_CLOCK_H__
#define __MCF52221_CLOCK_H__
/*********************************************************************
*
* Clock Module (CLOCK)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CLOCK_SYNCR (*(vuint16*)(0x40120000))
#define MCF_CLOCK_SYNSR (*(vuint8 *)(0x40120002))
#define MCF_CLOCK_ROCR (*(vuint16*)(0x40120004))
#define MCF_CLOCK_LPDR (*(vuint8 *)(0x40120007))
#define MCF_CLOCK_CCHR (*(vuint8 *)(0x40120008))
#define MCF_CLOCK_CCLR (*(vuint8 *)(0x40120009))
#define MCF_CLOCK_OCHR (*(vuint8 *)(0x4012000A))
#define MCF_CLOCK_OCLR (*(vuint8 *)(0x4012000B))
#define MCF_CLOCK_RTCDR (*(vuint32*)(0x4012000C))
/* Bit definitions and macros for MCF_CLOCK_SYNCR */
#define MCF_CLOCK_SYNCR_PLLEN (0x1)
#define MCF_CLOCK_SYNCR_PLLMODE (0x2)
#define MCF_CLOCK_SYNCR_CLKSRC (0x4)
#define MCF_CLOCK_SYNCR_FWKUP (0x20)
#define MCF_CLOCK_SYNCR_DISCLK (0x40)
#define MCF_CLOCK_SYNCR_LOCEN (0x80)
#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x7)<<0x8)
#define MCF_CLOCK_SYNCR_LOCRE (0x800)
#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x7)<<0xC)
#define MCF_CLOCK_SYNCR_LOLRE (0x8000)
/* Bit definitions and macros for MCF_CLOCK_SYNSR */
#define MCF_CLOCK_SYNSR_LOCS (0x4)
#define MCF_CLOCK_SYNSR_LOCK (0x8)
#define MCF_CLOCK_SYNSR_LOCKS (0x10)
#define MCF_CLOCK_SYNSR_CRYOSC (0x20)
#define MCF_CLOCK_SYNSR_OCOSC (0x40)
#define MCF_CLOCK_SYNSR_EXTOSC (0x80)
/* Bit definitions and macros for MCF_CLOCK_ROCR */
#define MCF_CLOCK_ROCR_TRIM(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_CLOCK_LPDR */
#define MCF_CLOCK_LPDR_LPD(x) (((x)&0xF)<<0)
/* Bit definitions and macros for MCF_CLOCK_CCHR */
#define MCF_CLOCK_CCHR_CCHR(x) (((x)&0x7)<<0)
/* Bit definitions and macros for MCF_CLOCK_CCLR */
#define MCF_CLOCK_CCLR_OSCSEL (0x1)
/* Bit definitions and macros for MCF_CLOCK_OCHR */
#define MCF_CLOCK_OCHR_STBY (0x40)
#define MCF_CLOCK_OCHR_OCOEN (0x80)
/* Bit definitions and macros for MCF_CLOCK_OCLR */
#define MCF_CLOCK_OCLR_RANGE (0x10)
#define MCF_CLOCK_OCLR_LPEN (0x20)
#define MCF_CLOCK_OCLR_REFS (0x40)
#define MCF_CLOCK_OCLR_OSCEN (0x80)
/* Bit definitions and macros for MCF_CLOCK_RTCDR */
#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0)
#endif /* __MCF52221_CLOCK_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_DMA.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_DMA_H__
#define __MCF52221_DMA_H__
/*********************************************************************
*
* DMA Controller (DMA)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_DMA0_SAR (*(vuint32*)(0x40000100))
#define MCF_DMA0_DAR (*(vuint32*)(0x40000104))
#define MCF_DMA0_DSR (*(vuint8 *)(0x40000108))
#define MCF_DMA0_BCR (*(vuint32*)(0x40000108))
#define MCF_DMA0_DCR (*(vuint32*)(0x4000010C))
#define MCF_DMA1_SAR (*(vuint32*)(0x40000110))
#define MCF_DMA1_DAR (*(vuint32*)(0x40000114))
#define MCF_DMA1_DSR (*(vuint8 *)(0x40000118))
#define MCF_DMA1_BCR (*(vuint32*)(0x40000118))
#define MCF_DMA1_DCR (*(vuint32*)(0x4000011C))
#define MCF_DMA2_SAR (*(vuint32*)(0x40000120))
#define MCF_DMA2_DAR (*(vuint32*)(0x40000124))
#define MCF_DMA2_DSR (*(vuint8 *)(0x40000128))
#define MCF_DMA2_BCR (*(vuint32*)(0x40000128))
#define MCF_DMA2_DCR (*(vuint32*)(0x4000012C))
#define MCF_DMA3_SAR (*(vuint32*)(0x40000130))
#define MCF_DMA3_DAR (*(vuint32*)(0x40000134))
#define MCF_DMA3_DSR (*(vuint8 *)(0x40000138))
#define MCF_DMA3_BCR (*(vuint32*)(0x40000138))
#define MCF_DMA3_DCR (*(vuint32*)(0x4000013C))
#define MCF_DMA_SAR(x) (*(vuint32*)(0x40000100 + ((x)*0x10)))
#define MCF_DMA_DAR(x) (*(vuint32*)(0x40000104 + ((x)*0x10)))
#define MCF_DMA_DSR(x) (*(vuint8 *)(0x40000108 + ((x)*0x10)))
#define MCF_DMA_BCR(x) (*(vuint32*)(0x40000108 + ((x)*0x10)))
#define MCF_DMA_DCR(x) (*(vuint32*)(0x4000010C + ((x)*0x10)))
/* Bit definitions and macros for MCF_DMA_SAR */
#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DAR */
#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DSR */
#define MCF_DMA_DSR_DONE (0x1)
#define MCF_DMA_DSR_BSY (0x2)
#define MCF_DMA_DSR_REQ (0x4)
#define MCF_DMA_DSR_BED (0x10)
#define MCF_DMA_DSR_BES (0x20)
#define MCF_DMA_DSR_CE (0x40)
/* Bit definitions and macros for MCF_DMA_BCR */
#define MCF_DMA_BCR_BCR(x) (((x)&0xFFFFFF)<<0)
#define MCF_DMA_BCR_DSR(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_DMA_DCR */
#define MCF_DMA_DCR_LCH2(x) (((x)&0x3)<<0)
#define MCF_DMA_DCR_LCH2_CH0 (0)
#define MCF_DMA_DCR_LCH2_CH1 (0x1)
#define MCF_DMA_DCR_LCH2_CH2 (0x2)
#define MCF_DMA_DCR_LCH2_CH3 (0x3)
#define MCF_DMA_DCR_LCH1(x) (((x)&0x3)<<0x2)
#define MCF_DMA_DCR_LCH1_CH0 (0)
#define MCF_DMA_DCR_LCH1_CH1 (0x1)
#define MCF_DMA_DCR_LCH1_CH2 (0x2)
#define MCF_DMA_DCR_LCH1_CH3 (0x3)
#define MCF_DMA_DCR_LINKCC(x) (((x)&0x3)<<0x4)
#define MCF_DMA_DCR_D_REQ (0x80)
#define MCF_DMA_DCR_DMOD(x) (((x)&0xF)<<0x8)
#define MCF_DMA_DCR_DMOD_DIS (0)
#define MCF_DMA_DCR_DMOD_16 (0x1)
#define MCF_DMA_DCR_DMOD_32 (0x2)
#define MCF_DMA_DCR_DMOD_64 (0x3)
#define MCF_DMA_DCR_DMOD_128 (0x4)
#define MCF_DMA_DCR_DMOD_256 (0x5)
#define MCF_DMA_DCR_DMOD_512 (0x6)
#define MCF_DMA_DCR_DMOD_1K (0x7)
#define MCF_DMA_DCR_DMOD_2K (0x8)
#define MCF_DMA_DCR_DMOD_4K (0x9)
#define MCF_DMA_DCR_DMOD_8K (0xA)
#define MCF_DMA_DCR_DMOD_16K (0xB)
#define MCF_DMA_DCR_DMOD_32K (0xC)
#define MCF_DMA_DCR_DMOD_64K (0xD)
#define MCF_DMA_DCR_DMOD_128K (0xE)
#define MCF_DMA_DCR_DMOD_256K (0xF)
#define MCF_DMA_DCR_SMOD(x) (((x)&0xF)<<0xC)
#define MCF_DMA_DCR_SMOD_DIS (0)
#define MCF_DMA_DCR_SMOD_16 (0x1)
#define MCF_DMA_DCR_SMOD_32 (0x2)
#define MCF_DMA_DCR_SMOD_64 (0x3)
#define MCF_DMA_DCR_SMOD_128 (0x4)
#define MCF_DMA_DCR_SMOD_256 (0x5)
#define MCF_DMA_DCR_SMOD_512 (0x6)
#define MCF_DMA_DCR_SMOD_1K (0x7)
#define MCF_DMA_DCR_SMOD_2K (0x8)
#define MCF_DMA_DCR_SMOD_4K (0x9)
#define MCF_DMA_DCR_SMOD_8K (0xA)
#define MCF_DMA_DCR_SMOD_16K (0xB)
#define MCF_DMA_DCR_SMOD_32K (0xC)
#define MCF_DMA_DCR_SMOD_64K (0xD)
#define MCF_DMA_DCR_SMOD_128K (0xE)
#define MCF_DMA_DCR_SMOD_256K (0xF)
#define MCF_DMA_DCR_START (0x10000)
#define MCF_DMA_DCR_DSIZE(x) (((x)&0x3)<<0x11)
#define MCF_DMA_DCR_DSIZE_LONG (0)
#define MCF_DMA_DCR_DSIZE_BYTE (0x1)
#define MCF_DMA_DCR_DSIZE_WORD (0x2)
#define MCF_DMA_DCR_DSIZE_LINE (0x3)
#define MCF_DMA_DCR_DINC (0x80000)
#define MCF_DMA_DCR_SSIZE(x) (((x)&0x3)<<0x14)
#define MCF_DMA_DCR_SSIZE_LONG (0)
#define MCF_DMA_DCR_SSIZE_BYTE (0x1)
#define MCF_DMA_DCR_SSIZE_WORD (0x2)
#define MCF_DMA_DCR_SSIZE_LINE (0x3)
#define MCF_DMA_DCR_SINC (0x400000)
#define MCF_DMA_DCR_BWC(x) (((x)&0x7)<<0x19)
#define MCF_DMA_DCR_BWC_16K (0x1)
#define MCF_DMA_DCR_BWC_32K (0x2)
#define MCF_DMA_DCR_BWC_64K (0x3)
#define MCF_DMA_DCR_BWC_128K (0x4)
#define MCF_DMA_DCR_BWC_256K (0x5)
#define MCF_DMA_DCR_BWC_512K (0x6)
#define MCF_DMA_DCR_BWC_1024K (0x7)
#define MCF_DMA_DCR_AA (0x10000000)
#define MCF_DMA_DCR_CS (0x20000000)
#define MCF_DMA_DCR_EEXT (0x40000000)
#define MCF_DMA_DCR_INT (0x80000000)
#endif /* __MCF52221_DMA_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_DTIM.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_DTIM_H__
#define __MCF52221_DTIM_H__
/*********************************************************************
*
* DMA Timers (DTIM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_DTIM0_DTMR (*(vuint16*)(0x40000400))
#define MCF_DTIM0_DTXMR (*(vuint8 *)(0x40000402))
#define MCF_DTIM0_DTER (*(vuint8 *)(0x40000403))
#define MCF_DTIM0_DTRR (*(vuint32*)(0x40000404))
#define MCF_DTIM0_DTCR (*(vuint32*)(0x40000408))
#define MCF_DTIM0_DTCN (*(vuint32*)(0x4000040C))
#define MCF_DTIM1_DTMR (*(vuint16*)(0x40000440))
#define MCF_DTIM1_DTXMR (*(vuint8 *)(0x40000442))
#define MCF_DTIM1_DTER (*(vuint8 *)(0x40000443))
#define MCF_DTIM1_DTRR (*(vuint32*)(0x40000444))
#define MCF_DTIM1_DTCR (*(vuint32*)(0x40000448))
#define MCF_DTIM1_DTCN (*(vuint32*)(0x4000044C))
#define MCF_DTIM2_DTMR (*(vuint16*)(0x40000480))
#define MCF_DTIM2_DTXMR (*(vuint8 *)(0x40000482))
#define MCF_DTIM2_DTER (*(vuint8 *)(0x40000483))
#define MCF_DTIM2_DTRR (*(vuint32*)(0x40000484))
#define MCF_DTIM2_DTCR (*(vuint32*)(0x40000488))
#define MCF_DTIM2_DTCN (*(vuint32*)(0x4000048C))
#define MCF_DTIM3_DTMR (*(vuint16*)(0x400004C0))
#define MCF_DTIM3_DTXMR (*(vuint8 *)(0x400004C2))
#define MCF_DTIM3_DTER (*(vuint8 *)(0x400004C3))
#define MCF_DTIM3_DTRR (*(vuint32*)(0x400004C4))
#define MCF_DTIM3_DTCR (*(vuint32*)(0x400004C8))
#define MCF_DTIM3_DTCN (*(vuint32*)(0x400004CC))
#define MCF_DTIM_DTMR(x) (*(vuint16*)(0x40000400 + ((x)*0x40)))
#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(0x40000402 + ((x)*0x40)))
#define MCF_DTIM_DTER(x) (*(vuint8 *)(0x40000403 + ((x)*0x40)))
#define MCF_DTIM_DTRR(x) (*(vuint32*)(0x40000404 + ((x)*0x40)))
#define MCF_DTIM_DTCR(x) (*(vuint32*)(0x40000408 + ((x)*0x40)))
#define MCF_DTIM_DTCN(x) (*(vuint32*)(0x4000040C + ((x)*0x40)))
/* Bit definitions and macros for MCF_DTIM_DTMR */
#define MCF_DTIM_DTMR_RST (0x1)
#define MCF_DTIM_DTMR_CLK(x) (((x)&0x3)<<0x1)
#define MCF_DTIM_DTMR_CLK_STOP (0)
#define MCF_DTIM_DTMR_CLK_DIV1 (0x2)
#define MCF_DTIM_DTMR_CLK_DIV16 (0x4)
#define MCF_DTIM_DTMR_CLK_DTIN (0x6)
#define MCF_DTIM_DTMR_FRR (0x8)
#define MCF_DTIM_DTMR_ORRI (0x10)
#define MCF_DTIM_DTMR_OM (0x20)
#define MCF_DTIM_DTMR_CE(x) (((x)&0x3)<<0x6)
#define MCF_DTIM_DTMR_CE_NONE (0)
#define MCF_DTIM_DTMR_CE_RISE (0x40)
#define MCF_DTIM_DTMR_CE_FALL (0x80)
#define MCF_DTIM_DTMR_CE_ANY (0xC0)
#define MCF_DTIM_DTMR_PS(x) (((x)&0xFF)<<0x8)
/* Bit definitions and macros for MCF_DTIM_DTXMR */
#define MCF_DTIM_DTXMR_MODE16 (0x1)
#define MCF_DTIM_DTXMR_HALTED (0x40)
#define MCF_DTIM_DTXMR_DMAEN (0x80)
/* Bit definitions and macros for MCF_DTIM_DTER */
#define MCF_DTIM_DTER_CAP (0x1)
#define MCF_DTIM_DTER_REF (0x2)
/* Bit definitions and macros for MCF_DTIM_DTRR */
#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DTIM_DTCR */
#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DTIM_DTCN */
#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
#endif /* __MCF52221_DTIM_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_EPORT.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_EPORT_H__
#define __MCF52221_EPORT_H__
/*********************************************************************
*
* Edge Port Module (EPORT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_EPORT_EPPAR (*(vuint16*)(0x40130000))
#define MCF_EPORT_EPDDR (*(vuint8 *)(0x40130002))
#define MCF_EPORT_EPIER (*(vuint8 *)(0x40130003))
#define MCF_EPORT_EPDR (*(vuint8 *)(0x40130004))
#define MCF_EPORT_EPPDR (*(vuint8 *)(0x40130005))
#define MCF_EPORT_EPFR (*(vuint8 *)(0x40130006))
/* Bit definitions and macros for MCF_EPORT_EPPAR */
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)
#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)
#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)
#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)
#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)
#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)
#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)
#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)
#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)
#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)
#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)
#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)
#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)
#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)
#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)
#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)
#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)
#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
#define MCF_EPORT_EPPAR_LEVEL (0)
#define MCF_EPORT_EPPAR_RISING (0x1)
#define MCF_EPORT_EPPAR_FALLING (0x2)
#define MCF_EPORT_EPPAR_BOTH (0x3)
/* Bit definitions and macros for MCF_EPORT_EPDDR */
#define MCF_EPORT_EPDDR_EPDD1 (0x2)
#define MCF_EPORT_EPDDR_EPDD2 (0x4)
#define MCF_EPORT_EPDDR_EPDD3 (0x8)
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPIER */
#define MCF_EPORT_EPIER_EPIE1 (0x2)
#define MCF_EPORT_EPIER_EPIE2 (0x4)
#define MCF_EPORT_EPIER_EPIE3 (0x8)
#define MCF_EPORT_EPIER_EPIE4 (0x10)
#define MCF_EPORT_EPIER_EPIE5 (0x20)
#define MCF_EPORT_EPIER_EPIE6 (0x40)
#define MCF_EPORT_EPIER_EPIE7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPDR */
#define MCF_EPORT_EPDR_EPD1 (0x2)
#define MCF_EPORT_EPDR_EPD2 (0x4)
#define MCF_EPORT_EPDR_EPD3 (0x8)
#define MCF_EPORT_EPDR_EPD4 (0x10)
#define MCF_EPORT_EPDR_EPD5 (0x20)
#define MCF_EPORT_EPDR_EPD6 (0x40)
#define MCF_EPORT_EPDR_EPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPPDR */
#define MCF_EPORT_EPPDR_EPPD1 (0x2)
#define MCF_EPORT_EPPDR_EPPD2 (0x4)
#define MCF_EPORT_EPPDR_EPPD3 (0x8)
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPFR */
#define MCF_EPORT_EPFR_EPF1 (0x2)
#define MCF_EPORT_EPFR_EPF2 (0x4)
#define MCF_EPORT_EPFR_EPF3 (0x8)
#define MCF_EPORT_EPFR_EPF4 (0x10)
#define MCF_EPORT_EPFR_EPF5 (0x20)
#define MCF_EPORT_EPFR_EPF6 (0x40)
#define MCF_EPORT_EPFR_EPF7 (0x80)
#endif /* __MCF52221_EPORT_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_GPIO.h
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Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_GPTA.h
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Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_I2C.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_I2C_H__
#define __MCF52221_I2C_H__
/*********************************************************************
*
* I2C Module (I2C)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_I2C_I2ADR (*(vuint8 *)(0x40000300))
#define MCF_I2C_I2FDR (*(vuint8 *)(0x40000304))
#define MCF_I2C_I2CR (*(vuint8 *)(0x40000308))
#define MCF_I2C_I2SR (*(vuint8 *)(0x4000030C))
#define MCF_I2C_I2DR (*(vuint8 *)(0x40000310))
/* Bit definitions and macros for MCF_I2C_I2ADR */
#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)
/* Bit definitions and macros for MCF_I2C_I2FDR */
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_I2C_I2CR */
#define MCF_I2C_I2CR_RSTA (0x4)
#define MCF_I2C_I2CR_TXAK (0x8)
#define MCF_I2C_I2CR_MTX (0x10)
#define MCF_I2C_I2CR_MSTA (0x20)
#define MCF_I2C_I2CR_IIEN (0x40)
#define MCF_I2C_I2CR_IEN (0x80)
/* Bit definitions and macros for MCF_I2C_I2SR */
#define MCF_I2C_I2SR_RXAK (0x1)
#define MCF_I2C_I2SR_IIF (0x2)
#define MCF_I2C_I2SR_SRW (0x4)
#define MCF_I2C_I2SR_IAL (0x10)
#define MCF_I2C_I2SR_IBB (0x20)
#define MCF_I2C_I2SR_IAAS (0x40)
#define MCF_I2C_I2SR_ICF (0x80)
/* Bit definitions and macros for MCF_I2C_I2DR */
#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)
#endif /* __MCF52221_I2C_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_INTC.h
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Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PAD.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_PAD_H__
#define __MCF52221_PAD_H__
/*********************************************************************
*
* Common GPIO
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PAD_PSRR (*(vuint32*)(0x40100078))
#define MCF_PAD_PDSR (*(vuint32*)(0x4010007C))
/* Bit definitions and macros for MCF_PAD_PSRR */
#define MCF_PAD_PSRR_PSRR0 (0x1)
#define MCF_PAD_PSRR_PSRR1 (0x2)
#define MCF_PAD_PSRR_PSRR2 (0x4)
#define MCF_PAD_PSRR_PSRR3 (0x8)
#define MCF_PAD_PSRR_PSRR4 (0x10)
#define MCF_PAD_PSRR_PSRR5 (0x20)
#define MCF_PAD_PSRR_PSRR6 (0x40)
#define MCF_PAD_PSRR_PSRR7 (0x80)
#define MCF_PAD_PSRR_PSRR8 (0x100)
#define MCF_PAD_PSRR_PSRR9 (0x200)
#define MCF_PAD_PSRR_PSRR10 (0x400)
#define MCF_PAD_PSRR_PSRR11 (0x800)
#define MCF_PAD_PSRR_PSRR12 (0x1000)
#define MCF_PAD_PSRR_PSRR13 (0x2000)
#define MCF_PAD_PSRR_PSRR14 (0x4000)
#define MCF_PAD_PSRR_PSRR15 (0x8000)
#define MCF_PAD_PSRR_PSRR16 (0x10000)
#define MCF_PAD_PSRR_PSRR17 (0x20000)
#define MCF_PAD_PSRR_PSRR18 (0x40000)
#define MCF_PAD_PSRR_PSRR19 (0x80000)
#define MCF_PAD_PSRR_PSRR20 (0x100000)
#define MCF_PAD_PSRR_PSRR21 (0x200000)
#define MCF_PAD_PSRR_PSRR22 (0x400000)
#define MCF_PAD_PSRR_PSRR23 (0x800000)
#define MCF_PAD_PSRR_PSRR24 (0x1000000)
#define MCF_PAD_PSRR_PSRR25 (0x2000000)
#define MCF_PAD_PSRR_PSRR26 (0x4000000)
#define MCF_PAD_PSRR_PSRR27 (0x8000000)
/* Bit definitions and macros for MCF_PAD_PDSR */
#define MCF_PAD_PDSR_PDSR0 (0x1)
#define MCF_PAD_PDSR_PDSR1 (0x2)
#define MCF_PAD_PDSR_PDSR2 (0x4)
#define MCF_PAD_PDSR_PDSR3 (0x8)
#define MCF_PAD_PDSR_PDSR4 (0x10)
#define MCF_PAD_PDSR_PDSR5 (0x20)
#define MCF_PAD_PDSR_PDSR6 (0x40)
#define MCF_PAD_PDSR_PDSR7 (0x80)
#define MCF_PAD_PDSR_PDSR8 (0x100)
#define MCF_PAD_PDSR_PDSR9 (0x200)
#define MCF_PAD_PDSR_PDSR10 (0x400)
#define MCF_PAD_PDSR_PDSR11 (0x800)
#define MCF_PAD_PDSR_PDSR12 (0x1000)
#define MCF_PAD_PDSR_PDSR13 (0x2000)
#define MCF_PAD_PDSR_PDSR14 (0x4000)
#define MCF_PAD_PDSR_PDSR15 (0x8000)
#define MCF_PAD_PDSR_PDSR16 (0x10000)
#define MCF_PAD_PDSR_PDSR17 (0x20000)
#define MCF_PAD_PDSR_PDSR18 (0x40000)
#define MCF_PAD_PDSR_PDSR19 (0x80000)
#define MCF_PAD_PDSR_PDSR20 (0x100000)
#define MCF_PAD_PDSR_PDSR21 (0x200000)
#define MCF_PAD_PDSR_PDSR22 (0x400000)
#define MCF_PAD_PDSR_PDSR23 (0x800000)
#define MCF_PAD_PDSR_PDSR24 (0x1000000)
#define MCF_PAD_PDSR_PDSR25 (0x2000000)
#define MCF_PAD_PDSR_PDSR26 (0x4000000)
#define MCF_PAD_PDSR_PDSR27 (0x8000000)
#endif /* __MCF52221_PAD_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PIT.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_PIT_H__
#define __MCF52221_PIT_H__
/*********************************************************************
*
* Programmable Interrupt Timer (PIT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PIT0_PCSR (*(vuint16*)(0x40150000))
#define MCF_PIT0_PMR (*(vuint16*)(0x40150002))
#define MCF_PIT0_PCNTR (*(vuint16*)(0x40150004))
#define MCF_PIT1_PCSR (*(vuint16*)(0x40160000))
#define MCF_PIT1_PMR (*(vuint16*)(0x40160002))
#define MCF_PIT1_PCNTR (*(vuint16*)(0x40160004))
#define MCF_PIT_PCSR(x) (*(vuint16*)(0x40150000 + ((x)*0x10000)))
#define MCF_PIT_PMR(x) (*(vuint16*)(0x40150002 + ((x)*0x10000)))
#define MCF_PIT_PCNTR(x) (*(vuint16*)(0x40150004 + ((x)*0x10000)))
/* Bit definitions and macros for MCF_PIT_PCSR */
#define MCF_PIT_PCSR_EN (0x1)
#define MCF_PIT_PCSR_RLD (0x2)
#define MCF_PIT_PCSR_PIF (0x4)
#define MCF_PIT_PCSR_PIE (0x8)
#define MCF_PIT_PCSR_OVW (0x10)
#define MCF_PIT_PCSR_DBG (0x20)
#define MCF_PIT_PCSR_DOZE (0x40)
#define MCF_PIT_PCSR_PRE(x) (((x)&0xF)<<0x8)
/* Bit definitions and macros for MCF_PIT_PMR */
#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_PIT_PCNTR */
#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)
#endif /* __MCF52221_PIT_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PMM.h
+44
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_PMM_H__
#define __MCF52221_PMM_H__
/*********************************************************************
*
* Power Management (PMM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PMM_LPICR (*(vuint8 *)(0x40000012))
#define MCF_PMM_LPCR (*(vuint8 *)(0x40110007))
/* Bit definitions and macros for MCF_PMM_LPICR */
#define MCF_PMM_LPICR_XLPM_IPL(x) (((x)&0x7)<<0x4)
#define MCF_PMM_LPICR_ENBSTOP (0x80)
/* Bit definitions and macros for MCF_PMM_LPCR */
#define MCF_PMM_LPCR_STPMD (0x8)
#define MCF_PMM_LPCR_LPMD(x) (((x)&0x3)<<0x6)
#define MCF_PMM_LPCR_LPMD_RUN (0)
#define MCF_PMM_LPCR_LPMD_DOZE (0x40)
#define MCF_PMM_LPCR_LPMD_WAIT (0x80)
#define MCF_PMM_LPCR_LPMD_STOP (0xC0)
#endif /* __MCF52221_PMM_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_PWM.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_PWM_H__
#define __MCF52221_PWM_H__
/*********************************************************************
*
* Pulse Width Modulation (PWM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PWM_PWME (*(vuint8 *)(0x401B0000))
#define MCF_PWM_PWMPOL (*(vuint8 *)(0x401B0001))
#define MCF_PWM_PWMCLK (*(vuint8 *)(0x401B0002))
#define MCF_PWM_PWMPRCLK (*(vuint8 *)(0x401B0003))
#define MCF_PWM_PWMCAE (*(vuint8 *)(0x401B0004))
#define MCF_PWM_PWMCTL (*(vuint8 *)(0x401B0005))
#define MCF_PWM_PWMSCLA (*(vuint8 *)(0x401B0008))
#define MCF_PWM_PWMSCLB (*(vuint8 *)(0x401B0009))
#define MCF_PWM_PWMCNT0 (*(vuint8 *)(0x401B000C))
#define MCF_PWM_PWMCNT1 (*(vuint8 *)(0x401B000D))
#define MCF_PWM_PWMCNT2 (*(vuint8 *)(0x401B000E))
#define MCF_PWM_PWMCNT3 (*(vuint8 *)(0x401B000F))
#define MCF_PWM_PWMCNT4 (*(vuint8 *)(0x401B0010))
#define MCF_PWM_PWMCNT5 (*(vuint8 *)(0x401B0011))
#define MCF_PWM_PWMCNT6 (*(vuint8 *)(0x401B0012))
#define MCF_PWM_PWMCNT7 (*(vuint8 *)(0x401B0013))
#define MCF_PWM_PWMPER0 (*(vuint8 *)(0x401B0014))
#define MCF_PWM_PWMPER1 (*(vuint8 *)(0x401B0015))
#define MCF_PWM_PWMPER2 (*(vuint8 *)(0x401B0016))
#define MCF_PWM_PWMPER3 (*(vuint8 *)(0x401B0017))
#define MCF_PWM_PWMPER4 (*(vuint8 *)(0x401B0018))
#define MCF_PWM_PWMPER5 (*(vuint8 *)(0x401B0019))
#define MCF_PWM_PWMPER6 (*(vuint8 *)(0x401B001A))
#define MCF_PWM_PWMPER7 (*(vuint8 *)(0x401B001B))
#define MCF_PWM_PWMDTY0 (*(vuint8 *)(0x401B001C))
#define MCF_PWM_PWMDTY1 (*(vuint8 *)(0x401B001D))
#define MCF_PWM_PWMDTY2 (*(vuint8 *)(0x401B001E))
#define MCF_PWM_PWMDTY3 (*(vuint8 *)(0x401B001F))
#define MCF_PWM_PWMDTY4 (*(vuint8 *)(0x401B0020))
#define MCF_PWM_PWMDTY5 (*(vuint8 *)(0x401B0021))
#define MCF_PWM_PWMDTY6 (*(vuint8 *)(0x401B0022))
#define MCF_PWM_PWMDTY7 (*(vuint8 *)(0x401B0023))
#define MCF_PWM_PWMSDN (*(vuint8 *)(0x401B0024))
#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(0x401B000C + ((x)*0x1)))
#define MCF_PWM_PWMPER(x) (*(vuint8 *)(0x401B0014 + ((x)*0x1)))
#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(0x401B001C + ((x)*0x1)))
/* Bit definitions and macros for MCF_PWM_PWME */
#define MCF_PWM_PWME_PWME0 (0x1)
#define MCF_PWM_PWME_PWME1 (0x2)
#define MCF_PWM_PWME_PWME2 (0x4)
#define MCF_PWM_PWME_PWME3 (0x8)
#define MCF_PWM_PWME_PWME4 (0x10)
#define MCF_PWM_PWME_PWME5 (0x20)
#define MCF_PWM_PWME_PWME6 (0x40)
#define MCF_PWM_PWME_PWME7 (0x80)
/* Bit definitions and macros for MCF_PWM_PWMPOL */
#define MCF_PWM_PWMPOL_PPOL0 (0x1)
#define MCF_PWM_PWMPOL_PPOL1 (0x2)
#define MCF_PWM_PWMPOL_PPOL2 (0x4)
#define MCF_PWM_PWMPOL_PPOL3 (0x8)
#define MCF_PWM_PWMPOL_PPOL4 (0x10)
#define MCF_PWM_PWMPOL_PPOL5 (0x20)
#define MCF_PWM_PWMPOL_PPOL6 (0x40)
#define MCF_PWM_PWMPOL_PPOL7 (0x80)
/* Bit definitions and macros for MCF_PWM_PWMCLK */
#define MCF_PWM_PWMCLK_PCLK0 (0x1)
#define MCF_PWM_PWMCLK_PCLK1 (0x2)
#define MCF_PWM_PWMCLK_PCLK2 (0x4)
#define MCF_PWM_PWMCLK_PCLK3 (0x8)
#define MCF_PWM_PWMCLK_PCLK4 (0x10)
#define MCF_PWM_PWMCLK_PCLK5 (0x20)
#define MCF_PWM_PWMCLK_PCLK6 (0x40)
#define MCF_PWM_PWMCLK_PCLK7 (0x80)
/* Bit definitions and macros for MCF_PWM_PWMPRCLK */
#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x7)<<0)
#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x7)<<0x4)
/* Bit definitions and macros for MCF_PWM_PWMCAE */
#define MCF_PWM_PWMCAE_CAE0 (0x1)
#define MCF_PWM_PWMCAE_CAE1 (0x2)
#define MCF_PWM_PWMCAE_CAE2 (0x4)
#define MCF_PWM_PWMCAE_CAE3 (0x8)
#define MCF_PWM_PWMCAE_CAE4 (0x10)
#define MCF_PWM_PWMCAE_CAE5 (0x20)
#define MCF_PWM_PWMCAE_CAE6 (0x40)
#define MCF_PWM_PWMCAE_CAE7 (0x80)
/* Bit definitions and macros for MCF_PWM_PWMCTL */
#define MCF_PWM_PWMCTL_PFRZ (0x4)
#define MCF_PWM_PWMCTL_PSWAI (0x8)
#define MCF_PWM_PWMCTL_CON01 (0x10)
#define MCF_PWM_PWMCTL_CON23 (0x20)
#define MCF_PWM_PWMCTL_CON45 (0x40)
#define MCF_PWM_PWMCTL_CON67 (0x80)
/* Bit definitions and macros for MCF_PWM_PWMSCLA */
#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PWM_PWMSCLB */
#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PWM_PWMCNT */
#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PWM_PWMPER */
#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PWM_PWMDTY */
#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PWM_PWMSDN */
#define MCF_PWM_PWMSDN_SDNEN (0x1)
#define MCF_PWM_PWMSDN_PWM7IL (0x2)
#define MCF_PWM_PWMSDN_PWM7IN (0x4)
#define MCF_PWM_PWMSDN_LVL (0x10)
#define MCF_PWM_PWMSDN_RESTART (0x20)
#define MCF_PWM_PWMSDN_IE (0x40)
#define MCF_PWM_PWMSDN_IF (0x80)
#endif /* __MCF52221_PWM_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_QSPI.h
+86
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_QSPI_H__
#define __MCF52221_QSPI_H__
/*********************************************************************
*
* Queued Serial Peripheral Interface (QSPI)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_QSPI_QMR (*(vuint16*)(0x40000340))
#define MCF_QSPI_QDLYR (*(vuint16*)(0x40000344))
#define MCF_QSPI_QWR (*(vuint16*)(0x40000348))
#define MCF_QSPI_QIR (*(vuint16*)(0x4000034C))
#define MCF_QSPI_QAR (*(vuint16*)(0x40000350))
#define MCF_QSPI_QDR (*(vuint16*)(0x40000354))
/* Bit definitions and macros for MCF_QSPI_QMR */
#define MCF_QSPI_QMR_BAUD(x) (((x)&0xFF)<<0)
#define MCF_QSPI_QMR_CPHA (0x100)
#define MCF_QSPI_QMR_CPOL (0x200)
#define MCF_QSPI_QMR_BITS(x) (((x)&0xF)<<0xA)
#define MCF_QSPI_QMR_DOHIE (0x4000)
#define MCF_QSPI_QMR_MSTR (0x8000)
/* Bit definitions and macros for MCF_QSPI_QDLYR */
#define MCF_QSPI_QDLYR_DTL(x) (((x)&0xFF)<<0)
#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x7F)<<0x8)
#define MCF_QSPI_QDLYR_SPE (0x8000)
/* Bit definitions and macros for MCF_QSPI_QWR */
#define MCF_QSPI_QWR_NEWQP(x) (((x)&0xF)<<0)
#define MCF_QSPI_QWR_CPTQP(x) (((x)&0xF)<<0x4)
#define MCF_QSPI_QWR_ENDQP(x) (((x)&0xF)<<0x8)
#define MCF_QSPI_QWR_CSIV (0x1000)
#define MCF_QSPI_QWR_WRTO (0x2000)
#define MCF_QSPI_QWR_WREN (0x4000)
#define MCF_QSPI_QWR_HALT (0x8000)
/* Bit definitions and macros for MCF_QSPI_QIR */
#define MCF_QSPI_QIR_SPIF (0x1)
#define MCF_QSPI_QIR_ABRT (0x4)
#define MCF_QSPI_QIR_WCEF (0x8)
#define MCF_QSPI_QIR_SPIFE (0x100)
#define MCF_QSPI_QIR_ABRTE (0x400)
#define MCF_QSPI_QIR_WCEFE (0x800)
#define MCF_QSPI_QIR_ABRTL (0x1000)
#define MCF_QSPI_QIR_ABRTB (0x4000)
#define MCF_QSPI_QIR_WCEFB (0x8000)
/* Bit definitions and macros for MCF_QSPI_QAR */
#define MCF_QSPI_QAR_ADDR(x) (((x)&0x3F)<<0)
#define MCF_QSPI_QAR_TRANS (0)
#define MCF_QSPI_QAR_RECV (0x10)
#define MCF_QSPI_QAR_CMD (0x20)
/* Bit definitions and macros for MCF_QSPI_QDR */
#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0)
#define MCF_QSPI_QDR_CONT (0x8000)
#define MCF_QSPI_QDR_BITSE (0x4000)
#define MCF_QSPI_QDR_DT (0x2000)
#define MCF_QSPI_QDR_DSCK (0x1000)
#define MCF_QSPI_QDR_QSPI_CS3 (0x800)
#define MCF_QSPI_QDR_QSPI_CS2 (0x400)
#define MCF_QSPI_QDR_QSPI_CS1 (0x200)
#define MCF_QSPI_QDR_QSPI_CS0 (0x100)
#endif /* __MCF52221_QSPI_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_RCM.h
+48
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_RCM_H__
#define __MCF52221_RCM_H__
/*********************************************************************
*
* Reset Controller Module (RCM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_RCM_RCR (*(vuint8 *)(0x40110000))
#define MCF_RCM_RSR (*(vuint8 *)(0x40110001))
/* Bit definitions and macros for MCF_RCM_RCR */
#define MCF_RCM_RCR_LVDE (0x1)
#define MCF_RCM_RCR_LVDRE (0x4)
#define MCF_RCM_RCR_LVDIE (0x8)
#define MCF_RCM_RCR_LVDF (0x10)
#define MCF_RCM_RCR_FRCRSTOUT (0x40)
#define MCF_RCM_RCR_SOFTRST (0x80)
/* Bit definitions and macros for MCF_RCM_RSR */
#define MCF_RCM_RSR_LOL (0x1)
#define MCF_RCM_RSR_LOC (0x2)
#define MCF_RCM_RSR_EXT (0x4)
#define MCF_RCM_RSR_POR (0x8)
#define MCF_RCM_RSR_SOFT (0x20)
#define MCF_RCM_RSR_LVD (0x40)
#endif /* __MCF52221_RCM_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_RTC.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_RTC_H__
#define __MCF52221_RTC_H__
/*********************************************************************
*
* Real-Time Clock (RTC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_RTC_HOURMIN (*(vuint32*)(0x400003C0))
#define MCF_RTC_SECONDS (*(vuint32*)(0x400003C4))
#define MCF_RTC_ALRM_HM (*(vuint32*)(0x400003C8))
#define MCF_RTC_ALRM_SEC (*(vuint32*)(0x400003CC))
#define MCF_RTC_RTCCTL (*(vuint32*)(0x400003D0))
#define MCF_RTC_RTCISR (*(vuint32*)(0x400003D4))
#define MCF_RTC_RTCIENR (*(vuint32*)(0x400003D8))
#define MCF_RTC_STPWCH (*(vuint32*)(0x400003DC))
#define MCF_RTC_DAYS (*(vuint32*)(0x400003E0))
#define MCF_RTC_ALRM_DAY (*(vuint32*)(0x400003E4))
/* Bit definitions and macros for MCF_RTC_HOURMIN */
#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x3F)<<0)
#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x1F)<<0x8)
/* Bit definitions and macros for MCF_RTC_SECONDS */
#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_RTC_ALRM_HM */
#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x3F)<<0)
#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x1F)<<0x8)
/* Bit definitions and macros for MCF_RTC_ALRM_SEC */
#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_RTC_RTCCTL */
#define MCF_RTC_RTCCTL_SWR (0x1)
#define MCF_RTC_RTCCTL_EN (0x80)
/* Bit definitions and macros for MCF_RTC_RTCISR */
#define MCF_RTC_RTCISR_SW (0x1)
#define MCF_RTC_RTCISR_MIN (0x2)
#define MCF_RTC_RTCISR_ALM (0x4)
#define MCF_RTC_RTCISR_DAY (0x8)
#define MCF_RTC_RTCISR_1HZ (0x10)
#define MCF_RTC_RTCISR_HR (0x20)
/* Bit definitions and macros for MCF_RTC_RTCIENR */
#define MCF_RTC_RTCIENR_SW (0x1)
#define MCF_RTC_RTCIENR_MIN (0x2)
#define MCF_RTC_RTCIENR_ALM (0x4)
#define MCF_RTC_RTCIENR_DAY (0x8)
#define MCF_RTC_RTCIENR_1HZ (0x10)
#define MCF_RTC_RTCIENR_HR (0x20)
/* Bit definitions and macros for MCF_RTC_STPWCH */
#define MCF_RTC_STPWCH_CNT(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_RTC_DAYS */
#define MCF_RTC_DAYS_DAYS(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_RTC_ALRM_DAY */
#define MCF_RTC_ALRM_DAY_DAYSAL(x) (((x)&0xFFFF)<<0)
#endif /* __MCF52221_RTC_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_SCM.h
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Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_UART.h
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Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_USB_OTG.h
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Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_CONSOLE_INTERNAL_RAM.lcf
+133
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# Sample Linker Command File for CodeWarrior for ColdFire
KEEP_SECTION {.vectortable}
# Memory ranges
MEMORY {
vectorram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000500
code (RX) : ORIGIN = 0x20000500, LENGTH = 0x00002B00
userram (RWX) : ORIGIN = 0x20003000, LENGTH = 0x00001000
}
SECTIONS {
# Heap and Stack sizes definition
___heap_size = 0x400;
___stack_size = 0x400;
# MCF52221 Derivative Memory map definitions from linker command files:
# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
# symbols must be defined in the linker command file.
# Memory Mapped Registers (IPSBAR= 0x40000000)
___IPSBAR = 0x40000000;
# 16 Kbytes Internal SRAM
___RAMBAR = 0x20000000;
___RAMBAR_SIZE = 0x00004000;
# 128 KByte Internal Flash Memory
___FLASHBAR = 0x00000000;
___FLASHBAR_SIZE = 0x00020000;
___SP_AFTER_RESET = ___RAMBAR + ___RAMBAR_SIZE - 4;
.userram : {} > userram
.code : {} > code
.vectorram : {} > vectorram
.vectors :
{
exceptions.c(.vectortable)
. = ALIGN (0x4);
} >> code
.text :
{
*(.text)
. = ALIGN (0x4);
*(.rodata)
. = ALIGN (0x4);
___ROM_AT = .;
___DATA_ROM = .;
} >> code
.data : AT(___ROM_AT)
{
___DATA_RAM = .;
. = ALIGN(0x4);
*(.exception)
. = ALIGN(0x4);
__exception_table_start__ = .;
EXCEPTION
__exception_table_end__ = .;
___sinit__ = .;
STATICINIT
__START_DATA = .;
*(.data)
. = ALIGN (0x4);
__END_DATA = .;
__START_SDATA = .;
*(.sdata)
. = ALIGN (0x4);
__END_SDATA = .;
___DATA_END = .;
__SDA_BASE = .;
. = ALIGN (0x4);
} >> userram
.bss :
{
___BSS_START = .;
__START_SBSS = .;
*(.sbss)
. = ALIGN (0x4);
*(SCOMMON)
__END_SBSS = .;
__START_BSS = .;
*(.bss)
. = ALIGN (0x4);
*(COMMON)
__END_BSS = .;
___BSS_END = .;
. = ALIGN(0x4);
} >> userram
.custom :
{
___HEAP_START = .;
___heap_addr = ___HEAP_START;
___HEAP_END = ___HEAP_START + ___heap_size;
___SP_END = ___HEAP_END;
___SP_INIT = ___SP_END + ___stack_size;
. = ALIGN (0x4);
} >> userram
___VECTOR_RAM = ADDR(.vectorram);
__SP_INIT = ___SP_INIT;
_romp_at = ___ROM_AT + SIZEOF(.data);
.romp : AT(_romp_at)
{
__S_romp = _romp_at;
WRITEW(___ROM_AT);
WRITEW(ADDR(.data));
WRITEW(SIZEOF(.data));
WRITEW(0);
WRITEW(0);
WRITEW(0);
}
}
Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_INTERNAL_FLASH.lcf
+140
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# Sample Linker Command File for CodeWarrior for ColdFire
KEEP_SECTION {.vectortable}
# Memory ranges
MEMORY {
vectorrom (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
cfmprotrom (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000020
code (RX) : ORIGIN = 0x00000500, LENGTH = 0x0001FB00
vectorram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000400
userram (RWX) : ORIGIN = 0x20000400, LENGTH = 0x00003C00
}
SECTIONS {
# Heap and Stack sizes definition
___heap_size = 0x1000;
___stack_size = 0x1000;
# MCF52221 Derivative Memory map definitions from linker command files:
# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
# symbols must be defined in the linker command file.
# Memory Mapped Registers (IPSBAR= 0x40000000)
___IPSBAR = 0x40000000;
# 16 Kbytes Internal SRAM
___RAMBAR = 0x20000000;
___RAMBAR_SIZE = 0x00004000;
# 128 KByte Internal Flash Memory
___FLASHBAR = 0x00000000;
___FLASHBAR_SIZE = 0x00020000;
___SP_AFTER_RESET = ___RAMBAR + ___RAMBAR_SIZE - 4;
.userram : {} > userram
.code : {} > code
.vectorram : {} > vectorram
.vectors :
{
exceptions.c(.vectortable)
. = ALIGN (0x4);
} > vectorrom
.cfmprotect :
{
*(.cfmconfig)
. = ALIGN (0x4);
} > cfmprotrom
.text :
{
*(.text)
. = ALIGN (0x4);
*(.rodata)
. = ALIGN (0x4);
___ROM_AT = .;
___DATA_ROM = .;
} >> code
.data : AT(___ROM_AT)
{
___DATA_RAM = .;
. = ALIGN(0x4);
*(.exception)
. = ALIGN(0x4);
__exception_table_start__ = .;
EXCEPTION
__exception_table_end__ = .;
___sinit__ = .;
STATICINIT
__START_DATA = .;
*(.data)
. = ALIGN (0x4);
__END_DATA = .;
__START_SDATA = .;
*(.sdata)
. = ALIGN (0x4);
__END_SDATA = .;
___DATA_END = .;
__SDA_BASE = .;
. = ALIGN (0x4);
} >> userram
.bss :
{
___BSS_START = .;
__START_SBSS = .;
*(.sbss)
. = ALIGN (0x4);
*(SCOMMON)
__END_SBSS = .;
__START_BSS = .;
*(.bss)
. = ALIGN (0x4);
*(COMMON)
__END_BSS = .;
___BSS_END = .;
. = ALIGN(0x4);
} >> userram
.custom :
{
___HEAP_START = .;
___heap_addr = ___HEAP_START;
___HEAP_END = ___HEAP_START + ___heap_size;
___SP_END = ___HEAP_END;
___SP_INIT = ___SP_END + ___stack_size;
. = ALIGN (0x4);
} >> userram
___VECTOR_RAM = ADDR(.vectorram);
__SP_INIT = ___SP_INIT;
_romp_at = ___ROM_AT + SIZEOF(.data);
.romp : AT(_romp_at)
{
__S_romp = _romp_at;
WRITEW(___ROM_AT);
WRITEW(ADDR(.data));
WRITEW(SIZEOF(.data));
WRITEW(0);
WRITEW(0);
WRITEW(0);
}
}
Demo/ColdFire_MCF52221_CodeWarrior/lcf/MCF52221_INTERNAL_RAM.lcf
+133
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@@ -0,0 +1,133 @@
# Sample Linker Command File for CodeWarrior for ColdFire
KEEP_SECTION {.vectortable}
# Memory ranges
MEMORY {
vectorram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000500
code (RX) : ORIGIN = 0x20000500, LENGTH = 0x00002B00
userram (RWX) : ORIGIN = 0x20003000, LENGTH = 0x00001000
}
SECTIONS {
# Heap and Stack sizes definition
___heap_size = 0x400;
___stack_size = 0x400;
# MCF52221 Derivative Memory map definitions from linker command files:
# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
# symbols must be defined in the linker command file.
# Memory Mapped Registers (IPSBAR= 0x40000000)
___IPSBAR = 0x40000000;
# 16 Kbytes Internal SRAM
___RAMBAR = 0x20000000;
___RAMBAR_SIZE = 0x00004000;
# 128 KByte Internal Flash Memory
___FLASHBAR = 0x00000000;
___FLASHBAR_SIZE = 0x00020000;
___SP_AFTER_RESET = ___RAMBAR + ___RAMBAR_SIZE - 4;
.userram : {} > userram
.code : {} > code
.vectorram : {} > vectorram
.vectors :
{
exceptions.c(.vectortable)
. = ALIGN (0x4);
} >> code
.text :
{
*(.text)
. = ALIGN (0x4);
*(.rodata)
. = ALIGN (0x4);
___ROM_AT = .;
___DATA_ROM = .;
} >> code
.data : AT(___ROM_AT)
{
___DATA_RAM = .;
. = ALIGN(0x4);
*(.exception)
. = ALIGN(0x4);
__exception_table_start__ = .;
EXCEPTION
__exception_table_end__ = .;
___sinit__ = .;
STATICINIT
__START_DATA = .;
*(.data)
. = ALIGN (0x4);
__END_DATA = .;
__START_SDATA = .;
*(.sdata)
. = ALIGN (0x4);
__END_SDATA = .;
___DATA_END = .;
__SDA_BASE = .;
. = ALIGN (0x4);
} >> userram
.bss :
{
___BSS_START = .;
__START_SBSS = .;
*(.sbss)
. = ALIGN (0x4);
*(SCOMMON)
__END_SBSS = .;
__START_BSS = .;
*(.bss)
. = ALIGN (0x4);
*(COMMON)
__END_BSS = .;
___BSS_END = .;
. = ALIGN(0x4);
} >> userram
.custom :
{
___HEAP_START = .;
___heap_addr = ___HEAP_START;
___HEAP_END = ___HEAP_START + ___heap_size;
___SP_END = ___HEAP_END;
___SP_INIT = ___SP_END + ___stack_size;
. = ALIGN (0x4);
} >> userram
___VECTOR_RAM = ADDR(.vectorram);
__SP_INIT = ___SP_INIT;
_romp_at = ___ROM_AT + SIZEOF(.data);
.romp : AT(_romp_at)
{
__S_romp = _romp_at;
WRITEW(___ROM_AT);
WRITEW(ADDR(.data));
WRITEW(SIZEOF(.data));
WRITEW(0);
WRITEW(0);
WRITEW(0);
}
}
Demo/ColdFire_MCF52221_CodeWarrior/readme.txt
+160
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@@ -0,0 +1,160 @@
//------------------------------------------------------------------------
// Readme.txt
//------------------------------------------------------------------------
This project is configure to get you up and running quickly using
CodeWarrior with the Freescale MCF52221 board.
This project provides full support for the selected board.
The created project provides Standard IO Support through console and terminal window.
Sample code for the following language:
- C
//------------------------------------------------------------------------
// Memory Maps
//------------------------------------------------------------------------
The Hardware has the following memory map:
# MCF52221 Derivative Memory map definitions from linker command files:
# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
# symbols must be defined in the linker command file.
# Memory Mapped Registers (IPSBAR= 0x40000000)
___IPSBAR = 0x40000000;
# 16 Kbytes Internal SRAM
___RAMBAR = 0x20000000;
___RAMBAR_SIZE = 0x00004000;
# 128 KByte Internal Flash Memory
___FLASHBAR = 0x00000000;
___FLASHBAR_SIZE = 0x00020000;
//------------------------------------------------------------------------
// Project Structure
//------------------------------------------------------------------------
The project generated contains various files/groups:
- readme.txt: information for this project
- Sources: application source codes, user customizable startup
code, uart library, exception table
- Includes: derivative and board header files, ...
- Libs: runtime and libs
- Project Settings: linker command files for the different build
targets, the initialization and memory configuration files for
the hardware debugging, the common startup code, etc...
//------------------------------------------------------------------------
// Build Targets
//------------------------------------------------------------------------
- CONSOLE_INTERNAL_RAM:
This project target is setup to load and debug code from internal RAM.
It should be used during your application development.
The application outputs to the CodeWarrior's console window.
- INTERNAL_RAM:
This project target is setup to load and debug code from internal RAM.
It should be used during your application development.
This is the very basic project that outputs to the UART.
You needs to connect a Terminal Program to see the output.
- INTERNAL_FLASH:
This project target is setup to load and debug code in Internal FLASH.
This is the very basic project that outputs to the UART. User needs
to connect the terminal to see the output.
===================================================================
WARNING regarding debugging new project wizard code with CCS-SIM
===================================================================
The CCS-SIM is an instruction set simulator, it does not implement
any peripherals.
The new project generated by the wizard are using startup code
performing some hardware peripheral initializations.
When debugging with the CCS-SIM it might happen that the simulation
stuck on loop using non implemented peripheral register flag as
condition (PLL initialization as example).
In this case, you should either:
- move the PC to next statement
- use a skip point
- define a simulator specific macro which used when define allos you
to comment out the unwanted code in order to debug with CCS-SIM
===================================================================
WARNING regarding code located in RAM
===================================================================
Many possible ColdFire target processors have an external bus, so
you can use large external RAM devices for debugging applications
during development. But some processors do not have an external
bus, so you must accommodate applications in on-chip memory.
Although this on-chip RAM accommodates this CodeWarrior project,
it probably is too small for full development of your application.
Accordingly, for a processor without external bus, you should locate
your applications in flash memory.
//------------------------------------------------------------------------
// Flashing the code
//------------------------------------------------------------------------
1. Select the appropriate project target and build it
2. Make sure the correct remote connection is selected in the Remote
Connection debugger panel
3. In the CodeWarrior IDE menu, select Project > Set Default Project
and select your project
4. In the CodeWarrior IDE menu, select Project > Set Default Target
and select the project target that has the code you want to flash
5. In the CodeWarrior IDE menu, select Tools > Flash Programmer
6. Go to the flash programmer Target Configuration panel, click Load
Settings
7. Browse to the <your project location>\cfg sub folder and
select the flash settings xml file matching your build target
8. Check that Use Custom Settings checkbox is not selected
9. Go to the Erase/Blank Check panel, select the All Sectors option and
click Erase
10. Go to Program/Verify panel, click Program
11. Your code should now be flashed
//------------------------------------------------------------------------
// Terminal Settings
//------------------------------------------------------------------------
In case the UART is supported, the terminal should be setup with:
- 19200 bauds,
- 8 data bits,
- no parity,
- 1 stop bit,
- no flow control.
Please check this file in the project.
//------------------------------------------------------------------------
// Getting Started
//------------------------------------------------------------------------
To build/debug your project, use the CodeWarrior IDE menu Project > Debug
or press F5. This will launch the debugger. Press again F5 in the
debugger (or the CodeWarrior IDE menu Project > Run) to start the
application. The CodeWarrior IDE menu Project > Break stops the
application.
//------------------------------------------------------------------------
// Adding your own code
//------------------------------------------------------------------------
Once everything is working as expected, you can begin adding your own code
to the project. Keep in mind that we provide this as an example of how to
get up and running quickly with CodeWarrior. There are certainly other
ways to handle interrupts and set up your linker command file. Feel free
to modify any of the source files provided.
//------------------------------------------------------------------------
// Additional documentation
//------------------------------------------------------------------------
Read the online documentation provided. In CodeWarrior IDE menu, select
Help > CodeWarrior Help.
//------------------------------------------------------------------------
// Contacting Freescale
//------------------------------------------------------------------------
For bug reports, technical questions, and suggestions, please use the
forms installed in the Release_Notes folder.
Demo/ColdFire_MCF52221_CodeWarrior/sources/FreeRTOSConfig.h
+142
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@@ -0,0 +1,142 @@
/*
FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
* and even write all or part of your application on your behalf. *
* See http://www.OpenRTOS.com for details of the services we provide to *
* expedite your project. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include "support_common.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 80000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 100 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 160 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 0 ) ) /* The heap size is worked out from the linker script, so this constant is not used. */
#define configMAX_TASK_NAME_LEN ( 12 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 0
#define configUSE_MUTEXES 1
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 0
#define configUSE_COUNTING_SEMAPHORES 0
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
#define configYIELD_INTERRUPT_VECTOR 16UL
#define configKERNEL_INTERRUPT_PRIORITY 1
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
void vApplicationSetupInterrupts( void );
/* Ethernet configuration. */
#define configMAC_0 0x00
#define configMAC_1 0x04
#define configMAC_2 0x9F
#define configMAC_3 0x00
#define configMAC_4 0xAB
#define configMAC_5 0x2B
#define configIP_ADDR0 192
#define configIP_ADDR1 168
#define configIP_ADDR2 0
#define configIP_ADDR3 11
#define configGW_ADDR0 172
#define configGW_ADDR1 25
#define configGW_ADDR2 218
#define configGW_ADDR3 3
#define configNET_MASK0 255
#define configNET_MASK1 255
#define configNET_MASK2 255
#define configNET_MASK3 0
#define configNUM_FEC_TX_BUFFERS 2
#define configNUM_FEC_RX_BUFFERS 4
#define configFEC_BUFFER_SIZE 1520
#define configUSE_PROMISCUOUS_MODE 0
#define configETHERNET_INPUT_TASK_STACK_SIZE ( 320 )
#define configETHERNET_INPUT_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define configPHY_ADDRESS 1
#if ( configFEC_BUFFER_SIZE & 0x0F ) != 0
#error configFEC_BUFFER_SIZE must be a multiple of 16.
#endif
#endif /* FREERTOS_CONFIG_H */
Demo/ColdFire_MCF52221_CodeWarrior/sources/FreeRTOS_Tick_Setup.c
+137
View File
@@ -0,0 +1,137 @@
/*
FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
* and even write all or part of your application on your behalf. *
* See http://www.OpenRTOS.com for details of the services we provide to *
* expedite your project. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#include "FreeRTOS.h"
#include "task.h"
__declspec(interrupt:0) void vPIT0InterruptHandler( void );
extern unsigned portLONG __VECTOR_RAM[];
/* Constants used to configure the interrupts. */
#define portPRESCALE_VALUE 64
#define portPRESCALE_REG_SETTING ( 5 << 8 )
#define portPIT_INTERRUPT_ENABLED ( 0x08 )
#define configPIT0_INTERRUPT_VECTOR ( 55 )
/*
* FreeRTOS.org requires two interrupts - a tick interrupt generated from a
* timer source, and a spare interrupt vector used for context switching.
* The configuration below uses PIT0 for the former, and vector 63 for the
* latter. **IF YOUR APPLICATION HAS BOTH OF THESE INTERRUPTS FREE THEN YOU DO
* NOT NEED TO CHANGE ANY OF THIS CODE** - otherwise instructions are provided
* here for using alternative interrupt sources.
*
* To change the tick interrupt source:
*
* 1) Modify vApplicationSetupInterrupts() below to be correct for whichever
* peripheral is to be used to generate the tick interrupt.
*
* 2) Change the name of the function __cs3_isr_interrupt_119() defined within
* this file to be correct for the interrupt vector used by the timer peripheral.
* The name of the function should contain the vector number, so by default vector
* number 119 is being used.
*
* 3) Make sure the tick interrupt is cleared within the interrupt handler function.
* Currently __cs3_isr_interrupt_119() clears the PIT0 interrupt.
*
* To change the spare interrupt source:
*
* 1) Modify vApplicationSetupInterrupts() below to be correct for whichever
* interrupt vector is to be used. Make sure you use a spare interrupt on interrupt
* controller 0, otherwise the register used to request context switches will also
* require modification.
*
* 2) Change the definition of configYIELD_INTERRUPT_VECTOR within FreeRTOSConfig.h
* to be correct for your chosen interrupt vector.
*
* 3) Change the name of the function __cs3_isr_interrupt_127() within portasm.S
* to be correct for whichever vector number is being used. By default interrupt
* controller 0 number 63 is used, which corresponds to vector number 127.
*/
void vApplicationSetupInterrupts( void )
{
const unsigned portSHORT usCompareMatchValue = ( ( configCPU_CLOCK_HZ / portPRESCALE_VALUE ) / configTICK_RATE_HZ );
/* Configure interrupt priority and level and unmask interrupt for PIT0. */
MCF_INTC0_ICR55 = ( 1 | ( configKERNEL_INTERRUPT_PRIORITY << 3 ) );
MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK55 );
/* Do the same for vector 63 (interrupt controller 0. I don't think the
write to MCF_INTC0_IMRH is actually required here but is included for
completeness. */
MCF_INTC0_ICR16 = ( 0 | configKERNEL_INTERRUPT_PRIORITY << 3 );
MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK16 | 0x01 );
/* Configure PIT0 to generate the RTOS tick. */
MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;
MCF_PIT0_PCSR = ( portPRESCALE_REG_SETTING | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );
MCF_PIT0_PMR = usCompareMatchValue;
}
/*-----------------------------------------------------------*/
__declspec(interrupt:0) void vPIT0InterruptHandler( void )
{
unsigned portLONG ulSavedInterruptMask;
/* Clear the PIT0 interrupt. */
MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;
/* Increment the RTOS tick. */
ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
vTaskIncrementTick();
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
/* If we are using the pre-emptive scheduler then also request a
context switch as incrementing the tick could have unblocked a task. */
#if configUSE_PREEMPTION == 1
{
taskYIELD();
}
#endif
}
Demo/ColdFire_MCF52221_CodeWarrior/sources/MCF52221_sysinit.c
+86
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@@ -0,0 +1,86 @@
/*
* File: mcf52221_sysinit.c
* Purpose: Power-on Reset configuration of the MCF52221.
*
* Notes:
*
*/
#include "support_common.h"
#include "exceptions.h"
/********************************************************************/
static void pll_init(void)
{
MCF_CLOCK_CCHR =0x05; // The PLL pre divider - 48MHz / 6 = 8MHz
/* The PLL pre-divider affects this!!!
* Multiply 8Mhz reference crystal /CCHR by 10 to acheive system clock of 80Mhz
*/
MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;
while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
{
}
}
/********************************************************************/
static void scm_init(void)
{
/*
* Enable on-chip modules to access internal SRAM
*/
MCF_SCM_RAMBAR = (0
| MCF_SCM_RAMBAR_BA(RAMBAR_ADDRESS)
| MCF_SCM_RAMBAR_BDE);
}
/********************************************************************/
/*
* Out of reset, the low-level assembly code calls this routine to
* initialize the mcf5206e for this board. A temporary stack has been
* setup in the internal SRAM, and the stack pointer will be changed
* to point to DRAM once this routine returns.
*/
void __initialize_hardware(void)
{
/*******************************************************
* Out of reset, the low-level assembly code calls this
* routine to initialize the MCF52221 modules for the
* M522223EVB board.
********************************************************/
asm
{
/* Initialize IPSBAR */
move.l #__IPSBAR,d0
andi.l #0xC0000000,d0 // need to mask
add.l #0x1,d0
move.l d0,0x40000000
/* Initialize FLASHBAR */
move.l #__FLASHBAR,d0
andi.l #0xFFF80000,d0 // need to mask
add.l #0x61,d0
movec d0,FLASHBAR
}
/* Set real time clock freq */
MCF_CLOCK_RTCDR = 48000000;
pll_init();
scm_init();
initialize_exceptions();
}
Demo/ColdFire_MCF52221_CodeWarrior/sources/MCF52221_sysinit.h
+55
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@@ -0,0 +1,55 @@
/*
* File: mcf52221demo_sysinit.h
* Purpose: Power-on Reset configuration of the MCF52221.
*
* Notes:
*
*/
#ifndef __MCF52221DEMO_SYSINIT_H__
#define __MCF52221DEMO_SYSINIT_H__
#ifdef __cplusplus
extern "C" {
#endif
#if ENABLE_UART_SUPPORT==1
#define TERMINAL_PORT 0
#define TERMINAL_BAUD kBaud19200
#endif /* ENABLE_UART_SUPPORT==1 */
#define SYSTEM_CLOCK_KHZ 80000 /* system bus frequency in kHz */
/********************************************************************/
/* __initialize_hardware Startup code routine
*
* __initialize_hardware is called by the startup code right after reset,
* with interrupt disabled and SP pre-set to a valid memory area.
* Here you should initialize memory and some peripherics;
* at this point global variables are not initialized yet.
* The startup code will initialize SP on return of this function.
*/
void __initialize_hardware(void);
/********************************************************************/
/* __initialize_system Startup code routine
*
* __initialize_system is called by the startup code when all languages
* specific initialization are done to allow additional hardware setup.
*/
void __initialize_system(void);
#ifdef __cplusplus
}
#endif
#endif /* __MCF52221DEMO_SYSINIT_H__ */
Demo/ColdFire_MCF52221_CodeWarrior/sources/ParTest/ParTest.c
+133
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@@ -0,0 +1,133 @@
/*
FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
* and even write all or part of your application on your behalf. *
* See http://www.OpenRTOS.com for details of the services we provide to *
* expedite your project. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
Changes from V2.5.2
+ All LED's are turned off to start.
*/
#include "FreeRTOS.h"
#include "task.h"
#include "partest.h"
#define partstNUM_LEDs 4
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* Enable signals as GPIO */
MCF_GPIO_PTCPAR = 0
| MCF_GPIO_PTCPAR_DTIN3_GPIO
| MCF_GPIO_PTCPAR_DTIN2_GPIO
| MCF_GPIO_PTCPAR_DTIN1_GPIO
| MCF_GPIO_PTCPAR_DTIN0_GPIO;
/* Enable signals as digital outputs */
MCF_GPIO_DDRTC = 0
| MCF_GPIO_DDRTC_DDRTC3
| MCF_GPIO_DDRTC_DDRTC2
| MCF_GPIO_DDRTC_DDRTC1
| MCF_GPIO_DDRTC_DDRTC0;
MCF_GPIO_PORTTC = 0x00; // TURN LEDS OFF
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned portBASE_TYPE uxLEDMask;
if( uxLED < partstNUM_LEDs )
{
uxLEDMask = 1UL << uxLED;
taskENTER_CRITICAL();
{
if( xValue )
{
MCF_GPIO_PORTTC |= uxLEDMask;
}
else
{
MCF_GPIO_PORTTC &= ~uxLEDMask;
}
}
taskEXIT_CRITICAL();
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned portBASE_TYPE uxLEDMask;
if( uxLED < partstNUM_LEDs )
{
uxLEDMask = 1UL << uxLED;
taskENTER_CRITICAL();
{
if( MCF_GPIO_PORTTC & uxLEDMask )
{
MCF_GPIO_PORTTC &= ~uxLEDMask;
}
else
{
MCF_GPIO_PORTTC |= uxLEDMask;
}
}
taskEXIT_CRITICAL();
}
}
Demo/ColdFire_MCF52221_CodeWarrior/sources/cfm.c
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/* CFM init */
#define KEY_UPPER 0
#define KEY_LOWER 0
#define CFMPROT 0
#define CFMSACC 0
#define CFMDACC 0
#define CFMSEC 0
#pragma define_section cfmconfig ".cfmconfig" far_absolute R
#pragma explicit_zero_data on
__declspec(cfmconfig) unsigned long _cfm[6] = {
KEY_UPPER, /* 0x00000400 */
KEY_LOWER, /* 0x00000404 */
CFMPROT, /* 0x00000408 */
CFMSACC, /* 0x0000040C */
CFMDACC, /* 0x00000410 */
CFMSEC, /* 0x00000414 */
};
Demo/ColdFire_MCF52221_CodeWarrior/sources/exceptions.c
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Demo/ColdFire_MCF52221_CodeWarrior/sources/exceptions.h
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/*
* File: exceptions.h
* Purpose: Generic exception handling for ColdFire processors
*
* Notes:
*/
#ifndef _MCF_EXCEPTIONS_H
#define _MCF_EXCEPTIONS_H
#ifdef __cplusplus
extern "C" {
#endif
/***********************************************************************/
/*
* This is the handler for all exceptions which are not common to all
* ColdFire Chips.
*
* Called by mcf_exception_handler
*
*/
void derivative_interrupt(unsigned long vector);
/***********************************************************************/
/*
* This is the exception handler for all exceptions common to all
* chips ColdFire. Most exceptions do nothing, but some of the more
* important ones are handled to some extent.
*
* Called by asm_exception_handler
*/
void mcf_exception_handler(void *framepointer);
/***********************************************************************/
/*
* This is the assembly exception handler defined in the vector table.
* This function is in assembler so that the frame pointer can be read
* from the stack.
* Note that the way to give the stack frame as argument to the c handler
* depends on the used ABI (Register, Compact or Standard).
*
*/
asm void asm_exception_handler(void);
/***********************************************************************/
/* MCF5xxx exceptions table initialization:
*
* Set VBR and performs RAM vector table initialization.
* The following symbol should be defined in the lcf:
* __VECTOR_RAM
*
* _vect is the start of the exception table in the code
* In case _vect address is different from __VECTOR_RAM,
* the vector table is copied from _vect to __VECTOR_RAM.
* In any case VBR is set to __VECTOR_RAM.
*/
void initialize_exceptions(void);
#ifdef __cplusplus
}
#endif
#endif /* _MCF_EXCEPTIONS_H */
Demo/ColdFire_MCF52221_CodeWarrior/sources/lwipopts.h
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Demo/ColdFire_MCF52221_CodeWarrior/sources/main.c
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Demo/ColdFire_MCF52221_CodeWarrior/sources/printf-stdarg.c
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Demo/ColdFire_MCF52221_CodeWarrior/sources/startcf.c
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Demo/ColdFire_MCF52221_CodeWarrior/sources/startcf.h
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/******************************************************************************
FILE : startcf.h
PURPOSE : startup code for ColdFire
LANGUAGE: C
Notes:
1) Default entry point is _startup.
. disable interrupts
. the SP is set to __SP_AFTER_RESET
. SP must be initialized to valid memory
in case the memory it points to is not valid using MEMORY_INIT macro
2) __initialize_hardware is called. Here you can initialize memory and some peripherics
at this point global variables are not initialized yet
3) After __initialize_hardware memory is setup; initialize SP to _SP_INIT and perform
needed initialisations for the language (clear memory, data rom copy).
4) void __initialize_system(void); is called
to allow additional hardware initialization (UART, GPIOs, etc...)
5) Jump to main
*/
/********************************************************************************/
#ifndef STARTCF_H
#define STARTCF_H
#ifdef __cplusplus
extern "C" {
#endif
#include "support_common.h"
extern unsigned long far __SP_INIT[];
extern unsigned long far __SP_AFTER_RESET[];
#ifndef MEMORY_INIT
/* If MEMORY_INIT is set then it performs
minimal memory initialization (to preset SP to __SP_AFTER_RESET, etc...)
*/
#define MEMORY_INIT
#endif
void _startup(void);
#ifndef SUPPORT_ROM_TO_RAM
/*
* If SUPPORT_ROM_TO_RAM is set, _S_romp is used to define the copy to be performed.
* If it is not set, there's a single block to copy, performed directly without
* using the __S_romp structure, based on __DATA_RAM, __DATA_ROM and
* __DATA_END symbols.
*
* Set to 0 for more aggressive dead stripping ...
*/
#define SUPPORT_ROM_TO_RAM 1
#endif
/* format of the ROM table info entry ... */
typedef struct RomInfo {
void *Source;
void *Target;
unsigned long Size;
} RomInfo;
/* imported data */
extern far RomInfo _S_romp[]; /* linker defined symbol */
#ifdef __cplusplus
}
#endif
#endif
Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.c
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Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.h
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/*
* File: stdlib.h
* Purpose: Function prototypes for standard library functions
*
* Notes:
*/
#ifndef _STDLIB_H
#define _STDLIB_H
/********************************************************************
* Standard library functions
********************************************************************/
int
isspace (int);
int
isalnum (int);
int
isdigit (int);
int
isupper (int);
int
strcasecmp (const char *, const char *);
int
strncasecmp (const char *, const char *, int);
unsigned long
strtoul (char *, char **, int);
int
strlen (const char *);
char *
strcat (char *, const char *);
char *
strncat (char *, const char *, int);
char *
strcpy (char *, const char *);
char *
strncpy (char *, const char *, int);
int
strcmp (const char *, const char *);
int
strncmp (const char *, const char *, int);
void *
memcpy (void *, const void *, unsigned);
void *
memset (void *, int, unsigned);
void
free (void *);
void *
malloc (unsigned);
#define RAND_MAX 32767
int
rand (void);
void
srand (int);
/********************************************************************/
#endif
Demo/ColdFire_MCF52221_CodeWarrior/sources/support_common.h
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/*
* File: support_common.h
* Purpose: Various project configurations.
*
* Notes:
*/
#ifndef _SUPPORT_COMMON_H_
#define _SUPPORT_COMMON_H_
/* Enable UART Support. */
#define ENABLE_UART_SUPPORT 0
#define MEMORY_INIT \
/* Initialize RAMBAR: locate SRAM and validate it */ \
move.l %#__RAMBAR + 0x21,d0; \
movec d0,RAMBAR;
#define SUPPORT_ROM_TO_RAM 1
/*
* Include the derivative header files
*/
#include "MCF52221.h"
/*
* Include the board specific header files
*/
#include "MCF52221_sysinit.h"
/********************************************************************/
#endif /* _SUPPORT_COMMON_H_ */
Demo/ColdFire_MCF52221_CodeWarrior/sources/uart_support.c
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Demo/ColdFire_MCF52221_CodeWarrior/sources/uart_support.h
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/*
* File: uart_support.h
* Purpose: Implements UART basic support, Derivative Specific Interrupt handler and need function needed
* for MSL Support (printf\cout to terminal), defined in <UART.h>
*
* Notes:
*
*/
#ifndef __UART_SUPPORT_H__
#define __UART_SUPPORT_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "support_common.h"
#if ENABLE_UART_SUPPORT==1
/*
* Include the Freescale UART specific header file for printf/cout/scanf support
*/
#include <ansi_parms.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <UART.h>
#ifdef __cplusplus
}
#endif
#define UART_STANDARD 0
#define UART_DIVIDER 1
#define UART_5407 2
#define UART_PSC 3
#define UART_54451 4
#define UART_SUPPORT_TYPE UART_STANDARD
void uart_init(int channel, unsigned long systemClockKHz, unsigned long baudRate);
/********************************************************************/
/*
* Wait for a character to be received on the specified UART
*
* Return Values:
* the received character
*/
char uart_getchar (int channel);
/********************************************************************/
/*
* Wait for space in the UART Tx FIFO and then send a character
*/
void uart_putchar (int channel, char ch);
#endif /* ENABLE_UART_SUPPORT */
#ifdef __cplusplus
}
#endif
#endif /* __UART_SUPPORT_H__ */