FreeRTOS source updates:

+ Add the pre-existing 64-bit Cortex-A53 port layer into the head revision of the main repository. Demo application updates: + Update Zynq demo to use SDK version 2015.4 + Add task static allocation standard demo to Zynq demo. + Make the XScuGic object accessible outside of the vConfigureTickInterrupt(), again in the Zynq demo.
2026-09-22 11:14:03 +08:00 · 2015-12-21 08:25:41 +00:00
parent ea95020ffd
commit 51560d9a96
167 changed files with 1756 additions and 47 deletions
@@ -133,6 +133,7 @@
 #define configUSE_APPLICATION_TASK_TAG			0
 #define configUSE_COUNTING_SEMAPHORES			1
 #define configUSE_QUEUE_SETS					1
+#define configSUPPORT_STATIC_ALLOCATION			1

 /* Co-routine definitions. */
 #define configUSE_CO_ROUTINES 					0
@@ -78,6 +78,7 @@
 #define XSCUTIMER_CLOCK_HZ ( XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ / 2UL )

 static XScuTimer xTimer;
+XScuGic xInterruptController; 	/* Interrupt controller instance */

 /*
 * The application must provide a function that configures a peripheral to
@@ -87,7 +88,6 @@ static XScuTimer xTimer;
 */
 void vConfigureTickInterrupt( void )
 {
-static XScuGic xInterruptController; 	/* Interrupt controller instance */
 BaseType_t xStatus;
 extern void FreeRTOS_Tick_Handler( void );
 XScuTimer_Config *pxTimerConfig;
@@ -150,6 +150,7 @@
 #include "EventGroupsDemo.h"
 #include "TaskNotify.h"
 #include "IntSemTest.h"
+#include "StaticAllocation.h"

 /* Priorities for the demo application tasks. */
 #define mainSEM_TEST_PRIORITY				( tskIDLE_PRIORITY + 1UL )
@@ -258,7 +259,7 @@ void main_full( void )
 	vStartEventGroupTasks();
 	vStartTaskNotifyTask();
 	vStartInterruptSemaphoreTasks();
-
+	vStartStaticallyAllocatedTasks();

 	/* Start the tasks that implements the command console on the UART, as
 	described above. */
@@ -400,17 +401,22 @@ unsigned long ulErrorFound = pdFALSE;
 			ulErrorFound |= 1UL << 14UL;
 		}

+		if( xAreStaticAllocationTasksStillRunning() != pdPASS )
+		{
+			ulErrorFound |= 1UL << 15UL;
+		}
+
 		/* Check that the register test 1 task is still running. */
 		if( ulLastRegTest1Value == ulRegTest1LoopCounter )
 		{
-			ulErrorFound |= 1UL << 15UL;
+			ulErrorFound |= 1UL << 16UL;
 		}
 		ulLastRegTest1Value = ulRegTest1LoopCounter;

 		/* Check that the register test 2 task is still running. */
 		if( ulLastRegTest2Value == ulRegTest2LoopCounter )
 		{
-			ulErrorFound |= 1UL << 16UL;
+			ulErrorFound |= 1UL << 17UL;
 		}
 		ulLastRegTest2Value = ulRegTest2LoopCounter;

@@ -403,6 +403,30 @@ const uint32_t ulMaxDivisor = 0xff, ulDivisorShift = 0x08;
 	 XScuWdt_SetTimerMode( &xWatchDogInstance );
 	 XScuWdt_Start( &xWatchDogInstance );
 }
-
+/*-----------------------------------------------------------*/
+
+void vApplicationGetIdleTaskMemory( DummyTCB_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint16_t *pusIdleTaskStackSize )
+{
+	/* configUSE_STATIC_ALLOCATION is set to 1, so the application has the
+	opportunity to supply the buffers that will be used by the Idle task as its
+	stack and to hold its TCB.  If these are set to NULL then the buffers will
+	be allocated dynamically, just as if xTaskCreate() had been called. */
+	*ppxIdleTaskTCBBuffer = NULL;
+	*ppxIdleTaskStackBuffer = NULL;
+	*pusIdleTaskStackSize = configMINIMAL_STACK_SIZE; /* In words.  NOT in bytes! */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationGetTimerTaskMemory( DummyTCB_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint16_t *pusTimerTaskStackSize )
+{
+	/* configUSE_STATIC_ALLOCATION is set to 1, so the application has the
+	opportunity to supply the buffers that will be used by the Timer/RTOS daemon
+	task as its	stack and to hold its TCB.  If these are set to NULL then the
+	buffers will be allocated dynamically, just as if xTaskCreate() had been
+	called. */
+	*ppxTimerTaskTCBBuffer = NULL;
+	*ppxTimerTaskStackBuffer = NULL;
+	*pusTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; /* In words.  NOT in bytes! */
+}


@@ -22,8 +22,8 @@
 *
 *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
 *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
@@ -33,6 +33,9 @@
 /**
 *
 * @file xadcps.h
+* @addtogroup xadcps_v2_0
+* @{
+* @details
 *
 * The XAdcPs driver supports the Xilinx XADC/ADC device.
 *
@@ -557,3 +560,4 @@ void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
 #endif

 #endif  /* End of protection macro. */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xadcps_hw.h
+* @addtogroup xadcps_v2_0
+* @{
 *
 * This header file contains identifiers and basic driver functions (or
 * macros) that can be used to access the XADC device through the Device
@@ -497,3 +499,4 @@ extern "C" {
 #endif

 #endif  /* End of protection macro. */
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xcanps.h
+* @addtogroup canps_v2_0
+* @{
+* @details
 *
 * The Xilinx CAN driver component.  This component supports the Xilinx
 * CAN Controller.
@@ -559,3 +562,4 @@ XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId);

 #endif /* end of protection macro */

+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xcanps_hw.h
+* @addtogroup canps_v2_0
+* @{
 *
 * This header file contains the identifiers and basic driver functions (or
 * macros) that can be used to access the device. Other driver functions
@@ -364,3 +366,4 @@ void XCanPs_ResetHw(u32 BaseAddr);

 #endif /* end of protection macro */

+/** @} */
@@ -33,7 +33,11 @@
 /**
 *
 * @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_0
+* @{
+* @details
 *
 * dummy file
 *
 ******************************************************************************/
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xdevcfg.h
+* @addtogroup devcfg_v3_1
+* @{
+* @details
 *
 * The is the main header file for the Device Configuration Interface of the Zynq
 * device. The device configuration interface has three main functionality.
@@ -378,3 +381,4 @@ void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
 #endif

 #endif	/* end of protection macro */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_1
+* @{
 *
 * This file contains the hardware interface to the Device Config Interface.
 *
@@ -390,3 +392,4 @@ void XDcfg_ResetHw(u32 BaseAddr);
 #endif

 #endif	/* end of protection macro */
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xdmaps.h
+* @addtogroup dmaps_v2_0
+* @{
+* @details
 *
 *
 * <pre>
@@ -314,3 +317,4 @@ int XDmaPs_SelfTest(XDmaPs *InstPtr);
 #endif

 #endif /* end of protection macro */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xdmaps_hw.h
+* @addtogroup dmaps_v2_0
+* @{
 *
 * This header file contains the hardware interface of an XDmaPs device.
 *
@@ -288,3 +290,4 @@ void XDmaPs_ResetHw(u32 BaseAddr);
 #endif

 #endif /* end of protection macro */
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xemacps.h
+* @addtogroup emacps_v2_0
+* @{
+* @details
 *
 * The Xilinx Embedded Processor Block Ethernet driver.
 *
@@ -710,3 +713,4 @@ void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, int BLength);
 #endif

 #endif /* end of protection macro */
+/** @} */
@@ -34,6 +34,8 @@
 /**
 *
 * @file xemacps_bd.h
+* @addtogroup emacps_v2_0
+* @{
 *
 * This header provides operations to manage buffer descriptors in support
 * of scatter-gather DMA.
@@ -726,3 +728,4 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
 #endif

 #endif /* end of protection macro */
+/** @} */
@@ -34,6 +34,8 @@
 /**
 *
 * @file xemacps_bdring.h
+* @addtogroup emacps_v2_0
+* @{
 *
 * The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
 * DMA functionalities.
@@ -231,3 +233,4 @@ int XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);


 #endif /* end of protection macros */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xemacps_hw.h
+* @addtogroup emacps_v2_0
+* @{
 *
 * This header file contains identifiers and low-level driver functions (or
 * macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
@@ -594,3 +596,4 @@ void XEmacPs_ResetHw(u32 BaseAddr);
 #endif

 #endif /* end of protection macro */
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xgpiops.h
+* @addtogroup gpiops_v2_1
+* @{
+* @details
 *
 * The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
 * Controller.
@@ -253,3 +256,4 @@ XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
 #endif

 #endif /* end of protection macro */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xgpiops_hw.h
+* @addtogroup gpiops_v2_1
+* @{
 *
 * This header file contains the identifiers and basic driver functions (or
 * macros) that can be used to access the device. Other driver functions
@@ -148,3 +150,4 @@ void XGpioPs_ResetHw(u32 BaseAddress);
 #endif /* __cplusplus */

 #endif /* XGPIOPS_HW_H */
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xiicps.h
+* @addtogroup iicps_v2_1
+* @{
+* @details
 *
 * This is an implementation of IIC driver in the PS block. The device can
 * be either a master or a slave on the IIC bus. This implementation supports
@@ -399,3 +402,4 @@ u32 XIicPs_GetSClk(XIicPs *InstancePtr);

 #endif /* end of protection macro */

+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xiicps_hw.h
+* @addtogroup iicps_v2_1
+* @{
 *
 * This header file contains the hardware definition for an IIC device.
 * It includes register definitions and interface functions to read/write
@@ -377,3 +379,4 @@ void XIicPs_ResetHw(u32 BaseAddr);

 #endif /* end of protection macro */

+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xqspips.h
+* @addtogroup qspips_v3_0
+* @{
+* @details
 *
 * This file contains the implementation of the XQspiPs driver. It supports only
 * master mode. User documentation for the driver functions is contained in this
@@ -779,3 +782,4 @@ void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,

 #endif /* end of protection macro */

+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xqspips_hw.h
+* @addtogroup qspips_v3_0
+* @{
 *
 * This header file contains the identifiers and basic HW access driver
 * functions (or  macros) that can be used to access the device. Other driver
@@ -370,3 +372,4 @@ void XQspiPs_LinearInit(u32 BaseAddress);
 #endif

 #endif /* end of protection macro */
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xscugic.h
+* @addtogroup scugic_v2_1
+* @{
+* @details
 *
 * The generic interrupt controller driver component.
 *
@@ -313,3 +316,4 @@ int  XScuGic_SelfTest(XScuGic *InstancePtr);

 #endif            /* end of protection macro */

+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xscugic_hw.h
+* @addtogroup scugic_v2_1
+* @{
 *
 * This header file contains identifiers and HW access functions (or
 * macros) that can be used to access the device.  The user should refer to the
@@ -630,3 +632,4 @@ void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,

 #endif            /* end of protection macro */

+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xscutimer.h
+* @addtogroup scutimer_v2_0
+* @{
+* @details
 *
 * The timer driver supports the Cortex A9 private timer.
 *
@@ -359,3 +362,4 @@ u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
 #endif

 #endif	/* end of protection macro */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xscutimer_hw.h
+* @addtogroup scutimer_v2_0
+* @{
 *
 * This file contains the hardware interface to the Timer.
 *
@@ -281,3 +283,4 @@ extern "C" {
 #endif

 #endif	/* end of protection macro */
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xscuwdt.h
+* @addtogroup scuwdt_v2_0
+* @{
+* @details
 *
 * The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
 * watchdog timer hardware.
@@ -378,3 +381,4 @@ int XScuWdt_SelfTest(XScuWdt *InstancePtr);
 #endif

 #endif	/* end of protection macro */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_0
+* @{
 *
 * This file contains the hardware interface to the Xilinx SCU private Watch Dog
 * Timer (XSCUWDT).
@@ -176,3 +178,4 @@ extern "C" {
 #endif

 #endif	/* end of protection macro */
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xsdps.h
+* @addtogroup sdps_v2_1
+* @{
+* @details
 *
 * This file contains the implementation of XSdPs driver.
 * This driver is used initialize read from and write to the SD card.
@@ -181,3 +184,4 @@ int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
 #endif

 #endif /* SD_H_ */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xsdps_hw.h
+* @addtogroup sdps_v2_1
+* @{
 *
 * This header file contains the identifiers and basic HW access driver
 * functions (or  macros) that can be used to access the device. Other driver
@@ -603,3 +605,4 @@ extern "C" {
 #endif

 #endif /* SD_HW_H_ */
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xttcps.h
+* @addtogroup ttcps_v2_0
+* @{
+* @details
 *
 * This is the driver for one 16-bit timer counter in the Triple Timer Counter
 * (TTC) module in the Ps block.
@@ -405,3 +408,4 @@ int XTtcPs_SelfTest(XTtcPs *InstancePtr);
 #endif

 #endif /* end of protection macro */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xttcps_hw.h
+* @addtogroup ttcps_v2_0
+* @{
 *
 * This file defines the hardware interface to one of the three timer counters
 * in the Ps block.
@@ -206,3 +208,4 @@ extern "C" {
 }
 #endif
 #endif /* end of protection macro */
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xuartps.h
+* @addtogroup uartps_v2_1
+* @{
+* @details
 *
 * This driver supports the following features:
 *
@@ -502,3 +505,4 @@ int XUartPs_SelfTest(XUartPs *InstancePtr);
 #endif

 #endif /* end of protection macro */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xuartps_hw.h
+* @addtogroup uartps_v2_1
+* @{
 *
 * This header file contains the hardware interface of an XUartPs device.
 *
@@ -421,3 +423,4 @@ void XUartPs_ResetHw(u32 BaseAddress);
 #endif

 #endif /* end of protection macro */
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xusbps.h
+* @addtogroup usbps_v2_1
+* @{
+* @details
 *
 * This file contains the implementation of the XUsbPs driver. It is the
 * driver for an USB controller in DEVICE or HOST mode.
@@ -1080,3 +1083,4 @@ XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
 #endif

 #endif /* XUSBPS_H */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xusbps_endpoint.h
+* @addtogroup usbps_v2_1
+* @{
 *
 * This is an internal file containung the definitions for endpoints. It is
 * included by the xusbps_endpoint.c which is implementing the endpoint
@@ -510,3 +512,4 @@ extern "C" {
 #endif

 #endif /* XUSBPS_ENDPOINT_H */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xusbps_hw.h
+* @addtogroup usbps_v2_1
+* @{
 *
 * This header file contains identifiers and low-level driver functions (or
 * macros) that can be used to access the device. High-level driver functions
@@ -521,3 +523,4 @@ void XUsbPs_ResetHw(u32 BaseAddress);
 #endif

 #endif /* XUSBPS_L_H */
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xcanps.c
+* @addtogroup canps_v2_0
+* @{
 *
 * Functions in this file are the minimum required functions for the XCanPs
 * driver. See xcanps.h for a detailed description of the driver.
@@ -1153,3 +1155,4 @@ static void StubHandler(void)
 	Xil_AssertVoidAlways();
 }

+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xcanps.h
+* @addtogroup canps_v2_0
+* @{
+* @details
 *
 * The Xilinx CAN driver component.  This component supports the Xilinx
 * CAN Controller.
@@ -559,3 +562,4 @@ XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId);

 #endif /* end of protection macro */

+/** @} */
@@ -22,8 +22,8 @@
 *
 *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
 *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
@@ -33,6 +33,8 @@
 /**
 *
 * @file xcanps_hw.c
+* @addtogroup canps_v2_0
+* @{
 *
 * This file contains the implementation of the canps interface reset sequence
 *
@@ -86,4 +88,5 @@ void XCanPs_ResetHw(u32 BaseAddr)
 {
 	XCanPs_WriteReg(BaseAddr, XCANPS_SRR_OFFSET, \
 			   XCANPS_SRR_SRST_MASK);
-}
+}
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xcanps_hw.h
+* @addtogroup canps_v2_0
+* @{
 *
 * This header file contains the identifiers and basic driver functions (or
 * macros) that can be used to access the device. Other driver functions
@@ -364,3 +366,4 @@ void XCanPs_ResetHw(u32 BaseAddr);

 #endif /* end of protection macro */

+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xcanps_intr.c
+* @addtogroup canps_v2_0
+* @{
 *
 * This file contains functions related to CAN interrupt handling.
 *
@@ -401,3 +403,4 @@ int XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
 	return (XST_SUCCESS);
 }

+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xcanps_selftest.c
+* @addtogroup canps_v2_0
+* @{
 *
 * This file contains a diagnostic self-test function for the XCanPs driver.
 *
@@ -205,3 +207,4 @@ int XCanPs_SelfTest(XCanPs *InstancePtr)
 }


+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xcanps_sinit.c
+* @addtogroup canps_v2_0
+* @{
 *
 * This file contains the implementation of the XCanPs driver's static
 * initialization functionality.
@@ -97,3 +99,4 @@ XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId)

 	return CfgPtr;
 }
+/** @} */
@@ -33,7 +33,11 @@
 /**
 *
 * @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_0
+* @{
+* @details
 *
 * dummy file
 *
 ******************************************************************************/
+/** @} */
@@ -33,6 +33,8 @@
 /**
 *
 * @file xdevcfg.c
+* @addtogroup devcfg_v3_1
+* @{
 *
 * This file contains the implementation of the interface functions for XDcfg
 * driver. Refer to the header file xdevcfg.h for more detailed information.
@@ -930,3 +932,4 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,

 	return XST_SUCCESS;
 }
+/** @} */
@@ -33,6 +33,9 @@
 /**
 *
 * @file xdevcfg.h
+* @addtogroup devcfg_v3_1
+* @{
+* @details
 *
 * The is the main header file for the Device Configuration Interface of the Zynq
 * device. The device configuration interface has three main functionality.
@@ -378,3 +381,4 @@ void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
 #endif

 #endif	/* end of protection macro */
+/** @} */
--- a/Show More
+++ b/Show More