Added Safe interrupt demo (#685)

Add project to be used for safer interrupts
2026-10-02 16:24:45 +08:00 · 2021-09-30 12:06:16 -07:00
parent 0390b0fc9b
commit 4c779335d6
77 changed files with 67427 additions and 0 deletions
@@ -0,0 +1,61 @@
+/*
+ * FreeRTOS V202107.00
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include"queue.h"
+
+/* Interface includes. */
+#include "interrupt_handler_task.h"
+
+/**
+ * @brief Time to block while waiting for a interrupt request on the interrupt queue.
+ */
+#define USER_IRQ_RECEIVE_TIMEOUT ( pdMS_TO_TICKS( 1000 ) )
+
+void vInterruptHandlerTask( void * pvParams )
+{
+    BaseType_t xStatus;
+    UserIrqRequest_t xIrqRequest;
+    QueueHandle_t xInterruptQueueHandle = ( QueueHandle_t ) pvParams;
+
+    for( ;; )
+    {
+        xStatus = xQueueReceive( xInterruptQueueHandle,
+                                 &( xIrqRequest ),
+                                 USER_IRQ_RECEIVE_TIMEOUT );
+        if ( xStatus != pdTRUE )
+        {
+            continue;
+        }
+
+        /* If a valid IRQ request is received, invoke the corresponding handler
+         * function. */
+        xIrqRequest.xHandlerFunction( xIrqRequest.ulData );
+    }
+}
+/*-----------------------------------------------------------*/
@@ -0,0 +1,65 @@
+/*
+ * FreeRTOS V202107.00
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef INTERRUPT_HANDLER_TASK_H_
+#define INTERRUPT_HANDLER_H_
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* The interrupt handler task serves user IRQ requests sent to the interrupt
+ * queue. A user IRQ request comprises of the following 2 things:
+ *
+ * 1. Data.
+ * 2. IRQ handler function.
+ */
+
+/**
+ * @brief Type of the handler function for every user IRQ request.
+ */
+typedef void ( * UserIrqHandlerFunction_t )( uint32_t ulData );
+
+/**
+ * @brief Represents user IRQ requests sent to the interrupt queue.
+ */
+typedef struct UserIrqRequest
+{
+    uint32_t ulData;
+    UserIrqHandlerFunction_t xHandlerFunction;
+} UserIrqRequest_t;
+
+/**
+ * @brief Function that implements the interrupt handler task.
+ *
+ * A FreeRTOS queue, known as interrupt queue, which holds UserIrqRequest_t items,
+ * is passed as the parameter to this task. The interrupt handler task reads the
+ * user IRQ requests from the interrupt queue and invokes the corresponding
+ * handlers.
+ */
+void vInterruptHandlerTask( void * pvParams );
+
+#endif /* INTERRUPT_HANDLER_H_ */
@@ -0,0 +1,125 @@
+/*
+ * FreeRTOS V202107.00
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* BSP includes. */
+#include "board.h"
+
+/* Demo interface include. */
+#include "led_demo.h"
+
+/**
+ * Represents which LEDs are on or off. pdTRUE is on.
+ */
+typedef struct LedState
+{
+    BaseType_t xRed;
+    BaseType_t xGreen;
+    BaseType_t xBlue;
+} LedState_t;
+
+/* The following needs to be placed in the shared memory as it is accessed in
+ * the button pressed IRQ handler which is unprivileged. */
+static LedState_t xLedState __attribute__( ( section( "user_irq_shared_memory" ) ) );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Turn on RGB Led according to the xLedState.
+ */
+static void prvTurnOnRgbLed( void );
+
+/**
+ * @brief Turn off RGB Led.
+ */
+static void prvTurnOffRgbLed( void );
+/*-----------------------------------------------------------*/
+
+static void prvTurnOnRgbLed( void )
+{
+    /* Setting the GPIO pin activates the color in RGB LED. */
+    if( xLedState.xRed == pdTRUE )
+    {
+        GPIO_PortClear( GPIO, BOARD_LED_RED_GPIO_PORT, 1u << BOARD_LED_RED_GPIO_PIN );
+    }
+    if( xLedState.xGreen == pdTRUE )
+    {
+        GPIO_PortClear( GPIO, BOARD_LED_GREEN_GPIO_PORT, 1u << BOARD_LED_GREEN_GPIO_PIN );
+    }
+    if( xLedState.xBlue == pdTRUE )
+    {
+        GPIO_PortClear( GPIO, BOARD_LED_BLUE_GPIO_PORT, 1u << BOARD_LED_BLUE_GPIO_PIN );
+    }
+}
+/*-----------------------------------------------------------*/
+
+static void prvTurnOffRgbLed( void )
+{
+    /* Setting the pins high turns off the LED. */
+    GPIO_PortSet( GPIO, BOARD_LED_RED_GPIO_PORT, 1u << BOARD_LED_RED_GPIO_PIN );
+    GPIO_PortSet( GPIO, BOARD_LED_GREEN_GPIO_PORT, 1u << BOARD_LED_GREEN_GPIO_PIN );
+    GPIO_PortSet( GPIO, BOARD_LED_BLUE_GPIO_PORT, 1u << BOARD_LED_BLUE_GPIO_PIN );
+}
+/*-----------------------------------------------------------*/
+
+void vLedDemoTask( void * pvParams )
+{
+    /* Set the initial LED state. */
+    xLedState.xRed = pdTRUE;
+    xLedState.xGreen = pdTRUE;
+    xLedState.xBlue = pdFALSE;
+
+    /* Silence compiler warnings about unused variables. */
+    ( void ) pvParams;
+
+    for( ;; )
+    {
+        prvTurnOnRgbLed();
+        vTaskDelay( pdMS_TO_TICKS( 1000 ) );
+
+        prvTurnOffRgbLed();
+        vTaskDelay( pdMS_TO_TICKS( 1000 ) );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vButtonPressedIRQHandler( uint32_t ulData )
+{
+    BaseType_t xPreviousRed;
+
+    /* Data is not used. */
+    ( void ) ulData;
+
+    /* Shift to the next color. */
+    xPreviousRed = xLedState.xRed;
+    xLedState.xRed = xLedState.xGreen;
+    xLedState.xGreen = xLedState.xBlue;
+    xLedState.xBlue = xPreviousRed;
+}
+/*-----------------------------------------------------------*/
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS V202107.00
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef LED_DEMO_H_
+#define LED_DEMO_H_
+
+/* Standard includes. */
+#include <stdint.h>
+
+/**
+ * @brief The function that implements the LED demo task.
+ *
+ * It periodically toggles the on board RGB led. The color of the LED changes
+ * whenever the user presses the USER button on the NXP LPC55S69-EVK board.
+ */
+void vLedDemoTask( void * pvParams );
+
+/**
+ * @brief Handler for the button pressed IRQ.
+ *
+ * It changes the color of the LED.
+ *
+ * @param [in] ulData Not used.
+ */
+void vButtonPressedIRQHandler( uint32_t ulData );
+
+#endif /* LED_DEMO_H_ */
@@ -0,0 +1,110 @@
+/*
+ * FreeRTOS V202107.00
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdio.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "board.h"
+#include "fsl_usart.h"
+
+/* Demo interface include. */
+#include "uart_demo.h"
+
+/**
+ * @brief The command menu presented to the user.
+ */
+#define UART_COMMAND_MENU           "\r\nChoose one of the following:\r\n" \
+                                    "1. Get current tick count.\r\n"       \
+                                    "2. Get number of tasks.\r\n"
+#define UART_COMMAND_MENU_LEN       ( sizeof( UART_COMMAND_MENU ) - 1 )
+
+/**
+ * @brief Prompt for the user input.
+ */
+#define UART_PROMPT_STR             "> "
+#define UART_PROMPT_STR_LEN         ( sizeof( UART_PROMPT_STR ) - 1 )
+
+/**
+ * @brief Valid commands entered by the user.
+ */
+#define GET_TICK_COUNT_COMMAND      49 /* ASCII code for char '1'. */
+#define GET_NUM_TASKS_COMMAND       50 /* ASCII code for char '2'. */
+
+/**
+ * @brief Length of the buffer used for the response.
+ */
+#define UART_RESPONSE_BUF_LEN      ( 32 )
+/*-----------------------------------------------------------*/
+
+/* The following needs to be placed in the shared memory as it is accessed in
+ * the UART received IRQ handler which is unprivileged. */
+TaskHandle_t xUartDemoTaskHandle __attribute__( ( section( "user_irq_shared_memory" ) ) );
+/*-----------------------------------------------------------*/
+
+void vUartDemoTask( void * pvParams )
+{
+    /* Silence compiler warnings about unused variables. */
+    ( void ) pvParams;
+
+    for( ;; )
+    {
+        USART_WriteBlocking( USART0, UART_COMMAND_MENU, UART_COMMAND_MENU_LEN );
+        USART_WriteBlocking( USART0, UART_PROMPT_STR, UART_PROMPT_STR_LEN );
+
+        ulTaskNotifyTake( pdFALSE, portMAX_DELAY );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vUartDataReceivedIRQHandler( uint32_t ulData )
+{
+    char response[ UART_RESPONSE_BUF_LEN ];
+
+    if( ulData == GET_TICK_COUNT_COMMAND )
+    {
+        TickType_t xTickCount = xTaskGetTickCount();
+        snprintf( response, sizeof( response ), "%c\r\nTick Count: %u\r\n", ( char ) ulData, xTickCount );
+    }
+    else if( ulData == GET_NUM_TASKS_COMMAND )
+    {
+        UBaseType_t xTaskCount = uxTaskGetNumberOfTasks();
+        snprintf( response, sizeof( response ), "%c\r\nTask Count: %u\r\n", ( char ) ulData, xTaskCount );
+    }
+    else
+    {
+        snprintf( response, sizeof( response ), "\r\nInvalid command: %c.\r\n", ( char ) ulData );
+    }
+
+    /* Print the response and unblock the UART demo task. */
+    USART_WriteBlocking( USART0, response, strlen( response ) );
+    xTaskNotifyGive( xUartDemoTaskHandle );
+}
+/*-----------------------------------------------------------*/
@@ -0,0 +1,52 @@
+/*
+ * FreeRTOS V202107.00
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef UART_DEMO_H_
+#define UART_DEMO_H_
+
+/* Standard includes. */
+#include <stdint.h>
+
+/**
+ * @brief The function that implements the UART demo.
+ *
+ * It prints a command menu on the serial console and then waits for a task
+ * notification. Whenever user enters any input on the serial console to run a
+ * command, the UART received IRQ handler handles it and prints the appropriate
+ * response on the serial console. The IRQ handler then unblocks the UART task
+ * using task notification.
+ */
+void vUartDemoTask( void * pvParams );
+
+/**
+ * @brief Handler for the UART received IRQ.
+ *
+ * @param [in] ulData Data entered by the user.
+ */
+void vUartDataReceivedIRQHandler( uint32_t ulData );
+
+#endif /* UART_DEMO_H_ */
@@ -0,0 +1,173 @@
+/*
+ * FreeRTOS V202107.00
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_TICKLESS_IDLE                 0
+#define configCPU_CLOCK_HZ                      ( SystemCoreClock )
+#define configTICK_RATE_HZ                      ( ( TickType_t ) 200 )
+#define configMAX_PRIORITIES                    5
+#define configMINIMAL_STACK_SIZE                ( ( unsigned short ) 128 )
+#define configMAX_TASK_NAME_LEN                 20
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_TASK_NOTIFICATIONS            1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configUSE_ALTERNATIVE_API               0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE               8
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c). */
+#define configFRTOS_MEMORY_SCHEME               4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+#define configTOTAL_HEAP_SIZE                   ( ( size_t )( 10 * 1024 ) )
+#define configAPPLICATION_ALLOCATED_HEAP        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                     0
+#define configUSE_TICK_HOOK                     0
+#define configCHECK_FOR_STACK_OVERFLOW          0
+#define configUSE_MALLOC_FAILED_HOOK            0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK      0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS           0
+#define configUSE_TRACE_FACILITY                1
+#define configUSE_STATS_FORMATTING_FUNCTIONS    0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS         1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES                   0
+#define configMAX_CO_ROUTINE_PRIORITIES         2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                        1
+#define configTIMER_TASK_PRIORITY               ( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH                10
+#define configTIMER_TASK_STACK_DEPTH            ( configMINIMAL_STACK_SIZE * 2 )
+
+/* Define to trap errors during development. */
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for (;;); }
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet                1
+#define INCLUDE_uxTaskPriorityGet               1
+#define INCLUDE_vTaskDelete                     1
+#define INCLUDE_vTaskSuspend                    1
+#define INCLUDE_vTaskDelayUntil                 1
+#define INCLUDE_vTaskDelay                      1
+#define INCLUDE_xTaskGetSchedulerState          1
+#define INCLUDE_xTaskGetCurrentTaskHandle       1
+#define INCLUDE_uxTaskGetStackHighWaterMark     0
+#define INCLUDE_xTaskGetIdleTaskHandle          0
+#define INCLUDE_eTaskGetState                   0
+#define INCLUDE_xTimerPendFunctionCall          1
+#define INCLUDE_xTaskAbortDelay                 0
+#define INCLUDE_xTaskGetHandle                  0
+#define INCLUDE_xTaskResumeFromISR              1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+    /* Clock manager provides in this variable system core clock frequency */
+    #include <stdint.h>
+    extern uint32_t SystemCoreClock;
+#endif
+
+
+#ifndef configENABLE_FPU
+  #define configENABLE_FPU                        1
+#endif
+#ifndef configENABLE_MPU
+  #define configENABLE_MPU                        1
+#endif
+#ifndef configENABLE_TRUSTZONE
+  #define configENABLE_TRUSTZONE                  0
+#endif
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+  #define configRUN_FREERTOS_SECURE_ONLY          1
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 3 /* 8 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ( ( 1U << ( configPRIO_BITS ) ) - 1 )
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define vPortPendSVHandler PendSV_Handler
+#define vPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.3
+ * @date     24. June 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_common.h"
+#include "fsl_power.h"
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.power"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Empty file since implementation is in header file and power library */
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_i2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
+
+    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+void BOARD_InitDebugConsole_Core1(void)
+{
+    /* attach 12 MHz clock to FLEXCOMM1 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH_CORE1);
+
+    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST_CORE1);
+
+    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ_CORE1;
+
+    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE_CORE1, BOARD_DEBUG_UART_BAUDRATE_CORE1, BOARD_DEBUG_UART_TYPE_CORE1,
+                    uartClkSrcFreq);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
+{
+    i2c_master_config_t i2cConfig = {0};
+
+    I2C_MasterGetDefaultConfig(&i2cConfig);
+    I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = txBuff;
+    masterXfer.dataSize       = txBuffSize;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = rxBuff;
+    masterXfer.dataSize       = rxBuffSize;
+    masterXfer.direction      = kI2C_Read;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+    uint8_t data = (uint8_t)txBuff;
+
+    return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+    return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+                          txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
@@ -0,0 +1,166 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK         96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK       150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL1_150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
@@ -0,0 +1,198 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v10.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 10.0.0
+pin_labels:
+- {pin_num: '1', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A, label: LED_BLUE, identifier: LED_BLUE}
+- {pin_num: '5', pin_signal: PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3, label: LED_RED, identifier: LED_RED}
+- {pin_num: '9', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4, label: LED_GREEN, identifier: LED_GREEN}
+- {pin_num: '10', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12, label: USER_BUTTON, identifier: USER_BUTTON}
+- {pin_num: '94', pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, label: UART_TX, identifier: UART_TX}
+- {pin_num: '92', pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29, label: UART_RX, identifier: UART_RX}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+    direction: INPUT, mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, direction: OUTPUT,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '1', peripheral: GPIO, signal: 'PIO1, 4', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A, direction: OUTPUT, gpio_init_state: 'true'}
+  - {pin_num: '5', peripheral: GPIO, signal: 'PIO1, 6', pin_signal: PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3, direction: OUTPUT, gpio_init_state: 'true'}
+  - {pin_num: '9', peripheral: GPIO, signal: 'PIO1, 7', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4, direction: OUTPUT, gpio_init_state: 'true'}
+  - {pin_num: '10', peripheral: GPIO, signal: 'PIO1, 9', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO1 module */
+    CLOCK_EnableClock(kCLOCK_Gpio1);
+
+    gpio_pin_config_t LED_BLUE_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PIO1_4 (pin 1)  */
+    GPIO_PinInit(BOARD_INITPINS_LED_BLUE_GPIO, BOARD_INITPINS_LED_BLUE_PORT, BOARD_INITPINS_LED_BLUE_PIN, &LED_BLUE_config);
+
+    gpio_pin_config_t LED_RED_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PIO1_6 (pin 5)  */
+    GPIO_PinInit(BOARD_INITPINS_LED_RED_GPIO, BOARD_INITPINS_LED_RED_PORT, BOARD_INITPINS_LED_RED_PIN, &LED_RED_config);
+
+    gpio_pin_config_t LED_GREEN_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PIO1_7 (pin 9)  */
+    GPIO_PinInit(BOARD_INITPINS_LED_GREEN_GPIO, BOARD_INITPINS_LED_GREEN_PORT, BOARD_INITPINS_LED_GREEN_PIN, &LED_GREEN_config);
+
+    const uint32_t UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+                              IOCON_PIO_FUNC1 |
+                              /* No addition pin function */
+                              IOCON_PIO_MODE_INACT |
+                              /* Standard mode, output slew rate control is enabled */
+                              IOCON_PIO_SLEW_STANDARD |
+                              /* Input function is not inverted */
+                              IOCON_PIO_INV_DI |
+                              /* Enables digital function */
+                              IOCON_PIO_DIGITAL_EN |
+                              /* Open drain is disabled */
+                              IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITPINS_UART_RX_PORT, BOARD_INITPINS_UART_RX_PIN, UART_RX);
+
+    const uint32_t UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+                              IOCON_PIO_FUNC1 |
+                              /* No addition pin function */
+                              IOCON_PIO_MODE_INACT |
+                              /* Standard mode, output slew rate control is enabled */
+                              IOCON_PIO_SLEW_STANDARD |
+                              /* Input function is not inverted */
+                              IOCON_PIO_INV_DI |
+                              /* Enables digital function */
+                              IOCON_PIO_DIGITAL_EN |
+                              /* Open drain is disabled */
+                              IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITPINS_UART_TX_PORT, BOARD_INITPINS_UART_TX_PIN, UART_TX);
+
+    IOCON->PIO[1][4] = ((IOCON->PIO[1][4] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT14 (pin 1) is configured as PIO1_4. */
+                        | IOCON_PIO_FUNC(PIO1_4_FUNC_ALT0)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO1_4_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][6] = ((IOCON->PIO[1][6] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT16 (pin 5) is configured as PIO1_6. */
+                        | IOCON_PIO_FUNC(PIO1_6_FUNC_ALT0)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO1_6_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][7] = ((IOCON->PIO[1][7] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT17 (pin 9) is configured as PIO1_7. */
+                        | IOCON_PIO_FUNC(PIO1_7_FUNC_ALT0)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO1_7_DIGIMODE_DIGITAL));
+
+    if (Chip_GetVersion()==1)
+    {
+        IOCON->PIO[1][9] = ((IOCON->PIO[1][9] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT19 (pin 10) is configured as PIO1_9. */
+                        | IOCON_PIO_FUNC(PIO1_9_FUNC_ALT0)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO1_9_DIGIMODE_DIGITAL));
+    }
+    else
+    {
+        IOCON->PIO[1][9] = ((IOCON->PIO[1][9] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT19 (pin 10) is configured as PIO1_9. */
+                        | IOCON_PIO_FUNC(PIO1_9_FUNC_ALT0)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO1_9_DIGIMODE_DIGITAL));
+    }
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
@@ -0,0 +1,118 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+#define PIO1_4_DIGIMODE_DIGITAL 0x01u /*!<@brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_4_FUNC_ALT0 0x00u        /*!<@brief Selects pin function.: Alternative connection 0. */
+#define PIO1_6_DIGIMODE_DIGITAL 0x01u /*!<@brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_6_FUNC_ALT0 0x00u        /*!<@brief Selects pin function.: Alternative connection 0. */
+#define PIO1_7_DIGIMODE_DIGITAL 0x01u /*!<@brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_7_FUNC_ALT0 0x00u        /*!<@brief Selects pin function.: Alternative connection 0. */
+#define PIO1_9_DIGIMODE_DIGITAL 0x01u /*!<@brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_9_FUNC_ALT0 0x00u        /*!<@brief Selects pin function.: Alternative connection 0. */
+
+/*! @name PIO0_29 (number 92), UART_RX
+  @{ */
+#define BOARD_INITPINS_UART_RX_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITPINS_UART_RX_PIN 29U                   /*!<@brief PORT pin number */
+#define BOARD_INITPINS_UART_RX_PIN_MASK (1U << 29U)      /*!<@brief PORT pin mask */
+                                                         /* @} */
+
+/*! @name PIO0_30 (number 94), UART_TX
+  @{ */
+#define BOARD_INITPINS_UART_TX_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITPINS_UART_TX_PIN 30U                   /*!<@brief PORT pin number */
+#define BOARD_INITPINS_UART_TX_PIN_MASK (1U << 30U)      /*!<@brief PORT pin mask */
+                                                         /* @} */
+
+/*! @name PIO1_4 (number 1), LED_BLUE
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_LED_BLUE_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITPINS_LED_BLUE_GPIO_PIN_MASK (1U << 4U) /*!<@brief GPIO pin mask */
+#define BOARD_INITPINS_LED_BLUE_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITPINS_LED_BLUE_PIN 4U                   /*!<@brief PORT pin number */
+#define BOARD_INITPINS_LED_BLUE_PIN_MASK (1U << 4U)      /*!<@brief PORT pin mask */
+                                                         /* @} */
+
+/*! @name PIO1_6 (number 5), LED_RED
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_LED_RED_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITPINS_LED_RED_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */
+#define BOARD_INITPINS_LED_RED_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITPINS_LED_RED_PIN 6U                   /*!<@brief PORT pin number */
+#define BOARD_INITPINS_LED_RED_PIN_MASK (1U << 6U)      /*!<@brief PORT pin mask */
+                                                        /* @} */
+
+/*! @name PIO1_7 (number 9), LED_GREEN
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_LED_GREEN_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITPINS_LED_GREEN_GPIO_PIN_MASK (1U << 7U) /*!<@brief GPIO pin mask */
+#define BOARD_INITPINS_LED_GREEN_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITPINS_LED_GREEN_PIN 7U                   /*!<@brief PORT pin number */
+#define BOARD_INITPINS_LED_GREEN_PIN_MASK (1U << 7U)      /*!<@brief PORT pin mask */
+                                                          /* @} */
+
+/*! @name PIO1_9 (number 10), USER_BUTTON
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 9U) /*!<@brief GPIO pin mask */
+#define BOARD_INITPINS_USER_BUTTON_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_PIN 9U                   /*!<@brief PORT pin number */
+#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 9U)      /*!<@brief PORT pin mask */
+                                                            /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2019-2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_PORT_INTERNAL_H__
+#define __SERIAL_PORT_INTERNAL_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig);
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartWriteBlocking(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif /* SERIAL_MANAGER_NON_BLOCKING_MODE */
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE) && (SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE > 0U))
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+#else
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
+                                                     serial_manager_callback_t callback,
+                                                     void *callbackParam);
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
+                                                     serial_manager_callback_t callback,
+                                                     void *callbackParam);
+void Serial_UartIsrFunction(serial_handle_t serialHandle);
+#endif
+serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle);
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
+serial_manager_status_t Serial_RpmsgInit(serial_handle_t serialHandle, void *serialConfig);
+serial_manager_status_t Serial_RpmsgDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_RpmsgWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_RpmsgWriteBlocking(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_RpmsgRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_RpmsgCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_RpmsgInstallTxCallback(serial_handle_t serialHandle,
+                                                      serial_manager_callback_t callback,
+                                                      void *callbackParam);
+serial_manager_status_t Serial_RpmsgInstallRxCallback(serial_handle_t serialHandle,
+                                                      serial_manager_callback_t callback,
+                                                      void *callbackParam);
+#endif
+serial_manager_status_t Serial_RpmsgEnterLowpower(serial_handle_t serialHandle);
+serial_manager_status_t Serial_RpmsgExitLowpower(serial_handle_t serialHandle);
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,
+                                                       serial_manager_callback_t callback,
+                                                       void *callbackParam);
+serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,
+                                                       serial_manager_callback_t callback,
+                                                       void *callbackParam);
+void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,
+                                                    serial_manager_callback_t callback,
+                                                    void *callbackParam);
+serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,
+                                                    serial_manager_callback_t callback,
+                                                    void *callbackParam);
+void Serial_SwoIsrFunction(serial_handle_t serialHandle);
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+serial_manager_status_t Serial_PortVirtualInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_PortVirtualDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_PortVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_PortVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_PortVirtualCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_PortVirtualInstallTxCallback(serial_handle_t serialHandle,
+                                                            serial_manager_callback_t callback,
+                                                            void *callbackParam);
+serial_manager_status_t Serial_PortVirtualInstallRxCallback(serial_handle_t serialHandle,
+                                                            serial_manager_callback_t callback,
+                                                            void *callbackParam);
+void Serial_PortVirtualIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __SERIAL_PORT_INTERNAL_H__ */
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_PORT_UART_H__
+#define __SERIAL_PORT_UART_H__
+
+#include "fsl_adapter_uart.h"
+
+/*!
+ * @addtogroup serial_port_uart
+ * @ingroup serialmanager
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief serial port uart handle size*/
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_PORT_UART_HANDLE_SIZE       (76U + HAL_UART_HANDLE_SIZE)
+#define SERIAL_PORT_UART_BLOCK_HANDLE_SIZE (HAL_UART_BLOCK_HANDLE_SIZE)
+#else
+#define SERIAL_PORT_UART_HANDLE_SIZE (HAL_UART_HANDLE_SIZE)
+#endif
+
+#ifndef SERIAL_USE_CONFIGURE_STRUCTURE
+#define SERIAL_USE_CONFIGURE_STRUCTURE (0U) /*!< Enable or disable the confgure structure pointer */
+#endif
+
+/*! @brief serial port uart parity mode*/
+typedef enum _serial_port_uart_parity_mode
+{
+    kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */
+    kSerialManager_UartParityEven     = 0x2U, /*!< Parity even enabled */
+    kSerialManager_UartParityOdd      = 0x3U, /*!< Parity odd enabled */
+} serial_port_uart_parity_mode_t;
+
+/*! @brief serial port uart stop bit count*/
+typedef enum _serial_port_uart_stop_bit_count
+{
+    kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */
+    kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */
+} serial_port_uart_stop_bit_count_t;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/*! @brief serial port uart block mode*/
+typedef enum _serial_port_uart_block_mode
+{
+    kSerialManager_UartNonBlockMode = 0x0U, /*!< Uart NonBlock Mode */
+    kSerialManager_UartBlockMode    = 0x1U, /*!< Uart Block Mode */
+} serial_port_uart_block_mode_t;
+#endif /* SERIAL_MANAGER_NON_BLOCKING_MODE */
+
+typedef struct _serial_port_uart_config
+{
+    uint32_t clockRate;                             /*!< clock rate  */
+    uint32_t baudRate;                              /*!< baud rate  */
+    serial_port_uart_parity_mode_t parityMode;      /*!< Parity mode, disabled (default), even, odd */
+    serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+
+    uint8_t enableRx;    /*!< Enable RX */
+    uint8_t enableTx;    /*!< Enable TX */
+    uint8_t enableRxRTS; /*!< Enable RX RTS */
+    uint8_t enableTxCTS; /*!< Enable TX CTS */
+    uint8_t instance;    /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
+                              please refer to the SOC corresponding RM. */
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serial_port_uart_block_mode_t mode; /*!< serial port uart block mode */
+#endif                                  /* SERIAL_MANAGER_NON_BLOCKING_MODE */
+#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
+    uint8_t txFifoWatermark;
+    uint8_t rxFifoWatermark;
+#endif
+} serial_port_uart_config_t;
+/*! @} */
+#endif /* __SERIAL_PORT_UART_H__ */
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || \
+     defined(CPU_LPC55S69JEV98_cm33_core0))
+
+#define LPC55S69_cm33_core0_SERIES
+
+/* CMSIS-style register definitions */
+#include "LPC55S69_cm33_core0.h"
+/* CPU specific feature definitions */
+#include "LPC55S69_cm33_core0_features.h"
+
+#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || \
+       defined(CPU_LPC55S69JEV98_cm33_core1))
+
+#define LPC55S69_cm33_core1_SERIES
+
+/* CMSIS-style register definitions */
+#include "LPC55S69_cm33_core1.h"
+/* CPU specific feature definitions */
+#include "LPC55S69_cm33_core1_features.h"
+
+#else
+#error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
@@ -0,0 +1,113 @@
+/*
+** ###################################################################
+**     Processors:          LPC55S69JBD100_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b200418
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-08-22)
+**         Initial version based on v0.2UM
+**     - rev. 1.1 (2019-05-16)
+**         Initial A1 version based on v1.3UM
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC55S69_cm33_core0
+ * @version 1.1
+ * @date 2019-05-16
+ * @brief Device specific configuration file for LPC55S69_cm33_core0 (header
+ *        file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_LPC55S69_cm33_core0_H_
+#define _SYSTEM_LPC55S69_cm33_core0_H_           /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK           12000000u           /* Default System clock value */
+#define CLK_RTC_32K_CLK                   32768u           /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ                  12000000u           /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_48MHZ                  48000000u           /* FRO 48 MHz (fro_48m) */
+#define CLK_FRO_96MHZ                  96000000u           /* FRO 96 MHz (fro_96m) */
+#define CLK_CLK_IN                     16000000u           /* Default CLK_IN pin clock */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_LPC55S69_cm33_core0_H_ */
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+#define SDK_MEM_MAGIC_NUMBER 12345U
+
+typedef struct _mem_align_control_block
+{
+    uint16_t identifier; /*!< Identifier for the memory control block. */
+    uint16_t offset;     /*!< offset from aligned address to real address */
+} mem_align_cb_t;
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common"
+#endif
+
+void *SDK_Malloc(size_t size, size_t alignbytes)
+{
+    mem_align_cb_t *p_cb = NULL;
+    uint32_t alignedsize;
+
+    /* Check overflow. */
+    alignedsize = SDK_SIZEALIGN(size, alignbytes);
+    if (alignedsize < size)
+    {
+        return NULL;
+    }
+
+    if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
+    {
+        return NULL;
+    }
+
+    alignedsize += alignbytes + sizeof(mem_align_cb_t);
+
+    union
+    {
+        void *pointer_value;
+        uint32_t unsigned_value;
+    } p_align_addr, p_addr;
+
+    p_addr.pointer_value = malloc(alignedsize);
+
+    if (p_addr.pointer_value == NULL)
+    {
+        return NULL;
+    }
+
+    p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
+
+    p_cb             = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
+    p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
+    p_cb->offset     = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
+
+    return p_align_addr.pointer_value;
+}
+
+void SDK_Free(void *ptr)
+{
+    union
+    {
+        void *pointer_value;
+        uint32_t unsigned_value;
+    } p_free;
+    p_free.pointer_value = ptr;
+    mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
+
+    if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
+    {
+        return;
+    }
+
+    p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
+
+    free(p_free.pointer_value);
+}
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_FLEXCOMM_H_
+#define _FSL_FLEXCOMM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexcomm_driver
+ * @{
+ */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexCOMM driver version 2.0.2. */
+#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*! @brief FLEXCOMM peripheral modes. */
+typedef enum
+{
+    FLEXCOMM_PERIPH_NONE,   /*!< No peripheral */
+    FLEXCOMM_PERIPH_USART,  /*!< USART peripheral */
+    FLEXCOMM_PERIPH_SPI,    /*!< SPI Peripheral */
+    FLEXCOMM_PERIPH_I2C,    /*!< I2C Peripheral */
+    FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
+    FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
+} FLEXCOMM_PERIPH_T;
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
+
+/*! @brief Array with IRQ number for each FLEXCOMM module. */
+extern IRQn_Type const kFlexcommIrqs[];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base);
+
+/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
+
+/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_FLEXCOMM_H_*/
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_inputmux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.inputmux"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief	Initialize INPUTMUX peripheral.
+
+ * This function enables the INPUTMUX clock.
+ *
+ * param base Base address of the INPUTMUX peripheral.
+ *
+ * retval None.
+ */
+void INPUTMUX_Init(INPUTMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE
+    CLOCK_EnableClock(kCLOCK_Sct);
+    CLOCK_EnableClock(kCLOCK_Dma);
+#else
+    CLOCK_EnableClock(kCLOCK_InputMux);
+#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Attaches a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * param base Base address of the INPUTMUX peripheral.
+ * param index Destination peripheral to attach the signal to.
+ * param connection Selects connection.
+ *
+ * retval None.
+ */
+void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection)
+{
+    uint32_t pmux_id;
+    uint32_t output_id;
+
+    /* extract pmux to be used */
+    pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT;
+    /*  extract function number */
+    output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U);
+    /* programm signal */
+    *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id;
+}
+
+#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA)
+/*!
+ * brief Enable/disable a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * param base Base address of the INPUTMUX peripheral.
+ * param signal Enable signal register id and bit offset.
+ * param enable Selects enable or disable.
+ *
+ * retval None.
+ */
+void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable)
+{
+    uint32_t ena_id;
+    uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U;
+    uint32_t bit_offset;
+
+#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX
+    uint32_t chmux_offset;
+    uint32_t chmux_value;
+
+    /* Only enable need to update channel mux */
+    if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U))
+    {
+        chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL);
+        chmux_value  = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL);
+        *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value;
+    }
+    ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U;
+#endif
+    /* extract enable register to be used */
+    ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask;
+    /* extract enable bit offset */
+    bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U);
+    /* set signal */
+    if (enable)
+    {
+        *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset);
+    }
+    else
+    {
+        *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset);
+    }
+}
+#endif
+
+/*!
+ * brief	Deinitialize INPUTMUX peripheral.
+
+ * This function disables the INPUTMUX clock.
+ *
+ * param base Base address of the INPUTMUX peripheral.
+ *
+ * retval None.
+ */
+void INPUTMUX_Deinit(INPUTMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE
+    CLOCK_DisableClock(kCLOCK_Sct);
+    CLOCK_DisableClock(kCLOCK_Dma);
+#else
+    CLOCK_DisableClock(kCLOCK_InputMux);
+#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_INPUTMUX_H_
+#define _FSL_INPUTMUX_H_
+
+#include "fsl_inputmux_connections.h"
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup inputmux_driver
+ * @{
+ */
+
+/*! @file */
+/*! @file fsl_inputmux_connections.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Group interrupt driver version for SDK */
+#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief	Initialize INPUTMUX peripheral.
+
+ * This function enables the INPUTMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ *
+ * @retval None.
+ */
+void INPUTMUX_Init(INPUTMUX_Type *base);
+
+/*!
+ * @brief Attaches a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ * @param index Destination peripheral to attach the signal to.
+ * @param connection Selects connection.
+ *
+ * @retval None.
+ */
+void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection);
+
+#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA)
+/*!
+ * @brief Enable/disable a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ * @param signal Enable signal register id and bit offset.
+ * @param enable Selects enable or disable.
+ *
+ * @retval None.
+ */
+void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable);
+#endif
+
+/*!
+ * @brief	Deinitialize INPUTMUX peripheral.
+
+ * This function disables the INPUTMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ *
+ * @retval None.
+ */
+void INPUTMUX_Deinit(INPUTMUX_Type *base);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_INPUTMUX_H_ */
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_reset.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.reset"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*!
+ * brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos   = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask  = 1UL << bitPos;
+
+    assert(bitPos < 32u);
+
+    /* reset register is in SYSCON */
+    /* set bit */
+    SYSCON->PRESETCTRLSET[regIndex] = bitMask;
+    /* wait until it reads 0b1 */
+    while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask))
+    {
+    }
+}
+
+/*!
+ * brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos   = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask  = 1UL << bitPos;
+
+    assert(bitPos < 32u);
+
+    /* reset register is in SYSCON */
+
+    /* clear bit */
+    SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
+    /* wait until it reads 0b0 */
+    while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask))
+    {
+    }
+}
+
+/*!
+ * brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral)
+{
+    RESET_SetPeripheralReset(peripheral);
+    RESET_ClearPeripheralReset(peripheral);
+}
+
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* freertos_tasks_c_additions.h Rev. 1.3 */
+#ifndef FREERTOS_TASKS_C_ADDITIONS_H
+#define FREERTOS_TASKS_C_ADDITIONS_H
+
+#include <stdint.h>
+
+#if (configUSE_TRACE_FACILITY == 0)
+#error "configUSE_TRACE_FACILITY must be enabled"
+#endif
+
+#define FREERTOS_DEBUG_CONFIG_MAJOR_VERSION 1
+#define FREERTOS_DEBUG_CONFIG_MINOR_VERSION 3
+
+/* NOTE!!
+ * Default to a FreeRTOS version which didn't include these macros. FreeRTOS
+ * v7.5.3 is used here.
+ */
+#ifndef tskKERNEL_VERSION_BUILD
+#define tskKERNEL_VERSION_BUILD 3
+#endif
+#ifndef tskKERNEL_VERSION_MINOR
+#define tskKERNEL_VERSION_MINOR 5
+#endif
+#ifndef tskKERNEL_VERSION_MAJOR
+#define tskKERNEL_VERSION_MAJOR 7
+#endif
+
+/* NOTE!!
+ * The configFRTOS_MEMORY_SCHEME macro describes the heap scheme using a value
+ * 1 - 5 which corresponds to the following schemes:
+ *
+ * heap_1 - the very simplest, does not permit memory to be freed
+ * heap_2 - permits memory to be freed, but not does coalescence adjacent free
+ *          blocks.
+ * heap_3 - simply wraps the standard malloc() and free() for thread safety
+ * heap_4 - coalesces adjacent free blocks to avoid fragmentation. Includes
+ *          absolute address placement option
+ * heap_5 - as per heap_4, with the ability to span the heap across
+ *          multiple nonOadjacent memory areas
+ */
+#ifndef configFRTOS_MEMORY_SCHEME
+#define configFRTOS_MEMORY_SCHEME 3 /* thread safe malloc */
+#endif
+
+#if ((configFRTOS_MEMORY_SCHEME > 5) || (configFRTOS_MEMORY_SCHEME < 1))
+#error "Invalid configFRTOS_MEMORY_SCHEME setting!"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const uint8_t FreeRTOSDebugConfig[];
+
+/* NOTES!!
+ * IAR documentation is confusing. It suggests the data must be statically
+ * linked, and the #pragma placed immediately before the symbol definition.
+ * The IAR supplied examples violate both "rules", so this is a best guess.
+ */
+
+#if (tskKERNEL_VERSION_MAJOR >= 10) && (tskKERNEL_VERSION_MINOR >= 2)
+#if defined(__GNUC__)
+char *const portArch_Name __attribute__((section(".rodata"))) = portARCH_NAME;
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+char *const portArch_Name __attribute__((used)) = portARCH_NAME;
+#elif defined(__IAR_SYSTEMS_ICC__)
+char *const portArch_Name = portARCH_NAME;
+#pragma required=portArch_Name
+#endif
+#else
+char *const portArch_Name = NULL;
+#endif	// tskKERNEL_VERSION_MAJOR
+
+#if defined(__GNUC__)
+const uint8_t FreeRTOSDebugConfig[] __attribute__((section(".rodata"))) =
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+const uint8_t FreeRTOSDebugConfig[] __attribute__((used)) =
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma required=FreeRTOSDebugConfig
+const uint8_t FreeRTOSDebugConfig[] =
+#endif
+{
+    FREERTOS_DEBUG_CONFIG_MAJOR_VERSION,
+    FREERTOS_DEBUG_CONFIG_MINOR_VERSION,
+    tskKERNEL_VERSION_MAJOR,
+    tskKERNEL_VERSION_MINOR,
+    tskKERNEL_VERSION_BUILD,
+    configFRTOS_MEMORY_SCHEME,
+    offsetof(struct tskTaskControlBlock, pxTopOfStack),
+#if (tskKERNEL_VERSION_MAJOR > 8)
+    offsetof(struct tskTaskControlBlock, xStateListItem),
+#else
+    offsetof(struct tskTaskControlBlock, xGenericListItem),
+#endif
+    offsetof(struct tskTaskControlBlock, xEventListItem),
+    offsetof(struct tskTaskControlBlock, pxStack),
+    offsetof(struct tskTaskControlBlock, pcTaskName),
+    offsetof(struct tskTaskControlBlock, uxTCBNumber),
+    offsetof(struct tskTaskControlBlock, uxTaskNumber),
+    configMAX_TASK_NAME_LEN,
+    configMAX_PRIORITIES,
+    configENABLE_MPU,
+    configENABLE_FPU,
+    configENABLE_TRUSTZONE,
+	configRUN_FREERTOS_SECURE_ONLY,
+	0, 			// 32-bit align
+	0, 0, 0, 0	// padding
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // FREERTOS_TASKS_C_ADDITIONS_H
@@ -0,0 +1,98 @@
+// ****************************************************************************
+// semihost_hardfault.c
+//                - Provides hard fault handler to allow semihosting code not
+//                  to hang application when debugger not connected.
+//
+// ****************************************************************************
+// Copyright 2017-2021 NXP
+// All rights reserved.
+//
+// NXP Confidential. This software is owned or controlled by NXP and may only be
+// used strictly in accordance with the applicable license terms.
+//
+// By expressly accepting such terms or by downloading, installing, activating
+// and/or otherwise using the software, you are agreeing that you have read, and
+// that you agree to comply with and are bound by, such license terms.
+// 
+// If you do not agree to be bound by the applicable license terms, then you may not
+// retain, install, activate or otherwise use the software.
+// ****************************************************************************
+//
+//                       ===== DESCRIPTION =====
+//
+// One of the issues with applications that make use of semihosting operations
+// (such as printf calls) is that the code will not execute correctly when the
+// debugger is not connected. Generally this will show up with the application
+// appearing to just hang. This may include the application running from reset
+// or powering up the board (with the application already in FLASH), and also
+// as the application failing to continue to execute after a debug session is
+// terminated.
+//
+// The problem here is that the "bottom layer" of the semihosted variants of
+// the C library, semihosting is implemented by a "BKPT 0xAB" instruction.
+// When the debug tools are not connected, this instruction triggers a hard
+// fault - and the default hard fault handler within an application will
+// typically just contains an infinite loop - causing the application to
+// appear to have hang when no debugger is connected.
+//
+// The below code provides an example hard fault handler which instead looks
+// to see what the instruction that caused the hard fault was - and if it
+// was a "BKPT 0xAB", then it instead returns back to the user application.
+//
+// In most cases this will allow applications containing semihosting
+// operations to execute (to some degree) when the debugger is not connected.
+//
+// == NOTE ==
+//
+// Correct execution of the application containing semihosted operations
+// which are vectored onto this hard fault handler cannot be guaranteed. This
+// is because the handler may not return data or return codes that the higher
+// level C library code or application code expects. This hard fault handler
+// is meant as a development aid, and it is not recommended to leave
+// semihosted code in a production build of your application!
+//
+// ****************************************************************************
+
+// Allow handler to be removed by setting a define (via command line)
+#if !defined (__SEMIHOST_HARDFAULT_DISABLE)
+
+__attribute__((naked))
+void HardFault_Handler(void){
+    __asm(  ".syntax unified\n"
+        // Check which stack is in use
+            "MOVS   R0, #4  \n"
+            "MOV    R1, LR  \n"
+            "TST    R0, R1  \n"
+            "BEQ    _MSP    \n"
+            "MRS    R0, PSP \n"
+            "B  _process      \n"
+            "_MSP:  \n"
+            "MRS    R0, MSP \n"
+        // Load the instruction that triggered hard fault
+        "_process:     \n"
+            "LDR    R1,[R0,#24] \n"
+            "LDRH    R2,[r1] \n"
+        // Semihosting instruction is "BKPT 0xAB" (0xBEAB)
+            "LDR    R3,=0xBEAB \n"
+            "CMP     R2,R3 \n"
+            "BEQ    _semihost_return \n"
+        // Wasn't semihosting instruction so enter infinite loop
+            "B . \n"
+        // Was semihosting instruction, so adjust location to
+        // return to by 1 instruction (2 bytes), then exit function
+        "_semihost_return: \n"
+            "ADDS    R1,#2 \n"
+            "STR    R1,[R0,#24] \n"
+    	// Set a return value from semihosting operation.
+    	// 32 is slightly arbitrary, but appears to allow most
+    	// C Library IO functions sitting on top of semihosting to
+    	// continue to operate to some degree
+    		    "MOVS   R1,#32 \n"
+    		    "STR R1,[ R0,#0 ] \n" // R0 is at location 0 on stack
+    	// Return from hard fault handler to application
+            "BX LR \n"
+        ".syntax divided\n") ;
+}
+
+#endif
+
@@ -0,0 +1,56 @@
+//*****************************************************************************
+// boot_multicore_slave.c
+//
+// Provides simple functions to boot slave core in LPC55xx multicore system
+//
+// Version : 181106
+//
+//*****************************************************************************
+//
+// Copyright 2016-2019 NXP
+// All rights reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+
+#if defined(__MULTICORE_MASTER)
+
+#include <stdint.h>
+
+//#define SYSCON_BASE       ((uint32_t) 0x40000000)
+#define SYSCON_BASE ((uint32_t)0x50000000)
+
+#define CPBOOT (((volatile uint32_t *)(SYSCON_BASE + 0x804)))
+#define CPUCTRL (((volatile uint32_t *)(SYSCON_BASE + 0x800)))
+#define CPUCFG (((volatile uint32_t *)(SYSCON_BASE + 0xFD4)))
+
+#define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16))
+#define CORE1_CLK_ENA (1 << 3)
+#define CORE1_RESET_ENA (1 << 5)
+#define CORE1_ENABLE (1 << 2)
+
+extern uint8_t __core_m33slave_START__;
+
+void boot_multicore_slave(void)
+{
+    volatile uint32_t *u32REG, u32Val;
+
+    unsigned int *slavevectortable_ptr = (unsigned int *)&__core_m33slave_START__;
+
+    // Enable CPU1 in SYSCON->CPUCFG
+    *CPUCFG |= CORE1_ENABLE;
+
+    // Set CPU1 boot address in SYSCON->CPBoot
+    *CPBOOT = (uint32_t)slavevectortable_ptr;
+
+    // Read SYSCON->CPUCTRL and set key value in bits 31:16
+    u32REG = (uint32_t *)CPUCTRL;
+    u32Val = *u32REG | CPUCTRL_KEY;
+
+    // Enable slave clock and reset in SYSCON->CPUCTRL
+    *u32REG = u32Val | CORE1_CLK_ENA | CORE1_RESET_ENA;
+
+    // Clear slave reset in SYSCON->CPUCTRL
+    *u32REG = (u32Val | CORE1_CLK_ENA) & (~CORE1_RESET_ENA);
+}
+#endif // defined (__MULTICORE_MASTER)
@@ -0,0 +1,26 @@
+//*****************************************************************************
+// boot_multicore_slave.h
+//
+// Header for functions used for booting of slave core in multicore system
+//*****************************************************************************
+//
+// Copyright 2016-2019 NXP
+// All rights reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+
+#ifndef BOOT_MULTICORE_SLAVE_H_
+#define BOOT_MULTICORE_SLAVE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void boot_multicore_slave(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOOT_MULTICORE_SLAVE_H_ */
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+#else
+    (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+#endif
+
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#elif (defined(__GNUC__))
+#if defined(__REDLIB__)
+void __assertion_failed(char *failedExpr)
+{
+    (void)PRINTF("ASSERT ERROR \" %s \n", failedExpr);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#else
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line,
+                 func);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#endif /* defined(__REDLIB__) */
+#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */
+#endif /* NDEBUG */
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2017 - 2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
+#define _FSL_DEBUG_CONSOLE_CONF_H_
+
+#include "fsl_common.h"
+
+/****************Debug console configuration********************/
+
+/*! @brief If Non-blocking mode is needed, please define it at project setting,
+ * otherwise blocking mode is the default transfer mode.
+ * Warning: If you want to use non-blocking transfer,please make sure the corresponding
+ * IO interrupt is enable, otherwise there is no output.
+ * And non-blocking is combine with buffer, no matter bare-metal or rtos.
+ * Below shows how to configure in your project if you want to use non-blocking mode.
+ * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols".
+ * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define".
+ * For ARMGCC, open CmakeLists.txt and add the following lines,
+ * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target.
+ * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target.
+ * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C
+ * Complier->Preprocessor".
+ *
+ */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
+ * when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed , because the log will not be
+ * buffered if the buffer is full, and the print will return immediately with -1.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
+#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
+#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
+
+/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
+#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U)
+#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
+
+/*!@ brief Whether enable the reliable TX function
+ * If the macro is zero, the reliable TX function of the debug console is disabled.
+ * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full.
+ */
+#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE
+#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+
+#else
+#define DEBUG_CONSOLE_TRANSFER_BLOCKING
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*!@ brief Whether enable the RX function
+ * If the macro is zero, the receive function of the debug console is disabled.
+ */
+#ifndef DEBUG_CONSOLE_RX_ENABLE
+#define DEBUG_CONSOLE_RX_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_RX_ENABLE */
+
+/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
+ * length can not bigger than this value.
+ * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
+ * the buffer is too big and current task stack size not big enough.
+ */
+#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
+#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
+
+/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
+ * length can not bigger than this value.
+ * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
+ */
+#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
+#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
+
+/*! @brief Debug console synchronization
+ * User should not change these macro for synchronization mode, but add the
+ * corresponding synchronization mechanism per different software environment.
+ * Such as, if another RTOS is used,
+ * add:
+ *  \#define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
+ * in this configuration file and implement the synchronization in fsl.log.c.
+ */
+/*! @brief synchronization for baremetal software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
+/*! @brief synchronization for freertos software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
+
+/*! @brief RTOS synchronization mechanism disable
+ * If not defined, default is enable, to avoid multitask log print mess.
+ * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
+ * If synchronization is disabled, log maybe messed on terminal.
+ */
+#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#ifdef SDK_OS_FREE_RTOS
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* SDK_OS_FREE_RTOS */
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
+
+/*! @brief echo function support
+ * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
+ * at your project setting.
+ */
+#ifndef DEBUG_CONSOLE_ENABLE_ECHO
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
+#else
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
+#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
+
+/*********************************************************************/
+
+/***************Debug console other configuration*********************/
+/*! @brief Definition to printf the float number. */
+#ifndef PRINTF_FLOAT_ENABLE
+#define PRINTF_FLOAT_ENABLE 0U
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*! @brief Definition to scanf the float number. */
+#ifndef SCANF_FLOAT_ENABLE
+#define SCANF_FLOAT_ENABLE 0U
+#endif /* SCANF_FLOAT_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for printf. */
+#ifndef PRINTF_ADVANCED_ENABLE
+#define PRINTF_ADVANCED_ENABLE 0U
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for scanf. */
+#ifndef SCANF_ADVANCED_ENABLE
+#define SCANF_ADVANCED_ENABLE 0U
+#endif /* SCANF_ADVANCED_ENABLE */
+
+/*! @brief Definition to select virtual com(USB CDC) as the debug console. */
+#ifndef BOARD_USE_VIRTUALCOM
+#define BOARD_USE_VIRTUALCOM 0U
+#endif
+/*******************************************************************/
+
+#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_STR_H
+#define _FSL_STR_H
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief A function pointer which is used when format printf log.
+ */
+typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);
+
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * @param[in] fmt   Format string for printf.
+ * @param[in] ap  Arguments to printf.
+ * @param[in] buf  pointer to the buffer
+ * @param cb print callbck function pointer
+ *
+ * @return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);
+
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format   Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_STR_H */
@@ -0,0 +1,121 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>FreeRTOSDemo</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>com.nxp.mcuxpresso.core.datamodels.sdkNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Application</name>
+			<type>2</type>
+			<locationURI>DEMO_ROOT/Application</locationURI>
+		</link>
+		<link>
+			<name>Config</name>
+			<type>2</type>
+			<locationURI>DEMO_ROOT/Config</locationURI>
+		</link>
+		<link>
+			<name>FreeRTOS</name>
+			<type>2</type>
+			<locationURI>FREERTOS_ROOT/Source</locationURI>
+		</link>
+		<link>
+			<name>NXP_Code</name>
+			<type>2</type>
+			<locationURI>DEMO_ROOT/NXP_Code</locationURI>
+		</link>
+	</linkedResources>
+	<filteredResources>
+		<filter>
+			<id>1631686154794</id>
+			<name>FreeRTOS</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1631688399693</id>
+			<name>FreeRTOS/portable</name>
+			<type>9</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-GCC</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1631688399727</id>
+			<name>FreeRTOS/portable</name>
+			<type>9</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-MemMang</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1631688399738</id>
+			<name>FreeRTOS/portable</name>
+			<type>9</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-Common</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1631686224516</id>
+			<name>FreeRTOS/portable/GCC</name>
+			<type>9</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-ARM_CM33_NTZ</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1631686202754</id>
+			<name>FreeRTOS/portable/MemMang</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-heap_4.c</arguments>
+			</matcher>
+		</filter>
+	</filteredResources>
+	<variableList>
+		<variable>
+			<name>DEMO_ROOT</name>
+			<value>$%7BPARENT-2-PROJECT_LOC%7D</value>
+		</variable>
+		<variable>
+			<name>FREERTOS_ROOT</name>
+			<value>$%7BPARENT-4-PROJECT_LOC%7D</value>
+		</variable>
+	</variableList>
+</projectDescription>
@@ -136,6 +136,7 @@ bnumconfigs
 bnumdescriptors
 bnumendpoints
 bo
+bod
 bootloader
 bootstrapcdn
 bp
@@ -655,6 +656,7 @@ eusci
 eval
 evb
 eventcallback
+evk
 evnt
 evt
 ewavr
@@ -906,6 +908,7 @@ initialises
 initializerequestheaders
 initirqlevels
 initstructure
+inputmux
 int
 intc
 intctl
@@ -1336,6 +1339,7 @@ numberofitems
 numofservers
 nvic
 nvs
+nxp
 ocd
 oe
 oer
@@ -2089,6 +2093,7 @@ retargets
 retored
 retr
 rfc
+rgb
 rhr
 ri
 richard
@@ -2776,6 +2781,7 @@ vapplicationstackoverflowhook
 vapplicationtickhook
 var
 vbasicwebserver
+vbat
 vblink
 vbus
 vbuttonhandlertask
@@ -3069,6 +3075,7 @@ xindex
 xinterface
 xinterruptcontroller
 xiptracevalues
+xirqrequest
 xisrautoreloadtimer
 xisroneshottimer
 xisrstatus
@@ -3082,6 +3089,7 @@ xlastwaketime
 xlatcherror
 xlcdqueue
 xledparaemtes
+xledstate
 xledtimer
 xlen
 xlength