mirror of
https://github.com/FreeRTOS/FreeRTOS.git
synced 2026-09-21 10:33:55 +08:00
Remove unused header files from new EFM32 demo.
Prep the code ready to create a tickless implementation.
This commit is contained in:
Richard Barry
@@ -72,7 +72,7 @@
|
||||
<tool id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.base.1942793763" name="GNU ARM C Linker" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.base">
|
||||
<option id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.nostdlibs.1238746537" name="No startup or default libs (-nostdlib)" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.nostdlibs" value="false" valueType="boolean"/>
|
||||
<option id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.printffloat.1689266799" name="Printf float" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.printffloat" value="true" valueType="boolean"/>
|
||||
<option id="gnu.c.link.option.libs.1846704343" name="Libraries (-l)" superClass="gnu.c.link.option.libs" valueType="libs"/>
|
||||
<option id="gnu.c.link.option.libs.1846704343" name="Libraries (-l)" superClass="gnu.c.link.option.libs"/>
|
||||
<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.301647948" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
@@ -83,7 +83,7 @@
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="Source/RTT|Source/SilLabs_Code/kits/bsp/bsp_dk_mcuboard.c|Source/SilLabs_Code/kits/bsp/bsp_dk_leds.c|Source/SilLabs_Code/kits/bsp/bsp_dk_3201.c|Source/SilLabs_Code/kits/bsp/bsp_dk_3200.c|Source/SilLabs_Code/kits/bsp/bsp_bcc.c|Source/SilLabs_Code/Device/SiliconLabs/EFM32GG/Source|CMSIS/efm32gg/startup_iar_efm32gg.s|FreeRTOS/efm32gg/port_iar.c|FreeRTOS/efm32gg/portasm.s" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
<entry excluding="Source/low_power_tick_management.c|Source/RTT|Source/SilLabs_Code/kits/bsp/bsp_dk_mcuboard.c|Source/SilLabs_Code/kits/bsp/bsp_dk_leds.c|Source/SilLabs_Code/kits/bsp/bsp_dk_3201.c|Source/SilLabs_Code/kits/bsp/bsp_dk_3200.c|Source/SilLabs_Code/kits/bsp/bsp_bcc.c|Source/SilLabs_Code/Device/SiliconLabs/EFM32GG/Source|CMSIS/efm32gg/startup_iar_efm32gg.s|FreeRTOS/efm32gg/port_iar.c|FreeRTOS/efm32gg/portasm.s" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
|
||||
+131
-180
@@ -1,215 +1,166 @@
|
||||
/*
|
||||
* FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
|
||||
*
|
||||
* FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
|
||||
* http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
*
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
*
|
||||
*
|
||||
* This file is part of the FreeRTOS distribution.
|
||||
*
|
||||
* FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License (version 2) as published by the
|
||||
* Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
*
|
||||
* >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
|
||||
* distribute a combined work that includes FreeRTOS without being obliged to
|
||||
* provide the source code for proprietary components outside of the FreeRTOS
|
||||
* kernel.
|
||||
*
|
||||
* FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
* WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
|
||||
* details. You should have received a copy of the GNU General Public License
|
||||
* and the FreeRTOS license exception along with FreeRTOS; if not it can be
|
||||
* viewed here: http://www.freertos.org/a00114.html and also obtained by
|
||||
* writing to Real Time Engineers Ltd., contact details for whom are available
|
||||
* on the FreeRTOS WEB site.
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*
|
||||
***************************************************************************
|
||||
* *
|
||||
* Having a problem? Start by reading the FAQ "My application does *
|
||||
* not run, what could be wrong?" *
|
||||
* *
|
||||
* http://www.FreeRTOS.org/FAQHelp.html *
|
||||
* *
|
||||
***************************************************************************
|
||||
*
|
||||
*
|
||||
* http://www.FreeRTOS.org - Documentation, books, training, latest versions,
|
||||
* license and Real Time Engineers Ltd. contact details.
|
||||
*
|
||||
* http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
* including FreeRTOS+Trace - an indispensable productivity tool, and our new
|
||||
* fully thread aware and reentrant UDP/IP stack.
|
||||
*
|
||||
* http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
|
||||
* Integrity Systems, who sell the code with commercial support,
|
||||
* indemnification and middleware, under the OpenRTOS brand.
|
||||
*
|
||||
* http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
* engineered and independently SIL3 certified version for use in safety and
|
||||
* mission critical applications that require provable dependability.
|
||||
*/
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
#include "em_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/********************** Configuration of FreeRTOS ****************************/
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
/* Implement FreeRTOS configASSERT as emlib assert */
|
||||
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
|
||||
|
||||
/* Modes of operations of operation system*/
|
||||
#define configUSE_PREEMPTION ( 1 )
|
||||
|
||||
/* Energy saving modes */
|
||||
#define configUSE_TICKLESS_IDLE ( 0 )
|
||||
/* Available options when configUSE_TICKLESS_IDLE set to 1
|
||||
* or configUSE_SLEEP_MODE_IN_IDLE set to 1 :
|
||||
* 1 - EM1, 2 - EM2, 3 - EM3, timer in EM3 is not very accurate*/
|
||||
#define configSLEEP_MODE ( 2 )
|
||||
|
||||
/* Definition used only if configUSE_TICKLESS_IDLE == 0 */
|
||||
#define configUSE_SLEEP_MODE_IN_IDLE ( 0 )
|
||||
|
||||
|
||||
/* EM1 use systick as system clock*/
|
||||
/* EM2 use crystal 32768Hz and RTC Component as system clock
|
||||
* We use 2 times divider of this clock to reduce energy consumtion
|
||||
* You can also in this mode choose crystal oscillator to get more preccision in
|
||||
* time measurement or RC oscillator for more energy reduction.*/
|
||||
/* EM3 use 2kHz RC and BURTC Component as system clock*/
|
||||
#if ( ( configSLEEP_MODE == 2 ) && ( configUSE_TICKLESS_IDLE == 1 || configUSE_SLEEP_MODE_IN_IDLE == 1 ) )
|
||||
/* Choose source of clock for RTC (system tick)
|
||||
* if configCRYSTAL_IN_EM2 set to 1 then Crystal oscillator is used,
|
||||
* when 0 RC oscillator */
|
||||
#define configCRYSTAL_IN_EM2 ( 1 )
|
||||
#endif
|
||||
#if ( (configSLEEP_MODE == 2 ) && ( configUSE_TICKLESS_IDLE == 1 || configUSE_SLEEP_MODE_IN_IDLE == 1 ) )
|
||||
/* When we use EM2 or EM3 System clock has got low frequency,
|
||||
* so we reduce Tick rate to 100 Hz and 40 Hz, which give more clock cycles between ticks*/
|
||||
#define configTICK_RATE_HZ ( 100 )
|
||||
#elif ( ( configSLEEP_MODE == 3 ) && ( configUSE_TICKLESS_IDLE == 1 || configUSE_SLEEP_MODE_IN_IDLE == 1 ) )
|
||||
#define configTICK_RATE_HZ ( 40 )
|
||||
#else
|
||||
#define configTICK_RATE_HZ ( 1000 )
|
||||
#endif
|
||||
|
||||
/* Definition used by Keil to replace default system clock source when we use EM2 or EM3 mode. */
|
||||
#if ( ( configSLEEP_MODE == 2 || configSLEEP_MODE == 3 ) && ( configUSE_TICKLESS_IDLE == 1 || configUSE_SLEEP_MODE_IN_IDLE == 1 ) )
|
||||
#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION ( 1 )
|
||||
#endif
|
||||
#define configSLEEP_MODE ( 2 )
|
||||
|
||||
/* Main functions*/
|
||||
#define configMAX_PRIORITIES ( 6 )
|
||||
#define configUSE_PREEMPTION ( 1 )
|
||||
#define configUSE_TICKLESS_IDLE ( 1 )
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION ( 1 )
|
||||
#define configMINIMAL_STACK_SIZE (( unsigned short ) 140)
|
||||
#define configTOTAL_HEAP_SIZE (( size_t )(40000))
|
||||
#define configMAX_TASK_NAME_LEN ( 10 )
|
||||
#define configUSE_TRACE_FACILITY ( 0 )
|
||||
#define configUSE_16_BIT_TICKS ( 0 )
|
||||
#define configIDLE_SHOULD_YIELD ( 0 )
|
||||
#define configUSE_MUTEXES ( 1 )
|
||||
#define configUSE_RECURSIVE_MUTEXES ( 1 )
|
||||
#define configUSE_COUNTING_SEMAPHORES ( 1 )
|
||||
#define configUSE_ALTERNATIVE_API ( 0 )/* Deprecated! */
|
||||
#define configQUEUE_REGISTRY_SIZE ( 10 )
|
||||
#define configUSE_QUEUE_SETS ( 0 )
|
||||
#define configCPU_CLOCK_HZ (( unsigned long ) 14000000)
|
||||
#define configMAX_PRIORITIES ( 6 )
|
||||
#define configTICK_RATE_HZ ( 1000 )
|
||||
#define configMINIMAL_STACK_SIZE (( unsigned short ) 140)
|
||||
#define configTOTAL_HEAP_SIZE (( size_t )(40000))
|
||||
#define configMAX_TASK_NAME_LEN ( 10 )
|
||||
#define configUSE_TRACE_FACILITY ( 0 )
|
||||
#define configUSE_16_BIT_TICKS ( 0 )
|
||||
#define configIDLE_SHOULD_YIELD ( 0 )
|
||||
#define configUSE_MUTEXES ( 1 )
|
||||
#define configUSE_RECURSIVE_MUTEXES ( 1 )
|
||||
#define configUSE_COUNTING_SEMAPHORES ( 1 )
|
||||
#define configUSE_ALTERNATIVE_API ( 0 )/* Deprecated! */
|
||||
#define configQUEUE_REGISTRY_SIZE ( 10 )
|
||||
#define configUSE_QUEUE_SETS ( 0 )
|
||||
|
||||
/* Hook function related definitions. */
|
||||
#define configUSE_TICK_HOOK ( 1 )
|
||||
#define configCHECK_FOR_STACK_OVERFLOW ( 2 )
|
||||
#define configUSE_MALLOC_FAILED_HOOK ( 1 )
|
||||
#define configUSE_TICK_HOOK ( 1 )
|
||||
#define configCHECK_FOR_STACK_OVERFLOW ( 2 )
|
||||
#define configUSE_MALLOC_FAILED_HOOK ( 1 )
|
||||
#define configUSE_IDLE_HOOK ( 1 )
|
||||
|
||||
/* Run time stats gathering related definitions. */
|
||||
#define configGENERATE_RUN_TIME_STATS ( 0 )
|
||||
#define configGENERATE_RUN_TIME_STATS ( 0 )
|
||||
|
||||
/* Co-routine related definitions. */
|
||||
#define configUSE_CO_ROUTINES ( 0 )
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 1 )
|
||||
#define configUSE_CO_ROUTINES ( 0 )
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 1 )
|
||||
|
||||
/* Software timer related definitions. */
|
||||
#define configUSE_TIMERS ( 1 )
|
||||
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) /* Highest priority */
|
||||
#define configTIMER_QUEUE_LENGTH ( 10 )
|
||||
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
|
||||
#define configUSE_TIMERS ( 1 )
|
||||
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) /* Highest priority */
|
||||
#define configTIMER_QUEUE_LENGTH ( 10 )
|
||||
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
|
||||
|
||||
/* Interrupt nesting behaviour configuration. */
|
||||
#define configKERNEL_INTERRUPT_PRIORITY ( 255 )
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 191 ) /* equivalent to 0xa0, or priority 5. */
|
||||
#define configKERNEL_INTERRUPT_PRIORITY ( 255 )
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 191 ) /* equivalent to 0xa0, or priority 5. */
|
||||
|
||||
/* Optional functions - most linkers will remove unused functions anyway. */
|
||||
#define INCLUDE_vTaskPrioritySet ( 1 )
|
||||
#define INCLUDE_uxTaskPriorityGet ( 1 )
|
||||
#define INCLUDE_vTaskDelete ( 1 )
|
||||
#define INCLUDE_vTaskSuspend ( 1 )
|
||||
#define INCLUDE_xResumeFromISR ( 1 )
|
||||
#define INCLUDE_vTaskDelayUntil ( 1 )
|
||||
#define INCLUDE_vTaskDelay ( 1 )
|
||||
#define INCLUDE_xTaskGetSchedulerState ( 1 )
|
||||
#define INCLUDE_xTaskGetCurrentTaskHandle ( 1 )
|
||||
#define INCLUDE_uxTaskGetStackHighWaterMark ( 0 )
|
||||
#define INCLUDE_xTaskGetIdleTaskHandle ( 0 )
|
||||
#define INCLUDE_xTimerGetTimerDaemonTaskHandle ( 0 )
|
||||
#define INCLUDE_pcTaskGetTaskName ( 0 )
|
||||
#define INCLUDE_eTaskGetState ( 1 )
|
||||
#define INCLUDE_xTimerPendFunctionCall ( 1 )
|
||||
|
||||
/* Default value of CPU clock (RC)*/
|
||||
#define configCPU_CLOCK_HZ (( unsigned long ) 14000000)
|
||||
|
||||
/* Defines used in energy modes */
|
||||
#if ( ( configSLEEP_MODE == 2 ) && ( ( configUSE_SLEEP_MODE_IN_IDLE == 1 ) || ( configUSE_TICKLESS_IDLE == 1 ) ) )
|
||||
#define configSYSTICK_CLOCK_HZ ( 16384 )
|
||||
#endif
|
||||
|
||||
#if ( ( configSLEEP_MODE == 3 ) && ( ( configUSE_SLEEP_MODE_IN_IDLE == 1 ) || ( configUSE_TICKLESS_IDLE == 1 ) ) )
|
||||
#define configSYSTICK_CLOCK_HZ ( 2000 )
|
||||
#endif
|
||||
|
||||
#if ( ( configUSE_TICKLESS_IDLE == 0 ) && ( configUSE_SLEEP_MODE_IN_IDLE == 1 ) )
|
||||
#define configUSE_IDLE_HOOK ( 1 )
|
||||
#else
|
||||
#define configUSE_IDLE_HOOK ( 0 )
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
#define INCLUDE_vTaskPrioritySet ( 1 )
|
||||
#define INCLUDE_uxTaskPriorityGet ( 1 )
|
||||
#define INCLUDE_vTaskDelete ( 1 )
|
||||
#define INCLUDE_vTaskSuspend ( 1 )
|
||||
#define INCLUDE_xResumeFromISR ( 1 )
|
||||
#define INCLUDE_vTaskDelayUntil ( 1 )
|
||||
#define INCLUDE_vTaskDelay ( 1 )
|
||||
#define INCLUDE_xTaskGetSchedulerState ( 1 )
|
||||
#define INCLUDE_xTaskGetCurrentTaskHandle ( 1 )
|
||||
#define INCLUDE_uxTaskGetStackHighWaterMark ( 0 )
|
||||
#define INCLUDE_xTaskGetIdleTaskHandle ( 0 )
|
||||
#define INCLUDE_xTimerGetTimerDaemonTaskHandle ( 0 )
|
||||
#define INCLUDE_pcTaskGetTaskName ( 0 )
|
||||
#define INCLUDE_eTaskGetState ( 1 )
|
||||
#define INCLUDE_xTimerPendFunctionCall ( 1 )
|
||||
|
||||
/* Stop if an assertion fails. */
|
||||
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
|
||||
|
||||
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
|
||||
* standard names. */
|
||||
#define vPortSVCHandler SVC_Handler
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
#define xPortSysTickHandler SysTick_Handler
|
||||
|
||||
standard names. */
|
||||
#define vPortSVCHandler SVC_Handler
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
#define xPortSysTickHandler SysTick_Handler
|
||||
|
||||
/* For the linker. */
|
||||
#define fabs __builtin_fabs
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
+5
-2
@@ -119,6 +119,7 @@
|
||||
|
||||
/* SiLabs includes. */
|
||||
#include "bsp.h"
|
||||
#include "segmentlcd.h"
|
||||
|
||||
/* Standard demo application includes. */
|
||||
#include "flop.h"
|
||||
@@ -210,6 +211,9 @@ extern volatile uint32_t ulLED;
|
||||
|
||||
void main_full( void )
|
||||
{
|
||||
SegmentLCD_Init( false );
|
||||
SegmentLCD_Write( "F'RTOS" );
|
||||
|
||||
/* Start all the other standard demo/test tasks. They have no particular
|
||||
functionality, but do demonstrate how to use the FreeRTOS API and test the
|
||||
kernel port. */
|
||||
@@ -355,8 +359,7 @@ unsigned long ulErrorFound = pdFALSE;
|
||||
{
|
||||
/* An error has been detected in one of the tasks - flash the LED
|
||||
at a higher frequency to give visible feedback that something has
|
||||
gone wrong (it might just be that the loop back connector required
|
||||
by the comtest tasks has not been fitted). */
|
||||
gone wrong. */
|
||||
xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;
|
||||
}
|
||||
|
||||
|
||||
+10
-5
@@ -121,7 +121,7 @@
|
||||
|
||||
/* The rate at which data is sent to the queue. The 200ms value is converted
|
||||
to ticks using the portTICK_PERIOD_MS constant. */
|
||||
#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )
|
||||
#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 500 )
|
||||
|
||||
/* The number of items the queue can hold. This is 1 as the receive task
|
||||
will remove items as they are added, meaning the send task should always find
|
||||
@@ -187,7 +187,7 @@ void main_low_power( void )
|
||||
static void prvQueueSendTask( void *pvParameters )
|
||||
{
|
||||
TickType_t xNextWakeTime;
|
||||
const unsigned long ulValueToSend = 100UL;
|
||||
const uint32_t ulValueToSend = 100UL;
|
||||
|
||||
/* Remove compiler warning about unused parameter. */
|
||||
( void ) pvParameters;
|
||||
@@ -211,8 +211,9 @@ const unsigned long ulValueToSend = 100UL;
|
||||
|
||||
static void prvQueueReceiveTask( void *pvParameters )
|
||||
{
|
||||
unsigned long ulReceivedValue;
|
||||
const unsigned long ulExpectedValue = 100UL;
|
||||
uint32_t ulReceivedValue;
|
||||
const uint32_t ulExpectedValue = 100UL;
|
||||
const TickType_t xShortDelay = pdMS_TO_TICKS( 10 );
|
||||
|
||||
/* Remove compiler warning about unused parameter. */
|
||||
( void ) pvParameters;
|
||||
@@ -228,7 +229,11 @@ const unsigned long ulExpectedValue = 100UL;
|
||||
is it the expected value? If it is, toggle the LED. */
|
||||
if( ulReceivedValue == ulExpectedValue )
|
||||
{
|
||||
BSP_LedToggle( mainTASK_LED );
|
||||
/* Turn the LED on for a brief time only so it doens't distort the
|
||||
enerty reading. */
|
||||
BSP_LedSet( mainTASK_LED );
|
||||
vTaskDelay( xShortDelay );
|
||||
BSP_LedClear( mainTASK_LED );
|
||||
ulReceivedValue = 0U;
|
||||
}
|
||||
}
|
||||
|
||||
-7544
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-3678
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-3657
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-3657
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Load Diff
-479
@@ -1,479 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file efm32gg900f1024.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG900F1024
|
||||
* @version 4.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __SILICON_LABS_EFM32GG900F1024_H__
|
||||
#define __SILICON_LABS_EFM32GG900F1024_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024 EFM32GG900F1024
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_Core EFM32GG900F1024 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG900F1024_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_Part EFM32GG900F1024 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG900F1024)
|
||||
#define EFM32GG900F1024 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG900F1024" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG900F1024 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG900F1024_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_Peripheral_TypeDefs EFM32GG900F1024 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG900F1024_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_Peripheral_Base EFM32GG900F1024 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG900F1024_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_Peripheral_Declaration EFM32GG900F1024 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG900F1024_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_BitFields EFM32GG900F1024 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_UNLOCK EFM32GG900F1024 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG900F1024_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG900F1024_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_Alternate_Function EFM32GG900F1024 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG900F1024_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG900F1024 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __SILICON_LABS_EFM32GG900F1024_H__ */
|
||||
-479
@@ -1,479 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file efm32gg900f512.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG900F512
|
||||
* @version 4.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __SILICON_LABS_EFM32GG900F512_H__
|
||||
#define __SILICON_LABS_EFM32GG900F512_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512 EFM32GG900F512
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_Core EFM32GG900F512 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG900F512_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_Part EFM32GG900F512 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG900F512)
|
||||
#define EFM32GG900F512 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG900F512" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG900F512 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG900F512_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_Peripheral_TypeDefs EFM32GG900F512 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG900F512_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_Peripheral_Base EFM32GG900F512 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG900F512_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_Peripheral_Declaration EFM32GG900F512 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG900F512_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_BitFields EFM32GG900F512 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_UNLOCK EFM32GG900F512 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG900F512_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG900F512_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_Alternate_Function EFM32GG900F512 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG900F512_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG900F512 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __SILICON_LABS_EFM32GG900F512_H__ */
|
||||
-3731
File diff suppressed because it is too large
Load Diff
-3731
File diff suppressed because it is too large
Load Diff
-3731
File diff suppressed because it is too large
Load Diff
-3731
File diff suppressed because it is too large
Load Diff
-479
@@ -1,479 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file efm32gg980f1024.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG980F1024
|
||||
* @version 4.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __SILICON_LABS_EFM32GG980F1024_H__
|
||||
#define __SILICON_LABS_EFM32GG980F1024_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024 EFM32GG980F1024
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_Core EFM32GG980F1024 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG980F1024_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_Part EFM32GG980F1024 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG980F1024)
|
||||
#define EFM32GG980F1024 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG980F1024" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG980F1024 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG980F1024_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_Peripheral_TypeDefs EFM32GG980F1024 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG980F1024_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_Peripheral_Base EFM32GG980F1024 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG980F1024_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_Peripheral_Declaration EFM32GG980F1024 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG980F1024_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_BitFields EFM32GG980F1024 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_UNLOCK EFM32GG980F1024 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG980F1024_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG980F1024_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_Alternate_Function EFM32GG980F1024 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG980F1024_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG980F1024 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __SILICON_LABS_EFM32GG980F1024_H__ */
|
||||
-479
@@ -1,479 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file efm32gg980f512.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG980F512
|
||||
* @version 4.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __SILICON_LABS_EFM32GG980F512_H__
|
||||
#define __SILICON_LABS_EFM32GG980F512_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512 EFM32GG980F512
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_Core EFM32GG980F512 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG980F512_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_Part EFM32GG980F512 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG980F512)
|
||||
#define EFM32GG980F512 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG980F512" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG980F512 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG980F512_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_Peripheral_TypeDefs EFM32GG980F512 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG980F512_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_Peripheral_Base EFM32GG980F512 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG980F512_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_Peripheral_Declaration EFM32GG980F512 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG980F512_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_BitFields EFM32GG980F512 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_UNLOCK EFM32GG980F512 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG980F512_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG980F512_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_Alternate_Function EFM32GG980F512 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG980F512_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG980F512 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __SILICON_LABS_EFM32GG980F512_H__ */
|
||||
-479
@@ -1,479 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file efm32gg990f512.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG990F512
|
||||
* @version 4.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __SILICON_LABS_EFM32GG990F512_H__
|
||||
#define __SILICON_LABS_EFM32GG990F512_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512 EFM32GG990F512
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_Core EFM32GG990F512 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG990F512_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_Part EFM32GG990F512 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG990F512)
|
||||
#define EFM32GG990F512 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG990F512" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG990F512 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG990F512_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_Peripheral_TypeDefs EFM32GG990F512 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG990F512_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_Peripheral_Base EFM32GG990F512 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG990F512_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_Peripheral_Declaration EFM32GG990F512 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG990F512_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_BitFields EFM32GG990F512 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_UNLOCK EFM32GG990F512 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG990F512_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG990F512_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_Alternate_Function EFM32GG990F512 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG990F512_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG990F512 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __SILICON_LABS_EFM32GG990F512_H__ */
|
||||
-479
@@ -1,479 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file efm32gg995f1024.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG995F1024
|
||||
* @version 4.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __SILICON_LABS_EFM32GG995F1024_H__
|
||||
#define __SILICON_LABS_EFM32GG995F1024_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024 EFM32GG995F1024
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_Core EFM32GG995F1024 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG995F1024_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_Part EFM32GG995F1024 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG995F1024)
|
||||
#define EFM32GG995F1024 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG995F1024" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG995F1024 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG995F1024_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_Peripheral_TypeDefs EFM32GG995F1024 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG995F1024_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_Peripheral_Base EFM32GG995F1024 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG995F1024_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_Peripheral_Declaration EFM32GG995F1024 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG995F1024_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_BitFields EFM32GG995F1024 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_UNLOCK EFM32GG995F1024 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG995F1024_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG995F1024_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_Alternate_Function EFM32GG995F1024 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG995F1024_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG995F1024 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __SILICON_LABS_EFM32GG995F1024_H__ */
|
||||
-479
@@ -1,479 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file efm32gg995f512.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG995F512
|
||||
* @version 4.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __SILICON_LABS_EFM32GG995F512_H__
|
||||
#define __SILICON_LABS_EFM32GG995F512_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512 EFM32GG995F512
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_Core EFM32GG995F512 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG995F512_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_Part EFM32GG995F512 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG995F512)
|
||||
#define EFM32GG995F512 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG995F512" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG995F512 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG995F512_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_Peripheral_TypeDefs EFM32GG995F512 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG995F512_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_Peripheral_Base EFM32GG995F512 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG995F512_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_Peripheral_Declaration EFM32GG995F512 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG995F512_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_BitFields EFM32GG995F512 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_UNLOCK EFM32GG995F512 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG995F512_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG995F512_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_Alternate_Function EFM32GG995F512 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG995F512_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG995F512 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __SILICON_LABS_EFM32GG995F512_H__ */
|
||||
@@ -94,7 +94,7 @@
|
||||
/* SiLabs includes. */
|
||||
#include "em_chip.h"
|
||||
#include "bsp.h"
|
||||
#include "segmentlcd.h"
|
||||
#include "bsp_trace.h"
|
||||
#include "sleep.h"
|
||||
|
||||
/* Set mainCREATE_LOW_POWER_DEMO to one to run the simple blinky demo, or 0 to
|
||||
@@ -125,9 +125,6 @@ void vApplicationIdleHook( void );
|
||||
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
|
||||
void vApplicationTickHook( void );
|
||||
|
||||
|
||||
// SegmentLCD_Write(text);
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
int main( void )
|
||||
@@ -159,9 +156,8 @@ static void prvSetupHardware( void )
|
||||
{
|
||||
/* Library initialisation routines. */
|
||||
CHIP_Init();
|
||||
//_RB_ BSP_TraceProfilerSetup();
|
||||
BSP_TraceProfilerSetup();
|
||||
SLEEP_Init( NULL, NULL );
|
||||
SegmentLCD_Init( false );
|
||||
BSP_LedsInit();
|
||||
|
||||
#if (configSLEEP_MODE < 3)
|
||||
|
||||
Reference in New Issue
Block a user