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remove stray semicolons
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Browse Source 
Remove stray semicolons from demo code.

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
This commit is contained in:
Florian La Roche
2026-01-29 17:25:55 -08:00
committed by Archit Gupta
parent e83f1402d5
commit 30b61e5503
26 changed files with 37 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_options.c
+1 -1
View File
@@ -773,7 +773,7 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
XSDPS_CLK_CTRL_OFFSET);
while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET);;
XSDPS_CLK_CTRL_OFFSET);
}
/* Enable SD clock */
FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/utils/lcd_draw.c
+2 -2
View File
@@ -591,11 +591,11 @@ void lcdd_draw_string_with_bgcolor(uint32_t x, uint32_t y,
while (*p_string) {
if (*p_string == '\n') {
y += height + char_space;;
y += height + char_space;
x = xorg;
} else {
lcdd_draw_char_with_bgcolor(x, y, *p_string, fontColor, bgColor);
x += width + char_space;;
x += width + char_space;
}
p_string++;
}
FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_dma_program.c
+1 -1
View File
@@ -741,7 +741,7 @@ ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm,
uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size;
// Assemble DMAMOV
buffer[0] = 0xbc;;
buffer[0] = 0xbc;
buffer[1] = rd_mask;
buffer[2] = (uint8_t)((val >> 0) & 0xff);
buffer[3] = (uint8_t)((val >> 8) & 0xff);
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_options.c
+1 -1
View File
@@ -773,7 +773,7 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
XSDPS_CLK_CTRL_OFFSET);
while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET);;
XSDPS_CLK_CTRL_OFFSET);
}
/* Enable SD clock */
FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_iccarm.h
+2 -2
View File
@@ -182,7 +182,7 @@ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
*(__packed uint16_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
@@ -204,7 +204,7 @@ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
*(__packed uint32_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/ST_Code/Drivers/CMSIS/Include/cmsis_iccarm.h
+2 -2
View File
@@ -182,7 +182,7 @@ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
*(__packed uint16_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
@@ -204,7 +204,7 @@ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
*(__packed uint32_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/drivers/I2S.h
+1 -1
View File
@@ -187,7 +187,7 @@
*
* while(1) {
* ret = I2S_writeReclaim(handle, &pDesc);
* pDesc->bufPtr = &hello;;
* pDesc->bufPtr = &hello;
* pDesc->bufSize = sizeof(hello);
* ret = I2S_writeIssue(handle, pDesc);
* }
FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/afe_dma.c
+1 -1
View File
@@ -244,5 +244,5 @@ uint32_t Afe_SendData( AfeDma *pAfed, AfeCmd *pCommand)
if (XDMAD_StartTransfer( pAfed->pXdmad, afeDmaRxChannel ))
return AFE_ERROR_LOCK;
return AFE_OK;;
return AFE_OK;
}
FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/afec.c
+1 -1
View File
@@ -432,7 +432,7 @@ void AFEC_SetAnalogOffset( Afec *pAFE, uint32_t dwChannel,uint32_t aoffset )
{
assert( dwChannel < 12 ) ;
pAFE->AFEC_CSELR = dwChannel;
pAFE->AFEC_COCR = (aoffset & AFEC_COCR_AOFF_Msk);;
pAFE->AFEC_COCR = (aoffset & AFEC_COCR_AOFF_Msk);
}
/**
FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/dac_dma.c
+1 -1
View File
@@ -230,5 +230,5 @@ uint32_t Dac_SendData( DacDma *pDacd, DacCmd *pCommand)
/* Start DMA TX */
if (XDMAD_StartTransfer( pDacd->pXdmad, dacDmaTxChannel ))
return DAC_ERROR_LOCK;
return DAC_OK;;
return DAC_OK;
}
FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/afe_dma.c
+2 -2
View File
@@ -157,7 +157,7 @@ static uint8_t _Afe_configureLinkList(Afec *pAfeHw, void *pXdmad, AfeCmd *pComma
xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |
XDMA_UBC_NDE_FETCH_EN|
XDMA_UBC_NDEN_UPDATED |
pCommand->RxSize;;
pCommand->RxSize;
xdmadRxCfg.mbr_da = (uint32_t)pCommand->pRxBuff;
xdmadRxCfg.mbr_sa = (uint32_t)&(pAfeHw->AFEC_LCDR);
xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
@@ -253,5 +253,5 @@ uint32_t Afe_SendData( AfeDma *pAfed, AfeCmd *pCommand)
if (XDMAD_StartTransfer( pAfed->pXdmad, afeDmaRxChannel ))
return AFE_ERROR_LOCK;
return AFE_OK;;
return AFE_OK;
}
FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/afec.c
+1 -1
View File
@@ -449,7 +449,7 @@ void AFEC_SetAnalogOffset( Afec *pAFE, uint32_t dwChannel,uint32_t aoffset )
{
assert( dwChannel < 12 ) ;
pAFE->AFEC_CSELR = dwChannel;
pAFE->AFEC_COCR = (aoffset & AFEC_COCR_AOFF_Msk);;
pAFE->AFEC_COCR = (aoffset & AFEC_COCR_AOFF_Msk);
}
/**
FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/dac_dma.c
+1 -1
View File
@@ -226,7 +226,7 @@ uint32_t Dac_SendData( DacDma *pDacd, DacCmd *pCommand)
/* Start DMA TX */
if (XDMAD_StartTransfer( pDacd->pXdmad, dacDmaTxChannel ))
return DAC_ERROR_LOCK;
return DAC_OK;;
return DAC_OK;
}
FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/cmsis_iccarm.h
+2 -2
View File
@@ -192,7 +192,7 @@ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
*(__packed uint16_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
@@ -214,7 +214,7 @@ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
*(__packed uint32_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h
+2 -2
View File
@@ -187,7 +187,7 @@ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
*(__packed uint16_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
@@ -209,7 +209,7 @@ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
*(__packed uint32_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h
+2 -2
View File
@@ -194,7 +194,7 @@ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
*(__packed uint16_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
@@ -216,7 +216,7 @@ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
*(__packed uint32_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/ST_Code/Drivers/CMSIS/Include/cmsis_iccarm.h
+2 -2
View File
@@ -182,7 +182,7 @@ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
*(__packed uint16_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
@@ -204,7 +204,7 @@ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
*(__packed uint32_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_iccarm.h
+2 -2
View File
@@ -182,7 +182,7 @@ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
*(__packed uint16_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
@@ -204,7 +204,7 @@ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
*(__packed uint32_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/ST_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c
+1 -1
View File
@@ -849,7 +849,7 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY
else
{
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;;
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/ST_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c
+1 -1
View File
@@ -410,7 +410,7 @@ HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL
pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
}
return HAL_OK;;
return HAL_OK;
}
/**
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_iccarm.h
+2 -2
View File
@@ -182,7 +182,7 @@ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
*(__packed uint16_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
@@ -204,7 +204,7 @@ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
*(__packed uint32_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c
+1 -1
View File
@@ -1249,7 +1249,7 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr,
*PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
*PCROPEndAddr = (reg_value << 4) + FLASH_BASE + 0xFU;;
*PCROPEndAddr = (reg_value << 4) + FLASH_BASE + 0xFU;
}
else
{
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_options.c
+1 -1
View File
@@ -773,7 +773,7 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
XSDPS_CLK_CTRL_OFFSET);
while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET);;
XSDPS_CLK_CTRL_OFFSET);
}
/* Enable SD clock */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.c
+1 -1
View File
@@ -547,7 +547,7 @@ uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn)
bool SystemInISR(void)
{
return ((EVENT_UNIT->INTPTENACTIVE) != 0);;
return ((EVENT_UNIT->INTPTENACTIVE) != 0);
}
void EVENT_SystemReset(void)
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.c
+1 -1
View File
@@ -526,7 +526,7 @@ void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority)
bool SystemInISR(void)
{
return ((EVENT_UNIT->INTPTENACTIVE) != 0);;
return ((EVENT_UNIT->INTPTENACTIVE) != 0);
}
void EVENT_SystemReset(void)
FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h
+2 -2
View File
@@ -192,7 +192,7 @@ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
*(__packed uint16_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
@@ -214,7 +214,7 @@ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
*(__packed uint32_t*)(ptr) = val;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)