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Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason).

Browse Source 
Add a project for the Vega board's RI5CY core.
This commit is contained in:
Richard Barry
2018-12-31 18:19:52 +00:00
parent e2af102c80
commit 11d9c440b8
61 changed files with 76183 additions and 53 deletions
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FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.cproject
+1 -1
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@@ -50,7 +50,7 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.874608690" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.545620458" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freedom-e-sdk/env}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V-RV32}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/RV32I_CLINT_no_extensions}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freedom-e-sdk/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freedom-e-sdk/env/freedom-e300-hifive1}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freedom-e-sdk/drivers}&quot;"/>
FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.project
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@@ -135,6 +135,17 @@
<locationURI>FREERTOS_ROOT/FreeRTOS/Source/portable/MemMang/heap_4.c</locationURI>
</link>
</linkedResources>
<filteredResources>
<filter>
<id>1546280186727</id>
<name>FreeRTOS_Source/portable/GCC/RISC-V-RV32/chip_specific_extensions</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-RV32I_CLINT_no_extensions</arguments>
</matcher>
</filter>
</filteredResources>
<variableList>
<variable>
<name>FREERTOS_ROOT</name>
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/pin_mux.c
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@@ -0,0 +1,61 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v3.0
processor: RV32M1
package_id: RV32M1
mcu_data: ksdk2_0
processor_version: 0.0.0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_port.h"
#include "pin_mux.h"
/*FUNCTION**********************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
*END**************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
}
#define PIN7_IDX 7u /*!< Pin number for pin 7 in a port */
#define PIN8_IDX 8u /*!< Pin number for pin 8 in a port */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'}
- pin_list:
- {pin_num: N2, peripheral: LPUART0, signal: RX, pin_signal: LPCMP0_IN0/PTC7/LLWU_P15/LPSPI0_PCS3/LPUART0_RX/LPI2C1_HREQ/TPM0_CH0/LPTMR1_ALT1}
- {pin_num: P3, peripheral: LPUART0, signal: TX, pin_signal: LPCMP0_IN1/PTC8/LPSPI0_SCK/LPUART0_TX/LPI2C0_HREQ/TPM0_CH1}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/*FUNCTION**********************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
*END**************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_PortC); /* Clock Gate Control: 0x01u */
PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt3); /* PORTC7 (pin N2) is configured as LPUART0_RX */
PORT_SetPinMux(PORTC, PIN8_IDX, kPORT_MuxAlt3); /* PORTC8 (pin P3) is configured as LPUART0_TX */
}
/*******************************************************************************
* EOF
******************************************************************************/
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/pin_mux.h
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@@ -0,0 +1,59 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/*******************************************************************************
* EOF
******************************************************************************/
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_ri5cy.cfg
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set _WORKAREASIZE 0x2000
adapter_khz 1000
interface jlink
transport select jtag
set _WORKAREASIZE 0x1000
set _CHIPNAME rv32m1
reset_config srst_only
# OpenCores Mohor JTAG TAP ID
set _CPUTAPID 0x249511C3
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME rv32m1 -endian little -chain-position $_TARGETNAME
# Select the TAP core we are using
tap_select mohor
# Select the debug unit core we are using. This debug unit as an option.
set ADBG_USE_HISPEED 1
# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
# on burst reads and writes to improve download speeds.
# This option must match the RTL configured option.
du_select adv [expr $ADBG_USE_HISPEED]
# Select core 0
core_select 0
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
$_TARGETNAME configure -event gdb-detach {
resume
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
proc ri5cy_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFF03FF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
proc cm4_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFFFFFF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
proc zero_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFF03BF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
proc cm0_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFFFFBF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
# All cores are available, CM4 & RI5CY boot first
proc core0_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFFA3FF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
# All cores are available, CM0 & ZERO_RISCY boot first
proc core1_boot { } {
# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80
sleep 1000
mwb 0x40023000 0x70
mww 0x40023008 0xFFFFA3BF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80
sleep 2
}
init
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/RISCV/core_riscv32.h
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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_RISCV32_H__
#define __CORE_RISCV32_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define RISCV32
#if defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
#if defined ( __GNUC__ )
#define __BKPT(x) __ASM("ebreak")
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("nop");
}
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("nop");
}
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
{
}
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("csrsi mstatus, 8");
}
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("csrci mstatus, 8");
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
return __builtin_bswap32(value);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
return __builtin_bswap16(value);
}
#else
#error Unknown compiler
#endif
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_RISCV32_H__ */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/board.c
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@@ -0,0 +1,29 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include "fsl_common.h"
#include "fsl_debug_console.h"
#include "board.h"
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/* Initialize debug console. */
void BOARD_InitDebugConsole(void)
{
CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFircAsync);
uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
}
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/board.h
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/*
* Copyright 2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#include "clock_config.h"
#include "fsl_gpio.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief The board name */
#define BOARD_NAME "RV32M1-VEGA"
/* The UART to use for debug messages. */
#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART0
#define BOARD_DEBUG_UART_INSTANCE 0U
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(kCLOCK_Lpuart0)
#define BOARD_UART_IRQ LPUART0_IRQn
#define BOARD_UART_IRQ_HANDLER LPUART0_IRQHandler
/* Definitions for eRPC MU transport layer */
#if defined(FSL_FEATURE_MU_SIDE_A)
#define MU_BASE MUA
#define MU_IRQ MUA_IRQn
#define MU_IRQ_HANDLER MUA_IRQHandler
#endif
#if defined(FSL_FEATURE_MU_SIDE_B)
#define MU_BASE MUB
#define MU_IRQ MUB_IRQn
#define MU_IRQ_HANDLER MUB_IRQHandler
#endif
#define MU_IRQ_PRIORITY (2)
/*! @brief Define the port interrupt number for the board switches */
#define BOARD_SW2_GPIO GPIOA
#define BOARD_SW2_PORT PORTA
#define BOARD_SW2_GPIO_PIN 0U
#define BOARD_SW2_IRQ PORTA_IRQn
#define BOARD_SW2_IRQ_HANDLER PORTA_IRQHandler
#define BOARD_SW2_NAME "SW2"
/* Board led color mapping */
#define BOARD_LED_RED_GPIO GPIOA
#define BOARD_LED_RED_GPIO_PIN 24U
/*! @brief The TPM channel used for board */
#define BOARD_TPM_CHANNEL 0U
#define LOGIC_LED_ON 1U
#define LOGIC_LED_OFF 0U
#define BOARD_LED1_GPIO GPIOA
#define BOARD_LED1_GPIO_PIN 24U
#define BOARD_LED2_GPIO GPIOA
#define BOARD_LED2_GPIO_PIN 23U
#define BOARD_LED3_GPIO GPIOA
#define BOARD_LED3_GPIO_PIN 22U
#define LED1_INIT(output) \
GPIO_WritePinOutput(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PIN, output); \
BOARD_LED1_GPIO->PDDR |= (1U << BOARD_LED1_GPIO_PIN) /*!< Enable target LED1 */
#define LED1_ON() GPIO_SetPinsOutput(BOARD_LED1_GPIO, 1U << BOARD_LED1_GPIO_PIN) /*!< Turn on target LED1 */
#define LED1_OFF() GPIO_ClearPinsOutput(BOARD_LED1_GPIO, 1U << BOARD_LED1_GPIO_PIN) /*!< Turn off target LED1 */
#define LED1_TOGGLE() GPIO_TogglePinsOutput(BOARD_LED1_GPIO, 1U << BOARD_LED1_GPIO_PIN) /*!< Toggle on target LED1 */
#define LED2_INIT(output) \
GPIO_WritePinOutput(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PIN, output); \
BOARD_LED2_GPIO->PDDR |= (1U << BOARD_LED2_GPIO_PIN) /*!< Enable target LED2 */
#define LED2_ON() GPIO_SetPinsOutput(BOARD_LED2_GPIO, 1U << BOARD_LED2_GPIO_PIN) /*!< Turn on target LED2 */
#define LED2_OFF() GPIO_ClearPinsOutput(BOARD_LED2_GPIO, 1U << BOARD_LED2_GPIO_PIN) /*!< Turn off target LED2 */
#define LED2_TOGGLE() GPIO_TogglePinsOutput(BOARD_LED2_GPIO, 1U << BOARD_LED2_GPIO_PIN) /*!< Toggle on target LED2 */
#define LED3_INIT(output) \
GPIO_WritePinOutput(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PIN, output); \
BOARD_LED3_GPIO->PDDR |= (1U << BOARD_LED3_GPIO_PIN) /*!< Enable target LED3 */
#define LED3_ON() GPIO_SetPinsOutput(BOARD_LED3_GPIO, 1U << BOARD_LED3_GPIO_PIN) /*!< Turn on target LED3 */
#define LED3_OFF() GPIO_ClearPinsOutput(BOARD_LED3_GPIO, 1U << BOARD_LED3_GPIO_PIN) /*!< Turn off target LED3 */
#define LED3_TOGGLE() GPIO_TogglePinsOutput(BOARD_LED3_GPIO, 1U << BOARD_LED3_GPIO_PIN) /*!< Toggle on target LED3 */
#define BOARD_USDHC0_BASEADDR USDHC0
#define BOARD_USDHC_CD_PORT_BASE PORTC
#define BOARD_USDHC_CD_GPIO_BASE GPIOC
#define BOARD_USDHC_CD_GPIO_PIN 27
#define BOARD_USDHC_CD_PORT_IRQ PORTC_IRQn
#define BOARD_USDHC_CD_PORT_IRQ_HANDLER PORTC_IRQHandler
#define BOARD_USDHC_CD_GPIO_INIT() \
{ \
gpio_pin_config_t sw_config = {kGPIO_DigitalInput, 0}; \
GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config); \
PORT_SetPinInterruptConfig(BOARD_USDHC_CD_PORT_BASE, BOARD_USDHC_CD_GPIO_PIN, kPORT_InterruptRisingEdge); \
}
#define BOARD_USDHC_CD_STATUS() (GPIO_ReadPinInput(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
#define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_GetPinsInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_ClearPinsInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (1U)
#define BOARD_USDHC0_CLK_FREQ (CLOCK_GetIpFreq(kCLOCK_Sdhc0))
#define BOARD_SD_HOST_BASEADDR BOARD_USDHC0_BASEADDR
#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC0_CLK_FREQ
#define BOARD_SD_HOST_IRQ USDHC0_IRQn
#define BOARD_SD_SUPPORT_180V (0U)
#define BOARD_MMC_HOST_BASEADDR BOARD_USDHC0_BASEADDR
#define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC0_CLK_FREQ
#define BOARD_MMC_HOST_IRQ USDHC0_IRQn
#define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindows270to360
#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
#define BOARD_MMC_PIN_CONFIG(speed, strength)
/* this define not implement, due to EVK board have no power reset circuit */
#define BOARD_SD_POWER_RESET_GPIO ()
#define BOARD_SD_POWER_RESET_GPIO_PIN ()
#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT()
#define BOARD_USDHC_SDCARD_POWER_CONTROL(state)
#define BOARD_SD_PIN_CONFIG(speed, strength)
#define BOARD_USDHC_MMCCARD_POWER_CONTROL(enable)
#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT()
#define LLWU_SW_GPIO BOARD_SW2_GPIO
#define LLWU_SW_PORT BOARD_SW2_PORT
#define LLWU_SW_GPIO_PIN BOARD_SW2_GPIO_PIN
#define LLWU_SW_IRQ BOARD_SW2_IRQ
#define LLWU_SW_IRQ_HANDLER BOARD_SW2_IRQ_HANDLER
#define LLWU_SW_NAME BOARD_SW2_NAME
#define NMI_PIN 0U
#define JTAG_TCLK_PIN 1U
#define JTAG_TDI_PIN 2U
#define JTAG_TDO_PIN 3U
#define JTAG_TMS_PIN 4U
#define NMI_PORT PORTA
#define JTAG_TCLK_PORT PORTA
#define JTAG_TDI_PORT PORTA
#define JTAG_TDO_PORT PORTA
#define JTAG_TMS_PORT PORTA
#define NMI_GPIO GPIOA
#define JTAG_TCLK_GPIO GPIOA
#define JTAG_TDI_GPIO GPIOA
#define JTAG_TDO_GPIO GPIOA
#define JTAG_TMS_GPIO GPIOA
#define BOARD_SPI_FLASH_SCLK_PORT PORTB
#define BOARD_SPI_FLASH_SCLK_GPIO GPIOB
#define BOARD_SPI_FLASH_SCLK_GPIO_PIN 20U
#define BOARD_SPI_FLASH_SI_PORT PORTB
#define BOARD_SPI_FLASH_SI_GPIO GPIOB
#define BOARD_SPI_FLASH_SI_GPIO_PIN 21U
#define BOARD_SPI_FLASH_CS_PORT PORTB
#define BOARD_SPI_FLASH_CS_GPIO GPIOB
#define BOARD_SPI_FLASH_CS_GPIO_PIN 22U
#define BOARD_SPI_FLASH_SO_PORT PORTB
#define BOARD_SPI_FLASH_SO_GPIO GPIOB
#define BOARD_SPI_FLASH_SO_GPIO_PIN 24U
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*******************************************************************************
* API
******************************************************************************/
void BOARD_InitDebugConsole(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _BOARD_H_ */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/clock_config.c
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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
* Note: The clock could not be set when it is being used as system clock.
* In default out of reset, the CPU is clocked from FIRC(IRC48M),
* so before setting FIRC, change to use another avaliable clock source.
*
* 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
*
* 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
* Wait until the system clock source is changed to target source.
*
* 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
* corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
* Supported run mode and clock restrictions could be found in Reference Manual.
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v3.0
processor: RV32M1
package_id: RV32M1
mcu_data: ksdk2_0
processor_version: 0.0.0
board: RV32M1_VEGA
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "fsl_msmc.h"
#include "clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define SCG_LPFLL_DISABLE 0U /*!< LPFLL clock disabled */
#define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
* Code
******************************************************************************/
#ifndef SDK_SECONDARY_CORE
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_CONFIG_FircSafeConfig
* Description : This function is used to safely configure FIRC clock.
* In default out of reset, the CPU is clocked from FIRC(IRC48M).
* Before setting FIRC, change to use SIRC as system clock,
* then configure FIRC.
* Param fircConfig : FIRC configuration.
*
*END**************************************************************************/
static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
{
scg_sys_clk_config_t curConfig;
const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
.div1 = kSCG_AsyncClkDisable,
.div2 = kSCG_AsyncClkDivBy2,
.range = kSCG_SircRangeHigh};
scg_sys_clk_config_t sysClkSafeConfigSource = {
.divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
.divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
.src = kSCG_SysClkSrcSirc /* System clock source. */
};
/* Init Sirc */
CLOCK_InitSirc(&scgSircConfig);
/* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
/* Wait for clock source switch finished */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != sysClkSafeConfigSource.src);
/* Init Firc */
CLOCK_InitFirc(fircConfig);
}
#endif
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: Bus_clock.outFreq, value: 48 MHz}
- {id: Core_clock.outFreq, value: 48 MHz}
- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
- {id: LPO_CLK.outFreq, value: 1 kHz}
- {id: Platform_clock.outFreq, value: 48 MHz}
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
- {id: Slow_clock.outFreq, value: 24 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
settings:
- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
- {id: SCG.LPFLLDIV1.scale, value: '1', locked: true}
- {id: SCG.LPFLLDIV3.scale, value: '0', locked: true}
- {id: SCG.SIRCDIV1.scale, value: '0', locked: true}
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
{
.divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
.divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
.src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
};
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
{
.freq = 0U, /* System Oscillator frequency: 0Hz */
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
};
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
{
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
};
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
{
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
.trimConfig = NULL,
};
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
{
.enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
.div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
.range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
.trimConfig = NULL,
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
#ifndef SDK_SECONDARY_CORE
scg_sys_clk_config_t curConfig;
/* Init FIRC */
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
/* Set SCG to FIRC mode. */
CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
/* Wait for clock source switch finished */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
/* Init SIRC */
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
/* Init LPFLL */
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
#endif
}
/*******************************************************************************
********************* Configuration BOARD_BootClockHSRUN **********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockHSRUN
outputs:
- {id: Bus_clock.outFreq, value: 72 MHz}
- {id: Core_clock.outFreq, value: 72 MHz}
- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
- {id: LPO_CLK.outFreq, value: 1 kHz}
- {id: Platform_clock.outFreq, value: 72 MHz}
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
- {id: Slow_clock.outFreq, value: 8 MHz}
- {id: System_clock.outFreq, value: 72 MHz}
settings:
- {id: SCGMode, value: LPFLL}
- {id: powerMode, value: HSRUN}
- {id: SCG.DIVCORE.scale, value: '1', locked: true}
- {id: SCG.DIVSLOW.scale, value: '9'}
- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
- {id: SCG.LPFLLDIV1.scale, value: '0', locked: true}
- {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
- {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
- {id: SCG.TRIMDIV.scale, value: '24'}
- {id: SCG.TRIMSRCSEL.sel, value: SCG.FIRC}
- {id: 'SCG::RCCR[SCS].bitField', value: '5'}
- {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockHSRUN configuration
******************************************************************************/
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
{
.divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
.divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
.src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
};
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
{
.freq = 0U, /* System Oscillator frequency: 0Hz */
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
};
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
{
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
};
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
{
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
.trimConfig = NULL,
};
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockHSRUN =
{
.enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
.div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
.range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
.trimConfig = NULL,
};
/*******************************************************************************
* Code for BOARD_BootClockHSRUN configuration
******************************************************************************/
void BOARD_BootClockHSRUN(void)
{
#ifndef SDK_SECONDARY_CORE
scg_sys_clk_config_t curConfig;
/* Init FIRC */
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
/* Init LPFLL */
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockHSRUN);
#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
/* Set HSRUN power mode */
SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC0);
while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateHsrun)
{
}
#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC1);
while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateHsrun)
{
}
#endif
/* Set SCG to LPFLL mode. */
CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
/* Wait for clock source switch finished */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
/* Init SIRC */
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
#endif
}
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockVLPR
outputs:
- {id: Bus_clock.outFreq, value: 2 MHz}
- {id: Core_clock.outFreq, value: 4 MHz}
- {id: LPO_CLK.outFreq, value: 1 kHz}
- {id: Platform_clock.outFreq, value: 4 MHz}
- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
- {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
- {id: Slow_clock.outFreq, value: 4000/9 kHz}
- {id: System_clock.outFreq, value: 4 MHz}
settings:
- {id: SCGMode, value: SIRC}
- {id: powerMode, value: VLPR}
- {id: SCG.DIVBUS.scale, value: '2', locked: true}
- {id: SCG.DIVCORE.scale, value: '2', locked: true}
- {id: SCG.DIVSLOW.scale, value: '9'}
- {id: SCG.FIRCDIV1.scale, value: '1'}
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
- {id: SCG.SIRCDIV2.scale, value: '1', locked: true}
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockVLPR configuration
******************************************************************************/
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
{
.divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
.divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
.divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
.src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
};
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
{
.freq = 0U, /* System Oscillator frequency: 0Hz */
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
};
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
{
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
.div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
};
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
{
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
.trimConfig = NULL,
};
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR =
{
.enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
.div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
.range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
.trimConfig = NULL,
};
/*******************************************************************************
* Code for BOARD_BootClockVLPR configuration
******************************************************************************/
void BOARD_BootClockVLPR(void)
{
#ifndef SDK_SECONDARY_CORE
scg_sys_clk_config_t curConfig;
/* Init SIRC */
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
/* Set SCG to SIRC mode. */
CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
/* Init FIRC */
CLOCK_InitFirc(&g_scgFircConfig_BOARD_BootClockVLPR);
/* Init LPFLL */
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockVLPR);
#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
/* Set VLPR power mode. */
SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC0);
while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateVlpr)
{
}
#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
/* Set VLPR power mode. */
SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC1);
while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateVlpr)
{
}
#endif
/* Wait for clock source switch finished */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockVLPR.src);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
#endif
}
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/clock_config.h
+159
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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
/*! @brief SCG set for BOARD_BootClockRUN configuration.
*/
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
/*! @brief System OSC set for BOARD_BootClockRUN configuration.
*/
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
/*! @brief SIRC set for BOARD_BootClockRUN configuration.
*/
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
/*! @brief FIRC set for BOARD_BootClockRUN configuration.
*/
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
*/
extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************* Configuration BOARD_BootClockHSRUN **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockHSRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 72000000U /*!< Core clock frequency: 72000000Hz */
/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockHSRUN;
/*******************************************************************************
* API for BOARD_BootClockHSRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockHSRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockVLPR configuration
******************************************************************************/
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */
/*! @brief SCG set for BOARD_BootClockVLPR configuration.
*/
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
*/
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
*/
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
*/
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
*/
extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockVLPR;
/*******************************************************************************
* API for BOARD_BootClockVLPR configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockVLPR(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/readme.txt
+48
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Overview
========
The Hello World demo application provides a sanity check for the new SDK build environments and board bring up. The Hello
World demo prints the "Hello World" string to the terminal using the SDK UART drivers. The purpose of this demo is to
show how to use the UART, and to provide a simple project for debugging and further development.
Toolchain supported
===================
- GCC RISC-V Embedded 7.1.1
- RISC-V Eclipse IDE 4.7.2
Hardware requirements
=====================
- Mini/micro USB cable
- RV32M1-VEGA board
- Personal Computer
Board settings
==============
No special settings are required.
If download M0+ core project, need to let MCU boot from M0+ core, please follow below steps:
1. Download blhost.exe from www.nxp.com/kboot.
2. Connect J8 on board to PC using USB cable.
3. After PC recognize the USB HID device, go to blhost.exe folder, open command line.
4. Run command "blhost.exe -u -- flash-erase-all-unsecure", it will erase the flash on chip.
5. Run command "blhost.exe -u -- flash-program-once 0x84 4 ffffffbf", set FOPT3 to boot from M0+ core.
Prepare the Demo
================
1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
2. Open a serial terminal with the following settings:
- 115200 baud rate
- 8 data bits
- No parity
- One stop bit
- No flow control
3. Download the program to the target board.
4. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Running the demo
================
The log below shows the output of the hello world demo in the terminal window:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
hello world.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Customization options
=====================
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_ri5cy.h
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_ri5cy_features.h
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy.h
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy_features.h
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.c
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.h
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.c
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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#include "fsl_debug_console.h"
#ifndef NDEBUG
#if (defined(__CC_ARM)) || (defined(__ICCARM__))
void __aeabi_assert(const char *failedExpr, const char *file, int line)
{
PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
for (;;)
{
__BKPT(0);
}
}
#elif(defined(__GNUC__))
void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
{
PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
for (;;)
{
__BKPT(0);
}
}
#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
#endif /* NDEBUG */
#ifndef __GIC_PRIO_BITS
#ifndef __riscv
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__CC_ARM)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
#elif defined(__ICCARM__)
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
#elif defined(__GNUC__)
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
#endif /* defined(__CC_ARM) */
uint32_t n;
uint32_t ret;
uint32_t irqMaskValue;
irqMaskValue = DisableGlobalIRQ();
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
{
/* Copy the vector table from ROM to RAM */
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
{
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the position of vector table */
SCB->VTOR = (uint32_t)__VECTOR_RAM;
}
ret = __VECTOR_RAM[irq + 16];
/* make sure the __VECTOR_RAM is noncachable */
__VECTOR_RAM[irq + 16] = irqHandler;
EnableGlobalIRQ(irqMaskValue);
return ret;
}
#endif
#endif
#ifndef QN908XC_SERIES
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
void EnableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t index = 0;
uint32_t intNumber = (uint32_t)interrupt;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERSET[index] = 1u << intNumber;
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
}
void DisableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t index = 0;
uint32_t intNumber = (uint32_t)interrupt;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
SYSCON->STARTERCLR[index] = 1u << intNumber;
}
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
#endif /* QN908XC_SERIES */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.h
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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_COMMON_H_
#define _FSL_COMMON_H_
#include <assert.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#if defined(__ICCARM__)
#include <stddef.h>
#endif
#include "fsl_device_registers.h"
/*!
* @addtogroup ksdk_common
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Construct a status code value from a group and code number. */
#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
/*! @brief Construct the version number for drivers. */
#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
/*! @name Driver version */
/*@{*/
/*! @brief common driver version 2.0.0. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* Debug console type definition. */
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */
/*! @brief Status group numbers. */
enum _status_groups
{
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
};
/*! @brief Generic status return codes. */
enum _generic_status
{
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
};
/*! @brief Type used for all status and error return values. */
typedef int32_t status_t;
/*
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
* defined in previous of this file.
*/
#include "fsl_clock.h"
/*
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
*/
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
#include "fsl_reset.h"
#endif
/*! @name Min/max macros */
/* @{ */
#if !defined(MIN)
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#endif
#if !defined(MAX)
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#endif
/* @} */
/*! @brief Computes the number of elements in an array. */
#if !defined(ARRAY_SIZE)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
/*! @name UINT16_MAX/UINT32_MAX value */
/* @{ */
#if !defined(UINT16_MAX)
#define UINT16_MAX ((uint16_t)-1)
#endif
#if !defined(UINT32_MAX)
#define UINT32_MAX ((uint32_t)-1)
#endif
/* @} */
/*! @name Timer utilities */
/* @{ */
/*! Macro to convert a microsecond period to raw count value */
#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
/*! Macro to convert a raw count value to microsecond */
#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
/*! Macro to convert a millisecond period to raw count value */
#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
/*! Macro to convert a raw count value to millisecond */
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
/* @} */
/*! @name Alignment variable definition macros */
/* @{ */
#if (defined(__ICCARM__))
/**
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
* http://supp.iar.com/Support/?note=24725
*/
_Pragma("diag_suppress=Pm120")
#define SDK_PRAGMA(x) _Pragma(#x)
_Pragma("diag_error=Pm120")
/*! Macro to define a variable with alignbytes alignment */
#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
/*! Macro to define a variable with L1 d-cache line size alignment */
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
#endif
/*! Macro to define a variable with L2 cache line size alignment */
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
#endif
#elif defined(__CC_ARM)
/*! Macro to define a variable with alignbytes alignment */
#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
/*! Macro to define a variable with L1 d-cache line size alignment */
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
#endif
/*! Macro to define a variable with L2 cache line size alignment */
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
#endif
#elif defined(__GNUC__)
/*! Macro to define a variable with alignbytes alignment */
#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
/*! Macro to define a variable with L1 d-cache line size alignment */
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
#endif
/*! Macro to define a variable with L2 cache line size alignment */
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
#endif
#else
#error Toolchain not supported
#define SDK_ALIGN(var, alignbytes) var
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) var
#endif
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) var
#endif
#endif
/*! Macro to change a value to a given size aligned value */
#define SDK_SIZEALIGN(var, alignbytes) \
((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
/* @} */
/*! @name Non-cacheable region definition macros */
/* @{ */
#if (defined(__ICCARM__))
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
#else
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
#endif
#elif(defined(__CC_ARM))
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
__attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
#else
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
#endif
#elif(defined(__GNUC__))
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
*/
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
__attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))
#else
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
#endif
#else
#error Toolchain not supported.
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
#endif
/* @} */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Enable specific interrupt.
*
* Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
* levels. For example, there are NVIC and intmux. Here the interrupts connected
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
* to NVIC first then routed to core.
*
* This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
*
* @param interrupt The IRQ number.
* @retval kStatus_Success Interrupt enabled successfully
* @retval kStatus_Fail Failed to enable the interrupt
*/
static inline status_t EnableIRQ(IRQn_Type interrupt)
{
if (NotAvail_IRQn == interrupt)
{
return kStatus_Fail;
}
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
{
return kStatus_Fail;
}
#endif
#if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0)
EVENT_UNIT->INTPTEN |= (uint32_t)(1 << interrupt);
/* Read back to make sure write finished. */
(void)EVENT_UNIT->INTPTEN;
#else
#if defined(__GIC_PRIO_BITS)
GIC_EnableIRQ(interrupt);
#else
NVIC_EnableIRQ(interrupt);
#endif
#endif
return kStatus_Success;
}
/*!
* @brief Disable specific interrupt.
*
* Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
* levels. For example, there are NVIC and intmux. Here the interrupts connected
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
* to NVIC first then routed to core.
*
* This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
*
* @param interrupt The IRQ number.
* @retval kStatus_Success Interrupt disabled successfully
* @retval kStatus_Fail Failed to disable the interrupt
*/
static inline status_t DisableIRQ(IRQn_Type interrupt)
{
if (NotAvail_IRQn == interrupt)
{
return kStatus_Fail;
}
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
{
return kStatus_Fail;
}
#endif
#if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0)
EVENT_UNIT->INTPTEN &= ~(uint32_t)(1 << interrupt);
/* Read back to make sure write finished. */
(void)EVENT_UNIT->INTPTEN;
#else
#if defined(__GIC_PRIO_BITS)
GIC_DisableIRQ(interrupt);
#else
NVIC_DisableIRQ(interrupt);
#endif
#endif
return kStatus_Success;
}
/*!
* @brief Disable the global IRQ
*
* Disable the global interrupt and return the current primask register. User is required to provided the primask
* register for the EnableGlobalIRQ().
*
* @return Current primask value.
*/
static inline uint32_t DisableGlobalIRQ(void)
{
#ifndef __riscv
#if defined(CPSR_I_Msk)
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
__disable_irq();
return cpsr;
#else
uint32_t regPrimask = __get_PRIMASK();
__disable_irq();
return regPrimask;
#endif
#else
uint32_t mstatus;
__ASM volatile ("csrrci %0, mstatus, 8" : "=r"(mstatus));
return mstatus;
#endif
}
/*!
* @brief Enaable the global IRQ
*
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
* convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
*
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
* DisableGlobalIRQ().
*/
static inline void EnableGlobalIRQ(uint32_t primask)
{
#ifndef __riscv
#if defined(CPSR_I_Msk)
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
#else
__set_PRIMASK(primask);
#endif
#else
__ASM volatile ("csrw mstatus, %0" : : "r"(primask));
#endif
}
/*!
* @brief install IRQ handler
*
* @param irq IRQ number
* @param irqHandler IRQ handler address
* @return The old IRQ handler address
*/
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
/*!
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
*
* Enable the interrupt for wake-up from deep sleep mode.
* Some interrupts are typically used in sleep mode only and will not occur during
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
* those clocks (significantly increasing power consumption in the reduced power mode),
* making these wake-ups possible.
*
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
*
* @param interrupt The IRQ number.
*/
void EnableDeepSleepIRQ(IRQn_Type interrupt);
/*!
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
*
* Disable the interrupt for wake-up from deep sleep mode.
* Some interrupts are typically used in sleep mode only and will not occur during
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
* those clocks (significantly increasing power consumption in the reduced power mode),
* making these wake-ups possible.
*
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
*
* @param interrupt The IRQ number.
*/
void DisableDeepSleepIRQ(IRQn_Type interrupt);
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
#if defined(__cplusplus)
}
#endif
/*! @} */
#endif /* _FSL_COMMON_H_ */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.c
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_gpio.h"
/*******************************************************************************
* Variables
******************************************************************************/
static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Array to map FGPIO instance number to clock name. */
static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Gets the GPIO instance according to the GPIO base
*
* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
* @retval GPIO instance
*/
static uint32_t GPIO_GetInstance(GPIO_Type *base);
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t GPIO_GetInstance(GPIO_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
{
if (s_gpioBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_gpioBases));
return instance;
}
void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
{
assert(config);
if (config->pinDirection == kGPIO_DigitalInput)
{
base->PDDR &= ~(1U << pin);
}
else
{
GPIO_WritePinOutput(base, pin, config->outputLogic);
base->PDDR |= (1U << pin);
}
}
uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)
{
uint8_t instance;
PORT_Type *portBase;
instance = GPIO_GetInstance(base);
portBase = s_portBases[instance];
return portBase->ISFR;
}
void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
{
uint8_t instance;
PORT_Type *portBase;
instance = GPIO_GetInstance(base);
portBase = s_portBases[instance];
portBase->ISFR = mask;
}
#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
{
base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
}
#endif
#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
/*******************************************************************************
* Variables
******************************************************************************/
static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Gets the FGPIO instance according to the GPIO base
*
* @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
* @retval FGPIO instance
*/
static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++)
{
if (s_fgpioBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_fgpioBases));
return instance;
}
#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
void FGPIO_Init(FGPIO_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Ungate FGPIO periphral clock */
CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
{
assert(config);
if (config->pinDirection == kGPIO_DigitalInput)
{
base->PDDR &= ~(1U << pin);
}
else
{
FGPIO_WritePinOutput(base, pin, config->outputLogic);
base->PDDR |= (1U << pin);
}
}
uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base)
{
uint8_t instance;
instance = FGPIO_GetInstance(base);
PORT_Type *portBase;
portBase = s_portBases[instance];
return portBase->ISFR;
}
void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask)
{
uint8_t instance;
instance = FGPIO_GetInstance(base);
PORT_Type *portBase;
portBase = s_portBases[instance];
portBase->ISFR = mask;
}
#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
{
base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) |
(attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT);
}
#endif
#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.h
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_GPIO_H_
#define _FSL_GPIO_H_
#include "fsl_common.h"
/*!
* @addtogroup gpio
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief GPIO driver version 2.2.0. */
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
/*@}*/
/*! @brief GPIO direction definition */
typedef enum _gpio_pin_direction
{
kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
} gpio_pin_direction_t;
#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
/*! @brief GPIO checker attribute */
typedef enum _gpio_checker_attribute
{
kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW =
0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */
kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW =
0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */
kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW =
0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */
kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW =
0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */
kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW =
0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */
kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW =
0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */
kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR =
0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */
kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN =
0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */
kGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */
} gpio_checker_attribute_t;
#endif
/*!
* @brief The GPIO pin configuration structure.
*
* Each pin can only be configured as either an output pin or an input pin at a time.
* If configured as an input pin, leave the outputConfig unused.
* Note that in some use cases, the corresponding port property should be configured in advance
* with the PORT_SetPinConfig().
*/
typedef struct _gpio_pin_config
{
gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
/* Output configurations; ignore if configured as an input pin */
uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
} gpio_pin_config_t;
/*! @} */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @addtogroup gpio_driver
* @{
*/
/*! @name GPIO Configuration */
/*@{*/
/*!
* @brief Initializes a GPIO pin used by the board.
*
* To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
* Then, call the GPIO_PinInit() function.
*
* This is an example to define an input pin or an output pin configuration.
* @code
* // Define a digital input pin configuration,
* gpio_pin_config_t config =
* {
* kGPIO_DigitalInput,
* 0,
* }
* //Define a digital output pin configuration,
* gpio_pin_config_t config =
* {
* kGPIO_DigitalOutput,
* 0,
* }
* @endcode
*
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
* @param pin GPIO port pin number
* @param config GPIO pin configuration pointer
*/
void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
/*@}*/
/*! @name GPIO Output Operations */
/*@{*/
/*!
* @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
*
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
* @param pin GPIO pin number
* @param output GPIO pin output logic level.
* - 0: corresponding pin output low-logic level.
* - 1: corresponding pin output high-logic level.
*/
static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
{
if (output == 0U)
{
base->PCOR = 1U << pin;
}
else
{
base->PSOR = 1U << pin;
}
}
/*!
* @brief Sets the output level of the multiple GPIO pins to the logic 1.
*
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
* @param mask GPIO pin number macro
*/
static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
{
base->PSOR = mask;
}
/*!
* @brief Sets the output level of the multiple GPIO pins to the logic 0.
*
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
* @param mask GPIO pin number macro
*/
static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
{
base->PCOR = mask;
}
/*!
* @brief Reverses the current output logic of the multiple GPIO pins.
*
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
* @param mask GPIO pin number macro
*/
static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask)
{
base->PTOR = mask;
}
/*@}*/
/*! @name GPIO Input Operations */
/*@{*/
/*!
* @brief Reads the current input value of the GPIO port.
*
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
* @param pin GPIO pin number
* @retval GPIO port input value
* - 0: corresponding pin input low-logic level.
* - 1: corresponding pin input high-logic level.
*/
static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
{
return (((base->PDIR) >> pin) & 0x01U);
}
/*@}*/
/*! @name GPIO Interrupt */
/*@{*/
/*!
* @brief Reads the GPIO port interrupt status flag.
*
* If a pin is configured to generate the DMA request, the corresponding flag
* is cleared automatically at the completion of the requested DMA transfer.
* Otherwise, the flag remains set until a logic one is written to that flag.
* If configured for a level sensitive interrupt that remains asserted, the flag
* is set again immediately.
*
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
* @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
* pin 0 and 17 have the interrupt.
*/
uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base);
/*!
* @brief Clears multiple GPIO pin interrupt status flags.
*
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
* @param mask GPIO pin number macro
*/
void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
/*!
* @brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
* words. Each 32-bit data port includes a GACR register, which defines the byte-level
* attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
* bytes in the GACR follow a standard little endian
* data convention.
*
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
* @param mask GPIO pin number macro
*/
void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
#endif
/*@}*/
/*! @} */
/*!
* @addtogroup fgpio_driver
* @{
*/
/*
* Introduces the FGPIO feature.
*
* The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT
* interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and
* complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
*/
#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
/*! @name FGPIO Configuration */
/*@{*/
/*!
* @brief Initializes the FGPIO peripheral.
*
* This function ungates the FGPIO clock.
*
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
*/
void FGPIO_Init(FGPIO_Type *base);
/*!
* @brief Initializes a FGPIO pin used by the board.
*
* To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
* Then, call the FGPIO_PinInit() function.
*
* This is an example to define an input pin or an output pin configuration:
* @code
* // Define a digital input pin configuration,
* gpio_pin_config_t config =
* {
* kGPIO_DigitalInput,
* 0,
* }
* //Define a digital output pin configuration,
* gpio_pin_config_t config =
* {
* kGPIO_DigitalOutput,
* 0,
* }
* @endcode
*
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
* @param pin FGPIO port pin number
* @param config FGPIO pin configuration pointer
*/
void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
/*@}*/
/*! @name FGPIO Output Operations */
/*@{*/
/*!
* @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
*
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
* @param pin FGPIO pin number
* @param output FGPIOpin output logic level.
* - 0: corresponding pin output low-logic level.
* - 1: corresponding pin output high-logic level.
*/
static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output)
{
if (output == 0U)
{
base->PCOR = 1 << pin;
}
else
{
base->PSOR = 1 << pin;
}
}
/*!
* @brief Sets the output level of the multiple FGPIO pins to the logic 1.
*
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
* @param mask FGPIO pin number macro
*/
static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask)
{
base->PSOR = mask;
}
/*!
* @brief Sets the output level of the multiple FGPIO pins to the logic 0.
*
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
* @param mask FGPIO pin number macro
*/
static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask)
{
base->PCOR = mask;
}
/*!
* @brief Reverses the current output logic of the multiple FGPIO pins.
*
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
* @param mask FGPIO pin number macro
*/
static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask)
{
base->PTOR = mask;
}
/*@}*/
/*! @name FGPIO Input Operations */
/*@{*/
/*!
* @brief Reads the current input value of the FGPIO port.
*
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
* @param pin FGPIO pin number
* @retval FGPIO port input value
* - 0: corresponding pin input low-logic level.
* - 1: corresponding pin input high-logic level.
*/
static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin)
{
return (((base->PDIR) >> pin) & 0x01U);
}
/*@}*/
/*! @name FGPIO Interrupt */
/*@{*/
/*!
* @brief Reads the FGPIO port interrupt status flag.
*
* If a pin is configured to generate the DMA request, the corresponding flag
* is cleared automatically at the completion of the requested DMA transfer.
* Otherwise, the flag remains set until a logic one is written to that flag.
* If configured for a level-sensitive interrupt that remains asserted, the flag
* is set again immediately.
*
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
* @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
* pin 0 and 17 have the interrupt.
*/
uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base);
/*!
* @brief Clears the multiple FGPIO pin interrupt status flag.
*
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
* @param mask FGPIO pin number macro
*/
void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask);
#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
/*!
* @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
* words. Each 32-bit data port includes a GACR register, which defines the byte-level
* attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
* bytes in the GACR follow a standard little endian
* data convention.
*
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
* @param mask FGPIO pin number macro
*/
void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
#endif
/*@}*/
#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _FSL_GPIO_H_*/
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.c
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.h
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.c
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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_msmc.h"
#if defined(__riscv)
#define CONFIG_NORMAL_SLEEP EVENT_UNIT->SLPCTRL = (EVENT_UNIT->SLPCTRL & ~0x03) | (1 << 0)
#define CONFIG_DEEP_SLEEP EVENT_UNIT->SLPCTRL |= 0x03;
#else
#define CONFIG_NORMAL_SLEEP SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk
#define CONFIG_DEEP_SLEEP SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk
#endif
status_t SMC_SetPowerModeRun(SMC_Type *base)
{
uint32_t reg;
reg = base->PMCTRL;
/* configure Normal RUN mode */
reg &= ~SMC_PMCTRL_RUNM_MASK;
reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT);
base->PMCTRL = reg;
return kStatus_Success;
}
status_t SMC_SetPowerModeHsrun(SMC_Type *base)
{
uint32_t reg;
reg = base->PMCTRL;
/* configure High Speed RUN mode */
reg &= ~SMC_PMCTRL_RUNM_MASK;
reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT);
base->PMCTRL = reg;
return kStatus_Success;
}
status_t SMC_SetPowerModeWait(SMC_Type *base)
{
/* configure Normal Wait mode */
CONFIG_NORMAL_SLEEP;
__DSB();
__WFI();
__ISB();
return kStatus_Success;
}
status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option)
{
uint32_t reg;
/* configure the Partial Stop mode in Noraml Stop mode */
reg = base->PMCTRL;
reg &= ~(SMC_PMCTRL_PSTOPO_MASK | SMC_PMCTRL_STOPM_MASK);
reg |= ((uint32_t)option << SMC_PMCTRL_PSTOPO_SHIFT) | (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT);
base->PMCTRL = reg;
/* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */
CONFIG_DEEP_SLEEP;
/* read back to make sure the configuration valid before entering stop mode */
(void)base->PMCTRL;
__DSB();
__WFI();
__ISB();
#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA)
/* check whether the power mode enter Stop mode succeed */
if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
{
return kStatus_SMC_StopAbort;
}
else
{
return kStatus_Success;
}
#else
return kStatus_Success;
#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */
}
status_t SMC_SetPowerModeVlpr(SMC_Type *base)
{
uint32_t reg;
reg = base->PMCTRL;
/* configure VLPR mode */
reg &= ~SMC_PMCTRL_RUNM_MASK;
reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT);
base->PMCTRL = reg;
return kStatus_Success;
}
status_t SMC_SetPowerModeVlpw(SMC_Type *base)
{
/* configure VLPW mode */
/* Clear the SLEEPDEEP bit to disable deep sleep mode */
CONFIG_NORMAL_SLEEP;
__DSB();
__WFI();
__ISB();
return kStatus_Success;
}
status_t SMC_SetPowerModeVlps(SMC_Type *base)
{
uint32_t reg;
/* configure VLPS mode */
reg = base->PMCTRL;
reg &= ~SMC_PMCTRL_STOPM_MASK;
reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT);
base->PMCTRL = reg;
/* Set the SLEEPDEEP bit to enable deep sleep mode */
CONFIG_DEEP_SLEEP;
/* read back to make sure the configuration valid before enter stop mode */
(void)base->PMCTRL;
__DSB();
__WFI();
__ISB();
#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA)
/* check whether the power mode enter Stop mode succeed */
if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
{
return kStatus_SMC_StopAbort;
}
else
{
return kStatus_Success;
}
#else
return kStatus_Success;
#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */
}
status_t SMC_SetPowerModeLls(SMC_Type *base)
{
uint32_t reg;
/* configure to LLS mode */
reg = base->PMCTRL;
reg &= ~SMC_PMCTRL_STOPM_MASK;
reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT);
base->PMCTRL = reg;
/* Set the SLEEPDEEP bit to enable deep sleep mode */
CONFIG_DEEP_SLEEP;
/* read back to make sure the configuration valid before entering stop mode */
(void)base->PMCTRL;
__DSB();
__WFI();
__ISB();
#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA)
/* check whether the power mode enter Stop mode succeed */
if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
{
return kStatus_SMC_StopAbort;
}
else
{
return kStatus_Success;
}
#else
return kStatus_Success;
#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */
}
#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
status_t SMC_SetPowerModeVlls0(SMC_Type *base)
{
uint32_t reg;
/* configure to VLLS mode */
reg = base->PMCTRL;
reg &= ~SMC_PMCTRL_STOPM_MASK;
reg |= (kSMC_StopVlls0 << SMC_PMCTRL_STOPM_SHIFT);
base->PMCTRL = reg;
/* Set the SLEEPDEEP bit to enable deep sleep mode */
CONFIG_DEEP_SLEEP;
/* read back to make sure the configuration valid before enter stop mode */
(void)base->PMCTRL;
__DSB();
__WFI();
__ISB();
return kStatus_Success;
}
#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
status_t SMC_SetPowerModeVlls2(SMC_Type *base)
{
uint32_t reg;
/* configure to VLLS mode */
reg = base->PMCTRL;
reg &= ~SMC_PMCTRL_STOPM_MASK;
reg |= (kSMC_StopVlls2 << SMC_PMCTRL_STOPM_SHIFT);
base->PMCTRL = reg;
/* Set the SLEEPDEEP bit to enable deep sleep mode */
CONFIG_DEEP_SLEEP;
/* read back to make sure the configuration valid before enter stop mode */
(void)base->PMCTRL;
__DSB();
__WFI();
__ISB();
return kStatus_Success;
}
#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
#else /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
status_t SMC_SetPowerModeVlls(SMC_Type *base)
{
uint32_t reg;
/* configure to VLLS mode */
reg = base->PMCTRL;
reg &= ~SMC_PMCTRL_STOPM_MASK;
reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT);
base->PMCTRL = reg;
#if defined(__riscv)
EVENT->SCR = (EVENT->SCR & ~0x03) | (1 << 1);
#else
/* Set the SLEEPDEEP bit to enable deep sleep mode */
CONFIG_DEEP_SLEEP;
#endif
/* read back to make sure the configuration valid before enter stop mode */
(void)base->PMCTRL;
__DSB();
__WFI();
__ISB();
#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA)
/* check whether the power mode enter Stop mode succeed */
if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
{
return kStatus_SMC_StopAbort;
}
else
{
return kStatus_Success;
}
#else
return kStatus_Success;
#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */
}
#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
void SMC_ConfigureResetPinFilter(SMC_Type *base, const smc_reset_pin_filter_config_t *config)
{
assert(config);
uint32_t reg;
reg = SMC_RPC_FILTCFG(config->slowClockFilterCount) | SMC_RPC_FILTEN(config->enableFilter);
#if (defined(FSL_FEATURE_SMC_HAS_RPC_LPOFEN) && FSL_FEATURE_SMC_HAS_RPC_LPOFEN)
if (config->enableLpoFilter)
{
reg |= SMC_RPC_LPOFEN_MASK;
}
#endif /* FSL_FEATURE_SMC_HAS_RPC_LPOFEN */
base->RPC = reg;
}
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_PORT_H_
#define _FSL_PORT_H_
#include "fsl_common.h"
/*!
* @addtogroup port
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! Version 2.0.2. */
#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
/*! @brief Internal resistor pull feature selection */
enum _port_pull
{
kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */
kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */
};
#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
/*! @brief Slew rate selection */
enum _port_slew_rate
{
kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
};
#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
/*! @brief Open Drain feature enable/disable */
enum _port_open_drain_enable
{
kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */
};
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
/*! @brief Passive filter feature enable/disable */
enum _port_passive_filter_enable
{
kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */
};
#endif
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
/*! @brief Configures the drive strength. */
enum _port_drive_strength
{
kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */
kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
};
#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
/*! @brief Unlock/lock the pin control register field[15:0] */
enum _port_lock_register
{
kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */
};
#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
/*! @brief Pin mux selection */
typedef enum _port_mux
{
kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */
kPORT_MuxAlt2 = 2U, /*!< Chip-specific */
kPORT_MuxAlt3 = 3U, /*!< Chip-specific */
kPORT_MuxAlt4 = 4U, /*!< Chip-specific */
kPORT_MuxAlt5 = 5U, /*!< Chip-specific */
kPORT_MuxAlt6 = 6U, /*!< Chip-specific */
kPORT_MuxAlt7 = 7U, /*!< Chip-specific */
kPORT_MuxAlt8 = 8U, /*!< Chip-specific */
kPORT_MuxAlt9 = 9U, /*!< Chip-specific */
kPORT_MuxAlt10 = 10U, /*!< Chip-specific */
kPORT_MuxAlt11 = 11U, /*!< Chip-specific */
kPORT_MuxAlt12 = 12U, /*!< Chip-specific */
kPORT_MuxAlt13 = 13U, /*!< Chip-specific */
kPORT_MuxAlt14 = 14U, /*!< Chip-specific */
kPORT_MuxAlt15 = 15U, /*!< Chip-specific */
} port_mux_t;
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
/*! @brief Configures the interrupt generation condition. */
typedef enum _port_interrupt
{
kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
#endif
#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG
kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
#endif
kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */
#endif
} port_interrupt_t;
#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
/*! @brief Digital filter clock source selection */
typedef enum _port_digital_filter_clock_source
{
kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
} port_digital_filter_clock_source_t;
/*! @brief PORT digital filter feature configuration definition */
typedef struct _port_digital_filter_config
{
uint32_t digitalFilterWidth; /*!< Set digital filter width */
port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
} port_digital_filter_config_t;
#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
/*! @brief PORT pin configuration structure */
typedef struct _port_pin_config
{
#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
#else
uint16_t : 2;
#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
#else
uint16_t : 1;
#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
uint16_t : 1;
#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
#else
uint16_t : 1;
#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
#else
uint16_t : 1;
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
#else
uint16_t : 1;
#endif
uint16_t : 1;
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3)
uint16_t mux : 3; /*!< Pin mux Configure */
uint16_t : 4;
#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4)
uint16_t mux : 4; /*!< Pin mux Configure */
uint16_t : 3;
#else
uint16_t : 7,
#endif
#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
#else
uint16_t : 1;
#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
} port_pin_config_t;
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
/*! @name Configuration */
/*@{*/
/*!
* @brief Sets the port PCR register.
*
* This is an example to define an input pin or output pin PCR configuration.
* @code
* // Define a digital input pin PCR configuration
* port_pin_config_t config = {
* kPORT_PullUp,
* kPORT_FastSlewRate,
* kPORT_PassiveFilterDisable,
* kPORT_OpenDrainDisable,
* kPORT_LowDriveStrength,
* kPORT_MuxAsGpio,
* kPORT_UnLockRegister,
* };
* @endcode
*
* @param base PORT peripheral base pointer.
* @param pin PORT pin number.
* @param config PORT PCR register configuration structure.
*/
static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
{
assert(config);
uint32_t addr = (uint32_t)&base->PCR[pin];
*(volatile uint16_t *)(addr) = *((const uint16_t *)config);
}
/*!
* @brief Sets the port PCR register for multiple pins.
*
* This is an example to define input pins or output pins PCR configuration.
* @code
* // Define a digital input pin PCR configuration
* port_pin_config_t config = {
* kPORT_PullUp ,
* kPORT_PullEnable,
* kPORT_FastSlewRate,
* kPORT_PassiveFilterDisable,
* kPORT_OpenDrainDisable,
* kPORT_LowDriveStrength,
* kPORT_MuxAsGpio,
* kPORT_UnlockRegister,
* };
* @endcode
*
* @param base PORT peripheral base pointer.
* @param mask PORT pin number macro.
* @param config PORT PCR register configuration structure.
*/
static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
{
assert(config);
uint16_t pcrl = *((const uint16_t *)config);
if (mask & 0xffffU)
{
base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
}
if (mask >> 16)
{
base->GPCHR = (mask & 0xffff0000U) | pcrl;
}
}
#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG
/*!
* @brief Sets the port interrupt configuration in PCR register for multiple pins.
*
* @param base PORT peripheral base pointer.
* @param mask PORT pin number macro.
* @param config PORT pin interrupt configuration.
* - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
* - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
* - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
* - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
* - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
* - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
* - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
* - #kPORT_InterruptLogicZero : Interrupt when logic zero.
* - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
* - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
* - #kPORT_InterruptEitherEdge : Interrupt on either edge.
* - #kPORT_InterruptLogicOne : Interrupt when logic one.
* - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
* - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit)..
*/
static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config)
{
assert(config);
if (mask & 0xffffU)
{
base->GICLR = (config << 16) | (mask & 0xffffU);
}
if (mask >> 16)
{
base->GICHR = (config << 16) | (mask & 0xffff0000U);
}
}
#endif
/*!
* @brief Configures the pin muxing.
*
* @param base PORT peripheral base pointer.
* @param pin PORT pin number.
* @param mux pin muxing slot selection.
* - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
* - #kPORT_MuxAsGpio : Set as GPIO.
* - #kPORT_MuxAlt2 : chip-specific.
* - #kPORT_MuxAlt3 : chip-specific.
* - #kPORT_MuxAlt4 : chip-specific.
* - #kPORT_MuxAlt5 : chip-specific.
* - #kPORT_MuxAlt6 : chip-specific.
* - #kPORT_MuxAlt7 : chip-specific.
* @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
* the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
* reset to zero : kPORT_PinDisabledOrAnalog).
* This function is recommended to use to reset the pin mux
*
*/
static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
{
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
}
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
/*!
* @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
*
* @param base PORT peripheral base pointer.
* @param mask PORT pin number macro.
*/
static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
{
if (enable == true)
{
base->DFER |= mask;
}
else
{
base->DFER &= ~mask;
}
}
/*!
* @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
*
* @param base PORT peripheral base pointer.
* @param config PORT digital filter configuration structure.
*/
static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
{
assert(config);
base->DFCR = PORT_DFCR_CS(config->clockSource);
base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
}
#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
/*@}*/
/*! @name Interrupt */
/*@{*/
/*!
* @brief Configures the port pin interrupt/DMA request.
*
* @param base PORT peripheral base pointer.
* @param pin PORT pin number.
* @param config PORT pin interrupt configuration.
* - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
* - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
* - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
* - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
* - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
* - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
* - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
* - #kPORT_InterruptLogicZero : Interrupt when logic zero.
* - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
* - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
* - #kPORT_InterruptEitherEdge : Interrupt on either edge.
* - #kPORT_InterruptLogicOne : Interrupt when logic one.
* - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
* - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).
*/
static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
{
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
}
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
/*!
* @brief Configures the port pin drive strength.
*
* @param base PORT peripheral base pointer.
* @param pin PORT pin number.
* @param config PORT pin drive strength
* - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured.
* - #kPORT_HighDriveStrength = 1U - High-drive strength is configured.
*/
static inline void PORT_SetPinDriveStrength(PORT_Type* base, uint32_t pin, uint8_t strength)
{
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength);
}
#endif
/*!
* @brief Reads the whole port status flag.
*
* If a pin is configured to generate the DMA request, the corresponding flag
* is cleared automatically at the completion of the requested DMA transfer.
* Otherwise, the flag remains set until a logic one is written to that flag.
* If configured for a level sensitive interrupt that remains asserted, the flag
* is set again immediately.
*
* @param base PORT peripheral base pointer.
* @return Current port interrupt status flags, for example, 0x00010001 means the
* pin 0 and 16 have the interrupt.
*/
static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
{
return base->ISFR;
}
/*!
* @brief Clears the multiple pin interrupt status flag.
*
* @param base PORT peripheral base pointer.
* @param mask PORT pin number macro.
*/
static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
{
base->ISFR = mask;
}
/*@}*/
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_PORT_H_ */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/fsl_device_registers.h
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/*
* Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef __FSL_DEVICE_REGISTERS_H__
#define __FSL_DEVICE_REGISTERS_H__
/*
* Include the cpu specific register header files.
*
* The CPU macro should be declared in the project or makefile.
*/
#if defined(CPU_RV32M1_cm0plus)
#define RV32M1_cm0plus_SERIES
/* CMSIS-style register definitions */
#include "RV32M1_cm0plus.h"
/* CPU specific feature definitions */
#include "RV32M1_cm0plus_features.h"
#elif defined(CPU_RV32M1_cm4)
#define RV32M1_cm4_SERIES
/* CMSIS-style register definitions */
#include "RV32M1_cm4.h"
/* CPU specific feature definitions */
#include "RV32M1_cm4_features.h"
#elif defined(CPU_RV32M1_zero_riscy)
#define RV32M1_zero_riscy_SERIES
/* CMSIS-style register definitions */
#include "RV32M1_zero_riscy.h"
/* CPU specific feature definitions */
#include "RV32M1_zero_riscy_features.h"
#elif defined(CPU_RV32M1_ri5cy)
#define RV32M1_ri5cy_SERIES
/* CMSIS-style register definitions */
#include "RV32M1_ri5cy.h"
/* CPU specific feature definitions */
#include "RV32M1_ri5cy_features.h"
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DEVICE_REGISTERS_H__ */
/*******************************************************************************
* EOF
******************************************************************************/
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_ri5cy.S
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/* ------------------------------------------------------------------------- */
/* @file: startup_RV32M1_ri5cy.s */
/* @purpose: RI5CY Core Device Startup File */
/* RV32M1_ri5cy */
/* @version: 1.0 */
/* @date: 2018-10-2 */
/* @build: b180926 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2018 NXP */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
.extern freertos_risc_v_trap_handler
#define EXCEPTION_STACK_SIZE 0x58
.text
.section .vectors, "ax"
.option norvc;
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
jal x0, freertos_risc_v_trap_handler
// reset vector
jal x0, Reset_Handler
// Illegal instrution exception
jal x0, IllegalInstruction_Handler
// ecall handler
jal x0, freertos_risc_v_trap_handler
// LSU error
jal x0, LSU_Handler
.section .startup
/* Reset Handler */
Reset_Handler:
# Disable global interrupt. */
csrci mstatus, 8
# initialize stack pointer
la sp, __StackTop
# initialize global pointer
la gp, __global_pointer
#ifndef __NO_SYSTEM_INIT
jal SystemInit
#endif
call __libc_init_array
# Enable global interrupt. */
csrsi mstatus, 8
jal main
ebreak
.size Reset_Handler, . - Reset_Handler
.global _init
.global _fini
_init:
_fini:
ret
// saves all caller-saved registers (except return address)
store_regs:
sw x3, 0x00(x2) // gp
sw x4, 0x04(x2) // tp
sw x5, 0x08(x2) // t0
sw x6, 0x0c(x2) // t1
sw x7, 0x10(x2) // t2
sw x10, 0x14(x2) // a0
sw x11, 0x18(x2) // a1
sw x12, 0x1c(x2) // a2
sw x13, 0x20(x2) // a3
sw x14, 0x24(x2) // a4
sw x15, 0x28(x2) // a5
sw x16, 0x2c(x2) // a6
sw x17, 0x30(x2) // a7
csrr a0, 0x7B0
csrr a1, 0x7B1
csrr a2, 0x7B2
sw a0, 0x34(x2) // lpstart[0]
sw a1, 0x38(x2) // lpend[0]
sw a2, 0x3c(x2) // lpcount[0]
csrr a0, 0x7B4
csrr a1, 0x7B5
csrr a2, 0x7B6
sw a0, 0x40(x2) // lpstart[1]
sw a1, 0x44(x2) // lpend[1]
sw a2, 0x48(x2) // lpcount[1]
csrr a0, 0x341
sw a0, 0x4c(x2) // mepc
csrr a1, 0x300
sw a1, 0x50(x2) // mstatus
jalr x0, x1
// load back registers from stack
end_except:
lw a1, 0x50(x2) // mstatus
csrrw x0, 0x300, a1
lw a0, 0x4c(x2) // mepc
csrrw x0, 0x341, a0
lw a0, 0x40(x2) // lpstart[1]
lw a1, 0x44(x2) // lpend[1]
lw a2, 0x48(x2) // lpcount[1]
csrrw x0, 0x7B4, a0
csrrw x0, 0x7B5, a1
csrrw x0, 0x7B6, a2
lw a0, 0x34(x2) // lpstart[0]
lw a1, 0x38(x2) // lpend[0]
lw a2, 0x3c(x2) // lpcount[0]
csrrw x0, 0x7B0, a0
csrrw x0, 0x7B1, a1
csrrw x0, 0x7B2, a2
lw x3, 0x00(x2) // gp
lw x4, 0x04(x2) // tp
lw x5, 0x08(x2) // t0
lw x6, 0x0c(x2) // t1
lw x7, 0x10(x2) // t2
lw x10, 0x14(x2) // a0
lw x11, 0x18(x2) // a1
lw x12, 0x1c(x2) // a2
lw x13, 0x20(x2) // a3
lw x14, 0x24(x2) // a4
lw x15, 0x28(x2) // a5
lw x16, 0x2c(x2) // a6
lw x17, 0x30(x2) // a7
lw x1, 0x54(x2)
addi x2, x2, EXCEPTION_STACK_SIZE
mret
.weak IRQ_Handler
.type IRQ_Handler, %function
IRQ_Handler:
addi x2, x2, -EXCEPTION_STACK_SIZE
sw x1, 0x54(x2)
jal x1, store_regs
la x1, end_except
csrr a0, mcause
jal x0, SystemIrqHandler
.size IRQ_Handler, . - IRQ_Handler
.macro define_exception_entry entry_name handler_name
.weak \entry_name
\entry_name:
addi x2, x2, -EXCEPTION_STACK_SIZE
sw x1, 0x54(x2)
jal x1, store_regs
la x1, end_except
jal x0, \handler_name
.endm
define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
define_exception_entry Ecall_Handler Ecall_HandlerFunc
define_exception_entry LSU_Handler LSU_HandlerFunc
.weak IllegalInstruction_HandlerFunc
.type IllegalInstruction_HandlerFunc, %function
IllegalInstruction_HandlerFunc:
j .
.size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
.weak Ecall_HandlerFunc
.type Ecall_HandlerFunc, %function
Ecall_HandlerFunc:
j .
.size Ecall_HandlerFunc, . - Ecall_HandlerFunc
.weak LSU_HandlerFunc
.type LSU_HandlerFunc, %function
LSU_HandlerFunc:
j .
.size LSU_HandlerFunc, . - LSU_HandlerFunc
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_zero_riscy.S
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/* ------------------------------------------------------------------------- */
/* @file: startup_RV32M1_zero_riscy.s */
/* @purpose: ZERO_RISCY Core Device Startup File */
/* RV32M1_zero_riscy */
/* @version: 1.0 */
/* @date: 2018-10-2 */
/* @build: b180926 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2018 NXP */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
#define EXCEPTION_STACK_SIZE 0x58
.text
.section .vectors, "ax"
.option norvc;
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
// reset vector
jal x0, Reset_Handler
// Illegal instrution exception
jal x0, IllegalInstruction_Handler
// ecall handler
jal x0, Ecall_Handler
// LSU error
jal x0, LSU_Handler
.section .startup
/* Reset Handler */
Reset_Handler:
# Disable global interrupt. */
csrci mstatus, 8
# initialize stack pointer
la sp, __StackTop
# initialize global pointer
la gp, __global_pointer
#ifndef __NO_SYSTEM_INIT
jal SystemInit
#endif
call __libc_init_array
# Enable global interrupt. */
csrsi mstatus, 8
jal main
ebreak
.size Reset_Handler, . - Reset_Handler
.global _init
.global _fini
_init:
_fini:
ret
// saves all caller-saved registers (except return address)
store_regs:
sw x3, 0x00(x2) // gp
sw x4, 0x04(x2) // tp
sw x5, 0x08(x2) // t0
sw x6, 0x0c(x2) // t1
sw x7, 0x10(x2) // t2
sw x10, 0x14(x2) // a0
sw x11, 0x18(x2) // a1
sw x12, 0x1c(x2) // a2
sw x13, 0x20(x2) // a3
sw x14, 0x24(x2) // a4
sw x15, 0x28(x2) // a5
sw x16, 0x2c(x2) // a6
sw x17, 0x30(x2) // a7
csrr a0, 0x7B0
csrr a1, 0x7B1
csrr a2, 0x7B2
sw a0, 0x34(x2) // lpstart[0]
sw a1, 0x38(x2) // lpend[0]
sw a2, 0x3c(x2) // lpcount[0]
csrr a0, 0x7B4
csrr a1, 0x7B5
csrr a2, 0x7B6
sw a0, 0x40(x2) // lpstart[1]
sw a1, 0x44(x2) // lpend[1]
sw a2, 0x48(x2) // lpcount[1]
csrr a0, 0x341
sw a0, 0x4c(x2) // mepc
csrr a1, 0x300
sw a1, 0x50(x2) // mstatus
jalr x0, x1
// load back registers from stack
end_except:
lw a1, 0x50(x2) // mstatus
csrrw x0, 0x300, a1
lw a0, 0x4c(x2) // mepc
csrrw x0, 0x341, a0
lw a0, 0x40(x2) // lpstart[1]
lw a1, 0x44(x2) // lpend[1]
lw a2, 0x48(x2) // lpcount[1]
csrrw x0, 0x7B4, a0
csrrw x0, 0x7B5, a1
csrrw x0, 0x7B6, a2
lw a0, 0x34(x2) // lpstart[0]
lw a1, 0x38(x2) // lpend[0]
lw a2, 0x3c(x2) // lpcount[0]
csrrw x0, 0x7B0, a0
csrrw x0, 0x7B1, a1
csrrw x0, 0x7B2, a2
lw x3, 0x00(x2) // gp
lw x4, 0x04(x2) // tp
lw x5, 0x08(x2) // t0
lw x6, 0x0c(x2) // t1
lw x7, 0x10(x2) // t2
lw x10, 0x14(x2) // a0
lw x11, 0x18(x2) // a1
lw x12, 0x1c(x2) // a2
lw x13, 0x20(x2) // a3
lw x14, 0x24(x2) // a4
lw x15, 0x28(x2) // a5
lw x16, 0x2c(x2) // a6
lw x17, 0x30(x2) // a7
lw x1, 0x54(x2)
addi x2, x2, EXCEPTION_STACK_SIZE
mret
.weak IRQ_Handler
.type IRQ_Handler, %function
IRQ_Handler:
addi x2, x2, -EXCEPTION_STACK_SIZE
sw x1, 0x54(x2)
jal x1, store_regs
la x1, end_except
csrr a0, mcause
jal x0, SystemIrqHandler
.size IRQ_Handler, . - IRQ_Handler
.macro define_exception_entry entry_name handler_name
.weak \entry_name
\entry_name:
addi x2, x2, -EXCEPTION_STACK_SIZE
sw x1, 0x54(x2)
jal x1, store_regs
la x1, end_except
jal x0, \handler_name
.endm
define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
define_exception_entry Ecall_Handler Ecall_HandlerFunc
define_exception_entry LSU_Handler LSU_HandlerFunc
.weak IllegalInstruction_HandlerFunc
.type IllegalInstruction_HandlerFunc, %function
IllegalInstruction_HandlerFunc:
j .
.size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
.weak Ecall_HandlerFunc
.type Ecall_HandlerFunc, %function
Ecall_HandlerFunc:
j .
.size Ecall_HandlerFunc, . - Ecall_HandlerFunc
.weak LSU_HandlerFunc
.type LSU_HandlerFunc, %function
LSU_HandlerFunc:
j .
.size LSU_HandlerFunc, . - LSU_HandlerFunc
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.c
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.h
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/*
** ###################################################################
** Processors: RV32M1_ri5cy
** RV32M1_ri5cy
**
** Compilers: Keil ARM C/C++ Compiler
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** MCUXpresso Compiler
**
** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
** Version: rev. 1.0, 2018-10-02
** Build: b180926
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-10-02)
** Initial version.
**
** ###################################################################
*/
/*!
* @file RV32M1_ri5cy
* @version 1.0
* @date 2018-10-02
* @brief Device specific configuration file for RV32M1_ri5cy (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef _SYSTEM_RV32M1_ri5cy_H_
#define _SYSTEM_RV32M1_ri5cy_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
/* Define clock source values */
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
/* Low power mode enable */
/* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */
#define SYSTEM_SMC_PMPROT_VALUE 0xABu /* SMC_PMPROT */
#define SYSTEM_SMC_PMCTRL_VALUE 0x0u /* SMC_PMCTRL */
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
/**
* @brief SystemInit function hook.
*
* This weak function allows to call specific initialization code during the
* SystemInit() execution.This can be used when an application specific code needs
* to be called as close to the reset entry as possible (for example the Multicore
* Manager MCMGR_EarlyInit() function call).
* NOTE: No global r/w variables can be used in this hook function because the
* initialization of these variables happens after this function.
*/
void SystemInitHook (void);
/**
* @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler.
*
* It is called from IRQ exception context and dispatches to registered handler according to
* MCAUSE interrupt number.
*
* @param mcause IRQ acknowledge value read from MCAUSE
*/
void SystemIrqHandler(uint32_t mcause);
/**
* @brief Get IRQ nesting level of current context.
*
* If the return value is 0, then the context is not ISR, otherwise the context is ISR.
*
* @return IRQ nesting level
*/
uint32_t SystemGetIRQNestingLevel (void);
/**
* @brief Setup systick for RTOS system.
*
* @param tickRateHz Tick number per second
* @param intPriority IRQ interrupt priority (the smaller, the higher priority)
*/
void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority);
/**
* @brief Clear systick flag status so that next tick interrupt may occur.
*/
void SystemClearSystickFlag (void);
/**
* @brief Sysem is in ISR or not.
*/
bool SystemInISR(void);
#define SysTick_Handler LPIT0_IRQHandler
/**
* @brief Set interrupt priority in Event unit.
*/
void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority);
/**
* @brief Get interrupt priority in Event unit.
*/
uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn);
/**
* @brief Reset the system.
*/
void EVENT_SystemReset(void);
#define NVIC_SystemReset EVENT_SystemReset
/* Priority setting macro remap. */
#define NVIC_SetPriority EVENT_SetIRQPriority
/* Priority getting macro remap. */
#define NVIC_GetPriority EVENT_GetIRQPriority
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_RV32M1_ri5cy_H_ */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.c
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/*
** ###################################################################
** Processors: RV32M1_zero_riscy
** RV32M1_zero_riscy
**
** Compilers: Keil ARM C/C++ Compiler
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** MCUXpresso Compiler
**
** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
** Version: rev. 1.0, 2018-10-02
** Build: b180926
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-10-02)
** Initial version.
**
** ###################################################################
*/
/*!
* @file RV32M1_zero_riscy
* @version 1.0
* @date 2018-10-02
* @brief Device specific configuration file for RV32M1_zero_riscy (header
* file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef _SYSTEM_RV32M1_zero_riscy_H_
#define _SYSTEM_RV32M1_zero_riscy_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
/* Define clock source values */
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
/* Low power mode enable */
/* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */
#define SYSTEM_SMC_PMPROT_VALUE 0xABu /* SMC_PMPROT */
#define SYSTEM_SMC_PMCTRL_VALUE 0x0u /* SMC_PMCTRL */
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
/**
* @brief SystemInit function hook.
*
* This weak function allows to call specific initialization code during the
* SystemInit() execution.This can be used when an application specific code needs
* to be called as close to the reset entry as possible (for example the Multicore
* Manager MCMGR_EarlyInit() function call).
* NOTE: No global r/w variables can be used in this hook function because the
* initialization of these variables happens after this function.
*/
void SystemInitHook (void);
/**
* @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler.
*
* It is called from IRQ exception context and dispatches to registered handler according to
* MCAUSE interrupt number.
*
* @param mcause IRQ acknowledge value read from MCAUSE
*/
void SystemIrqHandler(uint32_t mcause);
/**
* @brief Get IRQ nesting level of current context.
*
* If the return value is 0, then the context is not ISR, otherwise the context is ISR.
*
* @return IRQ nesting level
*/
uint32_t SystemGetIRQNestingLevel (void);
/**
* @brief Setup systick for RTOS system.
*
* @param tickRateHz Tick number per second
* @param intPriority IRQ interrupt priority (the smaller, the higher priority)
*/
void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority);
/**
* @brief Clear systick flag status so that next tick interrupt may occur.
*/
void SystemClearSystickFlag (void);
#define SysTick_Handler LPIT1_IRQHandler
/**
* @brief Sysem is in ISR or not.
*/
bool SystemInISR(void);
/**
* @brief Set interrupt priority in Event unit.
*/
void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority);
/* Priority setting macro remap. */
#define NVIC_SetPriority EVENT_SetIRQPriority
/**
* @brief Reset the system.
*/
void EVENT_SystemReset(void);
#define NVIC_SystemReset EVENT_SystemReset
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_RV32M1_zero_riscy_H_ */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.c
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/*
* This is a modified version of the file printf.c, which was distributed
* by Motorola as part of the M5407C3BOOT.zip package used to initialize
* the M5407C3 evaluation board.
*
* Copyright:
* 1999-2000 MOTOROLA, INC. All Rights Reserved.
* You are hereby granted a copyright license to use, modify, and
* distribute the SOFTWARE so long as this entire notice is
* retained without alteration in any modified and/or redistributed
* versions, and that such modified versions are clearly identified
* as such. No licenses are granted by implication, estoppel or
* otherwise under any patents or trademarks of Motorola, Inc. This
* software is provided on an "AS IS" basis and without warranty.
*
* To the maximum extent permitted by applicable law, MOTOROLA
* DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
* PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
* SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
* ACCOMPANYING WRITTEN MATERIALS.
*
* To the maximum extent permitted by applicable law, IN NO EVENT
* SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
* INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
* LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
*
* Motorola assumes no responsibility for the maintenance and support
* of this software
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdarg.h>
#include <stdlib.h>
#if defined(__CC_ARM)
#include <stdio.h>
#endif
#include "fsl_debug_console.h"
#include "fsl_debug_console_conf.h"
#include "fsl_log.h"
#include "fsl_str.h"
#if defined(__riscv)
#include <sys/stat.h>
#include <sys/types.h>
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief This is a printf call back function which is used to relocate the log to buffer
* or print the log immediately when the local buffer is full.
*
* @param[in] buf Buffer to store log.
* @param[in] indicator Buffer index.
* @param[in] val Target character to store.
* @param[in] len length of the character
*
*/
#if SDK_DEBUGCONSOLE
static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len);
#endif
/*******************************************************************************
* Code
******************************************************************************/
/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/
/* See fsl_debug_console.h for documentation of this function. */
status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq)
{
assert(device != DEBUG_CONSOLE_DEVICE_TYPE_NONE);
return LOG_Init(baseAddr, device, baudRate, clkSrcFreq);
}
/* See fsl_debug_console.h for documentation of this function. */
status_t DbgConsole_Deinit(void)
{
/* LOG deinit */
LOG_Deinit();
return kStatus_Success;
}
status_t DbgConsole_Flush(void)
{
/* wait log and io idle */
return LOG_WaitIdle();
}
#if SDK_DEBUGCONSOLE
/* See fsl_debug_console.h for documentation of this function. */
int DbgConsole_Printf(const char *fmt_s, ...)
{
va_list ap;
int logLength = 0U, result = 0U;
char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {0U};
va_start(ap, fmt_s);
/* format print log first */
logLength = StrFormatPrintf(fmt_s, ap, printBuf, DbgConsole_RelocateLog);
/* print log */
result = LOG_Push((uint8_t *)printBuf, logLength);
va_end(ap);
return result;
}
/* See fsl_debug_console.h for documentation of this function. */
int DbgConsole_Putchar(int ch)
{
/* print char */
return LOG_Push((uint8_t *)&ch, 1U);
}
/* See fsl_debug_console.h for documentation of this function. */
int DbgConsole_Scanf(char *fmt_ptr, ...)
{
va_list ap;
int result;
char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {0U};
/* scanf log */
LOG_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN);
/* get va_list */
va_start(ap, fmt_ptr);
/* format scanf log */
result = StrFormatScanf(scanfBuf, fmt_ptr, ap);
va_end(ap);
return result;
}
/* See fsl_debug_console.h for documentation of this function. */
int DbgConsole_Getchar(void)
{
uint8_t ch;
/* Get char */
LOG_ReadCharacter(&ch);
return ch;
}
static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len)
{
int i = 0;
for (i = 0; i < len; i++)
{
if ((*indicator + 1) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)
{
LOG_Push((uint8_t *)buf, *indicator);
*indicator = 0U;
}
buf[*indicator] = val;
(*indicator)++;
}
}
#endif /* SDK_DEBUGCONSOLE */
/*************Code to support toolchain's printf, scanf *******************************/
/* These function __write and __read is used to support IAR toolchain to printf and scanf*/
#if (defined(__ICCARM__))
#pragma weak __write
size_t __write(int handle, const unsigned char *buffer, size_t size)
{
if (buffer == 0)
{
/*
* This means that we should flush internal buffers. Since we don't we just return.
* (Remember, "handle" == -1 means that all handles should be flushed.)
*/
return 0;
}
/* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
if ((handle != 1) && (handle != 2))
{
return ((size_t)-1);
}
/* Send data. */
LOG_Push((uint8_t *)buffer, 1U);
return size;
}
#pragma weak __read
size_t __read(int handle, unsigned char *buffer, size_t size)
{
/* This function only reads from "standard in", for all other file handles it returns failure. */
if (handle != 0)
{
return ((size_t)-1);
}
/* Receive data.*/
LOG_ReadLine(buffer, size);
return size;
}
/* support LPC Xpresso with RedLib */
#elif(defined(__REDLIB__))
#if (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART))
int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
{
if (buffer == 0)
{
/* return -1 if error. */
return -1;
}
/* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
if ((handle != 1) && (handle != 2))
{
return -1;
}
/* Send data. */
LOG_Push((uint8_t *)buffer, size);
return 0;
}
int __attribute__((weak)) __sys_readc(void)
{
char tmp;
/* Receive data. */
LOG_ReadCharacter((uint8_t *)&tmp);
return tmp;
}
#endif
/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/
#elif(defined(__GNUC__))
#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO))) || \
(defined(__MCUXPRESSO) && (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART))))
int __attribute__((weak)) _write(int handle, char *buffer, int size)
{
if (buffer == 0)
{
/* return -1 if error. */
return -1;
}
/* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
if ((handle != 1) && (handle != 2))
{
return -1;
}
/* Send data. */
LOG_Push((uint8_t *)buffer, size);
return size;
}
int __attribute__((weak)) _read(int handle, char *buffer, int size)
{
/* This function only reads from "standard in", for all other file handles it returns failure. */
if (handle != 0)
{
return -1;
}
/* Receive data. */
return LOG_ReadLine((uint8_t *)buffer, size);
}
#endif
/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/
#elif defined(__CC_ARM)
struct __FILE
{
int handle;
/*
* Whatever you require here. If the only file you are using is standard output using printf() for debugging,
* no file handling is required.
*/
};
/* FILE is typedef in stdio.h. */
#pragma weak __stdout
#pragma weak __stdin
FILE __stdout;
FILE __stdin;
#pragma weak fputc
int fputc(int ch, FILE *f)
{
/* Send data. */
return LOG_Push((uint8_t *)(&ch), 1);
}
#pragma weak fgetc
int fgetc(FILE *f)
{
char ch;
/* Receive data. */
LOG_ReadCharacter((uint8_t *)&ch);
return ch;
}
#endif /* __ICCARM__ */
#if defined(__riscv)
int isatty(int fd)
{
return 1;
}
int fstat(int fd, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
}
int lseek(int fd, off_t ptr, int dir)
{
return 0;
}
int close(int fd)
{
return -1;
}
int read(int fd, void* ptr, size_t len)
{
/* This function only reads from "standard in", for all other file handles it returns failure. */
if (fd != 0)
{
return -1;
}
/* Receive data. */
return LOG_ReadLine((uint8_t *)ptr, len);
}
int write(int fd, const void* ptr, size_t len)
{
if (ptr == 0)
{
/* return -1 if error. */
return -1;
}
/* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
if ((fd != 1) && (fd != 2))
{
return -1;
}
/* Send data. */
LOG_Push((uint8_t *)ptr, len);
return len;
}
#endif
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.h
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/*
* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Debug console shall provide input and output functions to scan and print formatted data.
* o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
* - [flags] :'-', '+', '#', ' ', '0'
* - [width]: number (0,1...)
* - [.precision]: number (0,1...)
* - [length]: do not support
* - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
* o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
* - [*]: is supported.
* - [width]: number (0,1...)
* - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
* - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
*/
#ifndef _FSL_DEBUGCONSOLE_H_
#define _FSL_DEBUGCONSOLE_H_
#include "fsl_common.h"
/*
* @addtogroup debugconsole
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Definition to select sdk or toolchain printf, scanf. */
#ifndef SDK_DEBUGCONSOLE
#define SDK_DEBUGCONSOLE 1U
#endif
#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
#include <stdio.h>
#endif
#if SDK_DEBUGCONSOLE /* Select printf, scanf, putchar, getchar of SDK version. */
#define PRINTF DbgConsole_Printf
#define SCANF DbgConsole_Scanf
#define PUTCHAR DbgConsole_Putchar
#define GETCHAR DbgConsole_Getchar
#else /* Select printf, scanf, putchar, getchar of toolchain. */
#define PRINTF printf
#define SCANF scanf
#define PUTCHAR putchar
#define GETCHAR getchar
#endif /* SDK_DEBUGCONSOLE */
/*******************************************************************************
* Prototypes
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*! @name Initialization*/
/* @{ */
/*!
* @brief Initializes the the peripheral used for debug messages.
*
* Call this function to enable debug log messages to be output via the specified peripheral,
* frequency of peripheral source clock, and base address at the specified baud rate.
* After this function has returned, stdout and stdin are connected to the selected peripheral.
*
* @param baseAddr Indicates the address of the peripheral used to send debug messages.
* @param baudRate The desired baud rate in bits per second.
* @param device Low level device type for the debug console, can be one of the following.
* @arg DEBUG_CONSOLE_DEVICE_TYPE_UART,
* @arg DEBUG_CONSOLE_DEVICE_TYPE_LPUART,
* @arg DEBUG_CONSOLE_DEVICE_TYPE_LPSCI,
* @arg DEBUG_CONSOLE_DEVICE_TYPE_USBCDC.
* @param clkSrcFreq Frequency of peripheral source clock.
*
* @return Indicates whether initialization was successful or not.
* @retval kStatus_Success Execution successfully
* @retval kStatus_Fail Execution failure
* @retval kStatus_InvalidArgument Invalid argument existed
*/
status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq);
/*!
* @brief De-initializes the peripheral used for debug messages.
*
* Call this function to disable debug log messages to be output via the specified peripheral
* base address and at the specified baud rate.
*
* @return Indicates whether de-initialization was successful or not.
*/
status_t DbgConsole_Deinit(void);
/*!
* @brief Debug console flush log.
*
* Call this function to wait the buffer empty and io idle before.
* If interrupt transfer is using, make sure the global IRQ is enable before call this function
* This function should be called when
* 1, before enter power down mode
* 2, log is required to print to terminal immediately
* @return Indicates whether wait idle was successful or not.
*/
status_t DbgConsole_Flush(void);
#if SDK_DEBUGCONSOLE
/*!
* @brief Writes formatted output to the standard output stream.
*
* Call this function to write a formatted output to the standard output stream.
*
* @param fmt_s Format control string.
* @return Returns the number of characters printed or a negative value if an error occurs.
*/
int DbgConsole_Printf(const char *fmt_s, ...);
/*!
* @brief Writes a character to stdout.
*
* Call this function to write a character to stdout.
*
* @param ch Character to be written.
* @return Returns the character written.
*/
int DbgConsole_Putchar(int ch);
/*!
* @brief Reads formatted data from the standard input stream.
*
* Call this function to read formatted data from the standard input stream.
*
* @param fmt_ptr Format control string.
* @return Returns the number of fields successfully converted and assigned.
*/
int DbgConsole_Scanf(char *fmt_ptr, ...);
/*!
* @brief Reads a character from standard input.
*
* Call this function to read a character from standard input.
*
* @return Returns the character read.
*/
int DbgConsole_Getchar(void);
#endif /* SDK_DEBUGCONSOLE */
/*! @} */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/*! @} */
#endif /* _FSL_DEBUGCONSOLE_H_ */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console_conf.h
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/*
* Copyright 2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
#define _FSL_DEBUG_CONSOLE_CONF_H_
/****************Debug console configuration********************/
/*! @brief If Non-blocking mode is needed, please define it at project setting,
* otherwise blocking mode is the default transfer mode.
* Warning: If you want to use non-blocking transfer,please make sure the corresponding
* IO interrupt is enable, otherwise there is no output.
* And non-blocking is combine with buffer, no matter bare-metal or rtos.
*/
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
* when
* non-blocking transfer is using,
* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
* If it is configured too small, log maybe missed , because the log will not be
* buffered if the buffer is full, and the print will return immediately with -1.
* And this value should be multiple of 4 to meet memory alignment.
*
*/
#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
* non-blocking transfer is using,
* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
* If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
* And this value should be multiple of 4 to meet memory alignment.
*
*/
#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (512U)
#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
#else
#define DEBUG_CONSOLE_TRANSFER_BLOCKING
#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
* length can not bigger than this value.
* This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
* the buffer is too big and current task stack size not big enough.
*/
#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
* length can not bigger than this value.
* As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
*/
#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
/*! @brief Debug console synchronization
* User should not change these macro for synchronization mode, but add the
* corresponding synchronization mechanism per different software environment.
* Such as, if another RTOS is used,
* add:
* #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
* in this configuration file and implement the synchronization in fsl.log.c.
*/
/*! @brief synchronization for baremetal software */
#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
/*! @brief synchronization for freertos software */
#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
/*! @brief RTOS synchronization mechanism disable
* If not defined, default is enable, to avoid multitask log print mess.
* If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
* If synchronization is disabled, log maybe messed on terminal.
*/
#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
#ifdef FSL_RTOS_FREE_RTOS
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
#else
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
#endif /* FSL_RTOS_FREE_RTOS */
#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
/*! @brief echo function support
* If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
* at your project setting.
*/
#ifndef DEBUG_CONSOLE_ENABLE_ECHO
#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
#else
#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
/*********************************************************************/
/***************Debug console other configuration*********************/
/*! @brief Definition to printf the float number. */
#ifndef PRINTF_FLOAT_ENABLE
#define PRINTF_FLOAT_ENABLE 0U
#endif /* PRINTF_FLOAT_ENABLE */
/*! @brief Definition to scanf the float number. */
#ifndef SCANF_FLOAT_ENABLE
#define SCANF_FLOAT_ENABLE 0U
#endif /* SCANF_FLOAT_ENABLE */
/*! @brief Definition to support advanced format specifier for printf. */
#ifndef PRINTF_ADVANCED_ENABLE
#define PRINTF_ADVANCED_ENABLE 0U
#endif /* PRINTF_ADVANCED_ENABLE */
/*! @brief Definition to support advanced format specifier for scanf. */
#ifndef SCANF_ADVANCED_ENABLE
#define SCANF_ADVANCED_ENABLE 0U
#endif /* SCANF_ADVANCED_ENABLE */
/*******************************************************************/
#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */
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/*
* Copyright 2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef _FSL_IO_H
#define _FSL_IO_H
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief define a notify callback for IO
* @param size , transfer data size.
* @param rx, indicate a rx transfer is success.
* @param tx, indicate a tx transfer is success.
*/
typedef void (*notify)(size_t *size, bool rx, bool tx);
/*! @brief State structure storing io. */
typedef struct io_State
{
void *ioBase; /*!< Base of the IP register. */
uint8_t ioType; /*!< device type */
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
notify callBack; /*!< define the callback function for buffer */
#endif
} io_state_t;
/*******************************************************************************
* Prototypes
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*!
* @brief io init function.
*
* Call this function to init IO.
*
* @param io configuration pointer
* @param baudRate baud rate
* @param clkSrcFreq clock freq
* @param ringbuffer used to receive character
*/
void IO_Init(io_state_t *io, uint32_t baudRate, uint32_t clkSrcFreq, uint8_t *ringBuffer);
/*!
* @brief Deinit IO.
*
* Call this function to Deinit IO.
*
* @return deinit status
*/
status_t IO_Deinit(void);
/*!
* @brief io transfer function.
*
* Call this function to transfer log.
* Print log:
* @code
* IO_Transfer(ch, size, true);
* @endcode
* Scanf log:
* @code
* IO_Transfer(ch, size, false);
* @endcode
*
* @param ch transfer buffer pointer
* @param size transfer size
* @param tx indicate the transfer is TX or RX
*/
status_t IO_Transfer(uint8_t *ch, size_t size, bool tx);
/*!
* @brief io wait idle.
*
* Call this function to wait the io idle
*
* @return Indicates whether wait idle was successful or not.
*/
status_t IO_WaitIdle(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _FSL_IO_H */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.c
+547
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.h
+103
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@@ -0,0 +1,103 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef _FSL_LOG_H
#define _FSL_LOG_H
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*************************************************************************************************
* Prototypes
************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*!
* @brief Initializes
*
* Call this function to init the buffer
* @param baseAddr, device base address
* @param device, device type
* @param baudRate, device communicate baudrate
* @param clkSrcFreq, device source clock freq
*
* @return Indicates whether initialization was successful or not.
* @retval kStatus_Success Execution successfully
* @retval kStatus_Fail Execution failure
*/
status_t LOG_Init(uint32_t baseAddr, uint8_t device, uint32_t baudRate, uint32_t clkSrcFreq);
/*!
* @brief De-Initializes
*
* Call this function to deinit the buffer
*
* @return Indicates whether Deinit was successful or not.
*/
void LOG_Deinit(void);
/*!
* @brief log push interface
*
* Call this function to print log
* @param fmt, buffer pointer
* @param size, avaliable size
* @return indicate the push size
* @retval-1 indicate buffer is full or transfer fail.
* @retval size return the push log size.
*/
int LOG_Push(uint8_t *buf, size_t size);
/*!
* @brief log read one line function
*
* Call this function to print log
* @param fmt, buffer pointer
* @param size, avaliable size
* @reutrn the number of the recieved character
*/
int LOG_ReadLine(uint8_t *buf, size_t size);
/*!
* @brief log read one character function
*
* Call this function to GETCHAR
* @param ch receive address
* @reutrn the number of the recieved character
*/
int LOG_ReadCharacter(uint8_t *ch);
/*!
* @brief wait log and io idle
*
* Call this function to wait log buffer empty and io idle before enter low power mode.
* @return Indicates whether wait idle was successful or not.
*/
status_t LOG_WaitIdle(void);
/*!
* @brief log pop function
*
* Call this function to pop log from buffer.
* @param buf buffer address to pop
* @param size log size to pop
* @return pop log size.
*/
int LOG_Pop(uint8_t *buf, size_t size);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.c
+1300
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.h
+59
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@@ -0,0 +1,59 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef _FSL_STR_H
#define _FSL_STR_H
#include "fsl_common.h"
/*******************************************************************************
* Prototypes
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*!
* @brief A function pointer which is used when format printf log.
*/
typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);
/*!
* @brief This function outputs its parameters according to a formatted string.
*
* @note I/O is performed by calling given function pointer using following
* (*func_ptr)(c);
*
* @param[in] fmt_ptr Format string for printf.
* @param[in] args_ptr Arguments to printf.
* @param[in] buf pointer to the buffer
* @param cb print callbck function pointer
*
* @return Number of characters to be print
*/
int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);
/*!
* @brief Converts an input line of ASCII characters based upon a provided
* string format.
*
* @param[in] line_ptr The input line of ASCII data.
* @param[in] format Format first points to the format string.
* @param[in] args_ptr The list of parameters.
*
* @return Number of input items converted and assigned.
* @retval IO_EOF When line_ptr is empty string "".
*/
int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _FSL_STR_H */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.cproject
+216
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.settings/language.settings.xml
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FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h
+148
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/*
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include "clock_config.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configCLINT_BASE_ADDRESS 0
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ BOARD_BOOTCLOCKRUN_CORE_CLOCK
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 ) /* Can be as low as 60 but some of the demo tasks that use this constant require it to be higher. */
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 100 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configGENERATE_RUN_TIME_STATS 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define configTIMER_QUEUE_LENGTH 4
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
/* Task priorities. Allow these to be overridden. */
#ifndef uartPRIMARY_PRIORITY
#define uartPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 )
#endif
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTimerPendFunctionCall 1
#define INCLUDE_xTaskAbortDelay 1
#define INCLUDE_xTaskGetHandle 1
#define INCLUDE_xSemaphoreGetMutexHolder 1
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); }
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#define configKERNEL_INTERRUPT_PRIORITY 7
#endif /* FREERTOS_CONFIG_H */
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/RTOSDemo_ri5cy.launch
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<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="riscv32-unknown-elf-gdb"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="debug/RTOSDemo_ri5cy.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RTOSDemo_ri5cy"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2124579326"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/RTOSDemo_ri5cy"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/RV32M1_ri5cy_flash.ld
+181
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@@ -0,0 +1,181 @@
/*
** ###################################################################
** Processors: RV32M1_ri5cy
** RV32M1_ri5cy
**
** Compiler: GNU C Compiler
** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
** Version: rev. 1.0, 2018-10-02
** Build: b171115
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* Entry Point */
OUTPUT_ARCH( "riscv" )
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
/* Specify the memory areas */
MEMORY
{
m_vector (RX) : ORIGIN = 0x000FFF00, LENGTH = 0x00000100
m_text (RX) : ORIGIN = 0x00000000, LENGTH = 0x000FFF00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 - 0x1800
rpmsg_sh_mem (RW) : ORIGIN = 0x2002E800, LENGTH = 0x1800
m_usb_sram (RW) : ORIGIN = 0x48010000, LENGTH = 0x00000800
}
/* Define output sections */
SECTIONS
{
/* NOINIT section for rpmsg_sh_mem */
.noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
{
*(.noinit.$rpmsg_sh_mem*)
. = ALIGN(4) ;
} > rpmsg_sh_mem
.vectors : ALIGN(4)
{
__VECTOR_TABLE = .;
KEEP(*(.vectors))
} > m_vector
/* The program code and other data goes into internal flash */
.text :
{
. = ALIGN(4);
KEEP(*(.startup))
. = ALIGN(4);
__user_vector = .;
KEEP(*(user_vectors))
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.srodata .srodata.*)
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
*(.init)
*(.fini)
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__global_pointer = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
*(.sdata .sdata.*)
*(.heapsram*) /* This is only for the pulpino official test code. */
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
*(NonCacheable)
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
_edata = .;
/* Uninitialized data section */
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(.sbss)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
/* End of uninitalized data segement */
_end = .;
PROVIDE(end = .);
.heap :
{
. = ALIGN(8);
__heap_start = .;
. += HEAP_SIZE;
__heap_end = .;
_heap_end = __heap_end;
} > m_data
.stack :
{
. = ALIGN(8);
__StackLimit = .;
. += STACK_SIZE;
__StackTop = .;
__freertos_irq_stack_top = .;
} > m_data
m_usb_bdt (NOLOAD) :
{
. = ALIGN(512);
*(m_usb_bdt)
} > m_usb_sram
m_usb_global (NOLOAD) :
{
*(m_usb_global)
} > m_usb_sram
/* Initializes stack on the end of block */
PROVIDE(__stack = __StackTop);
}
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/blinky_demo/main_blinky.c
+206
View File
@@ -0,0 +1,206 @@
/*
* FreeRTOS Kernel V10.1.1
* Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky
* style project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the simply blinky style version.
*
* NOTE 2: This file only contains the source code that is specific to the
* basic demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware are defined in main.c.
******************************************************************************
*
* main_blinky() creates one queue, and two tasks. It then starts the
* scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 1000 milliseconds, before sending the value 100 to the queue that
* was created within main_blinky(). Once the value is sent, the task loops
* back around to block for another 1000 milliseconds...and so on.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
* blocks on attempts to read data from the queue that was created within
* main_blinky(). When data is received, the task checks the value of the
* data, and if the value equals the expected 100, writes 'Blink' to the UART
* (the UART is used in place of the LED to allow easy execution in QEMU). The
* 'block time' parameter passed to the queue receive function specifies that
* the task should be held in the Blocked state indefinitely to wait for data to
* be available on the queue. The queue receive task will only leave the
* Blocked state when the queue send task writes to the queue. As the queue
* send task writes to the queue every 1000 milliseconds, the queue receive
* task leaves the Blocked state every 1000 milliseconds, and therefore toggles
* the LED every 200 milliseconds.
*/
/* Standard includes. */
#include <stdio.h>
#include <string.h>
#include <unistd.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Priorities used by the tasks. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The 200ms value is converted
to ticks using the pdMS_TO_TICKS() macro. */
#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 1000 )
/* The maximum number items the queue can hold. The priority of the receiving
task is above the priority of the sending task, so the receiving task will
preempt the sending task and remove the queue items each time the sending task
writes to the queue. Therefore the queue will never have more than one item in
it at any time, and even with a queue length of 1, the sending task will never
find the queue full. */
#define mainQUEUE_LENGTH ( 1 )
/*-----------------------------------------------------------*/
/*
* Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in
* main.c.
*/
void main_blinky( void );
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static QueueHandle_t xQueue = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
"Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE * 2U, /* The size of the stack to allocate to the task. */
NULL, /* The parameter passed to the task - not used in this case. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE * 2U, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was insufficient FreeRTOS heap memory available for the Idle and/or
timer tasks to be created. See the memory management section on the
FreeRTOS web site for more details on the FreeRTOS heap
http://www.freertos.org/a00111.html. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
TickType_t xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
BaseType_t xReturned;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xReturned = xQueueSend( xQueue, &ulValueToSend, 0U );
configASSERT( xReturned == pdPASS );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
const unsigned long ulExpectedValue = 100UL;
const char * const pcPassMessage = "Blink\r\n";
const char * const pcFailMessage = "Unexpected value received\r\n";
extern void vSendString( const char * const pcString );
extern void vToggleLED( void );
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == ulExpectedValue )
{
vSendString( pcPassMessage );
vToggleLED();
ulReceivedValue = 0U;
}
else
{
vSendString( pcFailMessage );
}
}
}
/*-----------------------------------------------------------*/

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