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Add demo project for Polarfire board (#679)

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Add the demo project for PolarFire SoC

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Gaurav-Aggarwal-AWS
2021-09-02 14:02:46 -07:00
committed by GitHub
parent a40172758a
commit 008affa7bf
136 changed files with 61497 additions and 2 deletions
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FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/.cproject
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FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/.gitignore
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/LIM-Debug/
.settings/
/eNVM-Release/
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/.project
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>FreeRTOSDemo</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>FreeRTOS</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/Source</locationURI>
</link>
<link>
<name>full_demo/Demo_Tasks</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/Demo/Common</locationURI>
</link>
</linkedResources>
<filteredResources>
<filter>
<id>1629933517646</id>
<name>FreeRTOS</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-*.c</arguments>
</matcher>
</filter>
<filter>
<id>1629934227060</id>
<name>FreeRTOS/portable</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-MemMang</arguments>
</matcher>
</filter>
<filter>
<id>1629934227063</id>
<name>FreeRTOS/portable</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-GCC</arguments>
</matcher>
</filter>
<filter>
<id>1629933822134</id>
<name>full_demo/Demo_Tasks</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-include</arguments>
</matcher>
</filter>
<filter>
<id>1629933822135</id>
<name>full_demo/Demo_Tasks</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-Minimal</arguments>
</matcher>
</filter>
<filter>
<id>1629934267996</id>
<name>FreeRTOS/portable/GCC</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-RISC-V</arguments>
</matcher>
</filter>
<filter>
<id>1629934254036</id>
<name>FreeRTOS/portable/MemMang</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-heap_4.c</arguments>
</matcher>
</filter>
<filter>
<id>1629933988057</id>
<name>full_demo/Demo_Tasks/Minimal</name>
<type>6</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-comtest_strings.c</arguments>
</matcher>
</filter>
<filter>
<id>1629933988064</id>
<name>full_demo/Demo_Tasks/Minimal</name>
<type>6</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-crhook.c</arguments>
</matcher>
</filter>
<filter>
<id>1629933988070</id>
<name>full_demo/Demo_Tasks/Minimal</name>
<type>6</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-comtest.c</arguments>
</matcher>
</filter>
<filter>
<id>1629933988073</id>
<name>full_demo/Demo_Tasks/Minimal</name>
<type>6</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-crflash.c</arguments>
</matcher>
</filter>
<filter>
<id>1629933988075</id>
<name>full_demo/Demo_Tasks/Minimal</name>
<type>6</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-flash.c</arguments>
</matcher>
</filter>
<filter>
<id>1629933988076</id>
<name>full_demo/Demo_Tasks/Minimal</name>
<type>6</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-flash_timer.c</arguments>
</matcher>
</filter>
<filter>
<id>1629933988078</id>
<name>full_demo/Demo_Tasks/Minimal</name>
<type>6</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-sp_flop.c</arguments>
</matcher>
</filter>
<filter>
<id>1629933988079</id>
<name>full_demo/Demo_Tasks/Minimal</name>
<type>6</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-IntQueue.c</arguments>
</matcher>
</filter>
<filter>
<id>1629938834954</id>
<name>FreeRTOS/portable/GCC/RISC-V/chip_specific_extensions</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-RISCV_MTIME_CLINT_no_extensions</arguments>
</matcher>
</filter>
</filteredResources>
<variableList>
<variable>
<name>FREERTOS_ROOT</name>
<value>$%7BPARENT-2-PROJECT_LOC%7D</value>
</variable>
</variableList>
</projectDescription>
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/FreeRTOSConfig.h
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/*
* FreeRTOS V202107.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/* PolarFire HAL includes. */
#include "mpfs_hal/mss_hal.h"
#include "drivers/mss/mss_mmuart/mss_uart.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define CLINT_CTRL_ADDR ( 0x02000000UL )
#define configMTIME_BASE_ADDRESS ( CLINT_CTRL_ADDR + 0xBFF8UL )
#define configMTIMECMP_BASE_ADDRESS ( CLINT_CTRL_ADDR + 0x4000UL )
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( 32768 )
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configMAX_PRIORITIES ( 7 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 256 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 90 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configGENERATE_RUN_TIME_STATS 0
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configUSE_QUEUE_SETS 1
#define configTASK_NOTIFICATION_ARRAY_ENTRIES 3
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define configTIMER_QUEUE_LENGTH 8
#define configTIMER_TASK_STACK_DEPTH ( 160 )
/* Task priorities. Allow these to be overridden. */
#ifndef uartPRIMARY_PRIORITY
#define uartPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 )
#endif
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTimerPendFunctionCall 1
#define INCLUDE_xTaskAbortDelay 1
#define INCLUDE_xTaskGetHandle 1
#define INCLUDE_xSemaphoreGetMutexHolder 1
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
void vAssertCalled( void );
#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled()
/* Map to the platform write function. */
#define configPRINT_STRING( pcString ) MSS_UART_polled_tx_string( &( g_mss_uart0_lo ), pcString )
/* Test configurations. */
#define configSTART_TASK_NOTIFY_TESTS 1
#define configSTART_TASK_NOTIFY_ARRAY_TESTS 1
#define configSTART_BLOCKING_QUEUE_TESTS 1
#define configSTART_SEMAPHORE_TESTS 1
#define configSTART_POLLED_QUEUE_TESTS 1
#define configSTART_INTEGER_MATH_TESTS 1
#define configSTART_GENERIC_QUEUE_TESTS 1
#define configSTART_PEEK_QUEUE_TESTS 1
/* Cannot run math tests as E51 does not have floating point unit. */
#define configSTART_MATH_TESTS 0
#define configSTART_RECURSIVE_MUTEX_TESTS 1
#define configSTART_COUNTING_SEMAPHORE_TESTS 1
#define configSTART_QUEUE_SET_TESTS 1
#define configSTART_QUEUE_OVERWRITE_TESTS 0
#define configSTART_EVENT_GROUP_TESTS 0
#define configSTART_INTERRUPT_SEMAPHORE_TESTS 0
#define configSTART_QUEUE_SET_POLLING_TESTS 0
#define configSTART_BLOCK_TIME_TESTS 0
#define configSTART_ABORT_DELAY_TESTS 0
#define configSTART_MESSAGE_BUFFER_TESTS 0
#define configSTART_STREAM_BUFFER_TESTS 0
#define configSTART_STREAM_BUFFER_INTERRUPT_TESTS 0
#define configSTART_TIMER_TESTS 0
#define configSTART_REGISTER_TESTS 0
#define configSTART_DELETE_SELF_TESTS 0
#endif /* FREERTOS_CONFIG_H */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/FreeRTOSDemo_Debug.launch
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set $target_riscv=1&#13;&#10;set architecture riscv:rv64&#13;&#10;file ${config_name:FreeRTOSDemo}/FreeRTOSDemo.elf"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="--command &quot;set DEVICE MPFS&quot;&#13;&#10;--file board/microsemi-riscv.cfg"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="thread apply all set $pc=_start"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="init"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="false"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="e51"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${config_name:FreeRTOSDemo}/FreeRTOSDemo.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="FreeRTOSDemo"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/FreeRTOSDemo"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/README.md
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## UART configuration
On connecting Icicle kit J11 to the host PC, you should see four COM port
interfaces connected. This example project uses MMUART0. To use this
project the host PC must connect to the COM port interface0 using a terminal
emulator such as HyperTerminal or PuTTY configured as follows:
- 115200 baud.
- 8 data bits.
- 1 stop bit.
- no parity.
- no flow control.
## Target hardware
This example project is targeted at the Icicle kit.
Details are available at the following link: https://www.microsemi.com/existing-parts/parts/152514
## SoftConsole details
SoftConsole version used to test this project is available at link below:
https://www.microsemi.com/product-directory/design-tools/4879-softconsole#downloads
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/blinky_demo/main_blinky.c
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/*
* FreeRTOS V202107.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky
* style project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the simply blinky style version.
*
* NOTE 2: This file only contains the source code that is specific to the
* blinky demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware are defined in main.c.
******************************************************************************
*
* main_blinky() creates one queue, and two tasks. It then starts the
* scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 1000 milliseconds, before sending the value 100 to the queue that
* was created within main_blinky(). Once the value is sent, the task loops
* back around to block for another 1000 milliseconds...and so on.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
* blocks on attempts to read data from the queue that was created within
* main_blinky(). When data is received, the task checks the value of the
* data, and if the value equals the expected 100, toggles an LED. The 'block
* time' parameter passed to the queue receive function specifies that the task
* should be held in the Blocked state indefinitely to wait for data to be
* available on the queue. The queue receive task will only leave the Blocked
* state when the queue send task writes to the queue. As the queue send task
* writes to the queue every 1000 milliseconds, the queue receive task leaves
* the Blocked state every 1000 milliseconds, and therefore toggles the LED
* every 200 milliseconds.
*/
/* Standard includes. */
#include <stdio.h>
#include <string.h>
#include <unistd.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Priorities used by the tasks. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The 3000ms value is converted
to ticks using the pdMS_TO_TICKS() macro. */
#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 3000 )
/* The maximum number items the queue can hold. The priority of the receiving
task is above the priority of the sending task, so the receiving task will
preempt the sending task and remove the queue items each time the sending task
writes to the queue. Therefore the queue will never have more than one item in
it at any time, and even with a queue length of 1, the sending task will never
find the queue full. */
#define mainQUEUE_LENGTH ( 1 )
/*-----------------------------------------------------------*/
/*
* Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in
* main.c.
*/
void main_blinky( void );
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static QueueHandle_t xQueue = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
"Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
NULL, /* The parameter passed to the task - not used in this case. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was insufficient FreeRTOS heap memory available for the Idle and/or
timer tasks to be created. See the memory management section on the
FreeRTOS web site for more details on the FreeRTOS heap
http://www.freertos.org/a00111.html. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
TickType_t xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
BaseType_t xReturned;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xReturned = xQueueSend( xQueue, &ulValueToSend, 0U );
configASSERT( xReturned == pdPASS );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
const unsigned long ulExpectedValue = 100UL;
extern void vToggleLED( void );
TickType_t tickCount;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == ulExpectedValue )
{
tickCount = xTaskGetTickCount();
vToggleLED();
ulReceivedValue = 0U;
}
}
}
/*-----------------------------------------------------------*/
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/full_demo/README.md
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# Create a Test Project
## Initial Setup
1. Create a new directory in the [FreeRTOS Partner Supported Demos Repository](https://github.com/FreeRTOS/FreeRTOS-Partner-Supported-Demos/tree/main)
or [FreeRTOS Community Supported Demos Repository](https://github.com/FreeRTOS/FreeRTOS-Community-Supported-Demos/tree/main).
The suggested name for the directory is `<hardware_name>_<compiler_name>`.
2. Create a project for your hardware and tool-chain in this directory.
3. Copy all the files in the [FreeRTOS/Demo/ThirdParty/Template](https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS/Demo/ThirdParty/Template)
directory to your project directory:
* `IntQueueTimer.h`
* `IntQueueTimer.c`
* `TestRunner.h`
* `TestRunner.c`
* `RegTests.h`
* `RegTests.c`
## Project Configuration
1. Compile the following additional files in your project:
* All files in the [FreeRTOS/Demo/Common/Minimal](https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS/Demo/Common/Minimal) directory except
`comtest_strings.c`, `crhook.c` , `comtest.c` ,`crflash.c`,`flash.c`, `flash_timer.c` and `sp_flop.c`.
2. Add the following paths to your include search path:
* `FreeRTOS/Demo/Common/include`.
3. Call the `void vStartTests( void )` function from your `main` function after
doing all the hardware initialization. Note that this function starts the
scheduler and therefore, never returns.
```c
#include "TestRunner.h"
void main( void )
{
/* Startup and Hardware initialization. */
/* Start tests. */
vStartTests();
/* Should never reach here. */
for( ; ; );
}
```
## Set up FreeRTOSConfig.h
1. Enable tick hook by adding the following line in your `FreeRTOSConfig.h`:
```c
#define configUSE_TICK_HOOK 1
```
2. Set the task notification array size to 3 by adding the following line in
your `FreeRTOSConfig.h`:
```c
#define configTASK_NOTIFICATION_ARRAY_ENTRIES 3
```
3. Enable printing by mapping `configPRINTF` to your print function. Note that
`configPRINTF` calls are wrapped in double parentheses to support C89. If you
have a thread-safe `printf` function, the following is what should be added
in your `FreeRTOSConfig.h`:
```c
#define configPRINTF( X ) printf X
```
4. Add the following defines in your `FreeRTOSConfig.h`:
```c
#define configSTART_TASK_NOTIFY_TESTS 0
#define configSTART_TASK_NOTIFY_ARRAY_TESTS 0
#define configSTART_BLOCKING_QUEUE_TESTS 0
#define configSTART_SEMAPHORE_TESTS 0
#define configSTART_POLLED_QUEUE_TESTS 0
#define configSTART_INTEGER_MATH_TESTS 0
#define configSTART_GENERIC_QUEUE_TESTS 0
#define configSTART_PEEK_QUEUE_TESTS 0
#define configSTART_MATH_TESTS 0
#define configSTART_RECURSIVE_MUTEX_TESTS 0
#define configSTART_COUNTING_SEMAPHORE_TESTS 0
#define configSTART_QUEUE_SET_TESTS 0
#define configSTART_QUEUE_OVERWRITE_TESTS 0
#define configSTART_EVENT_GROUP_TESTS 0
#define configSTART_INTERRUPT_SEMAPHORE_TESTS 0
#define configSTART_QUEUE_SET_POLLING_TESTS 0
#define configSTART_BLOCK_TIME_TESTS 0
#define configSTART_ABORT_DELAY_TESTS 0
#define configSTART_MESSAGE_BUFFER_TESTS 0
#define configSTART_STREAM_BUFFER_TESTS 0
#define configSTART_STREAM_BUFFER_INTERRUPT_TESTS 0
#define configSTART_TIMER_TESTS 0
#define configSTART_INTERRUPT_QUEUE_TESTS 0
#define configSTART_REGISTER_TESTS 0
#define configSTART_DELETE_SELF_TESTS 0
```
## Create and Run Register Tests
1. Fill the definitions of the following functions in the `RegTests.c` file
copied in the [Initial Setup](#Initial-Setup) step:
* `prvRegisterTest1Task`
* `prvRegisterTest2Task`
* `prvRegisterTest3Task`
* `prvRegisterTest4Task`
2. Define `configSTART_REGISTER_TESTS` to `1` in your `FreeRTOSConfig.h`:
```c
#define configSTART_REGISTER_TESTS 1
```
3. Build and run the register tests. The output should look like the following:
```
No errors
No errors
No errors
No errors
```
## Setup and Run Interrupt Nesting Tests
1. If your hardware **does not** support interrupt nesting, skip this section.
2. Fill the `void vInitialiseTimerForIntQueueTest( void )` function in the
`IntQueueTimer.c` file copied in the [Initial Setup](#Initial-Setup) step to
initialize and start a hardware timer. Make sure that the timer interrupt
runs at a logical priority less than or equal to `configMAX_SYSCALL_INTERRUPT_PRIORITY`.
The following is an example for ARM MPS2 which starts TIM0 timer:
```c
void vInitialiseTimerForIntQueueTest( void )
{
/* Clear interrupt. */
CMSDK_TIMER0->INTCLEAR = ( 1ul << 0 );
/* Reload value is slightly offset from the other timer. */
CMSDK_TIMER0->RELOAD = ( configCPU_CLOCK_HZ / tmrTIMER_0_FREQUENCY ) + 1UL;
CMSDK_TIMER0->CTRL = ( ( 1ul << 3 ) | ( 1ul << 0 ) );
NVIC_SetPriority( TIMER0_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY );
NVIC_EnableIRQ( TIMER0_IRQn );
}
```
3. Either install `void IntQueueTestTimerHandler( void )` function as the timer
interrupt handler or call it from the timer interrupt handler of the above
timer. The following is an example for ARM MPS2 which calls
`IntQueueTestTimerHandler` from the TIM0 handler:
```c
void TIMER0_Handler( void )
{
/* Clear interrupt. */
CMSDK_TIMER0->INTCLEAR = ( 1ul << 0 );
IntQueueTestTimerHandler();
}
```
4. Define `configSTART_INTERRUPT_QUEUE_TESTS` to `1` in your `FreeRTOSConfig.h`:
```c
#define configSTART_INTERRUPT_QUEUE_TESTS 1
```
5. Build and run the tests. The output should look like the following:
```
No errors
No errors
No errors
No errors
```
## Running All Tests
1. Define all the `configSTART_<Test_Name>_TESTS` macros to `1` in your
`FreeRTOSConfig.h`.
2. Build and run the tests. The output should look like the following:
```
No errors
No errors
No errors
No errors
```
3. If you cannot fit all the tests in one binary because of Flash or RAM space,
you can run tests one by one or in groups by defining
`configSTART_<Test_Name>_TESTS` macros to `0` or `1` as needed.
## Add README
Add a `README.md` file in the project directory with the following information:
* Link to the hardware page.
* How to setup tool-chain.
* How to build and run the project.
* Any other relevant information.
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/full_demo/RegTest.S
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/*
* FreeRTOS V202107.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
.extern ulRegisterTest1Counter
.extern ulRegisterTest2Counter
.global vRegTest1Implementation
.global vRegTest2Implementation
/*-----------------------------------------------------------*/
/*
* The register check tasks are described in the comments at the top of
* main_full.c.
*/
.align( 4 )
vRegTest1Implementation:
/* Fill the core registers with known values. */
li x5, 0x5
li x6, 0x6
li x7, 0x7
li x8, 0x8
li x9, 0x9
li x10, 0xa
li x11, 0xb
li x12, 0xc
li x13, 0xd
li x14, 0xe
li x15, 0xf
li x16, 0x10
li x17, 0x11
li x18, 0x12
li x19, 0x13
li x20, 0x14
li x21, 0x15
li x22, 0x16
li x23, 0x17
li x24, 0x18
li x25, 0x19
li x26, 0x1a
li x27, 0x1b
li x28, 0x1c
li x29, 0x1d
li x30, 0x1e
reg1_loop:
/* Check each register still contains the expected known value.
vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
uses x5 as the temporary. */
li x31, 0x5
bne x31, x5, reg1_error_loop
li x31, 0x6
bne x31, x6, reg1_error_loop
li x31, 0x7
bne x31, x7, reg1_error_loop
li x31, 0x8
bne x31, x8, reg1_error_loop
li x31, 0x9
bne x31, x9, reg1_error_loop
li x31, 0xa
bne x31, x10, reg1_error_loop
li x31, 0xb
bne x31, x11, reg1_error_loop
li x31, 0xc
bne x31, x12, reg1_error_loop
li x31, 0xd
bne x31, x13, reg1_error_loop
li x31, 0xe
bne x31, x14, reg1_error_loop
li x31, 0xf
bne x31, x15, reg1_error_loop
li x31, 0x10
bne x31, x16, reg1_error_loop
li x31, 0x11
bne x31, x17, reg1_error_loop
li x31, 0x12
bne x31, x18, reg1_error_loop
li x31, 0x13
bne x31, x19, reg1_error_loop
li x31, 0x14
bne x31, x20, reg1_error_loop
li x31, 0x15
bne x31, x21, reg1_error_loop
li x31, 0x16
bne x31, x22, reg1_error_loop
li x31, 0x17
bne x31, x23, reg1_error_loop
li x31, 0x18
bne x31, x24, reg1_error_loop
li x31, 0x19
bne x31, x25, reg1_error_loop
li x31, 0x1a
bne x31, x26, reg1_error_loop
li x31, 0x1b
bne x31, x27, reg1_error_loop
li x31, 0x1c
bne x31, x28, reg1_error_loop
li x31, 0x1d
bne x31, x29, reg1_error_loop
li x31, 0x1e
bne x31, x30, reg1_error_loop
/* Everything passed, increment the loop counter. */
lw x31, ulRegisterTest1CounterConst
lw x30, 0(x31)
addi x30, x30, 1
sw x30, 0(x31)
/* Restore clobbered register reading for next loop. */
li x30, 0x1e
/* Yield to increase code coverage. */
ecall
/* Start again. */
jal reg1_loop
reg1_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop
counter being incremented so the check task knows an error was found. */
ebreak
jal reg1_error_loop
.align( 4 )
ulRegisterTest1CounterConst: .word ulRegisterTest1Counter
/*-----------------------------------------------------------*/
.align( 4 )
vRegTest2Implementation:
/* Fill the core registers with known values. */
li x6, 0x61
li x7, 0x71
li x8, 0x81
li x9, 0x91
li x10, 0xa1
li x11, 0xb1
li x12, 0xc1
li x13, 0xd1
li x14, 0xe1
li x15, 0xf1
li x16, 0x20
li x17, 0x21
li x18, 0x22
li x19, 0x23
li x20, 0x24
li x21, 0x25
li x22, 0x26
li x23, 0x27
li x24, 0x28
li x25, 0x29
li x26, 0x2a
li x27, 0x2b
li x28, 0x2c
li x29, 0x2d
li x30, 0x2e
li x31, 0x2f
Reg2_loop:
/* Check each register still contains the expected known value.
vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
uses x31 as the temporary. */
li x5, 0x61
bne x5, x6, reg2_error_loop
li x5, 0x71
bne x5, x7, reg2_error_loop
li x5, 0x81
bne x5, x8, reg2_error_loop
li x5, 0x91
bne x5, x9, reg2_error_loop
li x5, 0xa1
bne x5, x10, reg2_error_loop
li x5, 0xb1
bne x5, x11, reg2_error_loop
li x5, 0xc1
bne x5, x12, reg2_error_loop
li x5, 0xd1
bne x5, x13, reg2_error_loop
li x5, 0xe1
bne x5, x14, reg2_error_loop
li x5, 0xf1
bne x5, x15, reg2_error_loop
li x5, 0x20
bne x5, x16, reg2_error_loop
li x5, 0x21
bne x5, x17, reg2_error_loop
li x5, 0x22
bne x5, x18, reg2_error_loop
li x5, 0x23
bne x5, x19, reg2_error_loop
li x5, 0x24
bne x5, x20, reg2_error_loop
li x5, 0x25
bne x5, x21, reg2_error_loop
li x5, 0x26
bne x5, x22, reg2_error_loop
li x5, 0x27
bne x5, x23, reg2_error_loop
li x5, 0x28
bne x5, x24, reg2_error_loop
li x5, 0x29
bne x5, x25, reg2_error_loop
li x5, 0x2a
bne x5, x26, reg2_error_loop
li x5, 0x2b
bne x5, x27, reg2_error_loop
li x5, 0x2c
bne x5, x28, reg2_error_loop
li x5, 0x2d
bne x5, x29, reg2_error_loop
li x5, 0x2e
bne x5, x30, reg2_error_loop
li x5, 0x2f
bne x5, x31, reg2_error_loop
/* Everything passed, increment the loop counter. */
lw x5, ulRegisterTest2CounterConst
lw x6, 0(x5)
addi x6, x6, 1
sw x6, 0(x5)
/* Restore clobbered register reading for next loop. */
li x6, 0x61
/* Start again. */
jal Reg2_loop
reg2_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop
counter being incremented so the check task knows an error was found. */
ebreak
jal reg2_error_loop
.align( 4 )
ulRegisterTest2CounterConst: .word ulRegisterTest2Counter
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/full_demo/RegTests.c
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/*
* FreeRTOS V202104.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Interface include files. */
#include "RegTests.h"
/* Parameters that are passed into the register check tasks solely for the
* purpose of ensuring parameters are passed into tasks correctly. */
#define REG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )
#define REG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )
/*-----------------------------------------------------------*/
/* Tasks that implement register tests. */
static void prvRegisterTest1Task( void *pvParameters );
static void prvRegisterTest2Task( void *pvParameters );
extern void vRegTest1Implementation( void );
extern void vRegTest2Implementation( void );
/* Flag that will be latched to pdTRUE should any unexpected behaviour be
detected in any of the tasks. */
static volatile BaseType_t xErrorDetected = pdFALSE;
/* Counters that are incremented on each cycle of a test. This is used to
detect a stalled task - a test that is no longer running. */
volatile uint32_t ulRegisterTest1Counter = 0;
volatile uint32_t ulRegisterTest2Counter = 0;
/*-----------------------------------------------------------*/
static void prvRegisterTest1Task( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
* written in C for convenience of checking the task parameter is being
* passed in correctly. */
if( pvParameters == REG_TEST_TASK_1_PARAMETER )
{
/* Start the part of the test that is written in assembler. */
vRegTest1Implementation();
}
/* The following line will only execute if the task parameter is found to
* be incorrect. The check task will detect that the regtest loop counter
* is not being incremented and flag an error. */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvRegisterTest2Task( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
* written in C for convenience of checking the task parameter is being
* passed in correctly. */
if( pvParameters == REG_TEST_TASK_2_PARAMETER )
{
/* Start the part of the test that is written in assembler. */
vRegTest2Implementation();
}
/* The following line will only execute if the task parameter is found to
* be incorrect. The check task will detect that the regtest loop counter
* is not being incremented and flag an error. */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
void vStartRegisterTasks( UBaseType_t uxPriority )
{
BaseType_t ret;
ret = xTaskCreate( prvRegisterTest1Task,
"RegTest1",
configMINIMAL_STACK_SIZE,
REG_TEST_TASK_1_PARAMETER,
uxPriority,
NULL );
configASSERT( ret == pdPASS );
ret = xTaskCreate( prvRegisterTest2Task,
"RegTest2",
configMINIMAL_STACK_SIZE,
REG_TEST_TASK_2_PARAMETER,
uxPriority,
NULL );
configASSERT( ret == pdPASS );
}
/*-----------------------------------------------------------*/
BaseType_t xAreRegisterTasksStillRunning( void )
{
static uint32_t ulLastRegisterTest1Counter = 0, ulLastRegisterTest2Counter = 0;
/* If the register test task is still running then we expect the loop
* counters to have incremented since this function was last called. */
if( ulLastRegisterTest1Counter == ulRegisterTest1Counter )
{
xErrorDetected = pdTRUE;
}
if( ulLastRegisterTest2Counter == ulRegisterTest2Counter )
{
xErrorDetected = pdTRUE;
}
ulLastRegisterTest1Counter = ulRegisterTest1Counter;
ulLastRegisterTest2Counter = ulRegisterTest2Counter;
/* Errors detected in the task itself will have latched xErrorDetected
* to true. */
return ( BaseType_t ) !xErrorDetected;
}
/*-----------------------------------------------------------*/
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/full_demo/RegTests.h
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/*
* FreeRTOS V202104.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef REG_TEST_H
#define REG_TEST_H
void vStartRegisterTasks( UBaseType_t uxPriority );
BaseType_t xAreRegisterTasksStillRunning( void );
#endif /* REG_TEST_H */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/full_demo/main_full.c
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FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/main.c
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/*
* FreeRTOS V202107.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/******************************************************************************
* This project provides two demo applications. A simple blinky style project,
* and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
* select between the two. The simply blinky demo is implemented and described
* in main_blinky.c. The more comprehensive test and demo application is
* implemented and described in main_full.c.
*
* This file implements the code that is not demo specific, including the
* hardware setup and standard FreeRTOS hook functions.
*
* When running on the PolarFire SoC hardware:
* When executing correctly the yellow LED will toggle every three seconds. If
* the yellow LED toggles every 500ms then one of the self-monitoring test tasks
* discovered a potential issue. If the red led toggles rapidly then a hardware
* exception occurred.
*
* ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
* THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
* APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
*
*/
/* FreeRTOS kernel includes. */
#include <FreeRTOS.h>
#include <task.h>
/* PolarFire HAL includes. */
#include "mpfs_hal/mss_hal.h"
#include "drivers/mss/mss_gpio/mss_gpio.h"
#include "drivers/mss/mss_mmuart/mss_uart.h"
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application. */
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
/*-----------------------------------------------------------*/
/*
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
*/
#if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
extern void main_blinky( void );
#else
extern void main_full( void );
#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
/*
* Prototypes for the standard FreeRTOS callback/hook functions implemented
* within this file. See https://www.freertos.org/a00016.html
*/
void vApplicationMallocFailedHook( void );
void vApplicationIdleHook( void );
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
void vApplicationTickHook( void );
/*
* Setup the hardware to run this demo.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/* Main function for the HART0(E51 processor). Application code running on
* HART0 is placed here. */
void e51( void )
{
prvSetupHardware();
/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
* of this file. */
#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
{
main_blinky();
}
#else
{
main_full();
}
#endif
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Configure UART0. */
SYSREG->SUBBLK_CLOCK_CR |= SUBBLK_CLOCK_CR_MMUART0_MASK;
SYSREG->SOFT_RESET_CR &= ~SOFT_RESET_CR_MMUART0_MASK;
MSS_UART_init( &( g_mss_uart0_lo ),
MSS_UART_115200_BAUD,
MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );
/* Configure the LED. */
mss_config_clk_rst( MSS_PERIPH_GPIO2, ( uint8_t )MPFS_HAL_FIRST_HART, PERIPHERAL_ON );
MSS_GPIO_config( GPIO2_LO, MSS_GPIO_16, MSS_GPIO_OUTPUT_MODE ); /* Red Led (LED1). */
MSS_GPIO_config( GPIO2_LO, MSS_GPIO_18, MSS_GPIO_OUTPUT_MODE ); /* Yellow Led (LED3). */
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* vApplicationMallocFailedHook() will only be called if
* configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
* function that will get called if a call to pvPortMalloc() fails.
* pvPortMalloc() is called internally by the kernel whenever a task, queue,
* timer or semaphore is created. It is also called by various parts of the
* demo application. If heap_1.c or heap_2.c are used, then the size of the
* heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
* FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
* to query the size of free heap space that remains (although it does not
* provide information on how the remaining heap might be fragmented). */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
* to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
* task. It is essential that code added to this hook function never attempts
* to block in any way (for example, call xQueueReceive() with a block time
* specified, or call vTaskDelay()). If the application makes use of the
* vTaskDelete() API function (as this demo application does) then it is also
* important that vApplicationIdleHook() is permitted to return to its calling
* function, because it is the responsibility of the idle task to clean up
* memory allocated by the kernel to any task that has since been deleted. */
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
* configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
* function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
/* The tests in the full demo expect some interaction with interrupts. */
#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 )
{
extern void vFullDemoTickHook( void );
vFullDemoTickHook();
}
#endif
}
/*-----------------------------------------------------------*/
void vToggleLED( void )
{
static volatile uint8_t value = 0u;
value = ( value == 0u ) ? 1u : 0u;
MSS_GPIO_set_output( GPIO2_LO, MSS_GPIO_18, value );
}
/*-----------------------------------------------------------*/
void vAssertCalled( void )
{
volatile uint32_t ul;
const uint32_t ulNullLoopDelay = 0x1ffffUL;
static volatile uint8_t value = 0u;
taskDISABLE_INTERRUPTS();
/* Flash the red LED to indicate that assert was hit - interrupts are off
* here to prevent any further tick interrupts or context switches, so the
* delay is implemented as a crude loop instead of a peripheral timer. */
for( ;; )
{
for( ul = 0; ul < ulNullLoopDelay; ul++ )
{
__asm volatile( "nop" );
}
value = ( value == 0u ) ? 1u : 0u;
MSS_GPIO_set_output( GPIO2_LO, MSS_GPIO_16, value );
}
}
/*-----------------------------------------------------------*/
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design/fpga_design_description/ICICLE_MSS_eMMC_cfg.xml
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FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/clocks/hw_clk_ddr_pll.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_ddr_pll.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_DDR_PLL_H_
#define HW_CLK_DDR_PLL_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_DDR_SOFT_RESET)
/*This is a compulsory register for all SCB slaves and must be at the same
offset in all slaves to facilitate global soft reset of all SCB registers with
a single broadcast write from the SCB master. */
#define LIBERO_SETTING_DDR_SOFT_RESET 0x00000000UL
/* NV_MAP [0:1] RST */
/* V_MAP [1:1] RST */
/* PERIPH [8:1] RST */
/* BLOCKID [16:16] ID */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_CTRL)
/*PLL control register */
#define LIBERO_SETTING_DDR_PLL_CTRL 0x0100003FUL
/* REG_POWERDOWN_B [0:1] RW value= 0x1 */
/* REG_RFDIV_EN [1:1] RW value= 0x1 */
/* REG_DIVQ0_EN [2:1] RW value= 0x1 */
/* REG_DIVQ1_EN [3:1] RW value= 0x1 */
/* REG_DIVQ2_EN [4:1] RW value= 0x1 */
/* REG_DIVQ3_EN [5:1] RW value= 0x1 */
/* REG_RFCLK_SEL [6:1] RW value= 0x0 */
/* RESETONLOCK [7:1] RW value= 0x0 */
/* BYPCK_SEL [8:4] RW value= 0x0 */
/* REG_BYPASS_GO_B [12:1] RW value= 0x0 */
/* RESERVE10 [13:3] RSVD */
/* REG_BYPASSPRE [16:4] RW value= 0x0 */
/* REG_BYPASSPOST [20:4] RW value= 0x0 */
/* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */
/* LOCK [25:1] RO */
/* LOCK_INT_EN [26:1] RW value= 0x0 */
/* UNLOCK_INT_EN [27:1] RW value= 0x0 */
/* LOCK_INT [28:1] SW1C */
/* UNLOCK_INT [29:1] SW1C */
/* RESERVE11 [30:1] RSVD */
/* LOCK_B [31:1] RO */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_REF_FB)
/*PLL reference and feedback registers */
#define LIBERO_SETTING_DDR_PLL_REF_FB 0x00000500UL
/* FSE_B [0:1] RW value= 0x0 */
/* FBCK_SEL [1:2] RW value= 0x0 */
/* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */
/* RESERVE12 [4:4] RSVD */
/* RFDIV [8:6] RW value= 0x5 */
/* RESERVE13 [14:2] RSVD */
/* RESERVE14 [16:12] RSVD */
/* RESERVE15 [28:4] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_FRACN)
/*PLL fractional register */
#define LIBERO_SETTING_DDR_PLL_FRACN 0x00000000UL
/* FRACN_EN [0:1] RW value= 0x0 */
/* FRACN_DAC_EN [1:1] RW value= 0x0 */
/* RESERVE16 [2:6] RSVD */
/* RESERVE17 [8:24] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_DIV_0_1)
/*PLL 0/1 division registers */
#define LIBERO_SETTING_DDR_PLL_DIV_0_1 0x02000100UL
/* VCO0PH_SEL [0:3] RO */
/* DIV0_START [3:3] RW value= 0x0 */
/* RESERVE18 [6:2] RSVD */
/* POST0DIV [8:7] RW value= 0x1 */
/* RESERVE19 [15:1] RSVD */
/* VCO1PH_SEL [16:3] RO */
/* DIV1_START [19:3] RW value= 0x0 */
/* RESERVE20 [22:2] RSVD */
/* POST1DIV [24:7] RW value= 0x2 */
/* RESERVE21 [31:1] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_DIV_2_3)
/*PLL 2/3 division registers */
#define LIBERO_SETTING_DDR_PLL_DIV_2_3 0x01000100UL
/* VCO2PH_SEL [0:3] RO */
/* DIV2_START [3:3] RW value= 0x0 */
/* RESERVE22 [6:2] RSVD */
/* POST2DIV [8:7] RW value= 0x1 */
/* RESERVE23 [15:1] RSVD */
/* VCO3PH_SEL [16:3] RO */
/* DIV3_START [19:3] RW value= 0x0 */
/* RESERVE24 [22:2] RSVD */
/* POST3DIV [24:7] RW value= 0x1 */
/* CKPOST3_SEL [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_CTRL2)
/*PLL control register */
#define LIBERO_SETTING_DDR_PLL_CTRL2 0x00001020UL
/* BWI [0:2] RW value= 0x0 */
/* BWP [2:2] RW value= 0x0 */
/* IREF_EN [4:1] RW value= 0x0 */
/* IREF_TOGGLE [5:1] RW value= 0x1 */
/* RESERVE25 [6:3] RSVD */
/* LOCKCNT [9:4] RW value= 0x8 */
/* RESERVE26 [13:4] RSVD */
/* ATEST_EN [17:1] RW value= 0x0 */
/* ATEST_SEL [18:3] RW value= 0x0 */
/* RESERVE27 [21:11] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_CAL)
/*PLL calibration register */
#define LIBERO_SETTING_DDR_PLL_CAL 0x00000D06UL
/* DSKEWCALCNT [0:3] RW value= 0x6 */
/* DSKEWCAL_EN [3:1] RW value= 0x0 */
/* DSKEWCALBYP [4:1] RW value= 0x0 */
/* RESERVE28 [5:3] RSVD */
/* DSKEWCALIN [8:7] RW value= 0xd */
/* RESERVE29 [15:1] RSVD */
/* DSKEWCALOUT [16:7] RO */
/* RESERVE30 [23:9] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_PHADJ)
/*PLL phase registers */
#define LIBERO_SETTING_DDR_PLL_PHADJ 0x00005003UL
/* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */
/* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */
/* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */
/* REG_OUT1_PHSINIT [5:3] RW value= 0x0 */
/* REG_OUT2_PHSINIT [8:3] RW value= 0x0 */
/* REG_OUT3_PHSINIT [11:3] RW value= 0x2 */
/* REG_LOADPHS_B [14:1] RW value= 0x1 */
/* RESERVE31 [15:17] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_SSCG_REG_0)
/*SSCG registers 0 */
#define LIBERO_SETTING_DDR_SSCG_REG_0 0x00000000UL
/* DIVVAL [0:6] RW value= 0x0 */
/* FRACIN [6:24] RW value= 0x0 */
/* RESERVE00 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_SSCG_REG_1)
/*SSCG registers 1 */
#define LIBERO_SETTING_DDR_SSCG_REG_1 0x00000000UL
/* DOWNSPREAD [0:1] RW value= 0x0 */
/* SSMD [1:5] RW value= 0x0 */
/* FRACMOD [6:24] RO */
/* RESERVE01 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_SSCG_REG_2)
/*SSCG registers 2 */
#define LIBERO_SETTING_DDR_SSCG_REG_2 0x00000080UL
/* INTIN [0:12] RW value= 0x80 */
/* INTMOD [12:12] RO */
/* RESERVE02 [24:8] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_SSCG_REG_3)
/*SSCG registers 3 */
#define LIBERO_SETTING_DDR_SSCG_REG_3 0x00000001UL
/* SSE_B [0:1] RW value= 0x1 */
/* SEL_EXTWAVE [1:2] RW value= 0x0 */
/* EXT_MAXADDR [3:8] RW value= 0x0 */
/* TBLADDR [11:8] RO */
/* RANDOM_FILTER [19:1] RW value= 0x0 */
/* RANDOM_SEL [20:2] RW value= 0x0 */
/* RESERVE03 [22:1] RSVD */
/* RESERVE04 [23:9] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_DDR_PLL_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/clocks/hw_clk_mss_cfm.h
+114
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_mss_cfm.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_MSS_CFM_H_
#define HW_CLK_MSS_CFM_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MSS_BCLKMUX)
/*Input mux selections */
#define LIBERO_SETTING_MSS_BCLKMUX 0x00000208UL
/* BCLK0_SEL [0:5] RW value= 0x8 */
/* BCLK1_SEL [5:5] RW value= 0x10 */
/* BCLK2_SEL [10:5] RW value= 0x0 */
/* BCLK3_SEL [15:5] RW value= 0x0 */
/* BCLK4_SEL [20:5] RW value= 0x0 */
/* BCLK5_SEL [25:5] RW value= 0x0 */
/* RESERVED [30:2] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_CKMUX)
/*Input mux selections */
#define LIBERO_SETTING_MSS_PLL_CKMUX 0x00000155UL
/* CLK_IN_MAC_TSU_SEL [0:2] RW value= 0x1 */
/* PLL0_RFCLK0_SEL [2:2] RW value= 0x1 */
/* PLL0_RFCLK1_SEL [4:2] RW value= 0x1 */
/* PLL1_RFCLK0_SEL [6:2] RW value= 0x1 */
/* PLL1_RFCLK1_SEL [8:2] RW value= 0x1 */
/* PLL1_FDR_SEL [10:5] RW value= 0x0 */
/* RESERVED [15:17] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_MSSCLKMUX)
/*MSS Clock mux selections */
#define LIBERO_SETTING_MSS_MSSCLKMUX 0x00000003UL
/* MSSCLK_MUX_SEL [0:2] RW value= 0x3 */
/* MSSCLK_MUX_MD [2:2] RW value= 0x0 */
/* CLK_STANDBY_SEL [4:1] RW value= 0x0 */
/* RESERVED [5:27] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_SPARE0)
/*spare logic */
#define LIBERO_SETTING_MSS_SPARE0 0x00000000UL
/* SPARE0 [0:32] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_FMETER_ADDR)
/*Frequency_meter_address_selections */
#define LIBERO_SETTING_MSS_FMETER_ADDR 0x00000000UL
/* ADDR10 [0:2] RSVD */
/* ADDR [2:4] RW value= 0x0 */
/* RESERVE18 [6:26] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_FMETER_DATAW)
/*Frequency_meter_data_write */
#define LIBERO_SETTING_MSS_FMETER_DATAW 0x00000000UL
/* DATA [0:24] RW value= 0x0 */
/* STROBE [24:1] W1P */
/* RESERVE19 [25:7] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_FMETER_DATAR)
/*Frequency_meter_data_read */
#define LIBERO_SETTING_MSS_FMETER_DATAR 0x00000000UL
/* DATA [0:24] RO */
/* RESERVE20 [24:8] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_IMIRROR_TRIM)
/*Imirror TRIM Bits */
#define LIBERO_SETTING_MSS_IMIRROR_TRIM 0x00000000UL
/* BG_CODE [0:3] RW value= 0x0 */
/* CC_CODE [3:8] RW value= 0x0 */
/* RESERVE21 [11:21] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_TEST_CTRL)
/*Test MUX Controls */
#define LIBERO_SETTING_MSS_TEST_CTRL 0x00000000UL
/* OSC_ENABLE [0:4] RW value= 0x0 */
/* ATEST_EN [4:1] RW value= 0x0 */
/* ATEST_SEL [5:5] RW value= 0x0 */
/* DTEST_EN [10:1] RW value= 0x0 */
/* DTEST_SEL [11:5] RW value= 0x0 */
/* RESERVE22 [16:16] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_MSS_CFM_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/clocks/hw_clk_mss_pll.h
+187
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_mss_pll.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_MSS_PLL_H_
#define HW_CLK_MSS_PLL_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_CTRL)
/*PLL control register */
#define LIBERO_SETTING_MSS_PLL_CTRL 0x01000037UL
/* REG_POWERDOWN_B [0:1] RW value= 0x1 */
/* REG_RFDIV_EN [1:1] RW value= 0x1 */
/* REG_DIVQ0_EN [2:1] RW value= 0x1 */
/* REG_DIVQ1_EN [3:1] RW value= 0x0 */
/* REG_DIVQ2_EN [4:1] RW value= 0x1 */
/* REG_DIVQ3_EN [5:1] RW value= 0x1 */
/* REG_RFCLK_SEL [6:1] RW value= 0x0 */
/* RESETONLOCK [7:1] RW value= 0x0 */
/* BYPCK_SEL [8:4] RW value= 0x0 */
/* REG_BYPASS_GO_B [12:1] RW value= 0x0 */
/* RESERVE10 [13:3] RSVD */
/* REG_BYPASSPRE [16:4] RW value= 0x0 */
/* REG_BYPASSPOST [20:4] RW value= 0x0 */
/* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */
/* LOCK [25:1] RO */
/* LOCK_INT_EN [26:1] RW value= 0x0 */
/* UNLOCK_INT_EN [27:1] RW value= 0x0 */
/* LOCK_INT [28:1] SW1C */
/* UNLOCK_INT [29:1] SW1C */
/* RESERVE11 [30:1] RSVD */
/* LOCK_B [31:1] RO */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_REF_FB)
/*PLL reference and feedback registers */
#define LIBERO_SETTING_MSS_PLL_REF_FB 0x00000500UL
/* FSE_B [0:1] RW value= 0x0 */
/* FBCK_SEL [1:2] RW value= 0x0 */
/* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */
/* RESERVE12 [4:4] RSVD */
/* RFDIV [8:6] RW value= 0x5 */
/* RESERVE13 [14:2] RSVD */
/* RESERVE14 [16:12] RSVD */
/* RESERVE15 [28:4] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_FRACN)
/*PLL fractional register */
#define LIBERO_SETTING_MSS_PLL_FRACN 0x00000000UL
/* FRACN_EN [0:1] RW value= 0x0 */
/* FRACN_DAC_EN [1:1] RW value= 0x0 */
/* RESERVE16 [2:6] RSVD */
/* RESERVE17 [8:24] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_DIV_0_1)
/*PLL 0/1 division registers */
#define LIBERO_SETTING_MSS_PLL_DIV_0_1 0x01000200UL
/* VCO0PH_SEL [0:3] RO */
/* DIV0_START [3:3] RW value= 0x0 */
/* RESERVE18 [6:2] RSVD */
/* POST0DIV [8:7] RW value= 0x2 */
/* RESERVE19 [15:1] RSVD */
/* VCO1PH_SEL [16:3] RO */
/* DIV1_START [19:3] RW value= 0x0 */
/* RESERVE20 [22:2] RSVD */
/* POST1DIV [24:7] RW value= 0x1 */
/* RESERVE21 [31:1] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_DIV_2_3)
/*PLL 2/3 division registers */
#define LIBERO_SETTING_MSS_PLL_DIV_2_3 0x0F000600UL
/* VCO2PH_SEL [0:3] RO */
/* DIV2_START [3:3] RW value= 0x0 */
/* RESERVE22 [6:2] RSVD */
/* POST2DIV [8:7] RW value= 0x6 */
/* RESERVE23 [15:1] RSVD */
/* VCO3PH_SEL [16:3] RO */
/* DIV3_START [19:3] RW value= 0x0 */
/* RESERVE24 [22:2] RSVD */
/* POST3DIV [24:7] RW value= 0xF */
/* CKPOST3_SEL [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_CTRL2)
/*PLL control register */
#define LIBERO_SETTING_MSS_PLL_CTRL2 0x00001020UL
/* BWI [0:2] RW value= 0x0 */
/* BWP [2:2] RW value= 0x0 */
/* IREF_EN [4:1] RW value= 0x0 */
/* IREF_TOGGLE [5:1] RW value= 0x1 */
/* RESERVE25 [6:3] RSVD */
/* LOCKCNT [9:4] RW value= 0x8 */
/* RESERVE26 [13:4] RSVD */
/* ATEST_EN [17:1] RW value= 0x0 */
/* ATEST_SEL [18:3] RW value= 0x0 */
/* RESERVE27 [21:11] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_CAL)
/*PLL calibration register */
#define LIBERO_SETTING_MSS_PLL_CAL 0x00000D06UL
/* DSKEWCALCNT [0:3] RW value= 0x6 */
/* DSKEWCAL_EN [3:1] RW value= 0x0 */
/* DSKEWCALBYP [4:1] RW value= 0x0 */
/* RESERVE28 [5:3] RSVD */
/* DSKEWCALIN [8:7] RW value= 0xd */
/* RESERVE29 [15:1] RSVD */
/* DSKEWCALOUT [16:7] RO */
/* RESERVE30 [23:9] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_PHADJ)
/*PLL phase registers */
#define LIBERO_SETTING_MSS_PLL_PHADJ 0x00004003UL
/* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */
/* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */
/* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */
/* REG_OUT1_PHSINIT [5:3] RW value= 0x0 */
/* REG_OUT2_PHSINIT [8:3] RW value= 0x0 */
/* REG_OUT3_PHSINIT [11:3] RW value= 0x8 */
/* REG_LOADPHS_B [14:1] RW value= 0x0 */
/* RESERVE31 [15:17] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_SSCG_REG_0)
/*SSCG registers 0 */
#define LIBERO_SETTING_MSS_SSCG_REG_0 0x00000000UL
/* DIVVAL [0:6] RW value= 0x0 */
/* FRACIN [6:24] RW value= 0x0 */
/* RESERVE00 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_SSCG_REG_1)
/*SSCG registers 1 */
#define LIBERO_SETTING_MSS_SSCG_REG_1 0x00000000UL
/* DOWNSPREAD [0:1] RW value= 0x0 */
/* SSMD [1:5] RW value= 0x0 */
/* FRACMOD [6:24] RO */
/* RESERVE01 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_SSCG_REG_2)
/*SSCG registers 2 */
#define LIBERO_SETTING_MSS_SSCG_REG_2 0x000000C0UL
/* INTIN [0:12] RW value= 0xC0 */
/* INTMOD [12:12] RO */
/* RESERVE02 [24:8] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_SSCG_REG_3)
/*SSCG registers 3 */
#define LIBERO_SETTING_MSS_SSCG_REG_3 0x00000001UL
/* SSE_B [0:1] RW value= 0x1 */
/* SEL_EXTWAVE [1:2] RW value= 0x0 */
/* EXT_MAXADDR [3:8] RW value= 0x0 */
/* TBLADDR [11:8] RO */
/* RANDOM_FILTER [19:1] RW value= 0x0 */
/* RANDOM_SEL [20:2] RW value= 0x0 */
/* RESERVE03 [22:1] RSVD */
/* RESERVE04 [23:9] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_MSS_PLL_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/clocks/hw_clk_sgmii_cfm.h
+84
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@@ -0,0 +1,84 @@
/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_sgmii_cfm.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_SGMII_CFM_H_
#define HW_CLK_SGMII_CFM_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_SGMII_REFCLKMUX)
/*Input mux selections */
#define LIBERO_SETTING_SGMII_REFCLKMUX 0x00000005UL
/* PLL0_RFCLK0_SEL [0:2] RW value= 0x1 */
/* PLL0_RFCLK1_SEL [2:2] RW value= 0x1 */
/* RESERVED [4:28] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_SGMII_CLKMUX)
/*sgmii clk mux */
#define LIBERO_SETTING_SGMII_SGMII_CLKMUX 0x00000005UL
/* SGMII_CLKMUX [0:32] RW value= 0x5 */
#endif
#if !defined (LIBERO_SETTING_SGMII_SPARE0)
/*spare logic */
#define LIBERO_SETTING_SGMII_SPARE0 0x00000000UL
/* RESERVED [0:32] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_CLK_XCVR)
/*Clock_Receiver */
#define LIBERO_SETTING_SGMII_CLK_XCVR 0x00002C30UL
/* EN_UDRIVE_P [0:1] RW value= 0x0 */
/* EN_INS_HYST_P [1:1] RW value= 0x0 */
/* EN_TERM_P [2:2] RW value= 0x0 */
/* EN_RXMODE_P [4:2] RW value= 0x3 */
/* EN_UDRIVE_N [6:1] RW value= 0x0 */
/* EN_INS_HYST_N [7:1] RW value= 0x0 */
/* EN_TERM_N [8:2] RW value= 0x0 */
/* EN_RXMODE_N [10:2] RW value= 0x3 */
/* CLKBUF_EN_PULLUP [12:1] RW value= 0x0 */
/* EN_RDIFF [13:1] RW value= 0x1 */
/* RESERVED [14:18] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_TEST_CTRL)
/*Test MUX Controls */
#define LIBERO_SETTING_SGMII_TEST_CTRL 0x00000000UL
/* OSC_ENABLE [0:4] RW value= 0x0 */
/* ATEST_EN [4:1] RW value= 0x0 */
/* ATEST_SEL [5:5] RW value= 0x0 */
/* DTEST_EN [10:1] RW value= 0x0 */
/* DTEST_SEL [11:5] RW value= 0x0 */
/* RESERVE22 [16:16] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_SGMII_CFM_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/clocks/hw_clk_sgmii_pll.h
+197
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_sgmii_pll.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_SGMII_PLL_H_
#define HW_CLK_SGMII_PLL_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_SGMII_SOFT_RESET)
/*This is a compulsory register for all SCB slaves and must be at the same
offset in all slaves to facilitate global soft reset of all SCB registers with
a single broadcast write from the SCB master. */
#define LIBERO_SETTING_SGMII_SOFT_RESET 0x00000000UL
/* NV_MAP [0:1] RST */
/* V_MAP [1:1] RST */
/* PERIPH [8:1] RST */
/* BLOCKID [16:16] ID */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_CTRL)
/*PLL control register */
#define LIBERO_SETTING_SGMII_PLL_CTRL 0x0100003FUL
/* REG_POWERDOWN_B [0:1] RW value= 0x1 */
/* REG_RFDIV_EN [1:1] RW value= 0x1 */
/* REG_DIVQ0_EN [2:1] RW value= 0x1 */
/* REG_DIVQ1_EN [3:1] RW value= 0x1 */
/* REG_DIVQ2_EN [4:1] RW value= 0x1 */
/* REG_DIVQ3_EN [5:1] RW value= 0x1 */
/* REG_RFCLK_SEL [6:1] RW value= 0x0 */
/* RESETONLOCK [7:1] RW value= 0x0 */
/* BYPCK_SEL [8:4] RW value= 0x0 */
/* REG_BYPASS_GO_B [12:1] RW value= 0x0 */
/* RESERVE10 [13:3] RSVD */
/* REG_BYPASSPRE [16:4] RW value= 0x0 */
/* REG_BYPASSPOST [20:4] RW value= 0x0 */
/* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */
/* LOCK [25:1] RO */
/* LOCK_INT_EN [26:1] RW value= 0x0 */
/* UNLOCK_INT_EN [27:1] RW value= 0x0 */
/* LOCK_INT [28:1] SW1C */
/* UNLOCK_INT [29:1] SW1C */
/* RESERVE11 [30:1] RSVD */
/* LOCK_B [31:1] RO */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_REF_FB)
/*PLL reference and feedback registers */
#define LIBERO_SETTING_SGMII_PLL_REF_FB 0x00000100UL
/* FSE_B [0:1] RW value= 0x0 */
/* FBCK_SEL [1:2] RW value= 0x0 */
/* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */
/* RESERVE12 [4:4] RSVD */
/* RFDIV [8:6] RW value= 0x1 */
/* RESERVE13 [14:2] RSVD */
/* RESERVE14 [16:12] RSVD */
/* RESERVE15 [28:4] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_FRACN)
/*PLL fractional register */
#define LIBERO_SETTING_SGMII_PLL_FRACN 0x00000000UL
/* FRACN_EN [0:1] RW value= 0x0 */
/* FRACN_DAC_EN [1:1] RW value= 0x0 */
/* RESERVE16 [2:6] RSVD */
/* RESERVE17 [8:24] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_DIV_0_1)
/*PLL 0/1 division registers */
#define LIBERO_SETTING_SGMII_PLL_DIV_0_1 0x01000100UL
/* VCO0PH_SEL [0:3] RO */
/* DIV0_START [3:3] RW value= 0x0 */
/* RESERVE18 [6:2] RSVD */
/* POST0DIV [8:7] RW value= 0x1 */
/* RESERVE19 [15:1] RSVD */
/* VCO1PH_SEL [16:3] RO */
/* DIV1_START [19:3] RW value= 0x0 */
/* RESERVE20 [22:2] RSVD */
/* POST1DIV [24:7] RW value= 0x1 */
/* RESERVE21 [31:1] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_DIV_2_3)
/*PLL 2/3 division registers */
#define LIBERO_SETTING_SGMII_PLL_DIV_2_3 0x01000100UL
/* VCO2PH_SEL [0:3] RO */
/* DIV2_START [3:3] RW value= 0x0 */
/* RESERVE22 [6:2] RSVD */
/* POST2DIV [8:7] RW value= 0x1 */
/* RESERVE23 [15:1] RSVD */
/* VCO3PH_SEL [16:3] RO */
/* DIV3_START [19:3] RW value= 0x0 */
/* RESERVE24 [22:2] RSVD */
/* POST3DIV [24:7] RW value= 0x1 */
/* CKPOST3_SEL [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_CTRL2)
/*PLL control register */
#define LIBERO_SETTING_SGMII_PLL_CTRL2 0x00001020UL
/* BWI [0:2] RW value= 0x0 */
/* BWP [2:2] RW value= 0x0 */
/* IREF_EN [4:1] RW value= 0x0 */
/* IREF_TOGGLE [5:1] RW value= 0x1 */
/* RESERVE25 [6:3] RSVD */
/* LOCKCNT [9:4] RW value= 0x8 */
/* RESERVE26 [13:4] RSVD */
/* ATEST_EN [17:1] RW value= 0x0 */
/* ATEST_SEL [18:3] RW value= 0x0 */
/* RESERVE27 [21:11] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_CAL)
/*PLL calibration register */
#define LIBERO_SETTING_SGMII_PLL_CAL 0x00000D06UL
/* DSKEWCALCNT [0:3] RW value= 0x6 */
/* DSKEWCAL_EN [3:1] RW value= 0x0 */
/* DSKEWCALBYP [4:1] RW value= 0x0 */
/* RESERVE28 [5:3] RSVD */
/* DSKEWCALIN [8:7] RW value= 0xd */
/* RESERVE29 [15:1] RSVD */
/* DSKEWCALOUT [16:7] RO */
/* RESERVE30 [23:9] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_PHADJ)
/*PLL phase registers */
#define LIBERO_SETTING_SGMII_PLL_PHADJ 0x00007443UL
/* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */
/* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */
/* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */
/* REG_OUT1_PHSINIT [5:3] RW value= 0x2 */
/* REG_OUT2_PHSINIT [8:3] RW value= 0x4 */
/* REG_OUT3_PHSINIT [11:3] RW value= 0x6 */
/* REG_LOADPHS_B [14:1] RW value= 0x1 */
/* RESERVE31 [15:17] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_0)
/*SSCG registers 0 */
#define LIBERO_SETTING_SGMII_SSCG_REG_0 0x00000000UL
/* DIVVAL [0:6] RW value= 0x0 */
/* FRACIN [6:24] RW value= 0x0 */
/* RESERVE00 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_1)
/*SSCG registers 1 */
#define LIBERO_SETTING_SGMII_SSCG_REG_1 0x00000000UL
/* DOWNSPREAD [0:1] RW value= 0x0 */
/* SSMD [1:5] RW value= 0x0 */
/* FRACMOD [6:24] RO */
/* RESERVE01 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_2)
/*SSCG registers 2 */
#define LIBERO_SETTING_SGMII_SSCG_REG_2 0x00000014UL
/* INTIN [0:12] RW value= 0x14 */
/* INTMOD [12:12] RO */
/* RESERVE02 [24:8] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_3)
/*SSCG registers 3 */
#define LIBERO_SETTING_SGMII_SSCG_REG_3 0x00000001UL
/* SSE_B [0:1] RW value= 0x1 */
/* SEL_EXTWAVE [1:2] RW value= 0x0 */
/* EXT_MAXADDR [3:8] RW value= 0x0 */
/* TBLADDR [11:8] RO */
/* RANDOM_FILTER [19:1] RW value= 0x0 */
/* RANDOM_SEL [20:2] RW value= 0x0 */
/* RESERVE03 [22:1] RSVD */
/* RESERVE04 [23:9] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_SGMII_PLL_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/clocks/hw_clk_sysreg.h
+66
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@@ -0,0 +1,66 @@
/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_sysreg.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_SYSREG_H_
#define HW_CLK_SYSREG_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MSS_CLOCK_CONFIG_CR)
/*Master clock config (00=/1 01=/2 10=/4 11=/8 ) */
#define LIBERO_SETTING_MSS_CLOCK_CONFIG_CR 0x00000024UL
/* DIVIDER_CPU [0:2] RW value= 0x0 */
/* DIVIDER_AXI [2:2] RW value= 0x1 */
/* DIVIDER_APB_AHB [4:2] RW value= 0x2 */
#endif
#if !defined (LIBERO_SETTING_MSS_RTC_CLOCK_CR)
/*RTC clock divider */
#define LIBERO_SETTING_MSS_RTC_CLOCK_CR 0x0000007DUL
/* PERIOD [0:12] RW value= 0x7D */
#endif
#if !defined (LIBERO_SETTING_MSS_ENVM_CR)
/*ENVM AHB Controller setup - - Clock period = (Value+1) * (1000/AHBFREQMHZ)
e.g. 7 will generate a 40ns period 25MHz clock if the AHB clock is 200MHz */
#define LIBERO_SETTING_MSS_ENVM_CR 0x40050006UL
/* CLOCK_PERIOD [0:6] RW value= 0x6 */
/* CLOCK_CONTINUOUS [8:1] RW value= 0x0 */
/* CLOCK_SUPPRESS [9:1] RW value= 0x0 */
/* READAHEAD [16:1] RW value= 0x1 */
/* SLOWREAD [17:1] RW value= 0x0 */
/* INTERRUPT_ENABLE [18:1] RW value= 0x1 */
/* TIMER [24:8] RW value= 0x40 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_SYSREG_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/clocks/hw_mss_clks.h
+72
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@@ -0,0 +1,72 @@
/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mss_clks.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MSS_CLKS_H_
#define HW_MSS_CLKS_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK)
/*Ref Clock rate in MHz */
#define LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK 125000000
/* MSS_EXT_SGMII_REF_CLK [0:32] RW value= 125000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_COREPLEX_CPU_CLK)
/*CPU Clock rate in MHz */
#define LIBERO_SETTING_MSS_COREPLEX_CPU_CLK 600000000
/* MSS_COREPLEX_CPU_CLK [0:32] RW value= 600000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_SYSTEM_CLK)
/*System Clock rate in MHz static power. */
#define LIBERO_SETTING_MSS_SYSTEM_CLK 600000000
/* MSS_SYSTEM_CLK [0:32] RW value= 600000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_RTC_TOGGLE_CLK)
/*RTC toggle Clock rate in MHz static power. */
#define LIBERO_SETTING_MSS_RTC_TOGGLE_CLK 1000000
/* MSS_RTC_TOGGLE_CLK [0:32] RW value= 1000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_AXI_CLK)
/*AXI Clock rate in MHz static power. */
#define LIBERO_SETTING_MSS_AXI_CLK 300000000
/* MSS_AXI_CLK [0:32] RW value= 300000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_APB_AHB_CLK)
/*AXI Clock rate in MHz static power. */
#define LIBERO_SETTING_MSS_APB_AHB_CLK 150000000
/* MSS_APB_AHB_CLK [0:32] RW value= 150000000 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MSS_CLKS_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/ddr/hw_ddr_io_bank.h
+512
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FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/ddr/hw_ddr_mode.h
+69
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_ddr_mode.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_DDR_MODE_H_
#define HW_DDR_MODE_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_DDRPHY_MODE)
/*DDRPHY MODE (binary)- 000 ddr3, 001 ddr33L, 010 ddr4, 011 LPDDR3, 100 LPDDR4,
111 OFF_MODE */
#define LIBERO_SETTING_DDRPHY_MODE 0x00014B24UL
/* DDRMODE [0:3] RW value= 0x4 */
/* ECC [3:1] RW value= 0x0 */
/* CRC [4:1] RW value= 0x0 */
/* BUS_WIDTH [5:3] RW value= 0x1 */
/* DMI_DBI [8:1] RW value= 0x1 */
/* DQ_DRIVE [9:2] RW value= 0x1 */
/* DQS_DRIVE [11:2] RW value= 0x1 */
/* ADD_CMD_DRIVE [13:2] RW value= 0x2 */
/* CLOCK_OUT_DRIVE [15:2] RW value= 0x2 */
/* DQ_TERMINATION [17:2] RW value= 0x0 */
/* DQS_TERMINATION [19:2] RW value= 0x0 */
/* ADD_CMD_INPUT_PIN_TERMINATION [21:2] RW value= 0x0 */
/* PRESET_ODT_CLK [23:2] RW value= 0x0 */
/* POWER_DOWN [25:1] RW value= 0x0 */
/* RANK [26:1] RW value= 0x0 */
/* RESERVED [27:5] RSVD */
#endif
#if !defined (LIBERO_SETTING_DATA_LANES_USED)
/*number of lanes used for data- does not include ECC, infer from mode register
*/
#define LIBERO_SETTING_DATA_LANES_USED 0x00000004UL
/* DATA_LANES [0:3] RW value= 0x4 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_DDR_MODE_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/ddr/hw_ddr_off_mode.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_ddr_off_mode.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_DDR_OFF_MODE_H_
#define HW_DDR_OFF_MODE_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_DDRPHY_MODE_OFF)
/*DDRPHY MODE Register, ddr off */
#define LIBERO_SETTING_DDRPHY_MODE_OFF 0x00000000UL
/* DDRMODE [0:3] RW value= 0x0 */
/* ECC [3:1] RW value= 0x0 */
/* CRC [4:1] RW value= 0x0 */
/* BUS_WIDTH [5:3] RW value= 0x0 */
/* DMI_DBI [8:1] RW value= 0x0 */
/* DQ_DRIVE [9:2] RW value= 0x0 */
/* DQS_DRIVE [11:2] RW value= 0x0 */
/* ADD_CMD_DRIVE [13:2] RW value= 0x0 */
/* CLOCK_OUT_DRIVE [15:2] RW value= 0x0 */
/* DQ_TERMINATION [17:2] RW value= 0x0 */
/* DQS_TERMINATION [19:2] RW value= 0x0 */
/* ADD_CMD_INPUT_PIN_TERMINATION [21:2] RW value= 0x0 */
/* PRESET_ODT_CLK [23:2] RW value= 0x0 */
/* POWER_DOWN [25:1] RW value= 0x0 */
/* RANK [26:1] RW value= 0x0 */
/* RESERVED [27:5] RSVD */
#endif
#if !defined (LIBERO_SETTING_DPC_BITS_OFF_MODE)
/*DPC Bits Register off mode */
#define LIBERO_SETTING_DPC_BITS_OFF_MODE 0x00000000UL
/* DPC_VS [0:4] RW value= 0x0 */
/* DPC_VRGEN_H [4:6] RW value= 0x0 */
/* DPC_VRGEN_EN_H [10:1] RW value= 0x0 */
/* DPC_MOVE_EN_H [11:1] RW value= 0x0 */
/* DPC_VRGEN_V [12:6] RW value= 0x0 */
/* DPC_VRGEN_EN_V [18:1] RW value= 0x0 */
/* DPC_MOVE_EN_V [19:1] RW value= 0x0 */
/* RESERVE01 [20:12] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_DDR_OFF_MODE_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/ddr/hw_ddr_options.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_ddr_options.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_DDR_OPTIONS_H_
#define HW_DDR_OPTIONS_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_CA_BUS_RX_OFF_POST_TRAINING)
/*Tip config: Referenced receivers in the CA bus are turned on for CA training.
These burn static power.(0x01 => turn off ; 0x00 => no action ) */
#define LIBERO_SETTING_CA_BUS_RX_OFF_POST_TRAINING 0x00000001UL
/* CA_BUS_RX_OFF_POST_TRAINING [0:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_USER_INPUT_PHY_RANKS_TO_TRAIN)
/*Tip config: 1 => 1 rank, 3 => 2 ranks */
#define LIBERO_SETTING_USER_INPUT_PHY_RANKS_TO_TRAIN 0x00000001UL
/* USER_INPUT_PHY_RANKS_TO_TRAIN [0:2] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_TRAINING_SKIP_SETTING)
/*Tip config: Pick what trainings we want performed by the TIP, default is 0x1F
*/
#define LIBERO_SETTING_TRAINING_SKIP_SETTING 0x00000002UL
/* SKIP_BCLKSCLK_TIP_TRAINING [0:1] RW value= 0x0 */
/* SKIP_ADDCMD_TIP_TRAINING [1:1] RW value= 0x1 */
/* SKIP_WRLVL_TIP_TRAINING [2:1] RW value= 0x0 */
/* SKIP_RDGATE_TIP_TRAINING [3:1] RW value= 0x0 */
/* SKIP_DQ_DQS_OPT_TIP_TRAINING [4:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_TIP_CFG_PARAMS)
/*Tip config: default: 0x2,0x4,0x0,0x1F,0x1F */
#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE02AUL
/* ADDCMD_OFFSET [0:3] RW value= 0x2 */
/* BCKLSCLK_OFFSET [3:3] RW value= 0x5 */
/* WRCALIB_WRITE_COUNT [6:7] RW value= 0x0 */
/* READ_GATE_MIN_READS [13:8] RW value= 0x7F */
/* ADDRCMD_WAIT_COUNT [22:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_TIP_CONFIG_PARAMS_BCLK_VCOPHS_OFFSET)
/*in simulation we need to set this to 2, for hardware it will be dependent on
the trace lengths */
#define LIBERO_SETTING_TIP_CONFIG_PARAMS_BCLK_VCOPHS_OFFSET 0x00000002UL
/* TIP_CONFIG_PARAMS_BCLK_VCOPHS [0:32] RW value= 0x02 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_DDR_OPTIONS_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/ddr/hw_ddr_segs.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_ddr_segs.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_DDR_SEGS_H_
#define HW_DDR_SEGS_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_SEG0_0)
/*Cached access at 0x00_8000_0000 (-0x80+0x00) */
#define LIBERO_SETTING_SEG0_0 0x80007F80UL
/* ADDRESS_OFFSET [0:15] RW value= 0x7F80 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_SEG0_1)
/*Cached access at 0x10_0000_000 */
#define LIBERO_SETTING_SEG0_1 0x80007030UL
/* ADDRESS_OFFSET [0:15] RW value= 0x7030 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_SEG0_2)
/*not used */
#define LIBERO_SETTING_SEG0_2 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG0_3)
/*not used */
#define LIBERO_SETTING_SEG0_3 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG0_4)
/*not used */
#define LIBERO_SETTING_SEG0_4 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG0_5)
/*not used */
#define LIBERO_SETTING_SEG0_5 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:6] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG0_6)
/*not used */
#define LIBERO_SETTING_SEG0_6 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG0_7)
/*not used */
#define LIBERO_SETTING_SEG0_7 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG1_0)
/*not used */
#define LIBERO_SETTING_SEG1_0 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG1_1)
/*not used */
#define LIBERO_SETTING_SEG1_1 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG1_2)
/*Non-Cached access at 0x00_c000_0000 */
#define LIBERO_SETTING_SEG1_2 0x80007FB0UL
/* ADDRESS_OFFSET [0:15] RW value= 0x7FB0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_SEG1_3)
/*Non-Cached access at 0x14_0000_0000 */
#define LIBERO_SETTING_SEG1_3 0x80000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_SEG1_4)
/*Non-Cached WCB access at 0x00_d000_0000 */
#define LIBERO_SETTING_SEG1_4 0x80007FA0UL
/* ADDRESS_OFFSET [0:15] RW value= 0x7FA0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_SEG1_5)
/*Non-Cached WCB 0x18_0000_0000 */
#define LIBERO_SETTING_SEG1_5 0x80000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:6] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_SEG1_6)
/*Trace - Trace not in use here so can be left as 0 */
#define LIBERO_SETTING_SEG1_6 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG1_7)
/*not used */
#define LIBERO_SETTING_SEG1_7 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_DDR_SEGS_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/ddr/hw_ddrc.h
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FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file fpga_design_config.h
* @author Embedded Software
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef FPGA_DESIGN_CONFIG_H_
#define FPGA_DESIGN_CONFIG_H_
#define LIBERO_SETTING_MSS_CONFIGURATOR_VERSION "2021.1"
#define LIBERO_SETTING_DESIGN_NAME "ICICLE_MSS"
#define LIBERO_SETTING_MPFS_PART "MPFS250T_ES"
#define LIBERO_SETTING_GENERATION_DATE "04-11-2021_22:30:25"
#define LIBERO_SETTING_XML_VERSION "0.5.3"
#define LIBERO_SETTING_XML_VERSION_MAJOR 0
#define LIBERO_SETTING_XML_VERSION_MINOR 5
#define LIBERO_SETTING_XML_VERSION_PATCH 3
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION "0.6.3"
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_MAJOR 0
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_MINOR 6
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_PATCH 3
#include "memory_map/hw_memory.h"
#include "memory_map/hw_apb_split.h"
#include "memory_map/hw_cache.h"
#include "memory_map/hw_pmp_hart0.h"
#include "memory_map/hw_pmp_hart1.h"
#include "memory_map/hw_pmp_hart2.h"
#include "memory_map/hw_pmp_hart3.h"
#include "memory_map/hw_pmp_hart4.h"
#include "memory_map/hw_mpu_fic0.h"
#include "memory_map/hw_mpu_fic1.h"
#include "memory_map/hw_mpu_fic2.h"
#include "memory_map/hw_mpu_crypto.h"
#include "memory_map/hw_mpu_gem0.h"
#include "memory_map/hw_mpu_gem1.h"
#include "memory_map/hw_mpu_usb.h"
#include "memory_map/hw_mpu_mmc.h"
#include "memory_map/hw_mpu_scb.h"
#include "memory_map/hw_mpu_trace.h"
#include "io/hw_mssio_mux.h"
#include "io/hw_hsio_mux.h"
#include "sgmii/hw_sgmii_tip.h"
#include "ddr/hw_ddr_options.h"
#include "ddr/hw_ddr_io_bank.h"
#include "ddr/hw_ddr_mode.h"
#include "ddr/hw_ddr_off_mode.h"
#include "ddr/hw_ddr_segs.h"
#include "ddr/hw_ddrc.h"
#include "clocks/hw_mss_clks.h"
#include "clocks/hw_clk_sysreg.h"
#include "clocks/hw_clk_mss_pll.h"
#include "clocks/hw_clk_sgmii_pll.h"
#include "clocks/hw_clk_ddr_pll.h"
#include "clocks/hw_clk_mss_cfm.h"
#include "clocks/hw_clk_sgmii_cfm.h"
#include "general/hw_gen_peripherals.h"
#ifdef __cplusplus
extern "C" {
#endif
/* No content in this file, used for referencing header */
#ifdef __cplusplus
}
#endif
#endif /* #ifdef FPGA_DESIGN_CONFIG_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/general/hw_gen_peripherals.h
+61
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_gen_peripherals.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_GEN_PERIPHERALS_H_
#define HW_GEN_PERIPHERALS_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_GPIO_CR)
/*GPIO Blocks reset control- (soft_reset options chossen in Libero confgurator)
*/
#define LIBERO_SETTING_GPIO_CR 0x000F0703UL
/* GPIO0_SOFT_RESET_SELECT [0:2] RW value= 0x3 */
/* GPIO0_DEFAULT [4:2] RW value= 0x0 */
/* GPIO1_SOFT_RESET_SELECT [8:3] RW value= 0x7 */
/* GPIO1_DEFAULT [12:3] RW value= 0x0 */
/* GPIO2_SOFT_RESET_SELECT [16:4] RW value= 0xF */
/* GPIO2_DEFAULT [20:4] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_CRYPTO_CR_INFO)
/*Information on how Crypto setup on this MPFS */
#define LIBERO_SETTING_CRYPTO_CR_INFO 0x00000000UL
/* MSS_MODE [0:2] RO */
/* RESERVED [2:1] RO */
/* STREAM_ENABLE [3:1] RO */
/* RESERVED1 [4:28] RO */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_GEN_PERIPHERALS_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/io/hw_hsio_mux.h
+60
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_hsio_mux.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_HSIO_MUX_H_
#define HW_HSIO_MUX_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_TRIM_OPTIONS)
/*User trim options- set option to 1 to use */
#define LIBERO_SETTING_TRIM_OPTIONS 0x00000000UL
/* TRIM_DDR_OPTION [0:1] */
/* TRIM_SGMII_OPTION [1:1] */
#endif
#if !defined (LIBERO_SETTING_DDR_IOC_REG0)
/*Manual trim values */
#define LIBERO_SETTING_DDR_IOC_REG0 0x00000000UL
/* BANK_PCODE [0:6] RW value= 0x0 */
/* BANK_NCODE [6:6] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_IOC_REG0)
/*Manual trim values */
#define LIBERO_SETTING_SGMII_IOC_REG0 0x00000000UL
/* BANK_PCODE [0:6] RW value= 0x0 */
/* BANK_NCODE [6:6] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_HSIO_MUX_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/io/hw_mssio_mux.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mssio_mux.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MSSIO_MUX_H_
#define HW_MSSIO_MUX_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_IOMUX0_CR)
/*Selects whether the peripheral is connected to the Fabric or IOMUX structure.
*/
#define LIBERO_SETTING_IOMUX0_CR 0x00000F9DUL
/* SPI0_FABRIC [0:1] RW value= 0x1 */
/* SPI1_FABRIC [1:1] RW value= 0x0 */
/* I2C0_FABRIC [2:1] RW value= 0x1 */
/* I2C1_FABRIC [3:1] RW value= 0x1 */
/* CAN0_FABRIC [4:1] RW value= 0x1 */
/* CAN1_FABRIC [5:1] RW value= 0x0 */
/* QSPI_FABRIC [6:1] RW value= 0x0 */
/* MMUART0_FABRIC [7:1] RW value= 0x1 */
/* MMUART1_FABRIC [8:1] RW value= 0x1 */
/* MMUART2_FABRIC [9:1] RW value= 0x1 */
/* MMUART3_FABRIC [10:1] RW value= 0x1 */
/* MMUART4_FABRIC [11:1] RW value= 0x1 */
/* MDIO0_FABRIC [12:1] RW value= 0x0 */
/* MDIO1_FABRIC [13:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_IOMUX1_CR)
/*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies
EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies
I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved
(Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies
Logic 0,0xE implies Logic 1, 0xF implies Tristate */
#define LIBERO_SETTING_IOMUX1_CR 0x11111111UL
/* PAD0 [0:4] RW value= 0x1 */
/* PAD1 [4:4] RW value= 0x1 */
/* PAD2 [8:4] RW value= 0x1 */
/* PAD3 [12:4] RW value= 0x1 */
/* PAD4 [16:4] RW value= 0x1 */
/* PAD5 [20:4] RW value= 0x1 */
/* PAD6 [24:4] RW value= 0x1 */
/* PAD7 [28:4] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_IOMUX2_CR)
/*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies
EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies
I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved
(Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies
Logic 0,0xE implies Logic 1, 0xF implies Tristate */
#define LIBERO_SETTING_IOMUX2_CR 0x00FF1111UL
/* PAD8 [0:4] RW value= 0x1 */
/* PAD9 [4:4] RW value= 0x1 */
/* PAD10 [8:4] RW value= 0x1 */
/* PAD11 [12:4] RW value= 0x1 */
/* PAD12 [16:4] RW value= 0xF */
/* PAD13 [20:4] RW value= 0xF */
#endif
#if !defined (LIBERO_SETTING_IOMUX3_CR)
/*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies
EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies
I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved
(Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies
Logic 0,0xE implies Logic 1, 0xF implies Tristate */
#define LIBERO_SETTING_IOMUX3_CR 0x44444444UL
/* PAD14 [0:4] RW value= 0x4 */
/* PAD15 [4:4] RW value= 0x4 */
/* PAD16 [8:4] RW value= 0x4 */
/* PAD17 [12:4] RW value= 0x4 */
/* PAD18 [16:4] RW value= 0x4 */
/* PAD19 [20:4] RW value= 0x4 */
/* PAD20 [24:4] RW value= 0x4 */
/* PAD21 [28:4] RW value= 0x4 */
#endif
#if !defined (LIBERO_SETTING_IOMUX4_CR)
/*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies
EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies
I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved
(Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies
Logic 0,0xE implies Logic 1, 0xF implies Tristate */
#define LIBERO_SETTING_IOMUX4_CR 0x88CC4444UL
/* PAD22 [0:4] RW value= 0x4 */
/* PAD23 [4:4] RW value= 0x4 */
/* PAD24 [8:4] RW value= 0x4 */
/* PAD25 [12:4] RW value= 0x4 */
/* PAD26 [16:4] RW value= 0xC */
/* PAD27 [20:4] RW value= 0xC */
/* PAD28 [24:4] RW value= 0x8 */
/* PAD29 [28:4] RW value= 0x8 */
#endif
#if !defined (LIBERO_SETTING_IOMUX5_CR)
/*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies
EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies
I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved
(Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies
Logic 0,0xE implies Logic 1, 0xF implies Tristate */
#define LIBERO_SETTING_IOMUX5_CR 0xF7772222UL
/* PAD30 [0:4] RW value= 0x2 */
/* PAD31 [4:4] RW value= 0x2 */
/* PAD32 [8:4] RW value= 0x2 */
/* PAD33 [12:4] RW value= 0x2 */
/* PAD34 [16:4] RW value= 0x7 */
/* PAD35 [20:4] RW value= 0x7 */
/* PAD36 [24:4] RW value= 0x7 */
/* PAD37 [28:4] RW value= 0xF */
#endif
#if !defined (LIBERO_SETTING_IOMUX6_CR)
/*Sets whether the MMC/SD Voltage select lines are inverted on entry to the
IOMUX structure */
#define LIBERO_SETTING_IOMUX6_CR 0x00000000UL
/* VLT_SEL [0:1] RW value= 0x0 */
/* VLT_EN [1:1] RW value= 0x0 */
/* VLT_CMD_DIR [2:1] RW value= 0x0 */
/* VLT_DIR_0 [3:1] RW value= 0x0 */
/* VLT_DIR_1_3 [4:1] RW value= 0x0 */
/* SD_LED [5:1] RW value= 0x0 */
/* SD_VOLT_0 [6:1] RW value= 0x0 */
/* SD_VOLT_1 [7:1] RW value= 0x0 */
/* SD_VOLT_2 [8:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_CFG_CR)
/*Configures the MSSIO block using SCB write */
#define LIBERO_SETTING_MSSIO_BANK4_CFG_CR 0x00040A0DUL
/* BANK_PCODE [0:6] RW value= 0xD */
/* RESERVED0 [6:2] RW value= 0x00 */
/* BANK_NCODE [8:6] RW value= 0xA */
/* RESERVED1 [14:2] RW value= 0x0 */
/* VS [16:4] RW value= 0x4 */
/* RESERVED2 [20:12] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_0_1_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_0_1_CR 0x09280928UL
/* IO_CFG_0 [0:16] RW value= 0x0928 */
/* IO_CFG_1 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_2_3_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_2_3_CR 0x09280928UL
/* IO_CFG_2 [0:16] RW value= 0x0928 */
/* IO_CFG_3 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_4_5_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_4_5_CR 0x09280928UL
/* IO_CFG_4 [0:16] RW value= 0x0928 */
/* IO_CFG_5 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_6_7_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_6_7_CR 0x09280928UL
/* IO_CFG_6 [0:16] RW value= 0x0928 */
/* IO_CFG_7 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_8_9_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_8_9_CR 0x09280928UL
/* IO_CFG_8 [0:16] RW value= 0x0928 */
/* IO_CFG_9 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_10_11_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_10_11_CR 0x09280928UL
/* IO_CFG_10 [0:16] RW value= 0x0928 */
/* IO_CFG_11 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_12_13_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_12_13_CR 0x09280928UL
/* IO_CFG_12 [0:16] RW value= 0x0928 */
/* IO_CFG_13 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_CFG_CR)
/*Configures the MSSIO block using SCB write */
#define LIBERO_SETTING_MSSIO_BANK2_CFG_CR 0x00080907UL
/* BANK_PCODE [0:6] RW value= 0x7 */
/* RESERVED0 [6:2] RW value= 0x00 */
/* BANK_NCODE [8:6] RW value= 0x9 */
/* RESERVED1 [14:2] RW value= 0x0 */
/* VS [16:4] RW value= 0x8 */
/* RESERVED2 [20:12] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_0_1_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_0_1_CR 0x08290829UL
/* IO_CFG_0 [0:16] RW value= 0x0829 */
/* IO_CFG_1 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_2_3_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_2_3_CR 0x08290829UL
/* IO_CFG_2 [0:16] RW value= 0x0829 */
/* IO_CFG_3 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_4_5_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_4_5_CR 0x08290829UL
/* IO_CFG_4 [0:16] RW value= 0x0829 */
/* IO_CFG_5 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_6_7_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_6_7_CR 0x08290829UL
/* IO_CFG_6 [0:16] RW value= 0x0829 */
/* IO_CFG_7 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_8_9_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_8_9_CR 0x08290829UL
/* IO_CFG_8 [0:16] RW value= 0x0829 */
/* IO_CFG_9 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_10_11_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_10_11_CR 0x08290829UL
/* IO_CFG_10 [0:16] RW value= 0x0829 */
/* IO_CFG_11 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_12_13_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_12_13_CR 0x08290829UL
/* IO_CFG_12 [0:16] RW value= 0x0829 */
/* IO_CFG_13 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_14_15_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_14_15_CR 0x08290829UL
/* IO_CFG_14 [0:16] RW value= 0x0829 */
/* IO_CFG_15 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_16_17_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_16_17_CR 0x08290829UL
/* IO_CFG_16 [0:16] RW value= 0x0829 */
/* IO_CFG_17 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_18_19_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_18_19_CR 0x08290829UL
/* IO_CFG_18 [0:16] RW value= 0x0829 */
/* IO_CFG_19 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_20_21_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_20_21_CR 0x08290829UL
/* IO_CFG_20 [0:16] RW value= 0x0829 */
/* IO_CFG_21 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_22_23_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_22_23_CR 0x08290829UL
/* IO_CFG_22 [0:16] RW value= 0x0829 */
/* IO_CFG_23 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_VB2_CFG)
/*default dpc values for MSSIO bank 2 */
#define LIBERO_SETTING_MSSIO_VB2_CFG 0x00000828UL
/* DPC_IO_CFG_IBUFMD_0 [0:1] RW value= 0x0 */
/* DPC_IO_CFG_IBUFMD_1 [1:1] RW value= 0x0 */
/* DPC_IO_CFG_IBUFMD_2 [2:1] RW value= 0x0 */
/* DPC_IO_CFG_DRV_0 [3:1] RW value= 0x1 */
/* DPC_IO_CFG_DRV_1 [4:1] RW value= 0x0 */
/* DPC_IO_CFG_DRV_2 [5:1] RW value= 0x1 */
/* DPC_IO_CFG_DRV_3 [6:1] RW value= 0x0 */
/* DPC_IO_CFG_CLAMP [7:1] RW value= 0x0 */
/* DPC_IO_CFG_ENHYST [8:1] RW value= 0x0 */
/* DPC_IO_CFG_LOCKDN_EN [9:1] RW value= 0x0 */
/* DPC_IO_CFG_WPD [10:1] RW value= 0x0 */
/* DPC_IO_CFG_WPU [11:1] RW value= 0x1 */
/* DPC_IO_CFG_ATP_EN [12:1] RW value= 0x0 */
/* DPC_IO_CFG_LP_PERSIST_EN [13:1] RW value= 0x0 */
/* DPC_IO_CFG_LP_BYPASS_EN [14:1] RW value= 0x0 */
/* RESERVED [15:17] R */
#endif
#if !defined (LIBERO_SETTING_MSSIO_VB4_CFG)
/*default dpc values for MSSIO bank 4 */
#define LIBERO_SETTING_MSSIO_VB4_CFG 0x00000828UL
/* DPC_IO_CFG_IBUFMD_0 [0:1] RW value= 0x0 */
/* DPC_IO_CFG_IBUFMD_1 [1:1] RW value= 0x0 */
/* DPC_IO_CFG_IBUFMD_2 [2:1] RW value= 0x0 */
/* DPC_IO_CFG_DRV_0 [3:1] RW value= 0x1 */
/* DPC_IO_CFG_DRV_1 [4:1] RW value= 0x0 */
/* DPC_IO_CFG_DRV_2 [5:1] RW value= 0x1 */
/* DPC_IO_CFG_DRV_3 [6:1] RW value= 0x0 */
/* DPC_IO_CFG_CLAMP [7:1] RW value= 0x0 */
/* DPC_IO_CFG_ENHYST [8:1] RW value= 0x0 */
/* DPC_IO_CFG_LOCKDN_EN [9:1] RW value= 0x0 */
/* DPC_IO_CFG_WPD [10:1] RW value= 0x0 */
/* DPC_IO_CFG_WPU [11:1] RW value= 0x1 */
/* DPC_IO_CFG_ATP_EN [12:1] RW value= 0x0 */
/* DPC_IO_CFG_LP_PERSIST_EN [13:1] RW value= 0x0 */
/* DPC_IO_CFG_LP_BYPASS_EN [14:1] RW value= 0x0 */
/* RESERVED [15:17] R */
#endif
#if !defined (LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS)
/*Indicates if eMMC is configured for use (bit 0 == 1), If SD is configued for
use (bit 1 == 1). Bit 2 indicates which one should be used by default on MSS
embedded software startup ( bit2 == 0, implies default is eMMC, bit2 == 1,
implies default is SD). The eMMC configuration is always defined in xml tag
(io_mux, the SD configuration is always defined in xml tag (io_mux_alt). All
other elements in the (o_mux) and (io_mux_alt) not releating to eMMC/SD
differences should be the same values. */
#define LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS 0x00000000UL
/* EMMC_CONFIGURED [0:1] RW value= 0x0 */
/* SD_CONFIGURED [1:1] RW value= 0x0 */
/* DEFAULT_ON_START [2:1] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MSSIO_MUX_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_apb_split.h
+174
View File
@@ -0,0 +1,174 @@
/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_apb_split.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_APB_SPLIT_H_
#define HW_APB_SPLIT_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_APB_SPLIT_VERSION)
/*This version incrments when change to format of this file */
#define LIBERO_SETTING_APB_SPLIT_VERSION 0x00000001UL
/* VERSION [0:32] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_MEM_CONFIGS_ENABLED)
/*Enabled in configurator when bit set to 1 */
#define LIBERO_SETTING_MEM_CONFIGS_ENABLED 0x00000000UL
/* PMP [0:0] RW value= 0x0 */
/* MPU [1:0] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_APBBUS_CR)
/*AMP Mode peripheral mapping register. When the register bit is '0' the
peripheral is mapped into the 0x2000000 address range using AXI bus 5 from the
Coreplex. When the register bit is '1' the peripheral is mapped into the
0x28000000 address range using AXI bus 6 from the Coreplex. */
#define LIBERO_SETTING_APBBUS_CR 0x00000000UL
/* MMUART0 [0:1] RW value= 0x0 */
/* MMUART1 [1:1] RW value= 0x0 */
/* MMUART2 [2:1] RW value= 0x0 */
/* MMUART3 [3:1] RW value= 0x0 */
/* MMUART4 [4:1] RW value= 0x0 */
/* WDOG0 [5:1] RW value= 0x0 */
/* WDOG1 [6:1] RW value= 0x0 */
/* WDOG2 [7:1] RW value= 0x0 */
/* WDOG3 [8:1] RW value= 0x0 */
/* WDOG4 [9:1] RW value= 0x0 */
/* SPI0 [10:1] RW value= 0x0 */
/* SPI1 [11:1] RW value= 0x0 */
/* I2C0 [12:1] RW value= 0x0 */
/* I2C1 [13:1] RW value= 0x0 */
/* CAN0 [14:1] RW value= 0x0 */
/* CAN1 [15:1] RW value= 0x0 */
/* GEM0 [16:1] RW value= 0x0 */
/* GEM1 [17:1] RW value= 0x0 */
/* TIMER [18:1] RW value= 0x0 */
/* GPIO0 [19:1] RW value= 0x0 */
/* GPIO1 [20:1] RW value= 0x0 */
/* GPIO2 [21:1] RW value= 0x0 */
/* RTC [22:1] RW value= 0x0 */
/* H2FINT [23:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_CONTEXT_A_EN)
/*AMP context A. When the register bit is '0' the peripheral is not allowed
access from context A. */
#define LIBERO_SETTING_CONTEXT_A_EN 0x00000000UL
/* MMUART0 [0:1] RW value= 0x0 */
/* MMUART1 [1:1] RW value= 0x0 */
/* MMUART2 [2:1] RW value= 0x0 */
/* MMUART3 [3:1] RW value= 0x0 */
/* MMUART4 [4:1] RW value= 0x0 */
/* WDOG0 [5:1] RW value= 0x0 */
/* WDOG1 [6:1] RW value= 0x0 */
/* WDOG2 [7:1] RW value= 0x0 */
/* WDOG3 [8:1] RW value= 0x0 */
/* WDOG4 [9:1] RW value= 0x0 */
/* SPI0 [10:1] RW value= 0x0 */
/* SPI1 [11:1] RW value= 0x0 */
/* I2C0 [12:1] RW value= 0x0 */
/* I2C1 [13:1] RW value= 0x0 */
/* CAN0 [14:1] RW value= 0x0 */
/* CAN1 [15:1] RW value= 0x0 */
/* GEM0 [16:1] RW value= 0x0 */
/* GEM1 [17:1] RW value= 0x0 */
/* TIMER [18:1] RW value= 0x0 */
/* GPIO0 [19:1] RW value= 0x0 */
/* GPIO1 [20:1] RW value= 0x0 */
/* GPIO2 [21:1] RW value= 0x0 */
/* RTC [22:1] RW value= 0x0 */
/* H2FINT [23:1] RW value= 0x0 */
/* CRYPTO [24:1] RW value= 0x0 */
/* USB [25:1] RW value= 0x0 */
/* QSPIXIP [26:1] RW value= 0x0 */
/* ATHENA [27:1] RW value= 0x0 */
/* TRACE [28:1] RW value= 0x0 */
/* MAILBOX_SC [29:1] RW value= 0x0 */
/* EMMC [30:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_CONTEXT_B_EN)
/*AMP context B. When the register bit is '0' the peripheral is not allowed
access from context B. */
#define LIBERO_SETTING_CONTEXT_B_EN 0x00000000UL
/* MMUART0 [0:1] RW value= 0x0 */
/* MMUART1 [1:1] RW value= 0x0 */
/* MMUART2 [2:1] RW value= 0x0 */
/* MMUART3 [3:1] RW value= 0x0 */
/* MMUART4 [4:1] RW value= 0x0 */
/* WDOG0 [5:1] RW value= 0x0 */
/* WDOG1 [6:1] RW value= 0x0 */
/* WDOG2 [7:1] RW value= 0x0 */
/* WDOG3 [8:1] RW value= 0x0 */
/* WDOG4 [9:1] RW value= 0x0 */
/* SPI0 [10:1] RW value= 0x0 */
/* SPI1 [11:1] RW value= 0x0 */
/* I2C0 [12:1] RW value= 0x0 */
/* I2C1 [13:1] RW value= 0x0 */
/* CAN0 [14:1] RW value= 0x0 */
/* CAN1 [15:1] RW value= 0x0 */
/* GEM0 [16:1] RW value= 0x0 */
/* GEM1 [17:1] RW value= 0x0 */
/* TIMER [18:1] RW value= 0x0 */
/* GPIO0 [19:1] RW value= 0x0 */
/* GPIO1 [20:1] RW value= 0x0 */
/* GPIO2 [21:1] RW value= 0x0 */
/* RTC [22:1] RW value= 0x0 */
/* H2FINT [23:1] RW value= 0x0 */
/* CRYPTO [24:1] RW value= 0x0 */
/* USB [25:1] RW value= 0x0 */
/* QSPIXIP [26:1] RW value= 0x0 */
/* ATHENA [27:1] RW value= 0x0 */
/* TRACE [28:1] RW value= 0x0 */
/* MAILBOX_SC [29:1] RW value= 0x0 */
/* EMMC [30:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_CONTEXT_A_HART_EN)
/*When the register bit is '0' hart is not associated with context A. */
#define LIBERO_SETTING_CONTEXT_A_HART_EN 0x00000000UL
/* HART0 [0:1] RW value= 0x0 */
/* HART1 [1:1] RW value= 0x0 */
/* HART2 [2:1] RW value= 0x0 */
/* HART3 [3:1] RW value= 0x0 */
/* HART4 [4:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_CONTEXT_B_HART_EN)
/*When the register bit is '0' hart is not associated with context B. */
#define LIBERO_SETTING_CONTEXT_B_HART_EN 0x00000000UL
/* HART0 [0:1] RW value= 0x0 */
/* HART1 [1:1] RW value= 0x0 */
/* HART2 [2:1] RW value= 0x0 */
/* HART3 [3:1] RW value= 0x0 */
/* HART4 [4:1] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_APB_SPLIT_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_cache.h
+436
View File
@@ -0,0 +1,436 @@
/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_cache.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CACHE_H_
#define HW_CACHE_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_WAY_ENABLE)
/*Way indexes less than or equal to this register value may be used by the
cache. E.g. set to 0x7, will allocate 8 cache ways, 0-7 to cache, and leave
8-15 as LIM. Note 1: Way 0 is always allocated as cache. Note 2: each way is
128KB. */
#define LIBERO_SETTING_WAY_ENABLE 0x0000000BUL
/* WAY_ENABLE [0:8] RW value= 0xB */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_DMA)
/*Way mask register master DMA. Set field to zero to disable way from this
master. The available cache ways are 0 to number set in WAY_ENABLE register. If
using scratch pad memory, the ways you want reserved for scrathpad are not
available for selection, you must set to 0. e.g. If three ways reserved for
scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all
masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_DMA 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_0)
/*Way mask register master DMA. Set field to zero to disable way from this
master. The available cache ways are 0 to number set in WAY_ENABLE register. If
using scratch pad memory, the ways you want reserved for scrathpad are not
available for selection, you must set to 0. e.g. If three ways reserved for
scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all
masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_1)
/*Way mask register master DMA. Set field to zero to disable way from this
master. The available cache ways are 0 to number set in WAY_ENABLE register. If
using scratch pad memory, the ways you want reserved for scrathpad are not
available for selection, you must set to 0. e.g. If three ways reserved for
scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all
masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_2)
/*Way mask registerAXI slave port 2. Set field to zero to disable way from this
master. The available cache ways are 0 to number set in WAY_ENABLE register. If
using scratch pad memory, the ways you want reserved for scrathpad are not
available for selection, you must set to 0. e.g. If three ways reserved for
scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all
masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_3)
/*Way mask register AXI slave port 3. Set field to 1 to disable way from this
master. Set field to zero to disable way from this master. The available cache
ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory,
the ways you want reserved for scrathpad are not available for selection, you
must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0,
WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not
evict the way. */
#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_E51_DCACHE)
/*Way mask register E51 data cache (hart0). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_E51_DCACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_E51_ICACHE)
/*Way mask registerE52 instruction cache (hart0). Set field to zero to disable
way from this master. The available cache ways are 0 to number set in
WAY_ENABLE register. If using scratch pad memory, the ways you want reserved
for scrathpad are not available for selection, you must set to 0. e.g. If three
ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set
to zero for all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_E51_ICACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_DCACHE)
/*Way mask register data cache (hart1). Set field to zero to disable way from
this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_1_DCACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_ICACHE)
/*Way mask register instruction cache (hart1). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_1_ICACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_DCACHE)
/*Way mask register data cache (hart2). Set field to 1 to disable way from this
master. Set field to zero to disable way from this master. The available cache
ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory,
the ways you want reserved for scrathpad are not available for selection, you
must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0,
WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not
evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_2_DCACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_ICACHE)
/*Way mask register instruction cache (hart2). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_2_ICACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_DCACHE)
/*Way mask register data cache (hart3). Set field to 1 to disable way from this
master.Set field to zero to disable way from this master. The available cache
ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory,
the ways you want reserved for scrathpad are not available for selection, you
must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0,
WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not
evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_3_DCACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_ICACHE)
/*Way mask register instruction cache(hart3). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_3_ICACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_DCACHE)
/*Way mask register data cache (hart4). Set field to 1 to disable way from this
master. Set field to zero to disable way from this master. The available cache
ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory,
the ways you want reserved for scrathpad are not available for selection, you
must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0,
WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not
evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_4_DCACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_ICACHE)
/*Way mask register instruction cache (hart4). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_4_ICACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS)
/*Number of ways reserved for scratchpad. Note 1: This is not a register Note
2: each way is 128KB. Note 3: Embedded software expects cache ways allocated
for scratchpad start at way 0, and work up. */
#define LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS 0x00000004UL
/* NUM_OF_WAYS [0:8] RW value= 0x4 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CACHE_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_memory.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_memory.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MEMORY_H_
#define HW_MEMORY_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_RESET_VECTOR_HART0)
/*Reset vector hart0 */
#define LIBERO_SETTING_RESET_VECTOR_HART0 0x20220000
#define LIBERO_SETTING_RESET_VECTOR_HART0_SIZE 0x4 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_RESET_VECTOR_HART1)
/*Reset vector hart1 */
#define LIBERO_SETTING_RESET_VECTOR_HART1 0x20220000
#define LIBERO_SETTING_RESET_VECTOR_HART1_SIZE 0x4 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_RESET_VECTOR_HART2)
/*Reset vector hart2 */
#define LIBERO_SETTING_RESET_VECTOR_HART2 0x20220000
#define LIBERO_SETTING_RESET_VECTOR_HART2_SIZE 0x4 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_RESET_VECTOR_HART3)
/*Reset vector hart3 */
#define LIBERO_SETTING_RESET_VECTOR_HART3 0x20220000
#define LIBERO_SETTING_RESET_VECTOR_HART3_SIZE 0x4 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_RESET_VECTOR_HART4)
/*Reset vector hart4 */
#define LIBERO_SETTING_RESET_VECTOR_HART4 0x20220000
#define LIBERO_SETTING_RESET_VECTOR_HART4_SIZE 0x4 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_DDR_32_CACHE)
/*example instance of memory */
#define LIBERO_SETTING_DDR_32_CACHE 0x80000000
#define LIBERO_SETTING_DDR_32_CACHE_SIZE 0x100000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_DDR_32_NON_CACHE)
/*example instance */
#define LIBERO_SETTING_DDR_32_NON_CACHE 0xC0000000
#define LIBERO_SETTING_DDR_32_NON_CACHE_SIZE 0x100000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_DDR_64_CACHE)
/*64 bit address */
#define LIBERO_SETTING_DDR_64_CACHE 0x1000000000
#define LIBERO_SETTING_DDR_64_CACHE_SIZE 0x100000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_DDR_64_NON_CACHE)
/*64 bit address */
#define LIBERO_SETTING_DDR_64_NON_CACHE 0x1400000000
#define LIBERO_SETTING_DDR_64_NON_CACHE_SIZE 0x100000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_DDR_32_WCB)
/*example instance */
#define LIBERO_SETTING_DDR_32_WCB 0xD0000000
#define LIBERO_SETTING_DDR_32_WCB_SIZE 0x100000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_DDR_64_WCB)
/*64 bit address */
#define LIBERO_SETTING_DDR_64_WCB 0x1800000000
#define LIBERO_SETTING_DDR_64_WCB_SIZE 0x100000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_RESERVED_SNVM)
/*Offset and size of reserved sNVM. (Not available to MSS) */
#define LIBERO_SETTING_RESERVED_SNVM 0x00000000
#define LIBERO_SETTING_RESERVED_SNVM_SIZE 0x00000000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_RESERVED_ENVM)
/*Offset and size of reserved eNVM (Not available to MSS) */
#define LIBERO_SETTING_RESERVED_ENVM 0x00000000
#define LIBERO_SETTING_RESERVED_ENVM_SIZE 0x00000000 /* Length of memory block*/
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MEMORY_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_mpu_crypto.h
+70
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_crypto.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_CRYPTO_H_
#define HW_MPU_CRYPTO_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_CRYPTO_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_mpu_fic0.h
+154
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_fic0.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_FIC0_H_
#define HW_MPU_FIC0_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP4)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP5)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP6)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP7)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP8)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP8 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP9)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP9 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP10)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP10 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP11)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP11 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP12)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP12 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP13)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP13 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP14)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP14 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP15)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP15 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_FIC0_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_mpu_fic1.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_fic1.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_FIC1_H_
#define HW_MPU_FIC1_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP4)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP5)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP6)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP7)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP8)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP8 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP9)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP9 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP10)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP10 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP11)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP11 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP12)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP12 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP13)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP13 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP14)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP14 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP15)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP15 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_FIC1_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_mpu_fic2.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_fic2.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_FIC2_H_
#define HW_MPU_FIC2_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP4)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP5)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP6)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP7)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_FIC2_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_mpu_gem0.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_gem0.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_GEM0_H_
#define HW_MPU_GEM0_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP4)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP5)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP6)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP7)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_GEM0_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_mpu_gem1.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_gem1.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_GEM1_H_
#define HW_MPU_GEM1_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP4)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP5)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP6)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP7)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_GEM1_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_mpu_mmc.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_mmc.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_MMC_H_
#define HW_MPU_MMC_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_MMC_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_MMC_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_MMC_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_MMC_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_MMC_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_mpu_scb.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_scb.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_SCB_H_
#define HW_MPU_SCB_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP4)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP5)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP6)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP7)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_SCB_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_mpu_trace.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_trace.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_TRACE_H_
#define HW_MPU_TRACE_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_TRACE_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_TRACE_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_TRACE_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_TRACE_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_TRACE_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_mpu_usb.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_usb.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_USB_H_
#define HW_MPU_USB_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_USB_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_USB_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_USB_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_USB_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_USB_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_pmp_hart0.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_pmp_hart0.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_PMP_HART0_H_
#define HW_PMP_HART0_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPCFG0)
/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART0_CSR_PMPCFG0 0x0000000000000000ULL
/* PMP0CFG [0:8] RW value= 0x00 */
/* PMP1CFG [8:8] RW value= 0x0 */
/* PMP2CFG [16:8] RW value= 0x00 */
/* PMP3CFG [24:8] RW value= 0x00 */
/* PMP4CFG [32:8] RW value= 0x00 */
/* PMP5CFG [40:8] RW value= 0x00 */
/* PMP6CFG [48:8] RW value= 0x00 */
/* PMP7CFG [56:8] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPCFG2)
/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART0_CSR_PMPCFG2 0x0000000000000000ULL
/* PMP8CFG [0:8] RW value= 0x00 */
/* PMP9CFG [8:8] RW value= 0x00 */
/* PMP10CFG [16:8] RW value= 0x00 */
/* PMP11CFG [24:8] RW value= 0x00 */
/* PMP12CFG [32:8] RW value= 0x00 */
/* PMP13CFG [40:8] RW value= 0x00 */
/* PMP14CFG [48:8] RW value= 0x00 */
/* PMP15CFG [56:8] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR0)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR0 0x0000000000000000ULL
/* CSR_PMPADDR0 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR1)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR1 0x0000000000000000ULL
/* CSR_PMPADDR1 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR2)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR2 0x0000000000000000ULL
/* CSR_PMPADDR2 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR3)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR3 0x0000000000000000ULL
/* CSR_PMPADDR3 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR4)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR4 0x0000000000000000ULL
/* CSR_PMPADDR4 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR5)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR5 0x0000000000000000ULL
/* CSR_PMPADDR5 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR6)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR6 0x0000000000000000ULL
/* CSR_PMPADDR6 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR7)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR7 0x0000000000000000ULL
/* CSR_PMPADDR7 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR8)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR8 0x0000000000000000ULL
/* CSR_PMPADDR8 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR9)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR9 0x0000000000000000ULL
/* CSR_PMPADDR9 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR10)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR10 0x0000000000000000ULL
/* CSR_PMPADDR10 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR11)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR11 0x0000000000000000ULL
/* CSR_PMPADDR11 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR12)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR12 0x0000000000000000ULL
/* CSR_PMPADDR12 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR13)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR13 0x0000000000000000ULL
/* CSR_PMPADDR13 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR14)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR14 0x0000000000000000ULL
/* CSR_PMPADDR14 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR15)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR15 0x0000000000000000ULL
/* CSR_PMPADDR15 [0:64] RW value= 0x00 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_PMP_HART0_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_pmp_hart1.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_pmp_hart1.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_PMP_HART1_H_
#define HW_PMP_HART1_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPCFG0)
/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART1_CSR_PMPCFG0 0x000000000000009FULL
/* PMP0CFG [0:8] RW value= 0x9F */
/* PMP1CFG [8:8] RW value= 0x0 */
/* PMP2CFG [16:8] RW value= 0x0 */
/* PMP3CFG [24:8] RW value= 0x0 */
/* PMP4CFG [32:8] RW value= 0x0 */
/* PMP5CFG [40:8] RW value= 0x0 */
/* PMP6CFG [48:8] RW value= 0x0 */
/* PMP7CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPCFG2)
/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART1_CSR_PMPCFG2 0x0000000000000000ULL
/* PMP8CFG [0:8] RW value= 0x0 */
/* PMP9CFG [8:8] RW value= 0x0 */
/* PMP10CFG [16:8] RW value= 0x0 */
/* PMP11CFG [24:8] RW value= 0x0 */
/* PMP12CFG [32:8] RW value= 0x0 */
/* PMP13CFG [40:8] RW value= 0x0 */
/* PMP14CFG [48:8] RW value= 0x0 */
/* PMP15CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR0)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR0 0xFFFFFFFFFFFFFFFFULL
/* CSR_PMPADDR0 [0:64] RW value= 0xFFFFFFFFFFFFFFFF */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR1)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR1 0x0000000000000000ULL
/* CSR_PMPADDR1 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR2)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR2 0x0000000000000000ULL
/* CSR_PMPADDR2 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR3)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR3 0x0000000000000000ULL
/* CSR_PMPADDR3 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR4)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR4 0x0000000000000000ULL
/* CSR_PMPADDR4 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR5)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR5 0x0000000000000000ULL
/* CSR_PMPADDR5 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR6)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR6 0x0000000000000000ULL
/* CSR_PMPADDR6 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR7)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR7 0x0000000000000000ULL
/* CSR_PMPADDR7 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR8)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR8 0x0000000000000000ULL
/* CSR_PMPADDR8 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR9)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR9 0x0000000000000000ULL
/* CSR_PMPADDR9 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR10)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR10 0x0000000000000000ULL
/* CSR_PMPADDR10 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR11)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR11 0x0000000000000000ULL
/* CSR_PMPADDR11 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR12)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR12 0x0000000000000000ULL
/* CSR_PMPADDR12 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR13)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR13 0x0000000000000000ULL
/* CSR_PMPADDR13 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR14)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR14 0x0000000000000000ULL
/* CSR_PMPADDR14 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR15)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR15 0x0000000000000000ULL
/* CSR_PMPADDR15 [0:64] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_PMP_HART1_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_pmp_hart2.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_pmp_hart2.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_PMP_HART2_H_
#define HW_PMP_HART2_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPCFG0)
/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART2_CSR_PMPCFG0 0x000000000000009FULL
/* PMP0CFG [0:8] RW value= 0x9F */
/* PMP1CFG [8:8] RW value= 0x0 */
/* PMP2CFG [16:8] RW value= 0x0 */
/* PMP3CFG [24:8] RW value= 0x0 */
/* PMP4CFG [32:8] RW value= 0x0 */
/* PMP5CFG [40:8] RW value= 0x0 */
/* PMP6CFG [48:8] RW value= 0x0 */
/* PMP7CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPCFG2)
/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART2_CSR_PMPCFG2 0x0000000000000000ULL
/* PMP8CFG [0:8] RW value= 0x0 */
/* PMP9CFG [8:8] RW value= 0x0 */
/* PMP10CFG [16:8] RW value= 0x0 */
/* PMP11CFG [24:8] RW value= 0x0 */
/* PMP12CFG [32:8] RW value= 0x0 */
/* PMP13CFG [40:8] RW value= 0x0 */
/* PMP14CFG [48:8] RW value= 0x0 */
/* PMP15CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR0)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR0 0xFFFFFFFFFFFFFFFFULL
/* CSR_PMPADDR0 [0:64] RW value= 0xFFFFFFFFFFFFFFFF */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR1)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR1 0x0000000000000000ULL
/* CSR_PMPADDR1 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR2)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR2 0x0000000000000000ULL
/* CSR_PMPADDR2 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR3)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR3 0x0000000000000000ULL
/* CSR_PMPADDR3 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR4)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR4 0x0000000000000000ULL
/* CSR_PMPADDR4 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR5)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR5 0x0000000000000000ULL
/* CSR_PMPADDR5 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR6)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR6 0x0000000000000000ULL
/* CSR_PMPADDR6 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR7)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR7 0x0000000000000000ULL
/* CSR_PMPADDR7 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR8)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR8 0x0000000000000000ULL
/* CSR_PMPADDR8 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR9)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR9 0x0000000000000000ULL
/* CSR_PMPADDR9 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR10)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR10 0x0000000000000000ULL
/* CSR_PMPADDR10 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR11)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR11 0x0000000000000000ULL
/* CSR_PMPADDR11 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR12)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR12 0x0000000000000000ULL
/* CSR_PMPADDR12 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR13)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR13 0x0000000000000000ULL
/* CSR_PMPADDR13 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR14)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR14 0x0000000000000000ULL
/* CSR_PMPADDR14 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR15)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR15 0x0000000000000000ULL
/* CSR_PMPADDR15 [0:64] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_PMP_HART2_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_pmp_hart3.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_pmp_hart3.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_PMP_HART3_H_
#define HW_PMP_HART3_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPCFG0)
/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART3_CSR_PMPCFG0 0x000000000000009FULL
/* PMP0CFG [0:8] RW value= 0x9F */
/* PMP1CFG [8:8] RW value= 0x0 */
/* PMP2CFG [16:8] RW value= 0x0 */
/* PMP3CFG [24:8] RW value= 0x0 */
/* PMP4CFG [32:8] RW value= 0x0 */
/* PMP5CFG [40:8] RW value= 0x0 */
/* PMP6CFG [48:8] RW value= 0x0 */
/* PMP7CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPCFG2)
/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART3_CSR_PMPCFG2 0x0000000000000000ULL
/* PMP8CFG [0:8] RW value= 0x0 */
/* PMP9CFG [8:8] RW value= 0x0 */
/* PMP10CFG [16:8] RW value= 0x0 */
/* PMP11CFG [24:8] RW value= 0x0 */
/* PMP12CFG [32:8] RW value= 0x0 */
/* PMP13CFG [40:8] RW value= 0x0 */
/* PMP14CFG [48:8] RW value= 0x0 */
/* PMP15CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR0)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR0 0xFFFFFFFFFFFFFFFFULL
/* CSR_PMPADDR0 [0:64] RW value= 0xFFFFFFFFFFFFFFFF */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR1)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR1 0x0000000000000000ULL
/* CSR_PMPADDR1 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR2)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR2 0x0000000000000000ULL
/* CSR_PMPADDR2 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR3)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR3 0x0000000000000000ULL
/* CSR_PMPADDR3 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR4)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR4 0x0000000000000000ULL
/* CSR_PMPADDR4 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR5)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR5 0x0000000000000000ULL
/* CSR_PMPADDR5 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR6)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR6 0x0000000000000000ULL
/* CSR_PMPADDR6 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR7)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR7 0x0000000000000000ULL
/* CSR_PMPADDR7 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR8)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR8 0x0000000000000000ULL
/* CSR_PMPADDR8 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR9)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR9 0x0000000000000000ULL
/* CSR_PMPADDR9 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR10)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR10 0x0000000000000000ULL
/* CSR_PMPADDR10 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR11)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR11 0x0000000000000000ULL
/* CSR_PMPADDR11 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR12)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR12 0x0000000000000000ULL
/* CSR_PMPADDR12 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR13)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR13 0x0000000000000000ULL
/* CSR_PMPADDR13 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR14)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR14 0x0000000000000000ULL
/* CSR_PMPADDR14 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR15)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR15 0x0000000000000000ULL
/* CSR_PMPADDR15 [0:64] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_PMP_HART3_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_pmp_hart4.h
+164
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_pmp_hart4.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_PMP_HART4_H_
#define HW_PMP_HART4_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPCFG0)
/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART4_CSR_PMPCFG0 0x000000000000009FULL
/* PMP0CFG [0:8] RW value= 0x9F */
/* PMP1CFG [8:8] RW value= 0x0 */
/* PMP2CFG [16:8] RW value= 0x0 */
/* PMP3CFG [24:8] RW value= 0x0 */
/* PMP4CFG [32:8] RW value= 0x0 */
/* PMP5CFG [40:8] RW value= 0x0 */
/* PMP6CFG [48:8] RW value= 0x0 */
/* PMP7CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPCFG2)
/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART4_CSR_PMPCFG2 0x0000000000000000ULL
/* PMP8CFG [0:8] RW value= 0x0 */
/* PMP9CFG [8:8] RW value= 0x0 */
/* PMP10CFG [16:8] RW value= 0x0 */
/* PMP11CFG [24:8] RW value= 0x0 */
/* PMP12CFG [32:8] RW value= 0x0 */
/* PMP13CFG [40:8] RW value= 0x0 */
/* PMP14CFG [48:8] RW value= 0x0 */
/* PMP15CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR0)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR0 0xFFFFFFFFFFFFFFFFULL
/* CSR_PMPADDR0 [0:64] RW value= 0xFFFFFFFFFFFFFFFF */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR1)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR1 0x0000000000000000ULL
/* CSR_PMPADDR1 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR2)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR2 0x0000000000000000ULL
/* CSR_PMPADDR2 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR3)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR3 0x0000000000000000ULL
/* CSR_PMPADDR3 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR4)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR4 0x0000000000000000ULL
/* CSR_PMPADDR4 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR5)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR5 0x0000000000000000ULL
/* CSR_PMPADDR5 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR6)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR6 0x0000000000000000ULL
/* CSR_PMPADDR6 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR7)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR7 0x0000000000000000ULL
/* CSR_PMPADDR7 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR8)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR8 0x0000000000000000ULL
/* CSR_PMPADDR8 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR9)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR9 0x0000000000000000ULL
/* CSR_PMPADDR9 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR10)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR10 0x0000000000000000ULL
/* CSR_PMPADDR10 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR11)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR11 0x0000000000000000ULL
/* CSR_PMPADDR11 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR12)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR12 0x0000000000000000ULL
/* CSR_PMPADDR12 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR13)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR13 0x0000000000000000ULL
/* CSR_PMPADDR13 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR14)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR14 0x0000000000000000ULL
/* CSR_PMPADDR14 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR15)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR15 0x0000000000000000ULL
/* CSR_PMPADDR15 [0:64] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_PMP_HART4_H_ */
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/sgmii/hw_sgmii_tip.h
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_sgmii_tip.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_SGMII_TIP_H_
#define HW_SGMII_TIP_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_SGMII_MODE)
/*SGMII mode control (SEU) */
#define LIBERO_SETTING_SGMII_MODE 0x08C0E6FFUL
/* REG_PLL_EN [0:1] RW value= 0x1 */
/* REG_DLL_EN [1:1] RW value= 0x1 */
/* REG_PVT_EN [2:1] RW value= 0x1 */
/* REG_BC_VRGEN_EN [3:1] RW value= 0x1 */
/* REG_TX0_EN [4:1] RW value= 0x1 */
/* REG_RX0_EN [5:1] RW value= 0x1 */
/* REG_TX1_EN [6:1] RW value= 0x1 */
/* REG_RX1_EN [7:1] RW value= 0x1 */
/* REG_DLL_LOCK_FLT [8:2] RW value= 0x2 */
/* REG_DLL_ADJ_CODE [10:4] RW value= 0x9 */
/* REG_CH0_CDR_RESET_B [14:1] RW value= 0x1 */
/* REG_CH1_CDR_RESET_B [15:1] RW value= 0x1 */
/* REG_BC_VRGEN [16:6] RW value= 0x00 */
/* REG_CDR_MOVE_STEP [22:1] RW value= 0x1 */
/* REG_REFCLK_EN_RDIFF [23:1] RW value= 0x1 */
/* REG_BC_VS [24:4] RW value= 0x8 */
/* REG_REFCLK_EN_UDRIVE_P [28:1] RW value= 0x0 */
/* REG_REFCLK_EN_INS_HYST_P [29:1] RW value= 0x0 */
/* REG_REFCLK_EN_UDRIVE_N [30:1] RW value= 0x0 */
/* REG_REFCLK_EN_INS_HYST_N [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_PLL_CNTL)
/*PLL control register (SEU) */
#define LIBERO_SETTING_PLL_CNTL 0x80140101UL
/* REG_PLL_POSTDIV [0:7] RW value= 0x1 */
/* ARO_PLL0_LOCK [7:1] RO */
/* REG_PLL_RFDIV [8:6] RW value= 0x1 */
/* REG_PLL_REG_RFCLK_SEL [14:1] RW value= 0x0 */
/* REG_PLL_LP_REQUIRES_LOCK [15:1] RW value= 0x0 */
/* REG_PLL_INTIN [16:12] RW value= 0x14 */
/* REG_PLL_BWI [28:2] RW value= 0x0 */
/* REG_PLL_BWP [30:2] RW value= 0x2 */
#endif
#if !defined (LIBERO_SETTING_CH0_CNTL)
/*Channel0 control register */
#define LIBERO_SETTING_CH0_CNTL 0x37F07770UL
/* REG_TX0_WPU_P [0:1] RW value= 0x0 */
/* REG_TX0_WPD_P [1:1] RW value= 0x0 */
/* REG_TX0_SLEW_P [2:2] RW value= 0x0 */
/* REG_TX0_DRV_P [4:4] RW value= 0x7 */
/* REG_TX0_ODT_P [8:4] RW value= 0x7 */
/* REG_TX0_ODT_STATIC_P [12:3] RW value= 0x7 */
/* REG_RX0_TIM_LONG [15:1] RW value= 0x0 */
/* REG_RX0_WPU_P [16:1] RW value= 0x0 */
/* REG_RX0_WPD_P [17:1] RW value= 0x0 */
/* REG_RX0_IBUFMD_P [18:3] RW value= 0x4 */
/* REG_RX0_EYEWIDTH_P [21:3] RW value= 0x7 */
/* REG_RX0_ODT_P [24:4] RW value= 0x7 */
/* REG_RX0_ODT_STATIC_P [28:3] RW value= 0x3 */
/* REG_RX0_EN_FLAG_N [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_CH1_CNTL)
/*Channel1 control register */
#define LIBERO_SETTING_CH1_CNTL 0x37F07770UL
/* REG_TX1_WPU_P [0:1] RW value= 0x0 */
/* REG_TX1_WPD_P [1:1] RW value= 0x0 */
/* REG_TX1_SLEW_P [2:2] RW value= 0x0 */
/* REG_TX1_DRV_P [4:4] RW value= 0x7 */
/* REG_TX1_ODT_P [8:4] RW value= 0x7 */
/* REG_TX1_ODT_STATIC_P [12:3] RW value= 0x7 */
/* REG_RX1_TIM_LONG [15:1] RW value= 0x0 */
/* REG_RX1_WPU_P [16:1] RW value= 0x0 */
/* REG_RX1_WPD_P [17:1] RW value= 0x0 */
/* REG_RX1_IBUFMD_P [18:3] RW value= 0x4 */
/* REG_RX1_EYEWIDTH_P [21:3] RW value= 0x7 */
/* REG_RX1_ODT_P [24:4] RW value= 0x7 */
/* REG_RX1_ODT_STATIC_P [28:3] RW value= 0x3 */
/* REG_RX1_EN_FLAG_N [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RECAL_CNTL)
/*Recalibration control register */
#define LIBERO_SETTING_RECAL_CNTL 0x000020C8UL
/* REG_RECAL_DIFF_RANGE [0:5] RW value= 0x8 */
/* REG_RECAL_START_EN [5:1] RW value= 0x0 */
/* REG_PVT_CALIB_START [6:1] RW value= 0x1 */
/* REG_PVT_CALIB_LOCK [7:1] RW value= 0x1 */
/* REG_RECAL_UPD [8:1] RW value= 0x0 */
/* BC_VRGEN_DIRECTION [9:1] RW value= 0x0 */
/* BC_VRGEN_LOAD [10:1] RW value= 0x0 */
/* BC_VRGEN_MOVE [11:1] RW value= 0x0 */
/* REG_PVT_REG_CALIB_CLKDIV [12:2] RW value= 0x2 */
/* REG_PVT_REG_CALIB_DIFFR_VSEL [14:2] RW value= 0x0 */
/* SRO_DLL_90_CODE [16:7] RO */
/* SRO_DLL_LOCK [23:1] RO */
/* SRO_DLL_ST_CODE [24:7] RO */
/* SRO_RECAL_START [31:1] RO */
#endif
#if !defined (LIBERO_SETTING_CLK_CNTL)
/*Clock input and routing control registers */
#define LIBERO_SETTING_CLK_CNTL 0xF00050CCUL
/* REG_REFCLK_EN_TERM_P [0:2] RW value= 0x0 */
/* REG_REFCLK_EN_RXMODE_P [2:2] RW value= 0x3 */
/* REG_REFCLK_EN_TERM_N [4:2] RW value= 0x0 */
/* REG_REFCLK_EN_RXMODE_N [6:2] RW value= 0x3 */
/* REG_REFCLK_CLKBUF_EN_PULLUP [8:1] RW value= 0x0 */
/* REG_CLKMUX_FCLK_SEL [9:3] RW value= 0x0 */
/* REG_CLKMUX_PLL0_RFCLK0_SEL [12:2] RW value= 0x1 */
/* REG_CLKMUX_PLL0_RFCLK1_SEL [14:2] RW value= 0x1 */
/* REG_CLKMUX_SPARE0 [16:16] RW value= 0xf000 */
#endif
#if !defined (LIBERO_SETTING_DYN_CNTL)
/*Dynamic control registers */
#define LIBERO_SETTING_DYN_CNTL 0x00000000UL
/* REG_PLL_DYNEN [0:1] RW value= 0x0 */
/* REG_DLL_DYNEN [1:1] RW value= 0x0 */
/* REG_PVT_DYNEN [2:1] RW value= 0x0 */
/* REG_BC_DYNEN [3:1] RW value= 0x0 */
/* REG_CLKMUX_DYNEN [4:1] RW value= 0x0 */
/* REG_LANE0_DYNEN [5:1] RW value= 0x0 */
/* REG_LANE1_DYNEN [6:1] RW value= 0x0 */
/* BC_VRGEN_OOR [7:1] RO */
/* REG_PLL_SOFT_RESET_PERIPH [8:1] RW value= 0x0 */
/* REG_DLL_SOFT_RESET_PERIPH [9:1] RW value= 0x0 */
/* REG_PVT_SOFT_RESET_PERIPH [10:1] RW value= 0x0 */
/* REG_BC_SOFT_RESET_PERIPH [11:1] RW value= 0x0 */
/* REG_CLKMUX_SOFT_RESET_PERIPH [12:1] RW value= 0x0 */
/* REG_LANE0_SOFT_RESET_PERIPH [13:1] RW value= 0x0 */
/* REG_LANE1_SOFT_RESET_PERIPH [14:1] RW value= 0x0 */
/* PVT_CALIB_STATUS [15:1] RO */
/* ARO_PLL0_VCO0PH_SEL [16:3] RO */
/* ARO_PLL0_VCO1PH_SEL [19:3] RO */
/* ARO_PLL0_VCO2PH_SEL [22:3] RO */
/* ARO_PLL0_VCO3PH_SEL [25:3] RO */
/* ARO_REF_DIFFR [28:4] RO */
#endif
#if !defined (LIBERO_SETTING_PVT_STAT)
/*PVT calibrator status registers */
#define LIBERO_SETTING_PVT_STAT 0x00000000UL
/* ARO_REF_PCODE [0:6] RO */
/* ARO_IOEN_BNK [6:1] RO */
/* ARO_IOEN_BNK_B [7:1] RO */
/* ARO_REF_NCODE [8:6] RO */
/* ARO_CALIB_STATUS [14:1] RO */
/* ARO_CALIB_STATUS_B [15:1] RO */
/* ARO_PCODE [16:6] RO */
/* ARO_CALIB_INTRPT [22:1] RO */
/* PVT_CALIB_INTRPT [23:1] RO */
/* ARO_NCODE [24:6] RO */
/* PVT_CALIB_LOCK [30:1] RW value= 0x0 */
/* PVT_CALIB_START [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SPARE_CNTL)
/*Spare control register */
#define LIBERO_SETTING_SPARE_CNTL 0xFF000000UL
/* REG_SPARE [0:32] RW value= 0xFF000000 */
#endif
#if !defined (LIBERO_SETTING_SPARE_STAT)
/*Spare status register */
#define LIBERO_SETTING_SPARE_STAT 0x00000000UL
/* SRO_SPARE [0:32] RO */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_SGMII_TIP_H_ */

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