Frédéric Desbiens fb4a8761fc Fixed Erbium interrupt masking and PLIC update races ...

Polling UART output held machine interrupts off for an entire string, which
could lose ThreadX ticks. PLIC enable-word changes could overwrite an update
made by an interrupt handler.

The UART now polls with interrupts enabled and protects only the final status
check and byte write. PLIC enable and disable changes are protected across
their read-modify-write. The README explains the new simulator tests.

Both simulator tests failed on the original code and passed with these fixes.
The 100-million-cycle demo run reported all eight threads and five thread 0
wakeups. AI disclosure and port consistency checks passed. No silicon run.

Assisted-by: Codex (GPT-6-Sol) <noreply@openai.com>

2026-09-30 10:49:55 -04:00

..

example_build

Fixed Erbium interrupt masking and PLIC update races

2026-09-30 10:49:55 -04:00

inc

Updated ThreadX version constants and port strings to 6.5.2.202603 (#781)

2026-09-28 14:36:10 -04:00

src

Normalized the AI disclosure comment to one fixed line per file (#740)

2026-09-15 17:17:26 -04:00

CMakeLists.txt

riscv64: spec compliance and regression test fix (#698)

2026-09-09 09:26:11 -04:00

readme_threadx.txt

riscv64: spec compliance and regression test fix (#698)

2026-09-09 09:26:11 -04:00