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11 Commits
Author SHA1 Message Date
Frédéric Desbiens 5513b1724a Added port for the OpenHW CORE-V MCU platform (#535) 
Adds a complete ThreadX port for the OpenHW CORE-V MCU SoC, targeting the Digilent Nexys A7 FPGA board with an Ashling Opella-LD debug probe.

 New files
 ---------
 cmake/riscv64-gcc-rv32imc.cmake
   CMake toolchain file for riscv64-unknown-elf-gcc targeting rv32imc_zicsr/ilp32.

 ports/risc-v32/gnu/example_build/core_v_mcu/ -- Full BSP + demo application:

Assembly
     crt0.S                     C runtime startup (BSS clear, GP/SP init, call main)
     vectors.S                  32-entry vectored interrupt table at 0x1c000800
     tx_initialize_low_level.S  mtvec setup (vectored mode), stack/free-mem pointers

BSP drivers (bsp/)
     system_core_v_mcu.c  Top-level init and ISR dispatcher (isr_table[32])
     irq.c                PULP APB interrupt controller (enable/disable/mask)
     timer_irq.c          PULP FC Timer -- 100 Hz tick from 10 MHz SOC clock
     fll.c                Frequency Locked Loop -- 5 MHz to 50 MHz (FPGA)
     uart_driver.c        UDMA UART channel 0 -- polled TX, non-blocking RX (8-bit transfer width)
     gpio.c               PULP apb_gpiov2 driver: set/clear/toggle/direction by pin index;
                          pad-mux via per-pad indexed registers at APB_SOC_CTRL + 0x400 + pad*4;
                          full pinmux API (gpio_setpinmux, gpio_getpinmux, gpio_pin_set_dir,
                          gpio_pin_read_status)
     i2c_master.c         Polled UDMA I2C master
     adt7420.c            ADT7420 temperature sensor driver
     string.c             Freestanding memset/memcpy shim (no newlib)

Headers (include/)
     Peripheral register maps, MMIO inlines, BSP API declarations, tx_user.h

Application
     demo_threadx.c   Two threads: LED[0] blink at 1 Hz (IO pad 11, GPIO pin 4, MUX=2)
                      + UART heartbeat with startup banner
                      ("Eclipse ThreadX for OpenHW CORE-V MCU vX.Y.Z.BBBBB")
     link.ld          Linker script: .vectors@0x1c000800, .text@0x1c000880
     CMakeLists.txt   Build definition (references THREADX_ROOT)
     build.sh         One-shot CMake+Ninja build script

Tooling
     install_deps.sh               Automates toolchain/OpenOCD dependency setup
     deploy.sh                      One-step GDB flashing via Ashling Opella-LD;
                                           gdb-multiarch fallback when riscv64-unknown-elf-gdb is absent;
                                           supports --wsl flag required by usbipd-win v5.x
     openocd-nexys-Ashling-Opella-LD.cfg   OpenOCD config for Opella-LD over JTAG

Tests (tests/)
     test_irq.c / test_timer.c   Host-compiled unit tests (2/2 pass)
     mock/mmio_mock.*             Software MMIO register map for host testing

Documentation
     README.md   Hardware overview, build, flash/debug, BSP API reference

 Architecture notes
 ------------------
 - CV32E40P uses the PULP/PULPissimo interrupt controller (not CLINT); IRQ lines
   are masked via APB registers, not the mie CSR.
 - mtvec must be 256-byte aligned; vectors placed at 0x1c000800 (vectored mode).
 - Timer IRQ = line 10; dispatch via isr_table[mcause & 0x1f].
 - Build: -march=rv32imc_zicsr -mabi=ilp32, -ffreestanding, -nodefaultlibs.
 - Verified: ELF 11 KB text, sections at correct addresses, unit tests pass.

 Third-party attributions
 ------------------------
 BSP files derived from core-v-freertos (Apache-2.0):
   (c) 2019-2020 ETH Zurich and University of Bologna
   (c) 2020 GreenWaves Technologies
   (c) 2011-2014 Wind River Systems, Inc.
   (c) 2017 SiFive Inc. (crt0.S, BSD-2-Clause portions)
 All original copyright notices retained; see individual file headers.
 SPDX: Apache-2.0 AND MIT (crt0.S: (Apache-2.0 OR BSD-2-Clause) AND MIT).

 Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
 2026-05-25 11:28:55 -04:00
Ian Thompson 9ccdd5d822 Updated Xtensa support (#525) 
* Add LX8 support for > 32 interrupts

Also fix inconsistent SWPRI define in interrupt handler

* ThreadX: Fix context switch logic

- Disable interrupts prior to allocating a large exception frame;
  only reenable them after deallocating the extra memory.
- Any user tasks with stacks based on TX_MINIMUM_STACK do not
  have sufficient space for both a context switch frame and an ISR
  frame; ill-timed interrupts were causing stack overruns.

* ThreadX: Interrupt fixes for TX_ENABLE_EXECUTION_CHANGE_NOTIFY

- Must reload register trashed by notify hook function call
- Must ensure PS.WOE is set before using call8
- Remove unused XT_USE_INT_WRAPPER define and associated changes,
  which had a bug in XEA2 usage
- Fix another case where enabling the thread notify hooks for
  call0 ABI corrupted a register

* ThreadX: Support for __DYNAMIC_REENT__

- ThreadX change to handle dynamic reent for both newlib and xclib
- Adapt ThreadX xclib interface code to handle dynamic reent pointers

* ThreadX: Xtensa execution profiling support

- Update upstream execution profiling for Xtensa port

* ThreadX: Update xtensa port readme

* ThreadX: Add Xtensa example to EPK

- tx_execution_profile.h now defines an Xtensa example
  in addition to the existing Cortex example

* ThreadX: Add xtensa.cmake

* ThreadX: Update XSHAL_CLIB ifdefs in __getreent()

- Prevent a fall-through with no return value when neither
  xclib nor newlib are used.
 2026-05-19 11:11:37 -04:00
Francisco Manuel Merino Torres 42adda4457 Added a riscv32 for the OpenHW CVA6 (#511) 2026-05-13 07:46:54 -04:00
Frédéric Desbiens 98e4754381 build: add conditional CMake support for ThreadX SMP 
- Introduce THREADX_SMP option in root CMakeLists.txt.
- Implement conditional source and port directory selection for SMP builds.
- Add CMake support for common_smp and Cortex-A9 SMP port.
- Fix linker flags in Cortex-A9 SMP sample build script.
- Remove duplicate invalidateCaches_IS declarations in v7.h headers.

Assisted-by: Gemini (Experimental)
 2026-04-15 10:52:14 -04:00
Francisco Manuel Merino Torres 888f7a42b0 Added a RISC-V32 architecture port layer for Clang. 2026-02-26 10:49:23 +01:00
Akif Ejaz 757db54d6d Add RISC-V32 arch. port layer 
This update adapts the ThreadX low-level kernel routines
for RV32, including:
  - startup and initialization logic
  - context save/restore implementations
  - interrupt control and scheduler entry
  - thread stack build and system return paths
  - timer interrupt handling
  - made it complient as per new risc-v64/gnu
      & threadx style
  - added reademe for risc-v32/gnu port

These changes provide full low-level support needed to run
ThreadX on RISC-V32 targets.

Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
 2026-02-16 17:15:13 +05:00
Jer6y d24da0e2ea riscv : add riscv qemu virt support and fix fs bit error in mstatus 2024-10-25 20:03:11 +08:00
Yuxin Zhou d0dab58250 Release 6.1.8 2021-07-28 07:24:02 +00:00
Scott Larson 1b5816a206 6.1 minor release 2020-09-30 15:42:41 -07:00
PProvost f8e91d4762 Updated cmake system processor 2020-05-29 14:37:35 -06:00
PProvost 40081863d5 Updated readme, etc. 2020-05-13 11:47:56 -06:00