Replaced the stale system stack switch pseudo-code in the ARMv7-A ports with comments that describe what the code actually does (#735)

The context save, vectored context save and system return routines in the
ARMv7-A ports carried pseudo-code comments claiming that they saved the
thread stack pointer and then switched to _tx_thread_system_stack_ptr.
Neither of those things happens, and none of these ports references that
variable outside an unused IMPORT in their example builds.

On ARMv7-A each processor mode has its own banked stack pointer. The IRQ
handler branches to _tx_thread_context_save while still in IRQ mode, so the
core's banked IRQ stack already serves as the system stack, and the thread
stack pointer is stored in the control block by _tx_thread_context_restore,
and only when the interrupt results in preemption. The scheduler runs on the
banked SVC mode stack that the startup code sets up. There is nothing for a
software stack switch to do.

The comments were therefore misleading rather than merely redundant, and had
led at least one user to try to restore the code they described. They are now
replaced by a description of the actual mechanism.

The AArch64 SMP ports keep their comments unchanged, because ARMv8-A does not
bank a stack pointer per processor mode and those ports do reload
_tx_thread_system_stack_ptr[core] explicitly.

This is a comment-only change. Every changed line is a comment, and all
twenty-five GNU variants still assemble cleanly for their target core.

The fourteen files under ports/cortex_a{5,7,8,9,12,15,17} were regenerated
from ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S with
ports_arch/ARMv7-A/update.sh. The ARMv7-A SMP ports have no generator, so
those files were edited directly.

Fixes #734

Assisted-by: Copilot (Opus 5) <noreply@github.com>

ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.S

@@ -9,6 +9,7 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Copilot (Opus 5).
 
 /**************************************************************************/
 /**************************************************************************/
@@ -117,7 +118,9 @@ _tx_skip_solicited_vfp_save:
     LDR     r2, =_tx_timer_time_slice   // Pickup address of time slice
     LDR     r1, [r2]                    // Pickup current time slice
 
-    /* Save current stack and switch to system stack.  */
+    /* Save the current stack pointer in the thread control block. The
+           scheduler runs on the banked SVC mode stack that the startup code
+           set up, so there is no stack switch to perform.  */
 
     STR     sp, [r0, #8]                // Save thread stack pointer
 

ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s

@@ -1,5 +1,6 @@
 ;/***************************************************************************
 ; * Copyright (c) 2024 Microsoft Corporation
+; * Copyright (c) 2026-present Eclipse ThreadX contributors
 ; *
 ; * This program and the accompanying materials are made available under the
 ; * terms of the MIT License which is available at
@@ -8,6 +9,7 @@
 ; * SPDX-License-Identifier: MIT
 ; **************************************************************************/
 ;
+; // Some portions generated by Copilot (Opus 5).
 ;
 ;/**************************************************************************/
 ;/**************************************************************************/
@@ -113,7 +115,9 @@ _tx_skip_solicited_vfp_save:
     LDR     r2, =_tx_timer_time_slice   ; Pickup address of time slice
     LDR     r1, [r2]                    ; Pickup current time slice
 
-;   /* Save current stack and switch to system stack.  */
+;   /* Save the current stack pointer in the thread control block. The
+;          scheduler runs on the banked SVC mode stack that the startup code
+;          set up, so there is no stack switch to perform.  */
 
     STR     sp, [r0, #8]                ; Save thread stack pointer