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Release 6.1.11

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This commit is contained in:
Yuxin Zhou
2022-04-20 05:07:02 +00:00
parent f851772ce0
commit cef9cb22a5
784 changed files with 57616 additions and 101103 deletions
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ports_smp/cortex_a34_smp/ac6/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_unprotect.S
+7 -9
View File
@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect Cortex-A35-SMP/AC6 */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a34_smp/gnu/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_unprotect.S
+7 -9
View File
@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect Cortex-A35-SMP/AC6 */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a35_smp/ac6/example_build/tx/.cproject
+1 -1
View File
@@ -131,7 +131,7 @@
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428">
<inputType id="com.arm.tool.c.compiler.v6.base.input.1275109624" superClass="com.arm.tool.c.compiler.v6.base.input"/>
<inputType id="com.arm.tool.c.compiler.v6.base.input.1275455284" superClass="com.arm.tool.c.compiler.v6.base.input"/>
</tool>
ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/.cproject
+3 -3
View File
@@ -23,7 +23,7 @@
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;com.arm.eclipse.builder.armcc.error;org.eclipse.cdt.core.CWDLocator" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;com.arm.eclipse.builder.armcc.error;org.eclipse.cdt.core.CWDLocator" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
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@@ -47,7 +47,7 @@
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@@ -63,7 +63,7 @@
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ports_smp/cortex_a53_smp/ac6/example_build/tx/.cproject
+2 -6
View File
@@ -49,7 +49,7 @@
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
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@@ -129,11 +129,7 @@
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ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a53_smp/gnu/example_build/tx/.cproject
+6
View File
@@ -129,6 +129,12 @@
</folderInfo>
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ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/.cproject
+3 -3
View File
@@ -23,7 +23,7 @@
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@@ -47,7 +47,7 @@
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@@ -63,7 +63,7 @@
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ports_smp/cortex_a55_smp/ac6/example_build/tx/.cproject
+2 -6
View File
@@ -49,7 +49,7 @@
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@@ -129,11 +129,7 @@
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ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a55_smp/gnu/example_build/tx/.cproject
+6
View File
@@ -129,6 +129,12 @@
</folderInfo>
<fileInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674.1482422597" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610">
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701"/>
</fileInfo>
<sourceEntries>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/.cproject
+3 -3
View File
@@ -23,7 +23,7 @@
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;com.arm.eclipse.builder.armcc.error;org.eclipse.cdt.core.CWDLocator" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;com.arm.eclipse.builder.armcc.error;org.eclipse.cdt.core.CWDLocator" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142." name="/" resourcePath="">
@@ -47,7 +47,7 @@
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1747478037" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1133188329" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a57" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1133188329" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
<inputType id="com.arm.tool.c.compiler.v6.base.input.2103612806" superClass="com.arm.tool.c.compiler.v6.base.input"/>
@@ -63,7 +63,7 @@
<option id="com.arm.tool.assembler.v6.base.options.debug.level.2040227767" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
<option id="com.arm.tool.assembler.v6.base.option.cpu.143750331" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a57" valueType="string"/>
<option id="com.arm.tool.assembler.v6.base.option.cpu.143750331" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
<inputType id="com.arm.tool.assembler.v6.base.input.1316842528" superClass="com.arm.tool.assembler.v6.base.input"/>
ports_smp/cortex_a57_smp/ac6/example_build/tx/.cproject
+2 -6
View File
@@ -49,7 +49,7 @@
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1024278185" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a57" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1024278185" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.options.preproc.enableToolSpecificSettings.830475099" name="Enable tool specific settings" superClass="com.arm.tool.c.compiler.v6.base.options.preproc.enableToolSpecificSettings" useByScannerDiscovery="false" value="true" valueType="boolean"/>
@@ -129,11 +129,7 @@
<fileInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944.1145515026" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128">
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428">
<inputType id="com.arm.tool.c.compiler.v6.base.input.153404379" superClass="com.arm.tool.c.compiler.v6.base.input"/>
</tool>
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428"/>
</fileInfo>
ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a57_smp/gnu/example_build/tx/.cproject
+6
View File
@@ -129,6 +129,12 @@
</folderInfo>
<fileInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674.1482422597" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610">
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701"/>
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<sourceEntries>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_restore.S
+9 -77
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-A5x-SMP/AC6 */
/* 6.1.9 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -79,7 +79,7 @@ _tx_thread_context_restore:
MSR DAIFSet, 0x3 // Lockout interrupts
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR exit function to indicate an ISR is complete. */
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protect.S
+36 -277
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_unprotect.S
+8 -10
View File
@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect Cortex-A5x-SMP/AC6 */
/* 6.1.9 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_restore.S
+9 -77
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-A5x-SMP/GCC */
/* 6.1.9 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -79,7 +79,7 @@ _tx_thread_context_restore:
MSR DAIFSet, 0x3 // Lockout interrupts
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR exit function to indicate an ISR is complete. */
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protect.S
+36 -277
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_unprotect.S
+7 -9
View File
@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect Cortex-A5x-SMP/GCC */
/* 6.1.9 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -60,9 +60,12 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -104,11 +107,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a5x_smp/iar/src/tx_thread_context_restore.S
+27 -107
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_protect.S
+31 -274
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_unprotect.S
+4 -19
View File
@@ -21,19 +21,6 @@
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_smp_protection
EXTERN _tx_thread_preempt_disable
@@ -46,7 +33,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect Cortex-A5x-SMP/IAR */
/* 6.1.9 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -79,6 +66,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
PUBLIC _tx_thread_smp_unprotect
@@ -119,11 +109,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
B.NE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
B.NE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a65_smp/ac6/example_build/tx/.cproject
+1 -5
View File
@@ -129,11 +129,7 @@
<fileInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944.1145515026" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128">
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428">
<inputType id="com.arm.tool.c.compiler.v6.base.input.1006193665" superClass="com.arm.tool.c.compiler.v6.base.input"/>
</tool>
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428"/>
</fileInfo>
ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a65_smp/gnu/example_build/tx/.cproject
+6
View File
@@ -129,6 +129,12 @@
</folderInfo>
<fileInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674.1482422597" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610">
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701"/>
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<sourceEntries>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a65ae_smp/ac6/example_build/tx/.cproject
+1 -5
View File
@@ -129,11 +129,7 @@
<fileInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944.1145515026" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128">
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428">
<inputType id="com.arm.tool.c.compiler.v6.base.input.1782798207" superClass="com.arm.tool.c.compiler.v6.base.input"/>
</tool>
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428"/>
</fileInfo>
ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a65ae_smp/gnu/example_build/tx/.cproject
+6
View File
@@ -129,6 +129,12 @@
</folderInfo>
<fileInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674.1482422597" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610">
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701"/>
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<sourceEntries>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/.cproject
+3 -3
View File
@@ -23,7 +23,7 @@
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;com.arm.eclipse.builder.armcc.error;org.eclipse.cdt.core.CWDLocator" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;com.arm.eclipse.builder.armcc.error;org.eclipse.cdt.core.CWDLocator" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142." name="/" resourcePath="">
@@ -47,7 +47,7 @@
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1747478037" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1133188329" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a72" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1133188329" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
<inputType id="com.arm.tool.c.compiler.v6.base.input.2103612806" superClass="com.arm.tool.c.compiler.v6.base.input"/>
@@ -63,7 +63,7 @@
<option id="com.arm.tool.assembler.v6.base.options.debug.level.2040227767" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
<option id="com.arm.tool.assembler.v6.base.option.cpu.143750331" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a72" valueType="string"/>
<option id="com.arm.tool.assembler.v6.base.option.cpu.143750331" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
<inputType id="com.arm.tool.assembler.v6.base.input.1316842528" superClass="com.arm.tool.assembler.v6.base.input"/>
ports_smp/cortex_a72_smp/ac6/example_build/tx/.cproject
+2 -6
View File
@@ -49,7 +49,7 @@
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1024278185" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a72" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1024278185" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
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@@ -129,11 +129,7 @@
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<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428">
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</fileInfo>
ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a72_smp/gnu/example_build/tx/.cproject
+6
View File
@@ -129,6 +129,12 @@
</folderInfo>
<fileInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674.1482422597" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610">
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</fileInfo>
<sourceEntries>
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ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/.cproject
+3 -3
View File
@@ -23,7 +23,7 @@
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;com.arm.eclipse.builder.armcc.error;org.eclipse.cdt.core.CWDLocator" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;com.arm.eclipse.builder.armcc.error;org.eclipse.cdt.core.CWDLocator" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142." name="/" resourcePath="">
@@ -47,7 +47,7 @@
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1747478037" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1133188329" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a73" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1133188329" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
<inputType id="com.arm.tool.c.compiler.v6.base.input.2103612806" superClass="com.arm.tool.c.compiler.v6.base.input"/>
@@ -63,7 +63,7 @@
<option id="com.arm.tool.assembler.v6.base.options.debug.level.2040227767" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
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<option id="com.arm.tool.assembler.v6.base.option.cpu.143750331" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
<inputType id="com.arm.tool.assembler.v6.base.input.1316842528" superClass="com.arm.tool.assembler.v6.base.input"/>
ports_smp/cortex_a73_smp/ac6/example_build/tx/.cproject
+2 -6
View File
@@ -49,7 +49,7 @@
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1024278185" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a73" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1024278185" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
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@@ -129,11 +129,7 @@
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</fileInfo>
ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a73_smp/gnu/example_build/tx/.cproject
+6
View File
@@ -129,6 +129,12 @@
</folderInfo>
<fileInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674.1482422597" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610">
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701"/>
</fileInfo>
<sourceEntries>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/.cproject
+3 -3
View File
@@ -23,7 +23,7 @@
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;com.arm.eclipse.builder.armcc.error;org.eclipse.cdt.core.CWDLocator" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;com.arm.eclipse.builder.armcc.error;org.eclipse.cdt.core.CWDLocator" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142." name="/" resourcePath="">
@@ -47,7 +47,7 @@
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1747478037" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1133188329" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a75" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1133188329" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
<inputType id="com.arm.tool.c.compiler.v6.base.input.2103612806" superClass="com.arm.tool.c.compiler.v6.base.input"/>
@@ -63,7 +63,7 @@
<option id="com.arm.tool.assembler.v6.base.options.debug.level.2040227767" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
<option id="com.arm.tool.assembler.v6.base.option.cpu.143750331" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a75" valueType="string"/>
<option id="com.arm.tool.assembler.v6.base.option.cpu.143750331" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
<inputType id="com.arm.tool.assembler.v6.base.input.1316842528" superClass="com.arm.tool.assembler.v6.base.input"/>
ports_smp/cortex_a75_smp/ac6/example_build/tx/.cproject
+2 -6
View File
@@ -49,7 +49,7 @@
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1024278185" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a75" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1024278185" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.options.preproc.enableToolSpecificSettings.830475099" name="Enable tool specific settings" superClass="com.arm.tool.c.compiler.v6.base.options.preproc.enableToolSpecificSettings" useByScannerDiscovery="false" value="true" valueType="boolean"/>
@@ -129,11 +129,7 @@
<fileInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944.1145515026" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128">
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428">
<inputType id="com.arm.tool.c.compiler.v6.base.input.1189619687" superClass="com.arm.tool.c.compiler.v6.base.input"/>
</tool>
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428"/>
</fileInfo>
ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a75_smp/gnu/example_build/tx/.cproject
+6
View File
@@ -129,6 +129,12 @@
</folderInfo>
<fileInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674.1482422597" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610">
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701"/>
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<sourceEntries>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/.cproject
+3 -3
View File
@@ -23,7 +23,7 @@
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;com.arm.eclipse.builder.armcc.error;org.eclipse.cdt.core.CWDLocator" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;com.arm.eclipse.builder.armcc.error;org.eclipse.cdt.core.CWDLocator" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142." name="/" resourcePath="">
@@ -47,7 +47,7 @@
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1747478037" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1133188329" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a76" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1133188329" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
<inputType id="com.arm.tool.c.compiler.v6.base.input.2103612806" superClass="com.arm.tool.c.compiler.v6.base.input"/>
@@ -63,7 +63,7 @@
<option id="com.arm.tool.assembler.v6.base.options.debug.level.2040227767" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
<option id="com.arm.tool.assembler.v6.base.option.cpu.143750331" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a76" valueType="string"/>
<option id="com.arm.tool.assembler.v6.base.option.cpu.143750331" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
<inputType id="com.arm.tool.assembler.v6.base.input.1316842528" superClass="com.arm.tool.assembler.v6.base.input"/>
ports_smp/cortex_a76_smp/ac6/example_build/tx/.cproject
+2 -6
View File
@@ -49,7 +49,7 @@
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1024278185" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a76" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1024278185" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
<option id="com.arm.tool.c.compiler.v6.base.options.preproc.enableToolSpecificSettings.830475099" name="Enable tool specific settings" superClass="com.arm.tool.c.compiler.v6.base.options.preproc.enableToolSpecificSettings" useByScannerDiscovery="false" value="true" valueType="boolean"/>
@@ -129,11 +129,7 @@
<fileInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944.1145515026" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128">
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428">
<inputType id="com.arm.tool.c.compiler.v6.base.input.1616307318" superClass="com.arm.tool.c.compiler.v6.base.input"/>
</tool>
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428"/>
</fileInfo>
ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff
ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_unprotect.S
+6 -8
View File
@@ -60,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -105,11 +108,6 @@ _tx_thread_smp_unprotect:
CMP w3, #0 // Is the preempt disable flag set?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
LDR w3, [x2, x1, LSL #2] // Pickup wait list value
CMP w3, #0 // Are any entities on this core waiting?
BNE _still_protected // Yes, skip the protection release
LDR x2,=_tx_thread_smp_protection // Build address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
ports_smp/cortex_a76_smp/gnu/example_build/tx/.cproject
+6
View File
@@ -129,6 +129,12 @@
</folderInfo>
<fileInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674.1482422597" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610">
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701.1451532610" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701"/>
</fileInfo>
<sourceEntries>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_restore.S
+7 -75
View File
@@ -21,9 +21,6 @@
/**************************************************************************/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
@@ -31,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* 6.1.11 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,10 +60,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.10 */
/* 04-25-2022 William E. Lamie Modified comments, removed */
/* FIFO queueing, */
/* resulting in version 6.1.11 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -216,74 +216,6 @@ __tx_thread_no_preempt_restore:
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
CMP w3, #0
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
CMP w8, w3 // Compare our core to the owning core
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
SUB w3, w3, #1 // Decrement waiting value. Should be zero now
STR w3, [x2, x8, LSL #2] // Store new waiting value
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
STR w3, [x2, #4] // Mark the protected core as invalid
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
DSB ISH // To ensure update of the protection occurs before other CPUs awake
/* Wake up waiting processors. Note interrupts are already enabled. */
#ifdef TX_ENABLE_WFE
SEV // Send event to other CPUs
#endif
// }
// }
_nobody_waiting_for_lock:
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_protect.S
+35 -276
View File
File diff suppressed because it is too large Load Diff

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