/***************************************************************************
 * Copyright (C) 2026 Eclipse ThreadX contributors
 *
 * This program and the accompanying materials are made available under the
 * terms of the MIT License which is available at
 * https://opensource.org/licenses/MIT.
 *
 * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6).
 * The AI-generated portions may be considered public domain (CC0-1.0)
 * and not subject to the project's licence. The human contributor has
 * reviewed and verified that the code is correct.
 *
 * SPDX-License-Identifier: MIT and CC0-1.0
 **************************************************************************/

#ifndef I2C_MASTER_H
#define I2C_MASTER_H

#include <stdint.h>

/* i2c_master_init: enable I2C channel clock gate, configure clock divider.
 *   id: 0 or 1 (I2CM0 or I2CM1)
 *   i2c_freq: desired I2C clock in Hz (e.g. 200000)
 *   periph_freq: UDMA peripheral clock in Hz (5000000 on CORE-V FPGA)
 *   Returns 0 on success, -1 on bad params. */
int i2c_master_init(uint8_t id, uint32_t i2c_freq, uint32_t periph_freq);

/* i2c_master_read_reg: read len bytes from register reg_addr of 7-bit addressed device.
 *   id: I2CM channel (0 or 1)
 *   dev_addr7: 7-bit I2C device address
 *   reg_addr: register address to read from
 *   buf: output buffer (must be in RAM, not stack if possible)
 *   len: number of bytes to read (1..255)
 *   Returns 0 on success, -1 on timeout or arbitration loss. */
int i2c_master_read_reg(uint8_t id, uint8_t dev_addr7, uint8_t reg_addr,
                        uint8_t *buf, uint8_t len);

#endif /* I2C_MASTER_H */
