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同步 nano-3.1.3-zip 的内容
This commit is contained in:
yangjie
@@ -1,84 +1,62 @@
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# RT-Thread #
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# RT-Thread Nano 简介
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[中文页](README_zh.md) |
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RT-Thread Nano 是一个极简版的硬实时内核，它是由 C 语言开发，采用面向对象的编程思维，具有良好的代码风格，是一款可裁剪的、抢占式实时多任务的 RTOS。其内存资源占用极小，功能包括任务处理、软件定时器、信号量、邮箱和实时调度等相对完整的实时操作系统特性。适用于家电、消费电子、医疗设备、工控等领域大量使用的 32 位 ARM 入门级 MCU 的场合。
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[](https://github.com/RT-Thread/rt-thread/blob/master/LICENSE)
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[](https://github.com/RT-Thread/rt-thread/releases)
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[](https://travis-ci.org/RT-Thread/rt-thread)
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[](https://gitter.im/RT-Thread/rt-thread?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
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[](https://github.com/RT-Thread/rt-thread/pulls)
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[](https://github.com/RT-Thread/rt-thread/pulls)
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下图是 RT-Thread Nano 的软件框图，包含支持的 CPU 架构与内核源码，还有可拆卸的 FinSH 组件：
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RT-Thread is an open source IoT operating system from China, which has strong scalability: from a tiny kernel running on a tiny core, for example ARM Cortex-M0, or Cortex-M3/4/7, to a rich feature system running on MIPS32, ARM Cortex-A8, ARM Cortex-A9 DualCore etc.
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## Overview ##
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**支持架构**：ARM：Cortex M0/ M3/ M4/ M7 等、RISC-V 及其他。
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RT-Thread RTOS like a traditional real-time operating system. The kernel has real-time multi-task scheduling, semaphore, mutex, mail box, message queue, signal etc. However, it has three different things:
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**功能**：线程管理、线程间同步与通信、时钟管理、中断管理、内存管理。
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* Device Driver;
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* Component;
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* Dynamic Module
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## Nano 的特点
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The device driver is more like a driver framework, UART, IIC, SPI, SDIO, USB device/host, EMAC, MTD NAND etc. The developer can easily add low level driver and board configuration, then combined with the upper framework, he/she can use lots of features.
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### 简单
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The Component is a software concept upon RT-Thread kernel, for example a shell (finsh/msh shell), virtual file system (FAT, YAFFS, UFFS, ROM/RAM file system etc), TCP/IP protocol stack (lwIP), POSIX (thread) interface etc. One component must be a directory under RT-Thread/Components and one component can be descripted by a SConscript file (then be compiled and linked into the system).
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**1、下载简单**
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The Dynamic Module, formerly named as User Applicaion (UA) is a dynamic loaded module or library, it can be compiled standalone without Kernel. Each Dynamic Module has its own object list to manage thread/semaphore/kernel object which was created or initialized inside this UA. More information about UA, please visit another [git repo](https://github.com/RT-Thread/rtthread-apps).
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RT-Thread Nano 以软件包的方式集成在 Keil MDK 与 CubeMX 中，可以直接在软件中下载 Nano 软件包获取源码，获取方式详见 [使用 KEIL MDK 移植 RT-Thread Nano](nano-port-keil/nano-port-keil.md) 与 [使用 CubeMX 移植 RT-Thread Nano](nano-port-cube/nano-port-cube.md) 。
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## Board Support Package ##
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同时也提供 [下载 Nano 源码压缩包]() 的途径，方便在其他开发环境移植 RT-Thread Nano，如 [使用 IAR 移植 RT-Thread Nano](nano-port-iar/nano-port-iar.md)。
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RT-Thread RTOS can support many architectures:
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**2、代码简单**
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* ARM Cortex-M0
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* ARM Cortex-M3/M4/7
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* ARM Cortex-R4
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* ARM Cortex-A8/A9
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* ARM920T/ARM926 etc
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* MIPS32
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* x86
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* Andes
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* C-Sky
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* RISC-V
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* PowerPC
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与 RT-Thread 完整版不同的是，Nano 不含 Scons 构建系统，不需要 Kconfig 以及 Env 配置工具，也去除了完整版特有的 device 框架和组件，仅是一个纯净的内核。
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## License ##
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**3、移植简单**
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RT-Thread is Open Source software under the Apache License 2.0 since RT-Thread v3.1.1. License and copyright information can be found within the code.
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由于 Nano 的极简特性，使 Nano 的移植过程变得极为简单。添加 Nano 源码到工程，就已完成 90% 的移植工作。并且在 Keil MDK 与 Cube MX 中还提供了 Nano 的软件包，可以一键下载加入到工程。以下是使用不同开发环境时，可以选择移植 Nano 的方法：
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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- [使用 KEIL MDK 移植 RT-Thread Nano](nano-port-keil/nano-port-keil.md)
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- [使用 CubeMX 移植 RT-Thread Nano](nano-port-cube/nano-port-cube.md)
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- [使用 IAR 移植 RT-Thread Nano](nano-port-iar/nano-port-iar.md)
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- [移植 RT-Thread Nano 到 RISC-V](nano-port-gcc-riscv/nano-port-gcc-riscv.md)
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Since 9th of September 2018, PRs submitted by the community may be merged into the main line only after signing the Contributor License Agreement(CLA).
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**4、使用简单**
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## Usage ##
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RT-Thread Nano 在使用上也非常简单，带给开发者友好的开发体验。
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RT-Thread RTOS uses [scons](http://www.scons.org) as building system. Therefore, please install scons and Python 2.7 firstly.
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So far, the RT-Thread scons building system support the command line compile or generate some IDE's project. There are some option varaibles in the scons building script (rtconfig.py):
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- 易裁剪：Nano 的配置文件为 rtconfig.h，该文件中列出了内核中的所有宏定义，有些默认没有打开，如需使用，打开即可。具体的配置可见 Nano 版块的 [RT-Thread Nano 配置](nano-config/nano-config.md) 教程。
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- 易添加 FinSH 组件：[FinSH 组件](../../programming-manual/finsh/finsh.md) 可以很方便的在 Nano 上进行移植，而不再依赖 device 框架，只需要对接两个必要的函数即可完成 [FinSH 移植](finsh-port/finsh-port.md)。
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- 自选驱动库：可以使用厂商提供的固件驱动库，如 ST 的 STD 库、HAL 库、LL 库等，可以自行选择。
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- 完善的文档：包含 [内核基础](../../programming-manual/basic/basic.md)、[线程管理 (例程)](../../programming-manual/thread/thread.md)、[时钟管理 (例程)](../../programming-manual/timer/timer.md)、[线程间同步 (例程)](../../programming-manual/ipc1/ipc1.md)、[线程间通信 (例程)](../../programming-manual/ipc2/ipc2.md)、[内存管理 (例程)](../../programming-manual/memory/memory.md)、[中断管理](../../programming-manual/interrupt/interrupt.md) ，以及 Nano 版块的移植教程。
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* ```CROSS_TOOL``` the compiler which you want to use, gcc/keil/iar.
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* ```EXEC_PATH``` the path of compiler.
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### 小巧
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In SConstruct file:
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**资源占用小**：对 RAM 与 ROM 的开销非常小，在支持 semaphore 和 mailbox 特性，并运行两个线程 (main 线程 + idle 线程) 情况下，ROM 和 RAM 依然保持着极小的尺寸，RAM 占用约 1K 左右，ROM 占用 4K 左右。
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```RTT_ROOT``` This variable is the root directory of RT-Thread RTOS. If you build the porting in the bsp directory, you can use the default setting. Also, you can set the root directory in ```RTT_ROOT``` environment variable and not modify SConstruct files.
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Nano 资源占用情况举例：在运行两个线程 (main 线程 + idle 线程) 情况下，ROM 和 RAM 依然保持着极小的尺寸。以下是基于 Cortex M3 的 MDK 工程编译结果（优化等级 3）。
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When you set these variables correctly, you can use command:
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```
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Total RO Size (Code + RO Data) 4000 ( 3.91kB)
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Total RW Size (RW Data + ZI Data) 1168 ( 1.14kB)
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Total ROM Size (Code + RO Data + RW Data) 4092 ( 4.00kB)
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```
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scons
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> 注：如果需要丰富的组件、驱动以及软件包等功能，则建议使用 [RT-Thread 完整版](../../index.md)。
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under BSP directory to simplely compile RT-Thread RTOS.
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### 开源免费（Apache 2.0）
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If you want to generate the IDE's project file, you can use command:
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RT-Thread Nano 实时操作系统遵循 Apache 许可证 2.0 版本，实时操作系统内核及所有开源组件可以免费在商业产品中使用，不需要公布应用程序源码，没有潜在商业风险。
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scons --target=mdk/mdk4/mdk5/iar/cb -s
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to generate the project file.
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NOTE: RT-Thread scons building system will tailor the system according to your rtconfig.h configuration header file. For example, if you disable the lwIP in the rtconfig.h by commenting the ```#define RT_USING_LWIP```, the generated project file should have no lwIP related files.
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## Contribution ##
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Please refer the contributors in the github. Thank all of RT-Thread Developers.
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91
rt-thread/bsp/board.c
Normal file
91
rt-thread/bsp/board.c
Normal file
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-07-24 Tanek the first version
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* 2018-11-12 Ernest Chen modify copyright
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*/
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#include <stdint.h>
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#include <rthw.h>
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#include <rtthread.h>
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#define _SCB_BASE (0xE000E010UL)
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#define _SYSTICK_CTRL (*(rt_uint32_t *)(_SCB_BASE + 0x0))
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#define _SYSTICK_LOAD (*(rt_uint32_t *)(_SCB_BASE + 0x4))
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#define _SYSTICK_VAL (*(rt_uint32_t *)(_SCB_BASE + 0x8))
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#define _SYSTICK_CALIB (*(rt_uint32_t *)(_SCB_BASE + 0xC))
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#define _SYSTICK_PRI (*(rt_uint8_t *)(0xE000ED23UL))
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// Updates the variable SystemCoreClock and must be called
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// whenever the core clock is changed during program execution.
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extern void SystemCoreClockUpdate(void);
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// Holds the system core clock, which is the system clock
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// frequency supplied to the SysTick timer and the processor
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// core clock.
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extern uint32_t SystemCoreClock;
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static uint32_t _SysTick_Config(rt_uint32_t ticks)
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{
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if ((ticks - 1) > 0xFFFFFF)
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{
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return 1;
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}
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_SYSTICK_LOAD = ticks - 1;
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_SYSTICK_PRI = 0xFF;
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_SYSTICK_VAL = 0;
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_SYSTICK_CTRL = 0x07;
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return 0;
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}
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#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
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#define RT_HEAP_SIZE 1024
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static uint32_t rt_heap[RT_HEAP_SIZE]; // heap default size: 4K(1024 * 4)
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RT_WEAK void *rt_heap_begin_get(void)
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{
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return rt_heap;
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}
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RT_WEAK void *rt_heap_end_get(void)
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{
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return rt_heap + RT_HEAP_SIZE;
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}
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#endif
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/**
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* This function will initial your board.
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*/
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void rt_hw_board_init()
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{
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/* System Clock Update */
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SystemCoreClockUpdate();
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/* System Tick Configuration */
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_SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
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/* Call components board initial (use INIT_BOARD_EXPORT()) */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
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rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
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#endif
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}
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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142
rt-thread/bsp/gd32vf103-blink/.cproject
Normal file
142
rt-thread/bsp/gd32vf103-blink/.cproject
Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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<externalSettings/>
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<extensions>
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<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
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<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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</extensions>
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</storageModule>
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<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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<configuration artifactName="GD32VF103xB" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1573373326" name="GD32VF103xB" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug" postannouncebuildStep="" postbuildStep="riscv-none-embed-objcopy -O binary "GD32VF103xB.elf" "GD32VF103xB.bin"; riscv-none-embed-objdump -D "GD32VF103xB.elf" > "GD32VF103xB.dump"" preannouncebuildStep="" prebuildStep="">
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<toolChain errorParsers="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.debug.2046554316" name="RISC-V Cross GCC" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.debug">
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objcopy.932624507" name="Hex/Bin converter" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objcopy" useByScannerDiscovery="false" value="objcopy" valueType="string"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objdump.1010041609" name="Listing generator" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objdump" useByScannerDiscovery="false" value="objdump" valueType="string"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.size.2047288003" name="Size command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.size" useByScannerDiscovery="false" value="size" valueType="string"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.make.308827908" name="Build command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.make" useByScannerDiscovery="false" value="make" valueType="string"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.rm.1884924570" name="Remove command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.rm" useByScannerDiscovery="false" value="rm" valueType="string"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.base.1216590122" name="Architecture" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.base" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.arch.rv32i" valueType="enumerated"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.978480188" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.ilp32" valueType="enumerated"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.77807932" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.low" valueType="enumerated"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.div.1100870138" name="Integer divide instructions (-mdiv)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.div" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1101325214" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.1765202347" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.492278601" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.id.566596567" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.id" useByScannerDiscovery="false" value="512258282" valueType="string"/>
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||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.257777065" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
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||||
<builder buildPath="${workspace_loc:/GD32V103V_EVAL}/Debug" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.468614052" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
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||||
<tool command="${cross_prefix}${cross_c}${cross_suffix}" commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} -c ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.260700709" name="GNU RISC-V Cross Assembler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler">
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1247850980" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.380773705" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/rt-thread/lipcpu/common}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/libraries/RISCV/drivers}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}""/>
|
||||
</option>
|
||||
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input.553075976" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input"/>
|
||||
</tool>
|
||||
<tool command="${cross_prefix}${cross_c}${cross_suffix}" commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} -c ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.488215038" name="GNU RISC-V Cross C Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler">
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths.1356152463" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/drivers}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/rt-thread/include}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/libraries/RISCV/drivers}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/libraries/RISCV/env_Eclipse}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/libraries/RISCV/stubs}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/libraries/GD32VF103_standard_peripheral}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/libraries/GD32VF103_standard_peripheral/Include}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/GD32VF103V/drivers}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/GD32VF103V/rt-thread/lipcpu/common}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/GD32VF103V/rt-thread/components/finsh}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/GD32VF103V}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/GD32VF103V/libraries/GD32VF103_standard_peripheral}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/GD32VF103V/libraries/GD32VF103_standard_peripheral/Include}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/GD32VF103V/libraries/RISCV/drivers}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/GD32VF103V/libraries/RISCV/stubs}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/GD32VF103V/rt-thread}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/GD32VF103V/rt-thread/include}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/GD32VF103V/rt-thread/include/libc}""/>
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||||
</option>
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||||
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.888297046" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input"/>
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||||
</tool>
|
||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler.177215711" name="GNU RISC-V Cross C++ Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler"/>
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||||
<tool command="${cross_prefix}${cross_c}${cross_suffix}" commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.607423220" name="GNU RISC-V Cross C Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker">
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.gcsections.12119579" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.gcsections" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.1471711921" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1155013982" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/libraries/RISCV/env_Eclipse/GD32VF103xB.lds}""/>
|
||||
</option>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart.1536688125" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input.421391167" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input">
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
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|
||||
</tool>
|
||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker.1762099292" name="GNU RISC-V Cross C++ Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker">
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections.1774192569" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.228826367" name="GNU RISC-V Cross Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver"/>
|
||||
<tool command="${cross_prefix}${cross_objcopy}${cross_suffix}" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT}" errorParsers="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.1681627356" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash"/>
|
||||
<tool command="${cross_prefix}${cross_objdump}${cross_suffix}" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT}" errorParsers="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1458513031" name="GNU RISC-V Cross Create Listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting">
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source.1870404133" name="Display source (--source|-S)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders.754276605" name="Display all headers (--all-headers|-x)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle.1718260290" name="Demangle names (--demangle|-C)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers.90701945" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide.1117837454" name="Wide lines (--wide|-w)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
</tool>
|
||||
<tool command="${cross_prefix}${cross_size}${cross_suffix}" commandLinePattern="${COMMAND} ${FLAGS}" errorParsers="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.1188837593" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1723899866" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format" useByScannerDiscovery="false"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="GD32V103V_EVAL.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.756742950" name="Executable" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1542802236;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1542802236.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1471375400;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1349005409">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1573373326;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1573373326.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.488215038;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.888297046">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
<configuration configurationName="GD32VF103xB">
|
||||
<resource resourceType="PROJECT" workspacePath="/GD32V103V_EVAL"/>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
|
||||
</cproject>
|
||||
68
rt-thread/bsp/gd32vf103-blink/.project
Normal file
68
rt-thread/bsp/gd32vf103-blink/.project
Normal file
@@ -0,0 +1,68 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>GD32VF103</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>rt-thread</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/components</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/include</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/include</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/lipcpu</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/src</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/src</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/components/finsh</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/components/finsh</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/lipcpu/bumblebee</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/libcpu/risc-v/bumblebee</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/lipcpu/common</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/libcpu/risc-v/common</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,2 @@
|
||||
eclipse.preferences.version=1
|
||||
install.folder=E\:\\rtthread-nano\\samples\\gd32vf103-nano\\eclipse_toolchain\\openocd\\0.10.0-12-20190618-0815\\bin
|
||||
@@ -0,0 +1,2 @@
|
||||
buildTools.path=E\:\\rtthread-nano\\samples\\gd32vf103-nano\\eclipse_toolchain\\Build Tools\\2.10-20180103-1919\\bin
|
||||
eclipse.preferences.version=1
|
||||
@@ -0,0 +1,2 @@
|
||||
eclipse.preferences.version=1
|
||||
toolchain.path.512258282=E\:\\rtthread-nano\\samples\\gd32vf103-nano\\eclipse_toolchain\\RISC-V Embedded GCC\\RISC-V Embedded GCC\\8.2.0-2.2-20190521-0004\\bin
|
||||
@@ -0,0 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1573373326" name="GD32VF103xB">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1682983162688682364" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
@@ -0,0 +1,73 @@
|
||||
eclipse.preferences.version=1
|
||||
org.eclipse.cdt.codan.checkers.errnoreturn=Warning
|
||||
org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false}
|
||||
org.eclipse.cdt.codan.checkers.errreturnvalue=Error
|
||||
org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"}
|
||||
org.eclipse.cdt.codan.checkers.nocommentinside=-Error
|
||||
org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"}
|
||||
org.eclipse.cdt.codan.checkers.nolinecomment=-Error
|
||||
org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"}
|
||||
org.eclipse.cdt.codan.checkers.noreturn=Error
|
||||
org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false}
|
||||
org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false}
|
||||
org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()}
|
||||
org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true}
|
||||
org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info
|
||||
org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
|
||||
org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()}
|
||||
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false}
|
||||
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false}
|
||||
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"}
|
||||
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true}
|
||||
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true}
|
||||
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning
|
||||
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")}
|
||||
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error
|
||||
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"}
|
||||
@@ -0,0 +1,9 @@
|
||||
eclipse.preferences.version=1
|
||||
environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/CWD/delimiter=;
|
||||
environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/CWD/operation=replace
|
||||
environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/CWD/value=E\:\\Delivered_Pattern\\GD32501\\fw32501\\GD32VF103_Firmware_Library_V1.0.0\\project\\eclipse\\FLASH
|
||||
environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/PWD/delimiter=;
|
||||
environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/PWD/operation=replace
|
||||
environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/PWD/value=E\:\\Delivered_Pattern\\GD32501\\fw32501\\GD32VF103_Firmware_Library_V1.0.0\\project\\eclipse\\FLASH
|
||||
environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/append=true
|
||||
environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/appendContributed=true
|
||||
25
rt-thread/bsp/gd32vf103-blink/applications/main.c
Normal file
25
rt-thread/bsp/gd32vf103-blink/applications/main.c
Normal file
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-11-06 yangjie the first version
|
||||
*/
|
||||
|
||||
#include "gd32vf103v_eval.h"
|
||||
#include <rtthread.h>
|
||||
|
||||
int main(void)
|
||||
{
|
||||
gd_eval_led_init(LED1);
|
||||
|
||||
while (1)
|
||||
{
|
||||
gd_eval_led_on(LED1);
|
||||
rt_thread_mdelay(500);
|
||||
gd_eval_led_off(LED1);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
95
rt-thread/bsp/gd32vf103-blink/drivers/board.c
Normal file
95
rt-thread/bsp/gd32vf103-blink/drivers/board.c
Normal file
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-07-24 Tanek the first version
|
||||
* 2018-11-12 Ernest Chen modify copyright
|
||||
*/
|
||||
#include <rthw.h>
|
||||
#include <gd32vf103.h>
|
||||
#include "riscv_encoding.h"
|
||||
|
||||
#define TMR_MSIP 0xFFC
|
||||
#define TMR_MSIP_size 0x4
|
||||
#define TMR_MTIMECMP 0x8
|
||||
#define TMR_MTIMECMP_size 0x8
|
||||
#define TMR_MTIME 0x0
|
||||
#define TMR_MTIME_size 0x8
|
||||
|
||||
#define TMR_CTRL_ADDR 0xd1000000
|
||||
#define TMR_REG(offset) _REG32(TMR_CTRL_ADDR, offset)
|
||||
#define TMR_FREQ ((uint32_t)SystemCoreClock/4) //units HZ
|
||||
|
||||
void riscv_clock_init(void)
|
||||
{
|
||||
SystemInit();
|
||||
|
||||
/* ECLIC init */
|
||||
eclic_init(ECLIC_NUM_INTERRUPTS);
|
||||
eclic_mode_enable();
|
||||
set_csr(mstatus, MSTATUS_MIE);
|
||||
}
|
||||
|
||||
static void ostick_config(rt_uint32_t ticks)
|
||||
{
|
||||
/* set value */
|
||||
*(rt_uint64_t *)(TMR_CTRL_ADDR + TMR_MTIMECMP) = ticks;
|
||||
/* enable interrupt */
|
||||
eclic_irq_enable(CLIC_INT_TMR, 0, 0);
|
||||
/* clear value */
|
||||
*(rt_uint64_t *)(TMR_CTRL_ADDR + TMR_MTIME) = 0;
|
||||
}
|
||||
|
||||
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
|
||||
#define RT_HEAP_SIZE 1024
|
||||
static uint32_t rt_heap[RT_HEAP_SIZE]; // heap default size: 4K(1024 * 4)
|
||||
RT_WEAK void *rt_heap_begin_get(void)
|
||||
{
|
||||
return rt_heap;
|
||||
}
|
||||
|
||||
RT_WEAK void *rt_heap_end_get(void)
|
||||
{
|
||||
return rt_heap + RT_HEAP_SIZE;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* This function will initial your board.
|
||||
*/
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
/* system clock Configuration */
|
||||
riscv_clock_init();
|
||||
|
||||
/* OS Tick Configuration */
|
||||
ostick_config(TMR_FREQ / RT_TICK_PER_SECOND);
|
||||
|
||||
/* Call components board initial (use INIT_BOARD_EXPORT()) */
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
|
||||
rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
|
||||
#endif
|
||||
}
|
||||
|
||||
/* This is the timer interrupt service routine. */
|
||||
void eclic_mtip_handler(void)
|
||||
{
|
||||
/* clear value */
|
||||
*(rt_uint64_t *)(TMR_CTRL_ADDR + TMR_MTIME) = 0;
|
||||
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
/* tick increase */
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
61
rt-thread/bsp/gd32vf103-blink/drivers/gd32vf103_libopt.h
Normal file
61
rt-thread/bsp/gd32vf103-blink/drivers/gd32vf103_libopt.h
Normal file
@@ -0,0 +1,61 @@
|
||||
/*!
|
||||
\file gd32vf103_libopt.h
|
||||
\brief library optional for gd32vf103
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_LIBOPT_H
|
||||
#define GD32VF103_LIBOPT_H
|
||||
|
||||
#include "gd32vf103_adc.h"
|
||||
#include "gd32vf103_bkp.h"
|
||||
#include "gd32vf103_can.h"
|
||||
#include "gd32vf103_crc.h"
|
||||
#include "gd32vf103_dac.h"
|
||||
#include "gd32vf103_dma.h"
|
||||
#include "gd32vf103_eclic.h"
|
||||
#include "gd32vf103_exmc.h"
|
||||
#include "gd32vf103_exti.h"
|
||||
#include "gd32vf103_fmc.h"
|
||||
#include "gd32vf103_gpio.h"
|
||||
#include "gd32vf103_i2c.h"
|
||||
#include "gd32vf103_fwdgt.h"
|
||||
#include "gd32vf103_dbg.h"
|
||||
#include "gd32vf103_pmu.h"
|
||||
#include "gd32vf103_rcu.h"
|
||||
#include "gd32vf103_rtc.h"
|
||||
#include "gd32vf103_spi.h"
|
||||
#include "gd32vf103_timer.h"
|
||||
#include "gd32vf103_usart.h"
|
||||
#include "gd32vf103_wwdgt.h"
|
||||
#include "n200_func.h"
|
||||
|
||||
#endif /* GD32VF103_LIBOPT_H */
|
||||
247
rt-thread/bsp/gd32vf103-blink/drivers/gd32vf103v_eval.c
Normal file
247
rt-thread/bsp/gd32vf103-blink/drivers/gd32vf103v_eval.c
Normal file
@@ -0,0 +1,247 @@
|
||||
/*!
|
||||
\file gd32vf103v_eval.c
|
||||
\brief firmware functions to manage leds, keys, COM ports
|
||||
|
||||
\version 2019-6-5, V1.0.0, demo for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103v_eval.h"
|
||||
|
||||
/* private variables */
|
||||
static uint32_t GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT,
|
||||
LED3_GPIO_PORT, LED4_GPIO_PORT};
|
||||
static uint32_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, LED4_PIN};
|
||||
|
||||
static rcu_periph_enum COM_CLK[COMn] = {EVAL_COM0_CLK, EVAL_COM1_CLK};
|
||||
static uint32_t COM_TX_PIN[COMn] = {EVAL_COM0_TX_PIN, EVAL_COM1_TX_PIN};
|
||||
static uint32_t COM_RX_PIN[COMn] = {EVAL_COM0_RX_PIN, EVAL_COM1_RX_PIN};
|
||||
static uint32_t COM_GPIO_PORT[COMn] = {EVAL_COM0_GPIO_PORT, EVAL_COM1_GPIO_PORT};
|
||||
static rcu_periph_enum COM_GPIO_CLK[COMn] = {EVAL_COM0_GPIO_CLK, EVAL_COM1_GPIO_CLK};
|
||||
|
||||
static rcu_periph_enum GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK,
|
||||
LED3_GPIO_CLK, LED4_GPIO_CLK};
|
||||
|
||||
static uint32_t KEY_PORT[KEYn] = {KEY_A_GPIO_PORT,
|
||||
KEY_B_GPIO_PORT,
|
||||
KEY_C_GPIO_PORT,
|
||||
KEY_D_GPIO_PORT,
|
||||
KEY_CET_GPIO_PORT};
|
||||
static uint32_t KEY_PIN[KEYn] = {KEY_A_PIN,
|
||||
KEY_B_PIN,
|
||||
KEY_C_PIN,
|
||||
KEY_D_PIN,
|
||||
KEY_CET_PIN};
|
||||
static rcu_periph_enum KEY_CLK[KEYn] = {KEY_A_GPIO_CLK,
|
||||
KEY_B_GPIO_CLK,
|
||||
KEY_C_GPIO_CLK,
|
||||
KEY_D_GPIO_CLK,
|
||||
KEY_CET_GPIO_CLK};
|
||||
static exti_line_enum KEY_EXTI_LINE[KEYn] = {KEY_A_EXTI_LINE,
|
||||
KEY_B_EXTI_LINE,
|
||||
KEY_C_EXTI_LINE,
|
||||
KEY_D_EXTI_LINE,
|
||||
KEY_CET_EXTI_LINE};
|
||||
static uint8_t KEY_PORT_SOURCE[KEYn] = {KEY_A_EXTI_PORT_SOURCE,
|
||||
KEY_B_EXTI_PORT_SOURCE,
|
||||
KEY_C_EXTI_PORT_SOURCE,
|
||||
KEY_D_EXTI_PORT_SOURCE,
|
||||
KEY_CET_EXTI_PORT_SOURCE};
|
||||
static uint8_t KEY_PIN_SOURCE[KEYn] = {KEY_A_EXTI_PIN_SOURCE,
|
||||
KEY_B_EXTI_PIN_SOURCE,
|
||||
KEY_C_EXTI_PIN_SOURCE,
|
||||
KEY_D_EXTI_PIN_SOURCE,
|
||||
KEY_CET_EXTI_PIN_SOURCE};
|
||||
static uint8_t KEY_IRQn[KEYn] = {KEY_A_EXTI_IRQn,
|
||||
KEY_B_EXTI_IRQn,
|
||||
KEY_C_EXTI_IRQn,
|
||||
KEY_D_EXTI_IRQn,
|
||||
KEY_CET_EXTI_IRQn};
|
||||
|
||||
/*!
|
||||
\brief configure led GPIO
|
||||
\param[in] lednum: specify the led to be configured
|
||||
\arg LED1
|
||||
\arg LED2
|
||||
\arg LED3
|
||||
\arg LED4
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gd_eval_led_init(led_typedef_enum lednum)
|
||||
{
|
||||
/* enable the led clock */
|
||||
rcu_periph_clock_enable(GPIO_CLK[lednum]);
|
||||
/* configure led GPIO port */
|
||||
gpio_init(GPIO_PORT[lednum], GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN[lednum]);
|
||||
|
||||
GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief turn on selected led
|
||||
\param[in] lednum: specify the led to be turned on
|
||||
\arg LED1
|
||||
\arg LED2
|
||||
\arg LED3
|
||||
\arg LED4
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gd_eval_led_on(led_typedef_enum lednum)
|
||||
{
|
||||
GPIO_BOP(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief turn off selected led
|
||||
\param[in] lednum: specify the led to be turned off
|
||||
\arg LED1
|
||||
\arg LED2
|
||||
\arg LED3
|
||||
\arg LED4
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gd_eval_led_off(led_typedef_enum lednum)
|
||||
{
|
||||
GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief toggle selected led
|
||||
\param[in] lednum: specify the led to be toggled
|
||||
\arg LED1
|
||||
\arg LED2
|
||||
\arg LED3
|
||||
\arg LED4
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gd_eval_led_toggle(led_typedef_enum lednum)
|
||||
{
|
||||
gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum],
|
||||
(bit_status)(1-gpio_input_bit_get(GPIO_PORT[lednum], GPIO_PIN[lednum])));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure key
|
||||
\param[in] key_num: specify the key to be configured
|
||||
\arg KEY_A: wakeup key
|
||||
\arg KEY_B: tamper key
|
||||
\arg KEY_C: user key
|
||||
\arg KEY_D: user key
|
||||
\arg KEY_CET: user key
|
||||
\param[in] key_mode: specify button mode
|
||||
\arg KEY_MODE_GPIO: key will be used as simple IO
|
||||
\arg KEY_MODE_EXTI: key will be connected to EXTI line with interrupt
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
|
||||
void gd_eval_key_init(key_typedef_enum key_num, keymode_typedef_enum key_mode)
|
||||
{
|
||||
/* enable the key clock */
|
||||
rcu_periph_clock_enable(KEY_CLK[key_num]);
|
||||
rcu_periph_clock_enable(RCU_AF);
|
||||
|
||||
/* configure button pin as input */
|
||||
gpio_init(KEY_PORT[key_num], GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, KEY_PIN[key_num]);
|
||||
|
||||
if (key_mode == KEY_MODE_EXTI) {
|
||||
/* enable and set key EXTI interrupt to the lowest priority */
|
||||
eclic_global_interrupt_enable();
|
||||
eclic_irq_enable(KEY_IRQn[key_num],1, 1);
|
||||
|
||||
/* connect key EXTI line to key GPIO pin */
|
||||
gpio_exti_source_select(KEY_PORT_SOURCE[key_num], KEY_PIN_SOURCE[key_num]);
|
||||
|
||||
/* configure key EXTI line */
|
||||
exti_init(KEY_EXTI_LINE[key_num], EXTI_INTERRUPT, EXTI_TRIG_FALLING);
|
||||
exti_interrupt_flag_clear(KEY_EXTI_LINE[key_num]);
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief return the selected key state
|
||||
\param[in] key: specify the key to be checked
|
||||
\arg KEY_A: wakeup key
|
||||
\arg KEY_B: tamper key
|
||||
\arg KEY_C: user key
|
||||
\arg KEY_D: user key
|
||||
\arg KEY_CET: user key
|
||||
\param[out] none
|
||||
\retval the key's GPIO pin value
|
||||
*/
|
||||
uint8_t gd_eval_key_state_get(key_typedef_enum key)
|
||||
{
|
||||
return gpio_input_bit_get(KEY_PORT[key], KEY_PIN[key]);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure COM port
|
||||
\param[in] com: COM on the board
|
||||
\arg EVAL_COM0: COM0 on the board
|
||||
\arg EVAL_COM1: COM1 on the board
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gd_eval_com_init(uint32_t com)
|
||||
{
|
||||
uint32_t com_id = 0U;
|
||||
if(EVAL_COM0 == com){
|
||||
com_id = 0U;
|
||||
}else if(EVAL_COM1 == com){
|
||||
com_id = 1U;
|
||||
}
|
||||
|
||||
/* enable GPIO clock */
|
||||
rcu_periph_clock_enable(COM_GPIO_CLK[com_id]);
|
||||
|
||||
/* enable USART clock */
|
||||
rcu_periph_clock_enable(COM_CLK[com_id]);
|
||||
|
||||
/* connect port to USARTx_Tx */
|
||||
gpio_init(COM_GPIO_PORT[com_id], GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, COM_TX_PIN[com_id]);
|
||||
|
||||
/* connect port to USARTx_Rx */
|
||||
gpio_init(COM_GPIO_PORT[com_id], GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, COM_RX_PIN[com_id]);
|
||||
|
||||
/* USART configure */
|
||||
usart_deinit(com);
|
||||
usart_baudrate_set(com, 115200U);
|
||||
usart_word_length_set(com, USART_WL_8BIT);
|
||||
usart_stop_bit_set(com, USART_STB_1BIT);
|
||||
usart_parity_config(com, USART_PM_NONE);
|
||||
usart_hardware_flow_rts_config(com, USART_RTS_DISABLE);
|
||||
usart_hardware_flow_cts_config(com, USART_CTS_DISABLE);
|
||||
usart_receive_config(com, USART_RECEIVE_ENABLE);
|
||||
usart_transmit_config(com, USART_TRANSMIT_ENABLE);
|
||||
usart_enable(com);
|
||||
}
|
||||
168
rt-thread/bsp/gd32vf103-blink/drivers/gd32vf103v_eval.h
Normal file
168
rt-thread/bsp/gd32vf103-blink/drivers/gd32vf103v_eval.h
Normal file
@@ -0,0 +1,168 @@
|
||||
/*!
|
||||
\file gd32vf103v_eval.h
|
||||
\brief definitions for GD32VF103V_EVAL's leds, keys and COM ports hardware resources
|
||||
|
||||
\version 2019-6-5, V1.0.0, demo for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103V_EVAL_H
|
||||
#define GD32VF103V_EVAL_H
|
||||
|
||||
#ifdef cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* exported types */
|
||||
typedef enum
|
||||
{
|
||||
LED1 = 0,
|
||||
LED2 = 1,
|
||||
LED3 = 2,
|
||||
LED4 = 3
|
||||
} led_typedef_enum;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
KEY_A = 0,
|
||||
KEY_B = 1,
|
||||
KEY_C = 2,
|
||||
KEY_D = 3,
|
||||
KEY_CET = 4
|
||||
} key_typedef_enum;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
KEY_MODE_GPIO = 0,
|
||||
KEY_MODE_EXTI = 1
|
||||
} keymode_typedef_enum;
|
||||
|
||||
/* eval board low layer led */
|
||||
#define LEDn 4U
|
||||
|
||||
#define LED1_PIN GPIO_PIN_0
|
||||
#define LED1_GPIO_PORT GPIOC
|
||||
#define LED1_GPIO_CLK RCU_GPIOC
|
||||
|
||||
#define LED2_PIN GPIO_PIN_2
|
||||
#define LED2_GPIO_PORT GPIOC
|
||||
#define LED2_GPIO_CLK RCU_GPIOC
|
||||
|
||||
#define LED3_PIN GPIO_PIN_0
|
||||
#define LED3_GPIO_PORT GPIOE
|
||||
#define LED3_GPIO_CLK RCU_GPIOE
|
||||
|
||||
#define LED4_PIN GPIO_PIN_1
|
||||
#define LED4_GPIO_PORT GPIOE
|
||||
#define LED4_GPIO_CLK RCU_GPIOE
|
||||
|
||||
#define COMn 2U
|
||||
|
||||
#define EVAL_COM0 USART0
|
||||
#define EVAL_COM0_CLK RCU_USART0
|
||||
#define EVAL_COM0_TX_PIN GPIO_PIN_9
|
||||
#define EVAL_COM0_RX_PIN GPIO_PIN_10
|
||||
#define EVAL_COM0_GPIO_PORT GPIOA
|
||||
#define EVAL_COM0_GPIO_CLK RCU_GPIOA
|
||||
|
||||
#define EVAL_COM1 USART1
|
||||
#define EVAL_COM1_CLK RCU_USART1
|
||||
#define EVAL_COM1_TX_PIN GPIO_PIN_2
|
||||
#define EVAL_COM1_RX_PIN GPIO_PIN_3
|
||||
#define EVAL_COM1_GPIO_PORT GPIOA
|
||||
#define EVAL_COM1_GPIO_CLK RCU_GPIOA
|
||||
|
||||
#define KEYn 5U
|
||||
|
||||
/* wakeup push-button */
|
||||
#define KEY_A_PIN GPIO_PIN_0
|
||||
#define KEY_A_GPIO_PORT GPIOA
|
||||
#define KEY_A_GPIO_CLK RCU_GPIOA
|
||||
#define KEY_A_EXTI_LINE EXTI_0
|
||||
#define KEY_A_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOA
|
||||
#define KEY_A_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_0
|
||||
#define KEY_A_EXTI_IRQn EXTI0_IRQn
|
||||
|
||||
/* tamper push-button */
|
||||
#define KEY_B_PIN GPIO_PIN_13
|
||||
#define KEY_B_GPIO_PORT GPIOC
|
||||
#define KEY_B_GPIO_CLK RCU_GPIOC
|
||||
#define KEY_B_EXTI_LINE EXTI_13
|
||||
#define KEY_B_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOC
|
||||
#define KEY_B_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_13
|
||||
#define KEY_B_EXTI_IRQn EXTI10_15_IRQn
|
||||
|
||||
/* user push-button */
|
||||
#define KEY_C_PIN GPIO_PIN_14
|
||||
#define KEY_C_GPIO_PORT GPIOB
|
||||
#define KEY_C_GPIO_CLK RCU_GPIOB
|
||||
#define KEY_C_EXTI_LINE EXTI_14
|
||||
#define KEY_C_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOB
|
||||
#define KEY_C_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_14
|
||||
#define KEY_C_EXTI_IRQn EXTI10_15_IRQn
|
||||
|
||||
#define KEY_D_PIN GPIO_PIN_5
|
||||
#define KEY_D_GPIO_PORT GPIOC
|
||||
#define KEY_D_GPIO_CLK RCU_GPIOC
|
||||
#define KEY_D_EXTI_LINE EXTI_5
|
||||
#define KEY_D_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOC
|
||||
#define KEY_D_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_5
|
||||
#define KEY_D_EXTI_IRQn EXTI5_9_IRQn
|
||||
|
||||
#define KEY_CET_PIN GPIO_PIN_4
|
||||
#define KEY_CET_GPIO_PORT GPIOC
|
||||
#define KEY_CET_GPIO_CLK RCU_GPIOC
|
||||
#define KEY_CET_EXTI_LINE EXTI_4
|
||||
#define KEY_CET_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOC
|
||||
#define KEY_CET_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_4
|
||||
#define KEY_CET_EXTI_IRQn EXTI4_IRQn
|
||||
|
||||
/* function declarations */
|
||||
/* configure led GPIO */
|
||||
void gd_eval_led_init(led_typedef_enum lednum);
|
||||
/* turn on selected led */
|
||||
void gd_eval_led_on(led_typedef_enum lednum);
|
||||
/* turn off selected led */
|
||||
void gd_eval_led_off(led_typedef_enum lednum);
|
||||
/* toggle the selected led */
|
||||
void gd_eval_led_toggle(led_typedef_enum lednum);
|
||||
/* configure key */
|
||||
void gd_eval_key_init(key_typedef_enum key_num, keymode_typedef_enum key_mode);
|
||||
/* return the selected key state */
|
||||
uint8_t gd_eval_key_state_get(key_typedef_enum key);
|
||||
/* configure COM port */
|
||||
void gd_eval_com_init(uint32_t com);
|
||||
|
||||
#ifdef cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* GD32VF103V_EVAL_H */
|
||||
@@ -0,0 +1,396 @@
|
||||
/*!
|
||||
\file gd32vf103_adc.h
|
||||
\brief definitions for the ADC
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_ADC_H
|
||||
#define GD32VF103_ADC_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* ADC definitions */
|
||||
#define ADC0 ADC_BASE
|
||||
#define ADC1 (ADC_BASE + 0x400U)
|
||||
|
||||
/* registers definitions */
|
||||
#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
|
||||
#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */
|
||||
#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */
|
||||
#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */
|
||||
#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */
|
||||
#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */
|
||||
#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */
|
||||
#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */
|
||||
#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
|
||||
#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
|
||||
#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
|
||||
#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */
|
||||
#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */
|
||||
#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */
|
||||
#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
|
||||
#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
|
||||
#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
|
||||
#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
|
||||
#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
|
||||
#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */
|
||||
#define ADC_OVSCR(adcx) REG32((adcx) + 0x80U) /*!< ADC oversample control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* ADC_STAT */
|
||||
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
|
||||
#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
|
||||
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
|
||||
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
||||
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
|
||||
|
||||
/* ADC_CTL0 */
|
||||
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
||||
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
|
||||
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
|
||||
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
||||
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
||||
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
||||
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
|
||||
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
|
||||
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
||||
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
||||
#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */
|
||||
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
||||
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
|
||||
|
||||
/* ADC_CTL1 */
|
||||
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
|
||||
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
|
||||
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
|
||||
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
|
||||
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
|
||||
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
||||
#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */
|
||||
#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
|
||||
#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */
|
||||
#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */
|
||||
#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
|
||||
#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
|
||||
#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */
|
||||
|
||||
/* ADC_SAMPTx x=0..1 */
|
||||
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */
|
||||
|
||||
/* ADC_IOFFx x=0..3 */
|
||||
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
|
||||
|
||||
/* ADC_WDHT */
|
||||
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
|
||||
|
||||
/* ADC_WDLT */
|
||||
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
||||
|
||||
/* ADC_RSQx x=0..2 */
|
||||
#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */
|
||||
#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
|
||||
|
||||
/* ADC_ISQ */
|
||||
#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */
|
||||
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
||||
|
||||
/* ADC_IDATAx x=0..3*/
|
||||
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */
|
||||
|
||||
/* ADC_RDATA */
|
||||
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */
|
||||
#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */
|
||||
|
||||
/* ADC_OVSCR */
|
||||
#define ADC_OVSCR_OVSEN BIT(0) /*!< oversampling enable */
|
||||
#define ADC_OVSCR_OVSR BITS(2,4) /*!< oversampling ratio */
|
||||
#define ADC_OVSCR_OVSS BITS(5,8) /*!< oversampling shift */
|
||||
#define ADC_OVSCR_TOVS BIT(9) /*!< triggered oversampling */
|
||||
#define ADC_OVSCR_DRES BITS(12,13) /*!< ADC data resolution */
|
||||
|
||||
/* constants definitions */
|
||||
/* adc_stat register value */
|
||||
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
|
||||
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
|
||||
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
|
||||
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
|
||||
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
|
||||
|
||||
/* adc_ctl0 register value */
|
||||
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
|
||||
|
||||
/* scan mode */
|
||||
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
||||
|
||||
/* inserted channel group convert automatically */
|
||||
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
|
||||
|
||||
/* ADC sync mode */
|
||||
#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */
|
||||
#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */
|
||||
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */
|
||||
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */
|
||||
#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */
|
||||
#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */
|
||||
#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */
|
||||
#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */
|
||||
#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */
|
||||
#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */
|
||||
#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */
|
||||
|
||||
/* adc_ctl1 register value */
|
||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
|
||||
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
|
||||
|
||||
/* continuous mode */
|
||||
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
||||
|
||||
/* external trigger select for regular channel */
|
||||
#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */
|
||||
/* for ADC0 and ADC1 regular channel */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
|
||||
|
||||
/* external trigger mode for inserted channel */
|
||||
#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */
|
||||
/* for ADC0 and ADC1 inserted channel */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
|
||||
|
||||
/* adc_samptx register value */
|
||||
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */
|
||||
#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
|
||||
|
||||
/* adc_ioffx register value */
|
||||
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */
|
||||
|
||||
/* adc_wdht register value */
|
||||
#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */
|
||||
|
||||
/* adc_wdlt register value */
|
||||
#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */
|
||||
|
||||
/* adc_rsqx register value */
|
||||
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */
|
||||
|
||||
/* adc_isq register value */
|
||||
#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */
|
||||
|
||||
/* ADC channel group definitions */
|
||||
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */
|
||||
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */
|
||||
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
|
||||
|
||||
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
|
||||
|
||||
/* ADC inserted channel definitions */
|
||||
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
|
||||
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */
|
||||
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */
|
||||
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */
|
||||
|
||||
/* ADC channel definitions */
|
||||
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
|
||||
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
|
||||
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
|
||||
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
|
||||
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
|
||||
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
|
||||
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
|
||||
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
|
||||
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
|
||||
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
|
||||
#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
|
||||
#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
|
||||
#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
|
||||
#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
|
||||
#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
|
||||
#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
|
||||
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
|
||||
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
|
||||
|
||||
/* ADC interrupt */
|
||||
#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
||||
#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
|
||||
#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
|
||||
|
||||
/* ADC interrupt flag */
|
||||
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */
|
||||
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
|
||||
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
|
||||
|
||||
/* ADC resolution definitions */
|
||||
#define OVSCR_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
|
||||
#define ADC_RESOLUTION_12B OVSCR_DRES(0) /*!< 12-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_10B OVSCR_DRES(1) /*!< 10-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_8B OVSCR_DRES(2) /*!< 8-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_6B OVSCR_DRES(3) /*!< 6-bit ADC resolution */
|
||||
|
||||
/* ADC oversampling mode */
|
||||
#define ADC_OVERSAMPLING_ALL_CONVERT 0 /*!< all oversampled conversions for a channel are done consecutively after a trigger */
|
||||
#define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */
|
||||
|
||||
/* ADC oversampling shift */
|
||||
#define OVSCR_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
|
||||
#define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_3B OVSCR_OVSS(3) /*!< 3-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_4B OVSCR_OVSS(4) /*!< 4-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_5B OVSCR_OVSS(5) /*!< 5-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_6B OVSCR_OVSS(6) /*!< 6-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_7B OVSCR_OVSS(7) /*!< 7-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */
|
||||
|
||||
/* ADC oversampling ratio */
|
||||
#define OVSCR_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSCR_OVSR(0) /*!< oversampling ratio X2 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSCR_OVSR(1) /*!< oversampling ratio X4 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSCR_OVSR(2) /*!< oversampling ratio X8 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSCR_OVSR(3) /*!< oversampling ratio X16 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSCR_OVSR(4) /*!< oversampling ratio X32 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSCR_OVSR(5) /*!< oversampling ratio X64 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSCR_OVSR(6) /*!< oversampling ratio X128 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSCR_OVSR(7) /*!< oversampling ratio X256 */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization config */
|
||||
/* reset ADC */
|
||||
void adc_deinit(uint32_t adc_periph);
|
||||
/* configure the ADC sync mode */
|
||||
void adc_mode_config(uint32_t mode);
|
||||
/* enable or disable ADC special function */
|
||||
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue);
|
||||
/* configure ADC data alignment */
|
||||
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment);
|
||||
/* enable ADC interface */
|
||||
void adc_enable(uint32_t adc_periph);
|
||||
/* disable ADC interface */
|
||||
void adc_disable(uint32_t adc_periph);
|
||||
/* ADC calibration and reset calibration */
|
||||
void adc_calibration_enable(uint32_t adc_periph);
|
||||
/* enable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_enable(void);
|
||||
/* disable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_disable(void);
|
||||
|
||||
/* DMA config */
|
||||
/* enable DMA request */
|
||||
void adc_dma_mode_enable(uint32_t adc_periph);
|
||||
/* disable DMA request */
|
||||
void adc_dma_mode_disable(uint32_t adc_periph);
|
||||
|
||||
/* regular group and inserted group config */
|
||||
/* configure ADC discontinuous mode */
|
||||
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length);
|
||||
|
||||
/* configure the length of regular channel group or inserted channel group */
|
||||
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length);
|
||||
/* configure ADC regular channel */
|
||||
void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
|
||||
/* configure ADC inserted channel */
|
||||
void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
|
||||
/* configure ADC inserted channel offset */
|
||||
void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset);
|
||||
|
||||
/* configure ADC external trigger source */
|
||||
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source);
|
||||
/* configure ADC external trigger */
|
||||
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue);
|
||||
/* enable ADC software trigger */
|
||||
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group);
|
||||
|
||||
/* get channel data */
|
||||
/* read ADC regular group data register */
|
||||
uint16_t adc_regular_data_read(uint32_t adc_periph);
|
||||
/* read ADC inserted group data register */
|
||||
uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel);
|
||||
/* read the last ADC0 and ADC1 conversion result data in sync mode */
|
||||
uint32_t adc_sync_mode_convert_value_read(void);
|
||||
|
||||
/* watchdog config */
|
||||
/* configure ADC analog watchdog single channel */
|
||||
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
|
||||
/* configure ADC analog watchdog group channel */
|
||||
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group);
|
||||
/* disable ADC analog watchdog */
|
||||
void adc_watchdog_disable(uint32_t adc_periph);
|
||||
/* configure ADC analog watchdog threshold */
|
||||
void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get the ADC flag bits */
|
||||
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag);
|
||||
/* clear the ADC flag bits */
|
||||
void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag);
|
||||
/* get the bit state of ADCx software start conversion */
|
||||
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph);
|
||||
/* get the bit state of ADCx software inserted channel start conversion */
|
||||
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
|
||||
/* get the ADC interrupt bits */
|
||||
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt);
|
||||
/* clear the ADC flag */
|
||||
void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt);
|
||||
/* enable ADC interrupt */
|
||||
void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt);
|
||||
/* disable ADC interrupt */
|
||||
void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt);
|
||||
|
||||
/* ADC resolution & oversample */
|
||||
/* ADC resolution config */
|
||||
void adc_resolution_config(uint32_t adc_periph, uint32_t resolution);
|
||||
/* ADC oversample mode config */
|
||||
void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio);
|
||||
/* enable ADC oversample mode */
|
||||
void adc_oversample_mode_enable(uint32_t adc_periph);
|
||||
/* disable ADC oversample mode */
|
||||
void adc_oversample_mode_disable(uint32_t adc_periph);
|
||||
|
||||
#endif /* GD32VF103_ADC_H */
|
||||
@@ -0,0 +1,227 @@
|
||||
/*!
|
||||
\file gd32vf103_bkp.h
|
||||
\brief definitions for the BKP
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_BKP_H
|
||||
#define GD32VF103_BKP_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* BKP definitions */
|
||||
#define BKP BKP_BASE /*!< BKP base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */
|
||||
#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */
|
||||
#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */
|
||||
#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */
|
||||
#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */
|
||||
#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */
|
||||
#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */
|
||||
#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */
|
||||
#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */
|
||||
#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */
|
||||
#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */
|
||||
#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */
|
||||
#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */
|
||||
#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */
|
||||
#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */
|
||||
#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */
|
||||
#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */
|
||||
#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */
|
||||
#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */
|
||||
#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */
|
||||
#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */
|
||||
#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */
|
||||
#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */
|
||||
#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */
|
||||
#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */
|
||||
#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */
|
||||
#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */
|
||||
#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */
|
||||
#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */
|
||||
#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */
|
||||
#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */
|
||||
#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */
|
||||
#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */
|
||||
#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */
|
||||
#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */
|
||||
#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */
|
||||
#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */
|
||||
#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */
|
||||
#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */
|
||||
#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */
|
||||
#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */
|
||||
#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */
|
||||
#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */
|
||||
#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */
|
||||
#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* BKP_DATA */
|
||||
#define BKP_DATA BITS(0,15) /*!< backup data */
|
||||
|
||||
/* BKP_OCTL */
|
||||
#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */
|
||||
#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */
|
||||
#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */
|
||||
#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */
|
||||
|
||||
/* BKP_TPCTL */
|
||||
#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */
|
||||
#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */
|
||||
|
||||
/* BKP_TPCS */
|
||||
#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */
|
||||
#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */
|
||||
#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */
|
||||
#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */
|
||||
#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */
|
||||
|
||||
/* constants definitions */
|
||||
/* BKP data register number */
|
||||
typedef enum
|
||||
{
|
||||
BKP_DATA_0 = 1, /*!< BKP data register 0 */
|
||||
BKP_DATA_1, /*!< BKP data register 1 */
|
||||
BKP_DATA_2, /*!< BKP data register 2 */
|
||||
BKP_DATA_3, /*!< BKP data register 3 */
|
||||
BKP_DATA_4, /*!< BKP data register 4 */
|
||||
BKP_DATA_5, /*!< BKP data register 5 */
|
||||
BKP_DATA_6, /*!< BKP data register 6 */
|
||||
BKP_DATA_7, /*!< BKP data register 7 */
|
||||
BKP_DATA_8, /*!< BKP data register 8 */
|
||||
BKP_DATA_9, /*!< BKP data register 9 */
|
||||
BKP_DATA_10, /*!< BKP data register 10 */
|
||||
BKP_DATA_11, /*!< BKP data register 11 */
|
||||
BKP_DATA_12, /*!< BKP data register 12 */
|
||||
BKP_DATA_13, /*!< BKP data register 13 */
|
||||
BKP_DATA_14, /*!< BKP data register 14 */
|
||||
BKP_DATA_15, /*!< BKP data register 15 */
|
||||
BKP_DATA_16, /*!< BKP data register 16 */
|
||||
BKP_DATA_17, /*!< BKP data register 17 */
|
||||
BKP_DATA_18, /*!< BKP data register 18 */
|
||||
BKP_DATA_19, /*!< BKP data register 19 */
|
||||
BKP_DATA_20, /*!< BKP data register 20 */
|
||||
BKP_DATA_21, /*!< BKP data register 21 */
|
||||
BKP_DATA_22, /*!< BKP data register 22 */
|
||||
BKP_DATA_23, /*!< BKP data register 23 */
|
||||
BKP_DATA_24, /*!< BKP data register 24 */
|
||||
BKP_DATA_25, /*!< BKP data register 25 */
|
||||
BKP_DATA_26, /*!< BKP data register 26 */
|
||||
BKP_DATA_27, /*!< BKP data register 27 */
|
||||
BKP_DATA_28, /*!< BKP data register 28 */
|
||||
BKP_DATA_29, /*!< BKP data register 29 */
|
||||
BKP_DATA_30, /*!< BKP data register 30 */
|
||||
BKP_DATA_31, /*!< BKP data register 31 */
|
||||
BKP_DATA_32, /*!< BKP data register 32 */
|
||||
BKP_DATA_33, /*!< BKP data register 33 */
|
||||
BKP_DATA_34, /*!< BKP data register 34 */
|
||||
BKP_DATA_35, /*!< BKP data register 35 */
|
||||
BKP_DATA_36, /*!< BKP data register 36 */
|
||||
BKP_DATA_37, /*!< BKP data register 37 */
|
||||
BKP_DATA_38, /*!< BKP data register 38 */
|
||||
BKP_DATA_39, /*!< BKP data register 39 */
|
||||
BKP_DATA_40, /*!< BKP data register 40 */
|
||||
BKP_DATA_41, /*!< BKP data register 41 */
|
||||
}bkp_data_register_enum;
|
||||
|
||||
/* BKP register */
|
||||
#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U)
|
||||
#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U)
|
||||
|
||||
/* get data of BKP data register */
|
||||
#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15)
|
||||
|
||||
/* RTC clock calibration value */
|
||||
#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* RTC output selection */
|
||||
#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */
|
||||
#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */
|
||||
|
||||
/* tamper pin active level */
|
||||
#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */
|
||||
#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */
|
||||
|
||||
/* tamper flag */
|
||||
#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */
|
||||
|
||||
/* tamper interrupt flag */
|
||||
#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */
|
||||
|
||||
/* function declarations */
|
||||
/* reset BKP registers */
|
||||
void bkp_deinit(void);
|
||||
/* write BKP data register */
|
||||
void bkp_data_write(bkp_data_register_enum register_number, uint16_t data);
|
||||
/* read BKP data register */
|
||||
uint16_t bkp_data_read(bkp_data_register_enum register_number);
|
||||
|
||||
/* RTC related functions */
|
||||
/* enable RTC clock calibration output */
|
||||
void bkp_rtc_calibration_output_enable(void);
|
||||
/* disable RTC clock calibration output */
|
||||
void bkp_rtc_calibration_output_disable(void);
|
||||
/* enable RTC alarm or second signal output */
|
||||
void bkp_rtc_signal_output_enable(void);
|
||||
/* disable RTC alarm or second signal output */
|
||||
void bkp_rtc_signal_output_disable(void);
|
||||
/* select RTC output */
|
||||
void bkp_rtc_output_select(uint16_t outputsel);
|
||||
/* set RTC clock calibration value */
|
||||
void bkp_rtc_calibration_value_set(uint8_t value);
|
||||
|
||||
/* tamper pin related functions */
|
||||
/* enable tamper pin detection */
|
||||
void bkp_tamper_detection_enable(void);
|
||||
/* disable tamper pin detection */
|
||||
void bkp_tamper_detection_disable(void);
|
||||
/* set tamper pin active level */
|
||||
void bkp_tamper_active_level_set(uint16_t level);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* enable tamper interrupt */
|
||||
void bkp_interrupt_enable(void);
|
||||
/* disable tamper interrupt */
|
||||
void bkp_interrupt_disable(void);
|
||||
/* get tamper flag state */
|
||||
FlagStatus bkp_flag_get(void);
|
||||
/* clear tamper flag state */
|
||||
void bkp_flag_clear(void);
|
||||
/* get tamper interrupt flag state */
|
||||
FlagStatus bkp_interrupt_flag_get(void);
|
||||
/* clear tamper interrupt flag state */
|
||||
void bkp_interrupt_flag_clear(void);
|
||||
|
||||
#endif /* GD32VF103_BKP_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,78 @@
|
||||
/*!
|
||||
\file gd32vf103_crc.h
|
||||
\brief definitions for the CRC
|
||||
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_CRC_H
|
||||
#define GD32VF103_CRC_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* CRC definitions */
|
||||
#define CRC CRC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
|
||||
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
|
||||
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CRC_DATA */
|
||||
#define CRC_DATA_DATA BITS(0, 31) /*!< CRC calculation result bits */
|
||||
|
||||
/* CRC_FDATA */
|
||||
#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */
|
||||
|
||||
/* CRC_CTL */
|
||||
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit CRC calculation unit */
|
||||
void crc_deinit(void);
|
||||
|
||||
/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */
|
||||
void crc_data_register_reset(void);
|
||||
/* read the value of the data register */
|
||||
uint32_t crc_data_register_read(void);
|
||||
|
||||
/* read the value of the free data register */
|
||||
uint8_t crc_free_data_register_read(void);
|
||||
/* write data to the free data register */
|
||||
void crc_free_data_register_write(uint8_t free_data);
|
||||
|
||||
/* calculate the CRC value of a 32-bit data */
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata);
|
||||
/* calculate the CRC value of an array of 32-bit values */
|
||||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
|
||||
|
||||
#endif /* GD32VF103_CRC_H */
|
||||
@@ -0,0 +1,242 @@
|
||||
/*!
|
||||
\file gd32vf103_dac.h
|
||||
\brief definitions for the DAC
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_DAC_H
|
||||
#define GD32VF103_DAC_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* DACx(x=0,1) definitions */
|
||||
#define DAC DAC_BASE
|
||||
#define DAC0 (0U)
|
||||
#define DAC1 (1U)
|
||||
|
||||
/* registers definitions */
|
||||
#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */
|
||||
#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */
|
||||
#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */
|
||||
#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */
|
||||
#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */
|
||||
#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */
|
||||
#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */
|
||||
#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */
|
||||
#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */
|
||||
#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */
|
||||
#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */
|
||||
#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */
|
||||
#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DAC_CTL */
|
||||
#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */
|
||||
#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */
|
||||
#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */
|
||||
#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */
|
||||
#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */
|
||||
#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */
|
||||
#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */
|
||||
#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */
|
||||
#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */
|
||||
#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */
|
||||
#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */
|
||||
#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */
|
||||
#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */
|
||||
#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */
|
||||
|
||||
/* DAC_SWT */
|
||||
#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */
|
||||
#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */
|
||||
|
||||
/* DAC0_R12DH */
|
||||
#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */
|
||||
|
||||
/* DAC0_L12DH */
|
||||
#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */
|
||||
|
||||
/* DAC0_R8DH */
|
||||
#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */
|
||||
|
||||
/* DAC1_R12DH */
|
||||
#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */
|
||||
|
||||
/* DAC1_L12DH */
|
||||
#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */
|
||||
|
||||
/* DAC1_R8DH */
|
||||
#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */
|
||||
|
||||
/* DACC_R12DH */
|
||||
#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
|
||||
#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
|
||||
|
||||
/* DACC_L12DH */
|
||||
#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
|
||||
#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
|
||||
|
||||
/* DACC_R8DH */
|
||||
#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
|
||||
#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
|
||||
|
||||
/* DAC0_DO */
|
||||
#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */
|
||||
|
||||
/* DAC1_DO */
|
||||
#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* DAC trigger source */
|
||||
#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||
#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */
|
||||
#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */
|
||||
#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */
|
||||
#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */
|
||||
#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */
|
||||
#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */
|
||||
#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */
|
||||
#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */
|
||||
|
||||
/* DAC noise wave mode */
|
||||
#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||
#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */
|
||||
#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */
|
||||
#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */
|
||||
|
||||
/* DAC noise wave bit width */
|
||||
#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
|
||||
#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
|
||||
#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
|
||||
#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
|
||||
#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
|
||||
#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
|
||||
#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
|
||||
#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
|
||||
#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
|
||||
#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
|
||||
#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
|
||||
#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
|
||||
#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
|
||||
|
||||
/* unmask LFSR bits in DAC LFSR noise mode */
|
||||
#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
|
||||
#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
|
||||
#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
|
||||
#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
|
||||
#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
|
||||
#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
|
||||
#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
|
||||
#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
|
||||
#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
|
||||
#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
|
||||
#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
|
||||
#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
|
||||
|
||||
/* DAC data alignment */
|
||||
#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */
|
||||
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */
|
||||
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */
|
||||
/* triangle amplitude in DAC triangle noise mode */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* deinitialize DAC */
|
||||
void dac_deinit(void);
|
||||
/* enable DAC */
|
||||
void dac_enable(uint32_t dac_periph);
|
||||
/* disable DAC */
|
||||
void dac_disable(uint32_t dac_periph);
|
||||
/* enable DAC DMA */
|
||||
void dac_dma_enable(uint32_t dac_periph);
|
||||
/* disable DAC DMA */
|
||||
void dac_dma_disable(uint32_t dac_periph);
|
||||
/* enable DAC output buffer */
|
||||
void dac_output_buffer_enable(uint32_t dac_periph);
|
||||
/* disable DAC output buffer */
|
||||
void dac_output_buffer_disable(uint32_t dac_periph);
|
||||
/* get the last data output value */
|
||||
uint16_t dac_output_value_get(uint32_t dac_periph);
|
||||
/* set DAC data holding register value */
|
||||
void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
|
||||
|
||||
/* DAC trigger configuration */
|
||||
/* enable DAC trigger */
|
||||
void dac_trigger_enable(uint32_t dac_periph);
|
||||
/* disable DAC trigger */
|
||||
void dac_trigger_disable(uint32_t dac_periph);
|
||||
/* configure DAC trigger source */
|
||||
void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource);
|
||||
/* enable DAC software trigger */
|
||||
void dac_software_trigger_enable(uint32_t dac_periph);
|
||||
/* disable DAC software trigger */
|
||||
void dac_software_trigger_disable(uint32_t dac_periph);
|
||||
|
||||
/* DAC wave mode configuration */
|
||||
/* configure DAC wave mode */
|
||||
void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode);
|
||||
/* configure DAC wave bit width */
|
||||
void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width);
|
||||
/* configure DAC LFSR noise mode */
|
||||
void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits);
|
||||
/* configure DAC triangle noise mode */
|
||||
void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude);
|
||||
|
||||
/* DAC concurrent mode configuration */
|
||||
/* enable DAC concurrent mode */
|
||||
void dac_concurrent_enable(void);
|
||||
/* disable DAC concurrent mode */
|
||||
void dac_concurrent_disable(void);
|
||||
/* enable DAC concurrent software trigger */
|
||||
void dac_concurrent_software_trigger_enable(void);
|
||||
/* disable DAC concurrent software trigger */
|
||||
void dac_concurrent_software_trigger_disable(void);
|
||||
/* enable DAC concurrent buffer function */
|
||||
void dac_concurrent_output_buffer_enable(void);
|
||||
/* disable DAC concurrent buffer function */
|
||||
void dac_concurrent_output_buffer_disable(void);
|
||||
/* set DAC concurrent mode data holding register value */
|
||||
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1);
|
||||
|
||||
#endif /* GD32VF103_DAC_H */
|
||||
@@ -0,0 +1,109 @@
|
||||
/*!
|
||||
\file gd32vf103_dbg.h
|
||||
\brief definitions for the DBG
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_DBG_H
|
||||
#define GD32VF103_DBG_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* DBG definitions */
|
||||
#define DBG DBG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
|
||||
#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DBG_ID */
|
||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||
|
||||
/* DBG_CTL */
|
||||
#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||
#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
|
||||
#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
|
||||
#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
|
||||
#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */
|
||||
#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */
|
||||
#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */
|
||||
#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */
|
||||
#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
|
||||
#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
|
||||
#define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */
|
||||
#define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
|
||||
#define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */
|
||||
#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */
|
||||
|
||||
/* constants definitions */
|
||||
/* debug hold when core is halted */
|
||||
typedef enum
|
||||
{
|
||||
DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
|
||||
DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
|
||||
DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */
|
||||
DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */
|
||||
DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */
|
||||
DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */
|
||||
DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */
|
||||
DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */
|
||||
DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */
|
||||
DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */
|
||||
DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */
|
||||
DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */
|
||||
DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */
|
||||
}dbg_periph_enum;
|
||||
|
||||
/* DBG low power mode configurations */
|
||||
#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||
|
||||
/* function declarations */
|
||||
/* read DBG_ID code register */
|
||||
uint32_t dbg_id_get(void);
|
||||
|
||||
/* low power behavior configuration */
|
||||
/* enable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||
/* disable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||
|
||||
/* peripheral behavior configuration */
|
||||
/* enable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||
/* disable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||
|
||||
#endif /* GD32VF103_DBG_H */
|
||||
@@ -0,0 +1,282 @@
|
||||
/*!
|
||||
\file gd32vf103_dma.h
|
||||
\brief definitions for the DMA
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_DMA_H
|
||||
#define GD32VF103_DMA_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* DMA definitions */
|
||||
#define DMA0 (DMA_BASE) /*!< DMA0 base address */
|
||||
#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */
|
||||
#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */
|
||||
|
||||
#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */
|
||||
#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */
|
||||
#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */
|
||||
#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */
|
||||
|
||||
#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */
|
||||
#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */
|
||||
#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */
|
||||
#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */
|
||||
|
||||
#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */
|
||||
#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */
|
||||
#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */
|
||||
#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */
|
||||
|
||||
#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */
|
||||
#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */
|
||||
#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */
|
||||
#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */
|
||||
|
||||
#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */
|
||||
#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */
|
||||
#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */
|
||||
#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */
|
||||
|
||||
#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */
|
||||
#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */
|
||||
#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */
|
||||
#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */
|
||||
|
||||
#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */
|
||||
#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */
|
||||
#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */
|
||||
#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DMA_INTF */
|
||||
#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
|
||||
#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
|
||||
#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
|
||||
#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
|
||||
|
||||
/* DMA_INTC */
|
||||
#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
|
||||
#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
|
||||
#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
|
||||
#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL, x=0..6 */
|
||||
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */
|
||||
#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */
|
||||
#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */
|
||||
#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */
|
||||
#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */
|
||||
#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */
|
||||
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
|
||||
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
|
||||
#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */
|
||||
#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */
|
||||
#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */
|
||||
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
|
||||
|
||||
/* DMA_CHxCNT, x=0..6 */
|
||||
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
|
||||
|
||||
/* DMA_CHxPADDR, x=0..6 */
|
||||
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
|
||||
|
||||
/* DMA_CHxMADDR, x=0..6 */
|
||||
#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA channel select */
|
||||
typedef enum
|
||||
{
|
||||
DMA_CH0 = 0, /*!< DMA Channel0 */
|
||||
DMA_CH1, /*!< DMA Channel1 */
|
||||
DMA_CH2, /*!< DMA Channel2 */
|
||||
DMA_CH3, /*!< DMA Channel3 */
|
||||
DMA_CH4, /*!< DMA Channel4 */
|
||||
DMA_CH5, /*!< DMA Channel5 */
|
||||
DMA_CH6 /*!< DMA Channel6 */
|
||||
} dma_channel_enum;
|
||||
|
||||
/* DMA initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t periph_addr; /*!< peripheral base address */
|
||||
uint32_t periph_width; /*!< transfer data size of peripheral */
|
||||
uint32_t memory_addr; /*!< memory base address */
|
||||
uint32_t memory_width; /*!< transfer data size of memory */
|
||||
uint32_t number; /*!< channel transfer number */
|
||||
uint32_t priority; /*!< channel priority level */
|
||||
uint8_t periph_inc; /*!< peripheral increasing mode */
|
||||
uint8_t memory_inc; /*!< memory increasing mode */
|
||||
uint8_t direction; /*!< channel data transfer direction */
|
||||
|
||||
} dma_parameter_struct;
|
||||
|
||||
#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */
|
||||
|
||||
/* DMA_register address */
|
||||
#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
|
||||
|
||||
/* DMA reset value */
|
||||
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
|
||||
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
|
||||
DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */
|
||||
|
||||
/* DMA_INTF register */
|
||||
/* interrupt flag bits */
|
||||
#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
|
||||
|
||||
/* flag bits */
|
||||
#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
|
||||
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
|
||||
#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL register */
|
||||
/* interrupt enable bits */
|
||||
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
|
||||
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
|
||||
#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
|
||||
|
||||
/* transfer direction */
|
||||
#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x0000U) /*!< read from peripheral and write to memory */
|
||||
#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x0001U) /*!< read from memory and write to peripheral */
|
||||
|
||||
/* peripheral increasing mode */
|
||||
#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of peripheral is fixed address mode */
|
||||
#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of peripheral is increasing address mode */
|
||||
|
||||
/* memory increasing mode */
|
||||
#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of memory is fixed address mode */
|
||||
#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */
|
||||
|
||||
/* transfer data size of peripheral */
|
||||
#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */
|
||||
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */
|
||||
|
||||
/* transfer data size of memory */
|
||||
#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */
|
||||
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */
|
||||
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */
|
||||
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */
|
||||
|
||||
/* channel priority level */
|
||||
#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */
|
||||
#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */
|
||||
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */
|
||||
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */
|
||||
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */
|
||||
|
||||
/* memory to memory mode */
|
||||
#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */
|
||||
#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */
|
||||
|
||||
/* DMA_CHxCNT register */
|
||||
/* transfer counter */
|
||||
#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */
|
||||
|
||||
/* function declarations */
|
||||
/* DMA deinitialization and initialization functions */
|
||||
/* deinitialize DMA a channel registers */
|
||||
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* initialize the parameters of DMA struct with the default values */
|
||||
void dma_struct_para_init(dma_parameter_struct* init_struct);
|
||||
/* initialize DMA channel */
|
||||
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct);
|
||||
/* enable DMA circulation mode */
|
||||
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable DMA circulation mode */
|
||||
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* enable memory to memory mode */
|
||||
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable memory to memory mode */
|
||||
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* enable DMA channel */
|
||||
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable DMA channel */
|
||||
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
|
||||
/* DMA configuration functions */
|
||||
/* set DMA peripheral base address */
|
||||
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
|
||||
/* set DMA memory base address */
|
||||
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
|
||||
/* set the number of remaining data to be transferred by the DMA */
|
||||
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number);
|
||||
/* get the number of remaining data to be transferred by the DMA */
|
||||
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* configure priority level of DMA channel */
|
||||
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
|
||||
/* configure transfer data size of memory */
|
||||
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
|
||||
/* configure transfer data size of peripheral */
|
||||
void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
|
||||
/* enable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* enable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* configure the direction of data transfer on the channel */
|
||||
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* check DMA flag is set or not */
|
||||
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear the flag of a DMA channel */
|
||||
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* check DMA flag and interrupt enable bit is set or not */
|
||||
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear the interrupt flag of a DMA channel */
|
||||
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* enable DMA interrupt */
|
||||
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||
/* disable DMA interrupt */
|
||||
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||
|
||||
#endif /* GD32VF103_DMA_H */
|
||||
@@ -0,0 +1,66 @@
|
||||
/*!
|
||||
\file gd32vf103_eclic.h
|
||||
\brief definitions for the ECLIC(Enhancement Core-Local Interrupt Controller)
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_ECLIC_H
|
||||
#define GD32VF103_ECLIC_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* constants definitions */
|
||||
#define ECLIC_PRIGROUP_LEVEL0_PRIO4 0 /*!< 0 bits for level 4 bits for priority */
|
||||
#define ECLIC_PRIGROUP_LEVEL1_PRIO3 1 /*!< 1 bits for level 3 bits for priority */
|
||||
#define ECLIC_PRIGROUP_LEVEL2_PRIO2 2 /*!< 2 bits for level 2 bits for priority */
|
||||
#define ECLIC_PRIGROUP_LEVEL3_PRIO1 3 /*!< 3 bits for level 1 bits for priority */
|
||||
#define ECLIC_PRIGROUP_LEVEL4_PRIO0 4 /*!< 4 bits for level 0 bits for priority */
|
||||
|
||||
#define __SEV eclic_send_event
|
||||
|
||||
/* function declarations */
|
||||
/* enable the global interrupt */
|
||||
void eclic_global_interrupt_enable(void);
|
||||
/* disable the global interrupt */
|
||||
void eclic_global_interrupt_disable(void);
|
||||
/* set the priority group */
|
||||
void eclic_priority_group_set(uint32_t prigroup);
|
||||
/* enable the interrupt request */
|
||||
void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority);
|
||||
/* disable the interrupt request */
|
||||
void eclic_irq_disable(uint32_t source);
|
||||
|
||||
/* reset system */
|
||||
void eclic_system_reset(void);
|
||||
/* send event(SEV) */
|
||||
void eclic_send_event(void);
|
||||
|
||||
#endif /* GD32VF103_ECLIC_H */
|
||||
@@ -0,0 +1,126 @@
|
||||
/*!
|
||||
\file gd32vf103_exmc.h
|
||||
\brief definitions for the EXMC
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_EXMC_H
|
||||
#define GD32VF103_EXMC_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* EXMC definitions */
|
||||
#define EXMC (EXMC_BASE) /*!< EXMC register base address */
|
||||
|
||||
/* registers definitions */
|
||||
/* NOR/PSRAM */
|
||||
#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */
|
||||
#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */
|
||||
#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */
|
||||
|
||||
/* bits definitions */
|
||||
/* NOR/PSRAM */
|
||||
/* EXMC_SNCTLx, x=0 */
|
||||
#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
|
||||
#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */
|
||||
#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
|
||||
#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
|
||||
#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
|
||||
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
|
||||
#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
|
||||
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
|
||||
#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */
|
||||
|
||||
/* EXMC_SNTCFGx, x=0 */
|
||||
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */
|
||||
#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */
|
||||
#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */
|
||||
#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXMC NOR/SRAM timing initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t bus_latency; /*!< configure the bus latency */
|
||||
uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
|
||||
uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */
|
||||
uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
|
||||
}exmc_norsram_timing_parameter_struct;
|
||||
|
||||
/* EXMC NOR/SRAM initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
|
||||
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
|
||||
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal */
|
||||
uint32_t memory_write; /*!< enable or disable the write operation */
|
||||
uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
|
||||
uint32_t databus_width; /*!< specifies the databus width of external memory */
|
||||
uint32_t memory_type; /*!< specifies the type of external memory */
|
||||
uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
|
||||
exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write */
|
||||
}exmc_norsram_parameter_struct;
|
||||
|
||||
/* EXMC register address */
|
||||
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */
|
||||
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */
|
||||
|
||||
/* NOR bank memory data bus width */
|
||||
#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */
|
||||
#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */
|
||||
|
||||
/* NOR bank memory type */
|
||||
#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||
#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
|
||||
#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
|
||||
#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
|
||||
|
||||
/* EXMC NOR/SRAM bank region definition */
|
||||
#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
|
||||
|
||||
/* EXMC NWAIT signal polarity configuration */
|
||||
#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
|
||||
#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize EXMC NOR/SRAM region */
|
||||
void exmc_norsram_deinit(uint32_t norsram_region);
|
||||
/* exmc_norsram_parameter_struct parameter initialize */
|
||||
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||
/* initialize EXMC NOR/SRAM region */
|
||||
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||
/* EXMC NOR/SRAM bank enable */
|
||||
void exmc_norsram_enable(uint32_t norsram_region);
|
||||
/* EXMC NOR/SRAM bank disable */
|
||||
void exmc_norsram_disable(uint32_t norsram_region);
|
||||
|
||||
#endif /* GD32VF103_EXMC_H */
|
||||
@@ -0,0 +1,245 @@
|
||||
/*!
|
||||
\file gd32vf103_exti.h
|
||||
\brief definitions for the EXTI
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_EXTI_H
|
||||
#define GD32VF103_EXTI_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* EXTI definitions */
|
||||
#define EXTI EXTI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */
|
||||
#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */
|
||||
#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */
|
||||
#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */
|
||||
#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */
|
||||
#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */
|
||||
|
||||
/* bits definitions */
|
||||
/* EXTI_INTEN */
|
||||
#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
|
||||
#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
|
||||
#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
|
||||
#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
|
||||
#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
|
||||
#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
|
||||
#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
|
||||
#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
|
||||
#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
|
||||
#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
|
||||
#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
|
||||
#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
|
||||
#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
|
||||
#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
|
||||
#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
|
||||
#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
|
||||
#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
|
||||
#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
|
||||
#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
|
||||
|
||||
/* EXTI_EVEN */
|
||||
#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
|
||||
#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
|
||||
#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
|
||||
#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
|
||||
#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
|
||||
#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
|
||||
#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
|
||||
#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
|
||||
#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
|
||||
#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
|
||||
#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
|
||||
#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
|
||||
#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
|
||||
#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
|
||||
#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
|
||||
#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
|
||||
#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
|
||||
#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
|
||||
#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
|
||||
|
||||
/* EXTI_RTEN */
|
||||
#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
|
||||
#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
|
||||
#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
|
||||
#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
|
||||
#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
|
||||
#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
|
||||
#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
|
||||
#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
|
||||
#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
|
||||
#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
|
||||
#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
|
||||
#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
|
||||
#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
|
||||
#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
|
||||
#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
|
||||
#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
|
||||
#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
|
||||
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
|
||||
#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */
|
||||
|
||||
/* EXTI_FTEN */
|
||||
#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
|
||||
#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
|
||||
#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
|
||||
#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
|
||||
#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
|
||||
#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
|
||||
#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
|
||||
#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
|
||||
#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
|
||||
#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
|
||||
#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
|
||||
#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
|
||||
#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
|
||||
#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
|
||||
#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
|
||||
#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
|
||||
#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
|
||||
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
|
||||
#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */
|
||||
|
||||
/* EXTI_SWIEV */
|
||||
#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
|
||||
#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
|
||||
#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
|
||||
#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
|
||||
#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
|
||||
#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
|
||||
#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
|
||||
#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
|
||||
#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
|
||||
#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
|
||||
#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
|
||||
#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
|
||||
#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
|
||||
#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
|
||||
#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
|
||||
#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
|
||||
#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
|
||||
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
|
||||
#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
|
||||
|
||||
/* EXTI_PD */
|
||||
#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */
|
||||
#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */
|
||||
#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */
|
||||
#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */
|
||||
#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */
|
||||
#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */
|
||||
#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */
|
||||
#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */
|
||||
#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */
|
||||
#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */
|
||||
#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */
|
||||
#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */
|
||||
#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */
|
||||
#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */
|
||||
#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */
|
||||
#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */
|
||||
#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */
|
||||
#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */
|
||||
#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXTI line number */
|
||||
typedef enum {
|
||||
EXTI_0 = BIT(0), /*!< EXTI line 0 */
|
||||
EXTI_1 = BIT(1), /*!< EXTI line 1 */
|
||||
EXTI_2 = BIT(2), /*!< EXTI line 2 */
|
||||
EXTI_3 = BIT(3), /*!< EXTI line 3 */
|
||||
EXTI_4 = BIT(4), /*!< EXTI line 4 */
|
||||
EXTI_5 = BIT(5), /*!< EXTI line 5 */
|
||||
EXTI_6 = BIT(6), /*!< EXTI line 6 */
|
||||
EXTI_7 = BIT(7), /*!< EXTI line 7 */
|
||||
EXTI_8 = BIT(8), /*!< EXTI line 8 */
|
||||
EXTI_9 = BIT(9), /*!< EXTI line 9 */
|
||||
EXTI_10 = BIT(10), /*!< EXTI line 10 */
|
||||
EXTI_11 = BIT(11), /*!< EXTI line 11 */
|
||||
EXTI_12 = BIT(12), /*!< EXTI line 12 */
|
||||
EXTI_13 = BIT(13), /*!< EXTI line 13 */
|
||||
EXTI_14 = BIT(14), /*!< EXTI line 14 */
|
||||
EXTI_15 = BIT(15), /*!< EXTI line 15 */
|
||||
EXTI_16 = BIT(16), /*!< EXTI line 16 */
|
||||
EXTI_17 = BIT(17), /*!< EXTI line 17 */
|
||||
EXTI_18 = BIT(18), /*!< EXTI line 18 */
|
||||
} exti_line_enum;
|
||||
|
||||
/* external interrupt and event */
|
||||
typedef enum {
|
||||
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
|
||||
EXTI_EVENT /*!< EXTI event mode */
|
||||
} exti_mode_enum;
|
||||
|
||||
/* interrupt trigger mode */
|
||||
typedef enum {
|
||||
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
|
||||
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
|
||||
EXTI_TRIG_BOTH, /*!< EXTI rising edge and falling edge trigger */
|
||||
EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */
|
||||
} exti_trig_type_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* initialization, EXTI lines configuration functions */
|
||||
/* deinitialize the EXTI */
|
||||
void exti_deinit(void);
|
||||
/* enable the configuration of EXTI initialize */
|
||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
|
||||
/* enable the interrupts from EXTI line x */
|
||||
void exti_interrupt_enable(exti_line_enum linex);
|
||||
/* enable the events from EXTI line x */
|
||||
void exti_event_enable(exti_line_enum linex);
|
||||
/* disable the interrupts from EXTI line x */
|
||||
void exti_interrupt_disable(exti_line_enum linex);
|
||||
/* disable the events from EXTI line x */
|
||||
void exti_event_disable(exti_line_enum linex);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get EXTI lines pending flag */
|
||||
FlagStatus exti_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI lines pending flag */
|
||||
void exti_flag_clear(exti_line_enum linex);
|
||||
/* get EXTI lines flag when the interrupt flag is set */
|
||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI lines pending flag */
|
||||
void exti_interrupt_flag_clear(exti_line_enum linex);
|
||||
/* enable the EXTI software interrupt event */
|
||||
void exti_software_interrupt_enable(exti_line_enum linex);
|
||||
/* disable the EXTI software interrupt event */
|
||||
void exti_software_interrupt_disable(exti_line_enum linex);
|
||||
|
||||
#endif /* GD32VF103_EXTI_H */
|
||||
@@ -0,0 +1,311 @@
|
||||
/*!
|
||||
\file gd32vf103_fmc.h
|
||||
\brief definitions for the FMC
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_FMC_H
|
||||
#define GD32VF103_FMC_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* FMC and option byte definition */
|
||||
#define FMC FMC_BASE /*!< FMC register base address */
|
||||
#define OB OB_BASE /*!< option bytes base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
|
||||
#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */
|
||||
#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
|
||||
#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */
|
||||
#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */
|
||||
#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */
|
||||
#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
|
||||
#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */
|
||||
#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
|
||||
|
||||
#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */
|
||||
#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/
|
||||
#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */
|
||||
#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */
|
||||
#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */
|
||||
#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */
|
||||
|
||||
/* bits definitions */
|
||||
/* FMC_WS */
|
||||
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
|
||||
|
||||
/* FMC_KEY0 */
|
||||
#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */
|
||||
|
||||
/* FMC_OBKEY */
|
||||
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
|
||||
|
||||
/* FMC_STAT0 */
|
||||
#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */
|
||||
#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */
|
||||
#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */
|
||||
#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */
|
||||
|
||||
/* FMC_CTL0 */
|
||||
#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */
|
||||
#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */
|
||||
#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */
|
||||
#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */
|
||||
#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */
|
||||
#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */
|
||||
#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */
|
||||
#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
|
||||
#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */
|
||||
#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
|
||||
|
||||
/* FMC_ADDR0 */
|
||||
#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */
|
||||
|
||||
/* FMC_OBSTAT */
|
||||
#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */
|
||||
#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */
|
||||
#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */
|
||||
#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */
|
||||
|
||||
/* FMC_WP */
|
||||
#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */
|
||||
|
||||
/* FMC_WSEN */
|
||||
#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
|
||||
|
||||
/* FMC_PID */
|
||||
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the FMC bit position and its register index offset */
|
||||
#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6)))
|
||||
#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
|
||||
#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12)))
|
||||
#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
|
||||
#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
|
||||
#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12)
|
||||
|
||||
/* configuration register */
|
||||
#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */
|
||||
#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */
|
||||
#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */
|
||||
|
||||
/* fmc state */
|
||||
typedef enum
|
||||
{
|
||||
FMC_READY, /*!< the operation has been completed */
|
||||
FMC_BUSY, /*!< the operation is in progress */
|
||||
FMC_PGERR, /*!< program error */
|
||||
FMC_WPERR, /*!< erase/program protection error */
|
||||
FMC_TOERR, /*!< timeout error */
|
||||
}fmc_state_enum;
|
||||
|
||||
/* FMC interrupt enable */
|
||||
typedef enum
|
||||
{
|
||||
FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */
|
||||
FMC_INT_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */
|
||||
}fmc_int_enum;
|
||||
|
||||
/* FMC flags */
|
||||
typedef enum
|
||||
{
|
||||
FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC busy flag */
|
||||
FMC_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC operation error flag bit */
|
||||
FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC erase/program protection error flag bit */
|
||||
FMC_FLAG_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC end of operation flag bit */
|
||||
FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */
|
||||
}fmc_flag_enum;
|
||||
|
||||
/* FMC interrupt flags */
|
||||
typedef enum
|
||||
{
|
||||
FMC_INT_FLAG_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC operation error interrupt flag bit */
|
||||
FMC_INT_FLAG_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC erase/program protection error interrupt flag bit */
|
||||
FMC_INT_FLAG_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC end of operation interrupt flag bit */
|
||||
}fmc_interrupt_flag_enum;
|
||||
|
||||
/* unlock key */
|
||||
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
|
||||
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
|
||||
|
||||
/* FMC wait state counter */
|
||||
#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval)))
|
||||
#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */
|
||||
#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */
|
||||
#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */
|
||||
|
||||
/* option bytes software/hardware free watch dog timer */
|
||||
#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */
|
||||
#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */
|
||||
|
||||
/* option bytes reset or not entering deep sleep mode */
|
||||
#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */
|
||||
#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */
|
||||
|
||||
/* option bytes reset or not entering standby mode */
|
||||
#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */
|
||||
|
||||
/* option bytes boot bank value */
|
||||
#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */
|
||||
|
||||
#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */
|
||||
|
||||
/* read protect configure */
|
||||
#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */
|
||||
#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */
|
||||
|
||||
/* OB_SPC */
|
||||
#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */
|
||||
#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */
|
||||
|
||||
/* OB_USER */
|
||||
#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */
|
||||
#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */
|
||||
|
||||
/* OB_WP0 */
|
||||
#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */
|
||||
|
||||
/* OB_WP1 */
|
||||
#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */
|
||||
|
||||
/* OB_WP2 */
|
||||
#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */
|
||||
|
||||
/* OB_WP3 */
|
||||
#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */
|
||||
|
||||
/* option bytes write protection */
|
||||
#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */
|
||||
#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */
|
||||
#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */
|
||||
#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */
|
||||
#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */
|
||||
#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */
|
||||
#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */
|
||||
#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */
|
||||
#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */
|
||||
#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */
|
||||
#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */
|
||||
#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */
|
||||
#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */
|
||||
#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */
|
||||
#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */
|
||||
#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */
|
||||
#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */
|
||||
#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */
|
||||
#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */
|
||||
#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */
|
||||
#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */
|
||||
#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */
|
||||
#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */
|
||||
#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */
|
||||
#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */
|
||||
#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */
|
||||
#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */
|
||||
#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */
|
||||
#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */
|
||||
#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */
|
||||
#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */
|
||||
#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */
|
||||
#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */
|
||||
|
||||
/* FMC timeout */
|
||||
#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */
|
||||
|
||||
/* FMC BANK address */
|
||||
#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */
|
||||
#define SRAM_SIZE (*(uint16_t *)0x1FFFF7E2U) /*!< SRAM size*/
|
||||
|
||||
/* function declarations */
|
||||
/* FMC main memory programming functions */
|
||||
/* set the FMC wait state counter */
|
||||
void fmc_wscnt_set(uint32_t wscnt);
|
||||
/* unlock the main FMC operation */
|
||||
void fmc_unlock(void);
|
||||
/* lock the main FMC operation */
|
||||
void fmc_lock(void);
|
||||
/* FMC erase page */
|
||||
fmc_state_enum fmc_page_erase(uint32_t page_address);
|
||||
/* FMC erase whole chip */
|
||||
fmc_state_enum fmc_mass_erase(void);
|
||||
/* FMC program a word at the corresponding address */
|
||||
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
|
||||
/* FMC program a half word at the corresponding address */
|
||||
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
|
||||
|
||||
/* FMC option bytes programming functions */
|
||||
/* unlock the option byte operation */
|
||||
void ob_unlock(void);
|
||||
/* lock the option byte operation */
|
||||
void ob_lock(void);
|
||||
/* erase the FMC option byte */
|
||||
fmc_state_enum ob_erase(void);
|
||||
/* enable write protect */
|
||||
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
|
||||
/* configure the option byte security protection */
|
||||
fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
|
||||
/* write the FMC option byte */
|
||||
fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot);
|
||||
/* program option bytes data */
|
||||
fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
|
||||
/* get the FMC option byte user */
|
||||
uint8_t ob_user_get(void);
|
||||
/* get OB_DATA in register FMC_OBSTAT */
|
||||
uint16_t ob_data_get(void);
|
||||
/* get the FMC option byte write protection */
|
||||
uint32_t ob_write_protection_get(void);
|
||||
/* get FMC option byte security protection code value */
|
||||
FlagStatus ob_spc_get(void);
|
||||
|
||||
/* FMC interrupts and flags management functions */
|
||||
/* enable FMC interrupt */
|
||||
void fmc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable FMC interrupt */
|
||||
void fmc_interrupt_disable(uint32_t interrupt);
|
||||
/* check flag is set or not */
|
||||
FlagStatus fmc_flag_get(uint32_t flag);
|
||||
/* clear the FMC flag */
|
||||
void fmc_flag_clear(uint32_t flag);
|
||||
/* get FMC interrupt flag state */
|
||||
FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag);
|
||||
/* clear FMC interrupt flag state */
|
||||
void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag);
|
||||
/* return the FMC state */
|
||||
fmc_state_enum fmc_state_get(void);
|
||||
/* check FMC ready or not */
|
||||
fmc_state_enum fmc_ready_wait(uint32_t timeout);
|
||||
|
||||
#endif /* GD32VF103_FMC_H */
|
||||
@@ -0,0 +1,104 @@
|
||||
/*!
|
||||
\file gd32vf103_fwdgt.h
|
||||
\brief definitions for the FWDGT
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_FWDGT_H
|
||||
#define GD32VF103_FWDGT_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* FWDGT definitions */
|
||||
#define FWDGT FWDGT_BASE /*!< FWDGT base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */
|
||||
#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */
|
||||
#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */
|
||||
#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* FWDGT_CTL */
|
||||
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
||||
|
||||
/* FWDGT_PSC */
|
||||
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
||||
|
||||
/* FWDGT_RLD */
|
||||
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
||||
|
||||
/* FWDGT_STAT */
|
||||
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
||||
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
||||
|
||||
/* constants definitions */
|
||||
/* psc register value */
|
||||
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
||||
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
||||
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
||||
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
||||
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
||||
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
||||
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
||||
|
||||
/* control value */
|
||||
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
|
||||
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
|
||||
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
||||
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
||||
|
||||
/* FWDGT timeout value */
|
||||
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
||||
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
||||
|
||||
/* FWDGT flag definitions */
|
||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
|
||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
|
||||
|
||||
/* function declarations */
|
||||
/* enable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_enable(void);
|
||||
/* disable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_disable(void);
|
||||
/* start the free watchdog timer counter */
|
||||
void fwdgt_enable(void);
|
||||
|
||||
/* reload the counter of FWDGT */
|
||||
void fwdgt_counter_reload(void);
|
||||
/* configure counter reload value, and prescaler divider value */
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
|
||||
|
||||
/* get flag state of FWDGT */
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag);
|
||||
|
||||
#endif /* GD32VF103_FWDGT_H */
|
||||
@@ -0,0 +1,422 @@
|
||||
/*!
|
||||
\file gd32vf103_gpio.h
|
||||
\brief definitions for the GPIO
|
||||
|
||||
\version 2019-06-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_GPIO_H
|
||||
#define GD32VF103_GPIO_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* GPIOx(x=A,B,C,D,E) definitions */
|
||||
#define GPIOA (GPIO_BASE + 0x00000000U)
|
||||
#define GPIOB (GPIO_BASE + 0x00000400U)
|
||||
#define GPIOC (GPIO_BASE + 0x00000800U)
|
||||
#define GPIOD (GPIO_BASE + 0x00000C00U)
|
||||
#define GPIOE (GPIO_BASE + 0x00001000U)
|
||||
|
||||
/* AFIO definitions */
|
||||
#define AFIO AFIO_BASE
|
||||
|
||||
/* registers definitions */
|
||||
|
||||
/* GPIO registers definitions */
|
||||
#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */
|
||||
#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */
|
||||
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */
|
||||
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */
|
||||
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */
|
||||
#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */
|
||||
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */
|
||||
|
||||
/* AFIO registers definitions */
|
||||
#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */
|
||||
#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */
|
||||
#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */
|
||||
#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */
|
||||
#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */
|
||||
#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */
|
||||
#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */
|
||||
|
||||
/* bits definitions */
|
||||
/* GPIO_CTL0 */
|
||||
#define GPIO_CTL0_MD0 BITS(0, 1) /*!< port 0 mode bits */
|
||||
#define GPIO_CTL0_CTL0 BITS(2, 3) /*!< pin 0 configuration bits */
|
||||
#define GPIO_CTL0_MD1 BITS(4, 5) /*!< port 1 mode bits */
|
||||
#define GPIO_CTL0_CTL1 BITS(6, 7) /*!< pin 1 configuration bits */
|
||||
#define GPIO_CTL0_MD2 BITS(8, 9) /*!< port 2 mode bits */
|
||||
#define GPIO_CTL0_CTL2 BITS(10, 11) /*!< pin 2 configuration bits */
|
||||
#define GPIO_CTL0_MD3 BITS(12, 13) /*!< port 3 mode bits */
|
||||
#define GPIO_CTL0_CTL3 BITS(14, 15) /*!< pin 3 configuration bits */
|
||||
#define GPIO_CTL0_MD4 BITS(16, 17) /*!< port 4 mode bits */
|
||||
#define GPIO_CTL0_CTL4 BITS(18, 19) /*!< pin 4 configuration bits */
|
||||
#define GPIO_CTL0_MD5 BITS(20, 21) /*!< port 5 mode bits */
|
||||
#define GPIO_CTL0_CTL5 BITS(22, 23) /*!< pin 5 configuration bits */
|
||||
#define GPIO_CTL0_MD6 BITS(24, 25) /*!< port 6 mode bits */
|
||||
#define GPIO_CTL0_CTL6 BITS(26, 27) /*!< pin 6 configuration bits */
|
||||
#define GPIO_CTL0_MD7 BITS(28, 29) /*!< port 7 mode bits */
|
||||
#define GPIO_CTL0_CTL7 BITS(30, 31) /*!< pin 7 configuration bits */
|
||||
|
||||
/* GPIO_CTL1 */
|
||||
#define GPIO_CTL1_MD8 BITS(0, 1) /*!< port 8 mode bits */
|
||||
#define GPIO_CTL1_CTL8 BITS(2, 3) /*!< pin 8 configuration bits */
|
||||
#define GPIO_CTL1_MD9 BITS(4, 5) /*!< port 9 mode bits */
|
||||
#define GPIO_CTL1_CTL9 BITS(6, 7) /*!< pin 9 configuration bits */
|
||||
#define GPIO_CTL1_MD10 BITS(8, 9) /*!< port 10 mode bits */
|
||||
#define GPIO_CTL1_CTL10 BITS(10, 11) /*!< pin 10 configuration bits */
|
||||
#define GPIO_CTL1_MD11 BITS(12, 13) /*!< port 11 mode bits */
|
||||
#define GPIO_CTL1_CTL11 BITS(14, 15) /*!< pin 11 configuration bits */
|
||||
#define GPIO_CTL1_MD12 BITS(16, 17) /*!< port 12 mode bits */
|
||||
#define GPIO_CTL1_CTL12 BITS(18, 19) /*!< pin 12 configuration bits */
|
||||
#define GPIO_CTL1_MD13 BITS(20, 21) /*!< port 13 mode bits */
|
||||
#define GPIO_CTL1_CTL13 BITS(22, 23) /*!< pin 13 configuration bits */
|
||||
#define GPIO_CTL1_MD14 BITS(24, 25) /*!< port 14 mode bits */
|
||||
#define GPIO_CTL1_CTL14 BITS(26, 27) /*!< pin 14 configuration bits */
|
||||
#define GPIO_CTL1_MD15 BITS(28, 29) /*!< port 15 mode bits */
|
||||
#define GPIO_CTL1_CTL15 BITS(30, 31) /*!< pin 15 configuration bits */
|
||||
|
||||
/* GPIO_ISTAT */
|
||||
#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
|
||||
#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
|
||||
#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
|
||||
#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */
|
||||
#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */
|
||||
#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */
|
||||
#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */
|
||||
#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */
|
||||
#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */
|
||||
#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */
|
||||
#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */
|
||||
#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */
|
||||
#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */
|
||||
#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */
|
||||
#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */
|
||||
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
|
||||
|
||||
/* GPIO_OCTL */
|
||||
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */
|
||||
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */
|
||||
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */
|
||||
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */
|
||||
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */
|
||||
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */
|
||||
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */
|
||||
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */
|
||||
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */
|
||||
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */
|
||||
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */
|
||||
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */
|
||||
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */
|
||||
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */
|
||||
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */
|
||||
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */
|
||||
|
||||
/* GPIO_BOP */
|
||||
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
|
||||
#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
|
||||
#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
|
||||
#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
|
||||
#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
|
||||
#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
|
||||
#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
|
||||
#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
|
||||
#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
|
||||
#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
|
||||
#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */
|
||||
#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */
|
||||
#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */
|
||||
#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */
|
||||
#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */
|
||||
#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */
|
||||
#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */
|
||||
#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */
|
||||
#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */
|
||||
#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */
|
||||
#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */
|
||||
#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */
|
||||
#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */
|
||||
#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */
|
||||
#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */
|
||||
#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */
|
||||
#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */
|
||||
#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */
|
||||
#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */
|
||||
#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */
|
||||
#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */
|
||||
#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */
|
||||
|
||||
/* GPIO_BC */
|
||||
#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */
|
||||
#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */
|
||||
#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */
|
||||
#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */
|
||||
#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */
|
||||
#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */
|
||||
#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */
|
||||
#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */
|
||||
#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */
|
||||
#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */
|
||||
#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */
|
||||
#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */
|
||||
#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */
|
||||
#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */
|
||||
#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */
|
||||
#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */
|
||||
|
||||
/* GPIO_LOCK */
|
||||
#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */
|
||||
#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */
|
||||
#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */
|
||||
#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */
|
||||
#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */
|
||||
#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */
|
||||
#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */
|
||||
#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */
|
||||
#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */
|
||||
#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */
|
||||
#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */
|
||||
#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */
|
||||
#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */
|
||||
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
|
||||
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
|
||||
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
|
||||
#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */
|
||||
|
||||
/* AFIO_EC */
|
||||
#define AFIO_EC_PIN BITS(0, 3) /*!< event output pin selection */
|
||||
#define AFIO_EC_PORT BITS(4, 6) /*!< event output port selection */
|
||||
#define AFIO_EC_EOE BIT(7) /*!< event output enable */
|
||||
|
||||
/* AFIO_PCF0 */
|
||||
/* memory map and bit definitions for GD32F10X_CL devices */
|
||||
#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */
|
||||
#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */
|
||||
#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */
|
||||
#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */
|
||||
#define AFIO_PCF0_USART2_REMAP BITS(4, 5) /*!< USART2 remapping */
|
||||
#define AFIO_PCF0_TIMER0_REMAP BITS(6, 7) /*!< TIMER0 remapping */
|
||||
#define AFIO_PCF0_TIMER1_REMAP BITS(8, 9) /*!< TIMER1 remapping */
|
||||
#define AFIO_PCF0_TIMER2_REMAP BITS(10, 11) /*!< TIMER2 remapping */
|
||||
#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */
|
||||
#define AFIO_PCF0_CAN_REMAP BITS(13, 14) /*!< CAN remapping */
|
||||
#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */
|
||||
#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER3 channel3 internal remapping */
|
||||
#define AFIO_PCF0_SWJ_CFG BITS(24, 26) /*!< serial wire JTAG configuration */
|
||||
#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */
|
||||
#define AFIO_PCF0_TIMER1_ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */
|
||||
|
||||
/* AFIO_EXTISS0 */
|
||||
#define AFIO_EXTI0_SS BITS(0, 3) /*!< EXTI 0 sources selection */
|
||||
#define AFIO_EXTI1_SS BITS(4, 7) /*!< EXTI 1 sources selection */
|
||||
#define AFIO_EXTI2_SS BITS(8, 11) /*!< EXTI 2 sources selection */
|
||||
#define AFIO_EXTI3_SS BITS(12, 15) /*!< EXTI 3 sources selection */
|
||||
|
||||
/* AFIO_EXTISS1 */
|
||||
#define AFIO_EXTI4_SS BITS(0, 3) /*!< EXTI 4 sources selection */
|
||||
#define AFIO_EXTI5_SS BITS(4, 7) /*!< EXTI 5 sources selection */
|
||||
#define AFIO_EXTI6_SS BITS(8, 11) /*!< EXTI 6 sources selection */
|
||||
#define AFIO_EXTI7_SS BITS(12, 15) /*!< EXTI 7 sources selection */
|
||||
|
||||
/* AFIO_EXTISS2 */
|
||||
#define AFIO_EXTI8_SS BITS(0, 3) /*!< EXTI 8 sources selection */
|
||||
#define AFIO_EXTI9_SS BITS(4, 7) /*!< EXTI 9 sources selection */
|
||||
#define AFIO_EXTI10_SS BITS(8, 11) /*!< EXTI 10 sources selection */
|
||||
#define AFIO_EXTI11_SS BITS(12, 15) /*!< EXTI 11 sources selection */
|
||||
|
||||
/* AFIO_EXTISS3 */
|
||||
#define AFIO_EXTI12_SS BITS(0, 3) /*!< EXTI 12 sources selection */
|
||||
#define AFIO_EXTI13_SS BITS(4, 7) /*!< EXTI 13 sources selection */
|
||||
#define AFIO_EXTI14_SS BITS(8, 11) /*!< EXTI 14 sources selection */
|
||||
#define AFIO_EXTI15_SS BITS(12, 15) /*!< EXTI 15 sources selection */
|
||||
|
||||
/* AFIO_PCF1 */
|
||||
#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */
|
||||
|
||||
/* constants definitions */
|
||||
typedef FlagStatus bit_status;
|
||||
|
||||
/* GPIO mode values set */
|
||||
#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n))))
|
||||
#define GPIO_MODE_MASK(n) (0xFU << (4U * (n)))
|
||||
|
||||
/* GPIO mode definitions */
|
||||
#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */
|
||||
#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */
|
||||
#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */
|
||||
#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */
|
||||
#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */
|
||||
#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */
|
||||
#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */
|
||||
#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */
|
||||
|
||||
/* GPIO output max speed value */
|
||||
#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */
|
||||
#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */
|
||||
#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */
|
||||
|
||||
/* GPIO event output port definitions */
|
||||
#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */
|
||||
#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */
|
||||
#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */
|
||||
#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */
|
||||
#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */
|
||||
|
||||
/* GPIO output port source definitions */
|
||||
#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */
|
||||
#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */
|
||||
#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */
|
||||
#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */
|
||||
#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */
|
||||
|
||||
/* GPIO event output pin definitions */
|
||||
#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */
|
||||
#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */
|
||||
#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */
|
||||
#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */
|
||||
#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */
|
||||
#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */
|
||||
#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */
|
||||
#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */
|
||||
#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */
|
||||
#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */
|
||||
#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */
|
||||
#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */
|
||||
#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */
|
||||
#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */
|
||||
#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */
|
||||
#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */
|
||||
|
||||
/* GPIO output pin source definitions */
|
||||
#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */
|
||||
#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */
|
||||
#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */
|
||||
#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */
|
||||
#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */
|
||||
#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */
|
||||
#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */
|
||||
#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */
|
||||
#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */
|
||||
#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */
|
||||
#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */
|
||||
#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */
|
||||
#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */
|
||||
#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */
|
||||
#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */
|
||||
#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */
|
||||
|
||||
/* GPIO pin definitions */
|
||||
#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */
|
||||
#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */
|
||||
#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */
|
||||
#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */
|
||||
#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */
|
||||
#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */
|
||||
#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */
|
||||
#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */
|
||||
#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */
|
||||
#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */
|
||||
#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */
|
||||
#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */
|
||||
#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */
|
||||
#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */
|
||||
#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */
|
||||
#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */
|
||||
#define GPIO_PIN_ALL BITS(0, 15) /*!< GPIO pin all */
|
||||
|
||||
/* GPIO remap definitions */
|
||||
#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */
|
||||
#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */
|
||||
#define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */
|
||||
#define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */
|
||||
#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */
|
||||
#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */
|
||||
#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */
|
||||
#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */
|
||||
#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */
|
||||
#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */
|
||||
#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */
|
||||
#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */
|
||||
#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */
|
||||
#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */
|
||||
#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping */
|
||||
#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping */
|
||||
#define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */
|
||||
#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping */
|
||||
#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping */
|
||||
#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< JTAG-DP,but without NJTRST */
|
||||
#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled */
|
||||
#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping */
|
||||
#define GPIO_TIMER1ITI1_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 1 remapping */
|
||||
#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */
|
||||
|
||||
/* function declarations */
|
||||
/* reset GPIO port */
|
||||
void gpio_deinit(uint32_t gpio_periph);
|
||||
/* reset alternate function I/O(AFIO) */
|
||||
void gpio_afio_deinit(void);
|
||||
/* GPIO parameter initialization */
|
||||
void gpio_init(uint32_t gpio_periph,uint32_t mode,uint32_t speed,uint32_t pin);
|
||||
|
||||
/* set GPIO pin bit */
|
||||
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
|
||||
/* reset GPIO pin bit */
|
||||
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
|
||||
/* write data to the specified GPIO pin */
|
||||
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
|
||||
/* write data to the specified GPIO port */
|
||||
void gpio_port_write(uint32_t gpio_periph, uint16_t data);
|
||||
|
||||
/* get GPIO pin input status */
|
||||
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||
/* get GPIO port input status */
|
||||
uint16_t gpio_input_port_get(uint32_t gpio_periph);
|
||||
/* get GPIO pin output status */
|
||||
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||
/* get GPIO port output status */
|
||||
uint16_t gpio_output_port_get(uint32_t gpio_periph);
|
||||
|
||||
/* configure GPIO pin remap */
|
||||
void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue);
|
||||
|
||||
/* select GPIO pin exti sources */
|
||||
void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin);
|
||||
/* configure GPIO pin event output */
|
||||
void gpio_event_output_config(uint8_t output_port, uint8_t output_pin);
|
||||
/* enable GPIO pin event output */
|
||||
void gpio_event_output_enable(void);
|
||||
/* disable GPIO pin event output */
|
||||
void gpio_event_output_disable(void);
|
||||
|
||||
/* lock GPIO pin bit */
|
||||
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
|
||||
|
||||
#endif /* GD32VF103_GPIO_H */
|
||||
@@ -0,0 +1,342 @@
|
||||
/*!
|
||||
\file gd32vf103_i2c.h
|
||||
\brief definitions for the I2C
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_I2C_H
|
||||
#define GD32VF103_I2C_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* I2Cx(x=0,1) definitions */
|
||||
#define I2C0 I2C_BASE /*!< I2C0 base address */
|
||||
#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */
|
||||
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */
|
||||
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/
|
||||
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */
|
||||
#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */
|
||||
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */
|
||||
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */
|
||||
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */
|
||||
#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */
|
||||
|
||||
/* bits definitions */
|
||||
/* I2Cx_CTL0 */
|
||||
#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
|
||||
#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
|
||||
#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
|
||||
#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
|
||||
#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
|
||||
#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
|
||||
#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
|
||||
#define I2C_CTL0_START BIT(8) /*!< start generation */
|
||||
#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
|
||||
#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
|
||||
#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
|
||||
#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
|
||||
#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
|
||||
#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
|
||||
|
||||
/* I2Cx_CTL1 */
|
||||
#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */
|
||||
#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */
|
||||
#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
|
||||
#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
|
||||
#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
|
||||
#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
|
||||
|
||||
/* I2Cx_SADDR0 */
|
||||
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
|
||||
|
||||
/* I2Cx_SADDR1 */
|
||||
#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
|
||||
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
|
||||
|
||||
/* I2Cx_DATA */
|
||||
#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
|
||||
|
||||
/* I2Cx_STAT0 */
|
||||
#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
|
||||
#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
|
||||
#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
|
||||
#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
|
||||
#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
|
||||
#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
|
||||
#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
|
||||
#define I2C_STAT0_BERR BIT(8) /*!< bus error */
|
||||
#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
|
||||
#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
|
||||
#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
|
||||
#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
|
||||
#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
|
||||
#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
|
||||
|
||||
/* I2Cx_STAT1 */
|
||||
#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
|
||||
#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
|
||||
#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */
|
||||
#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
|
||||
#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
|
||||
#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
|
||||
#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
|
||||
#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */
|
||||
|
||||
/* I2Cx_CKCFG */
|
||||
#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */
|
||||
#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */
|
||||
#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
|
||||
|
||||
/* I2Cx_RT */
|
||||
#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the I2C bit position and its register index offset */
|
||||
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
|
||||
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
|
||||
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
|
||||
|
||||
/* register offset */
|
||||
#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */
|
||||
#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */
|
||||
#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */
|
||||
|
||||
/* I2C flags */
|
||||
typedef enum {
|
||||
/* flags in STAT0 register */
|
||||
I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
|
||||
I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
|
||||
I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||
I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
|
||||
I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
|
||||
I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */
|
||||
I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
|
||||
I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
|
||||
I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
|
||||
I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
|
||||
I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
|
||||
I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
|
||||
I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
|
||||
I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
|
||||
/* flags in STAT1 register */
|
||||
I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
|
||||
I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
|
||||
I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
|
||||
I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
|
||||
I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
|
||||
I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
|
||||
I2C_FLAG_DUMODF = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
|
||||
} i2c_flag_enum;
|
||||
|
||||
/* I2C interrupt flags */
|
||||
typedef enum {
|
||||
/* interrupt flags in CTL1 register */
|
||||
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
|
||||
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
|
||||
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
|
||||
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
|
||||
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
|
||||
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
|
||||
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
|
||||
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
|
||||
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
|
||||
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */
|
||||
} i2c_interrupt_flag_enum;
|
||||
|
||||
/* I2C interrupt enable or disable */
|
||||
typedef enum {
|
||||
/* interrupt in CTL1 register */
|
||||
I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */
|
||||
I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */
|
||||
I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */
|
||||
} i2c_interrupt_enum;
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
|
||||
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
|
||||
#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
|
||||
|
||||
/* I2C transfer direction */
|
||||
#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
|
||||
#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
|
||||
|
||||
/* whether or not to send an ACK */
|
||||
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
|
||||
#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */
|
||||
|
||||
/* I2C POAP position*/
|
||||
#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */
|
||||
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
|
||||
|
||||
/* I2C dual-address mode switch */
|
||||
#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */
|
||||
#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */
|
||||
|
||||
/* whether or not to stretch SCL low */
|
||||
#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */
|
||||
#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */
|
||||
|
||||
/* whether or not to response to a general call */
|
||||
#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
|
||||
#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
|
||||
|
||||
/* software reset I2C */
|
||||
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
|
||||
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
|
||||
|
||||
/* I2C DMA mode configure */
|
||||
/* DMA mode switch */
|
||||
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */
|
||||
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */
|
||||
|
||||
/* flag indicating DMA last transfer */
|
||||
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
|
||||
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
|
||||
|
||||
/* I2C PEC configure */
|
||||
/* PEC enable */
|
||||
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
|
||||
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
|
||||
|
||||
/* PEC transfer */
|
||||
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */
|
||||
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
|
||||
|
||||
/* I2C SMBus configure */
|
||||
/* issue or not alert through SMBA pin */
|
||||
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
|
||||
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
|
||||
|
||||
/* ARP protocol in SMBus switch */
|
||||
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */
|
||||
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */
|
||||
|
||||
/* transmit I2C data */
|
||||
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* receive I2C data */
|
||||
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
||||
|
||||
/* I2C duty cycle in fast mode */
|
||||
#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */
|
||||
#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */
|
||||
|
||||
/* address mode for the I2C slave */
|
||||
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */
|
||||
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */
|
||||
|
||||
/* function declarations */
|
||||
/* reset I2C */
|
||||
void i2c_deinit(uint32_t i2c_periph);
|
||||
/* configure I2C clock */
|
||||
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
|
||||
/* configure I2C address */
|
||||
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode,uint32_t addformat, uint32_t addr);
|
||||
/* SMBus type selection */
|
||||
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
|
||||
/* whether or not to send an ACK */
|
||||
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
|
||||
/* configure I2C POAP position */
|
||||
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
|
||||
/* master sends slave address */
|
||||
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirection);
|
||||
/* configure I2C saddress1 */
|
||||
void i2c_saddr1_config(uint32_t i2c_periph,uint32_t addr);
|
||||
/* enable dual-address mode */
|
||||
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr);
|
||||
/* disable dual-address mode */
|
||||
void i2c_dualaddr_disable(uint32_t i2c_periph);
|
||||
/* enable I2C */
|
||||
void i2c_enable(uint32_t i2c_periph);
|
||||
/* disable I2C */
|
||||
void i2c_disable(uint32_t i2c_periph);
|
||||
|
||||
/* generate a START condition on I2C bus */
|
||||
void i2c_start_on_bus(uint32_t i2c_periph);
|
||||
/* generate a STOP condition on I2C bus */
|
||||
void i2c_stop_on_bus(uint32_t i2c_periph);
|
||||
/* I2C transmit data function */
|
||||
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
|
||||
/* I2C receive data function */
|
||||
uint8_t i2c_data_receive(uint32_t i2c_periph);
|
||||
/* enable I2C DMA mode */
|
||||
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
|
||||
/* configure whether next DMA EOT is DMA last transfer or not */
|
||||
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
|
||||
/* whether to stretch SCL low when data is not ready in slave mode */
|
||||
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
|
||||
/* whether or not to response to a general call */
|
||||
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
|
||||
/* software reset I2C */
|
||||
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
|
||||
|
||||
/* I2C PEC calculation on or off */
|
||||
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);
|
||||
/* I2C whether to transfer PEC value */
|
||||
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara);
|
||||
/* packet error checking value */
|
||||
uint8_t i2c_pec_value_get(uint32_t i2c_periph);
|
||||
/* I2C issue alert through SMBA pin */
|
||||
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
|
||||
/* I2C ARP protocol in SMBus switch */
|
||||
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
|
||||
|
||||
/* check I2C flag is set or not */
|
||||
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* clear I2C flag */
|
||||
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* enable I2C interrupt */
|
||||
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* disable I2C interrupt */
|
||||
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* check I2C interrupt flag */
|
||||
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag);
|
||||
/* clear I2C interrupt flag */
|
||||
void i2c_interrupt_flag_clear(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag);
|
||||
|
||||
#endif /* GD32VF103_I2C_H */
|
||||
@@ -0,0 +1,125 @@
|
||||
/*!
|
||||
\file gd32vf103_pmu.h
|
||||
\brief definitions for the PMU
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_PMU_H
|
||||
#define GD32VF103_PMU_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* PMU definitions */
|
||||
#define PMU PMU_BASE /*!< PMU base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
|
||||
#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* PMU_CTL */
|
||||
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
|
||||
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
|
||||
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
|
||||
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
|
||||
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
|
||||
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
|
||||
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
|
||||
|
||||
/* PMU_CS */
|
||||
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
|
||||
#define PMU_CS_STBF BIT(1) /*!< standby flag */
|
||||
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
|
||||
#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* PMU low voltage detector threshold definitions */
|
||||
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5))
|
||||
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */
|
||||
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
|
||||
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
|
||||
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */
|
||||
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */
|
||||
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */
|
||||
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */
|
||||
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */
|
||||
|
||||
/* PMU flag definitions */
|
||||
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
|
||||
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
|
||||
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */
|
||||
|
||||
/* PMU ldo definitions */
|
||||
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */
|
||||
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
|
||||
|
||||
/* PMU flag reset definitions */
|
||||
#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
|
||||
#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
|
||||
|
||||
/* PMU command constants definitions */
|
||||
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
|
||||
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
|
||||
|
||||
/* function declarations */
|
||||
/* reset PMU registers */
|
||||
void pmu_deinit(void);
|
||||
|
||||
/* select low voltage detector threshold */
|
||||
void pmu_lvd_select(uint32_t lvdt_n);
|
||||
/* disable PMU lvd */
|
||||
void pmu_lvd_disable(void);
|
||||
|
||||
/* set PMU mode */
|
||||
/* PMU work at sleep mode */
|
||||
void pmu_to_sleepmode(uint8_t sleepmodecmd);
|
||||
/* PMU work at deepsleep mode */
|
||||
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
|
||||
/* PMU work at standby mode */
|
||||
void pmu_to_standbymode(uint8_t standbymodecmd);
|
||||
/* enable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_enable(void);
|
||||
/* disable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_disable(void);
|
||||
|
||||
/* backup related functions */
|
||||
/* enable write access to the registers in backup domain */
|
||||
void pmu_backup_write_enable(void);
|
||||
/* disable write access to the registers in backup domain */
|
||||
void pmu_backup_write_disable(void);
|
||||
|
||||
/* flag functions */
|
||||
/* get flag state */
|
||||
FlagStatus pmu_flag_get(uint32_t flag);
|
||||
/* clear flag bit */
|
||||
void pmu_flag_clear(uint32_t flag_reset);
|
||||
|
||||
#endif /* GD32VF103_PMU_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,148 @@
|
||||
/*!
|
||||
\file gd32vf103_rtc.h
|
||||
\brief definitions for the RTC
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_RTC_H
|
||||
#define GD32VF103_RTC_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* RTC definitions */
|
||||
#define RTC RTC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */
|
||||
#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */
|
||||
#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */
|
||||
#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */
|
||||
#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */
|
||||
#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */
|
||||
#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */
|
||||
#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */
|
||||
#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */
|
||||
#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */
|
||||
|
||||
/* bits definitions */
|
||||
/* RTC_INTEN */
|
||||
#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */
|
||||
#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */
|
||||
#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */
|
||||
|
||||
/* RTC_CTL */
|
||||
#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */
|
||||
#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */
|
||||
#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */
|
||||
#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */
|
||||
#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */
|
||||
#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */
|
||||
|
||||
/* RTC_PSCH */
|
||||
#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */
|
||||
|
||||
/* RTC_PSCL */
|
||||
#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */
|
||||
|
||||
/* RTC_DIVH */
|
||||
#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */
|
||||
|
||||
/* RTC_DIVL */
|
||||
#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */
|
||||
|
||||
/* RTC_CNTH */
|
||||
#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */
|
||||
|
||||
/* RTC_CNTL */
|
||||
#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */
|
||||
|
||||
/* RTC_ALRMH */
|
||||
#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */
|
||||
|
||||
/* RTC_ALRML */
|
||||
#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */
|
||||
|
||||
/* constants definitions */
|
||||
/* RTC interrupt enable or disable definitions */
|
||||
#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */
|
||||
#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */
|
||||
#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */
|
||||
|
||||
/* RTC interrupt flag definitions */
|
||||
#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
|
||||
#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
|
||||
#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
|
||||
|
||||
/* RTC flag definitions */
|
||||
#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
|
||||
#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
|
||||
#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
|
||||
#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */
|
||||
#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* enter RTC configuration mode */
|
||||
void rtc_configuration_mode_enter(void);
|
||||
/* exit RTC configuration mode */
|
||||
void rtc_configuration_mode_exit(void);
|
||||
/* set RTC counter value */
|
||||
void rtc_counter_set(uint32_t cnt);
|
||||
/* set RTC prescaler value */
|
||||
void rtc_prescaler_set(uint32_t psc);
|
||||
|
||||
/* operation functions */
|
||||
/* wait RTC last write operation finished flag set */
|
||||
void rtc_lwoff_wait(void);
|
||||
/* wait RTC registers synchronized flag set */
|
||||
void rtc_register_sync_wait(void);
|
||||
/* set RTC alarm value */
|
||||
void rtc_alarm_config(uint32_t alarm);
|
||||
/* get RTC counter value */
|
||||
uint32_t rtc_counter_get(void);
|
||||
/* get RTC divider value */
|
||||
uint32_t rtc_divider_get(void);
|
||||
|
||||
/* flag & interrupt functions */
|
||||
/* get RTC flag status */
|
||||
FlagStatus rtc_flag_get(uint32_t flag);
|
||||
/* clear RTC flag status */
|
||||
void rtc_flag_clear(uint32_t flag);
|
||||
/* get RTC interrupt flag status */
|
||||
FlagStatus rtc_interrupt_flag_get(uint32_t flag);
|
||||
/* clear RTC interrupt flag status */
|
||||
void rtc_interrupt_flag_clear(uint32_t flag);
|
||||
/* enable RTC interrupt */
|
||||
void rtc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable RTC interrupt */
|
||||
void rtc_interrupt_disable(uint32_t interrupt);
|
||||
|
||||
#endif /* GD32VF103_RTC_H */
|
||||
@@ -0,0 +1,341 @@
|
||||
/*!
|
||||
\file gd32vf103_spi.h
|
||||
\brief definitions for the SPI
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF10X_SPI_H
|
||||
#define GD32VF10X_SPI_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* SPIx(x=0,1,2) definitions */
|
||||
#define SPI0 (SPI_BASE + 0x0000F800U)
|
||||
#define SPI1 SPI_BASE
|
||||
#define SPI2 (SPI_BASE + 0x00000400U)
|
||||
|
||||
/* SPI registers definitions */
|
||||
#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */
|
||||
#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/
|
||||
#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */
|
||||
#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */
|
||||
#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */
|
||||
#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */
|
||||
#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */
|
||||
#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */
|
||||
#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */
|
||||
|
||||
/* bits definitions */
|
||||
/* SPI_CTL0 */
|
||||
#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/
|
||||
#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */
|
||||
#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */
|
||||
#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */
|
||||
#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/
|
||||
#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */
|
||||
#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */
|
||||
#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */
|
||||
#define SPI_CTL0_RO BIT(10) /*!< receive only */
|
||||
#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */
|
||||
#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */
|
||||
#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */
|
||||
#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/
|
||||
#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */
|
||||
|
||||
/* SPI_CTL1 */
|
||||
#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */
|
||||
#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */
|
||||
#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */
|
||||
#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */
|
||||
#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */
|
||||
#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */
|
||||
#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */
|
||||
#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */
|
||||
|
||||
/* SPI_STAT */
|
||||
#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */
|
||||
#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */
|
||||
#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */
|
||||
#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */
|
||||
#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */
|
||||
#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */
|
||||
#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */
|
||||
#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */
|
||||
#define SPI_STAT_FERR BIT(8) /*!< format error bit */
|
||||
|
||||
/* SPI_DATA */
|
||||
#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */
|
||||
|
||||
/* SPI_CRCPOLY */
|
||||
#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */
|
||||
|
||||
/* SPI_RCRC */
|
||||
#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */
|
||||
|
||||
/* SPI_TCRC */
|
||||
#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */
|
||||
|
||||
/* SPI_I2SCTL */
|
||||
#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
|
||||
#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
|
||||
#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
|
||||
#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
|
||||
#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
|
||||
#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
|
||||
#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
|
||||
#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
|
||||
|
||||
/* SPI_I2SPSC */
|
||||
#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */
|
||||
#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */
|
||||
#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* SPI and I2S parameter struct definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t device_mode; /*!< SPI master or slave */
|
||||
uint32_t trans_mode; /*!< SPI transtype */
|
||||
uint32_t frame_size; /*!< SPI frame size */
|
||||
uint32_t nss; /*!< SPI NSS control by handware or software */
|
||||
uint32_t endian; /*!< SPI big endian or little endian */
|
||||
uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
|
||||
uint32_t prescale; /*!< SPI prescale factor */
|
||||
}spi_parameter_struct;
|
||||
|
||||
/* SPI mode definitions */
|
||||
#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
|
||||
#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
|
||||
|
||||
/* SPI bidirectional transfer direction */
|
||||
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */
|
||||
#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */
|
||||
|
||||
/* SPI transmit type */
|
||||
#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
|
||||
#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */
|
||||
#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */
|
||||
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/
|
||||
|
||||
/* SPI frame size */
|
||||
#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */
|
||||
#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */
|
||||
|
||||
/* SPI NSS control mode */
|
||||
#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by software */
|
||||
#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */
|
||||
|
||||
/* SPI transmit way */
|
||||
#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
|
||||
#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */
|
||||
|
||||
/* SPI clock phase and polarity */
|
||||
#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
|
||||
#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */
|
||||
#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */
|
||||
#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
|
||||
|
||||
/* SPI clock prescale factor */
|
||||
#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||
#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */
|
||||
#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */
|
||||
#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */
|
||||
#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */
|
||||
#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */
|
||||
#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */
|
||||
#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */
|
||||
#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */
|
||||
|
||||
/* I2S audio sample rate */
|
||||
#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
|
||||
#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
|
||||
#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
|
||||
#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
|
||||
#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
|
||||
#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
|
||||
#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
|
||||
#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
|
||||
#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
|
||||
|
||||
/* I2S frame format */
|
||||
#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
|
||||
|
||||
/* I2S master clock output */
|
||||
#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
|
||||
#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */
|
||||
|
||||
/* I2S operation mode */
|
||||
#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
|
||||
#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
|
||||
#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
|
||||
#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
|
||||
#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
|
||||
|
||||
/* I2S standard */
|
||||
#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */
|
||||
#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
|
||||
#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
|
||||
#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
|
||||
#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
|
||||
|
||||
/* I2S clock polarity */
|
||||
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
|
||||
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
|
||||
|
||||
/* SPI DMA constants definitions */
|
||||
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
|
||||
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
|
||||
|
||||
/* SPI CRC constants definitions */
|
||||
#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
|
||||
#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
|
||||
|
||||
/* SPI/I2S interrupt enable/disable constants definitions */
|
||||
#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */
|
||||
#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */
|
||||
#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */
|
||||
|
||||
/* SPI/I2S interrupt flag constants definitions */
|
||||
#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */
|
||||
#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */
|
||||
#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */
|
||||
#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */
|
||||
|
||||
/* SPI/I2S flag definitions */
|
||||
#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
|
||||
#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */
|
||||
#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */
|
||||
#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */
|
||||
#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */
|
||||
#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
|
||||
#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
|
||||
#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */
|
||||
|
||||
/* function declarations */
|
||||
/* SPI/I2S deinitialization and initialization functions */
|
||||
/* reset SPI and I2S */
|
||||
void spi_i2s_deinit(uint32_t spi_periph);
|
||||
/* initialize the parameters of SPI struct with the default values */
|
||||
void spi_struct_para_init(spi_parameter_struct* spi_struct);
|
||||
/* initialize SPI parameter */
|
||||
void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct);
|
||||
/* enable SPI */
|
||||
void spi_enable(uint32_t spi_periph);
|
||||
/* disable SPI */
|
||||
void spi_disable(uint32_t spi_periph);
|
||||
|
||||
/* initialize I2S parameter */
|
||||
void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
|
||||
/* configure I2S prescaler */
|
||||
void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
|
||||
/* enable I2S */
|
||||
void i2s_enable(uint32_t spi_periph);
|
||||
/* disable I2S */
|
||||
void i2s_disable(uint32_t spi_periph);
|
||||
|
||||
/* NSS functions */
|
||||
/* enable SPI NSS output */
|
||||
void spi_nss_output_enable(uint32_t spi_periph);
|
||||
/* disable SPI NSS output */
|
||||
void spi_nss_output_disable(uint32_t spi_periph);
|
||||
/* SPI NSS pin high level in software mode */
|
||||
void spi_nss_internal_high(uint32_t spi_periph);
|
||||
/* SPI NSS pin low level in software mode */
|
||||
void spi_nss_internal_low(uint32_t spi_periph);
|
||||
|
||||
/* DMA communication */
|
||||
/* enable SPI DMA */
|
||||
void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
|
||||
/* disable SPI DMA */
|
||||
void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
|
||||
|
||||
/* normal mode communication */
|
||||
/* configure SPI/I2S data frame format */
|
||||
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
|
||||
/* SPI transmit data */
|
||||
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
|
||||
/* SPI receive data */
|
||||
uint16_t spi_i2s_data_receive(uint32_t spi_periph);
|
||||
/* configure SPI bidirectional transfer direction */
|
||||
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
|
||||
|
||||
/* SPI CRC functions */
|
||||
/* set SPI CRC polynomial */
|
||||
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
|
||||
/* get SPI CRC polynomial */
|
||||
uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
|
||||
/* turn on SPI CRC function */
|
||||
void spi_crc_on(uint32_t spi_periph);
|
||||
/* turn off SPI CRC function */
|
||||
void spi_crc_off(uint32_t spi_periph);
|
||||
/* SPI next data is CRC value */
|
||||
void spi_crc_next(uint32_t spi_periph);
|
||||
/* get SPI CRC send value or receive value */
|
||||
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
|
||||
|
||||
/* SPI TI mode functions */
|
||||
/* enable SPI TI mode */
|
||||
void spi_ti_mode_enable(uint32_t spi_periph);
|
||||
/* disable SPI TI mode */
|
||||
void spi_ti_mode_disable(uint32_t spi_periph);
|
||||
|
||||
/* SPI NSS pulse mode functions */
|
||||
/* enable SPI NSS pulse mode */
|
||||
void spi_nssp_mode_enable(uint32_t spi_periph);
|
||||
/* disable SPI NSS pulse mode */
|
||||
void spi_nssp_mode_disable(uint32_t spi_periph);
|
||||
/* flag and interrupt functions */
|
||||
/* enable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* disable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* get SPI and I2S interrupt status */
|
||||
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* get SPI and I2S flag status */
|
||||
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
|
||||
/* clear SPI CRC error flag status */
|
||||
void spi_crc_error_clear(uint32_t spi_periph);
|
||||
|
||||
#endif /* GD32VF103_SPI_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,374 @@
|
||||
/*!
|
||||
\file gd32vf103_usart.h
|
||||
\brief definitions for the USART
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_USART_H
|
||||
#define GD32VF103_USART_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */
|
||||
#define USART1 USART_BASE /*!< USART1 base address */
|
||||
#define USART2 (USART_BASE+(0x00000400U)) /*!< USART2 base address */
|
||||
#define UART3 (USART_BASE+(0x00000800U)) /*!< UART3 base address */
|
||||
#define UART4 (USART_BASE+(0x00000C00U)) /*!< UART4 base address */
|
||||
#define USART0 (USART_BASE+(0x0000F400U)) /*!< USART0 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register */
|
||||
#define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */
|
||||
#define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate register */
|
||||
#define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register 0 */
|
||||
#define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register 1 */
|
||||
#define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register 2 */
|
||||
#define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and prescaler register */
|
||||
|
||||
/* bits definitions */
|
||||
/* USARTx_STAT */
|
||||
#define USART_STAT_PERR BIT(0) /*!< parity error flag */
|
||||
#define USART_STAT_FERR BIT(1) /*!< frame error flag */
|
||||
#define USART_STAT_NERR BIT(2) /*!< noise error flag */
|
||||
#define USART_STAT_ORERR BIT(3) /*!< overrun error */
|
||||
#define USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */
|
||||
#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */
|
||||
#define USART_STAT_TC BIT(6) /*!< transmission complete */
|
||||
#define USART_STAT_TBE BIT(7) /*!< transmit data buffer empty */
|
||||
#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */
|
||||
#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */
|
||||
|
||||
/* USARTx_DATA */
|
||||
#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */
|
||||
|
||||
/* USARTx_BAUD */
|
||||
#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */
|
||||
#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */
|
||||
|
||||
/* USARTx_CTL0 */
|
||||
#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */
|
||||
#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */
|
||||
#define USART_CTL0_REN BIT(2) /*!< receiver enable */
|
||||
#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */
|
||||
#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */
|
||||
#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */
|
||||
#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */
|
||||
#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */
|
||||
#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */
|
||||
#define USART_CTL0_PM BIT(9) /*!< parity mode */
|
||||
#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */
|
||||
#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
|
||||
#define USART_CTL0_WL BIT(12) /*!< word length */
|
||||
#define USART_CTL0_UEN BIT(13) /*!< USART enable */
|
||||
|
||||
/* USARTx_CTL1 */
|
||||
#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */
|
||||
#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
|
||||
#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */
|
||||
#define USART_CTL1_CLEN BIT(8) /*!< CK length */
|
||||
#define USART_CTL1_CPH BIT(9) /*!< CK phase */
|
||||
#define USART_CTL1_CPL BIT(10) /*!< CK polarity */
|
||||
#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */
|
||||
#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */
|
||||
#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */
|
||||
|
||||
/* USARTx_CTL2 */
|
||||
#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */
|
||||
#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */
|
||||
#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */
|
||||
#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */
|
||||
#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */
|
||||
#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */
|
||||
#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */
|
||||
#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */
|
||||
#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */
|
||||
#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */
|
||||
#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */
|
||||
|
||||
/* USARTx_GP */
|
||||
#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */
|
||||
#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the USART bit position and its register index offset */
|
||||
#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6)))
|
||||
#define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU))
|
||||
#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||
#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
|
||||
#define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16)
|
||||
|
||||
/* register offset */
|
||||
#define USART_STAT_REG_OFFSET (0x00000000U) /*!< STAT register offset */
|
||||
#define USART_CTL0_REG_OFFSET (0x0000000CU) /*!< CTL0 register offset */
|
||||
#define USART_CTL1_REG_OFFSET (0x00000010U) /*!< CTL1 register offset */
|
||||
#define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */
|
||||
|
||||
/* USART flags */
|
||||
typedef enum
|
||||
{
|
||||
/* flags in STAT register */
|
||||
USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */
|
||||
USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */
|
||||
USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */
|
||||
USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */
|
||||
USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */
|
||||
USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */
|
||||
USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */
|
||||
USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */
|
||||
USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */
|
||||
USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */
|
||||
}usart_flag_enum;
|
||||
|
||||
/* USART interrupt flags */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt flags in CTL0 register */
|
||||
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
|
||||
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
|
||||
USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */
|
||||
USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */
|
||||
USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
|
||||
USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */
|
||||
/* interrupt flags in CTL1 register */
|
||||
USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */
|
||||
/* interrupt flags in CTL2 register */
|
||||
USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */
|
||||
USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */
|
||||
USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */
|
||||
USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */
|
||||
}usart_interrupt_flag_enum;
|
||||
|
||||
/* USART interrupt enable or disable */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt in CTL0 register */
|
||||
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
|
||||
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
|
||||
USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */
|
||||
USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */
|
||||
USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */
|
||||
/* interrupt in CTL1 register */
|
||||
USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */
|
||||
/* interrupt in CTL2 register */
|
||||
USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */
|
||||
USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */
|
||||
}usart_interrupt_enum;
|
||||
|
||||
/* USART receiver configure */
|
||||
#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
||||
#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */
|
||||
#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */
|
||||
|
||||
/* USART transmitter configure */
|
||||
#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
|
||||
#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */
|
||||
#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */
|
||||
|
||||
/* USART parity bits definitions */
|
||||
#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
|
||||
#define USART_PM_NONE CTL0_PM(0) /*!< no parity */
|
||||
#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */
|
||||
#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */
|
||||
|
||||
/* USART wakeup method in mute mode */
|
||||
#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
|
||||
#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */
|
||||
#define USART_WM_ADDR CTL0_WM(1) /*!< address match */
|
||||
|
||||
/* USART word length definitions */
|
||||
#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
|
||||
#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */
|
||||
#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */
|
||||
|
||||
/* USART stop bits definitions */
|
||||
#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
|
||||
#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */
|
||||
#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */
|
||||
#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */
|
||||
#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */
|
||||
|
||||
/* USART LIN break frame length */
|
||||
#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
|
||||
#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */
|
||||
#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */
|
||||
|
||||
/* USART CK length */
|
||||
#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
|
||||
#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */
|
||||
#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */
|
||||
|
||||
/* USART clock phase */
|
||||
#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
|
||||
#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */
|
||||
#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */
|
||||
|
||||
/* USART clock polarity */
|
||||
#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
|
||||
#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */
|
||||
#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */
|
||||
|
||||
/* USART DMA request for receive configure */
|
||||
#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
|
||||
#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */
|
||||
#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */
|
||||
|
||||
/* USART DMA request for transmission configure */
|
||||
#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
|
||||
#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */
|
||||
#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */
|
||||
|
||||
/* USART RTS configure */
|
||||
#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
|
||||
#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */
|
||||
#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */
|
||||
|
||||
/* USART CTS configure */
|
||||
#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
|
||||
#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */
|
||||
#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */
|
||||
|
||||
/* USART IrDA low-power enable */
|
||||
#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
||||
#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */
|
||||
#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset USART */
|
||||
void usart_deinit(uint32_t usart_periph);
|
||||
/* configure USART baud rate value */
|
||||
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
|
||||
/* configure USART parity function */
|
||||
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
|
||||
/* configure USART word length */
|
||||
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
|
||||
/* configure USART stop bit length */
|
||||
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
|
||||
|
||||
/* USART normal mode communication */
|
||||
/* enable USART */
|
||||
void usart_enable(uint32_t usart_periph);
|
||||
/* disable USART */
|
||||
void usart_disable(uint32_t usart_periph);
|
||||
/* configure USART transmitter */
|
||||
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
|
||||
/* configure USART receiver */
|
||||
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
|
||||
/* USART transmit data function */
|
||||
void usart_data_transmit(uint32_t usart_periph, uint32_t data);
|
||||
/* USART receive data function */
|
||||
uint16_t usart_data_receive(uint32_t usart_periph);
|
||||
|
||||
/* multi-processor communication */
|
||||
/* configure address of the USART */
|
||||
void usart_address_config(uint32_t usart_periph, uint8_t addr);
|
||||
/* enable mute mode */
|
||||
void usart_mute_mode_enable(uint32_t usart_periph);
|
||||
/* disable mute mode */
|
||||
void usart_mute_mode_disable(uint32_t usart_periph);
|
||||
/* configure wakeup method in mute mode */
|
||||
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
|
||||
|
||||
/* LIN mode communication */
|
||||
/* LIN mode enable */
|
||||
void usart_lin_mode_enable(uint32_t usart_periph);
|
||||
/* LIN mode disable */
|
||||
void usart_lin_mode_disable(uint32_t usart_periph);
|
||||
/* LIN break detection length */
|
||||
void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
|
||||
/* send break frame */
|
||||
void usart_send_break(uint32_t usart_periph);
|
||||
|
||||
/* half-duplex communication */
|
||||
/* half-duplex enable */
|
||||
void usart_halfduplex_enable(uint32_t usart_periph);
|
||||
/* half-duplex disable */
|
||||
void usart_halfduplex_disable(uint32_t usart_periph);
|
||||
|
||||
/* synchronous communication */
|
||||
/* clock enable */
|
||||
void usart_synchronous_clock_enable(uint32_t usart_periph);
|
||||
/* clock disable */
|
||||
void usart_synchronous_clock_disable(uint32_t usart_periph);
|
||||
/* configure usart synchronous mode parameters */
|
||||
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
|
||||
|
||||
/* smartcard communication */
|
||||
/* guard time value configure in smartcard mode */
|
||||
void usart_guard_time_config(uint32_t usart_periph, uint32_t gaut);
|
||||
/* smartcard mode enable */
|
||||
void usart_smartcard_mode_enable(uint32_t usart_periph);
|
||||
/* smartcard mode disable */
|
||||
void usart_smartcard_mode_disable(uint32_t usart_periph);
|
||||
/* NACK enable in smartcard mode */
|
||||
void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
|
||||
/* NACK disable in smartcard mode */
|
||||
void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
|
||||
|
||||
/* IrDA communication */
|
||||
/* enable IrDA mode */
|
||||
void usart_irda_mode_enable(uint32_t usart_periph);
|
||||
/* disable IrDA mode */
|
||||
void usart_irda_mode_disable(uint32_t usart_periph);
|
||||
/* configure the peripheral clock prescaler */
|
||||
void usart_prescaler_config(uint32_t usart_periph, uint8_t psc);
|
||||
/* configure IrDA low-power */
|
||||
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
|
||||
|
||||
/* hardware flow communication */
|
||||
/* configure hardware flow control RTS */
|
||||
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
|
||||
/* configure hardware flow control CTS */
|
||||
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
|
||||
|
||||
/* configure USART DMA for reception */
|
||||
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
|
||||
/* configure USART DMA for transmission */
|
||||
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
|
||||
|
||||
/* flag functions */
|
||||
/* get flag in STAT register */
|
||||
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
|
||||
/* clear flag in STAT register */
|
||||
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
|
||||
|
||||
/* interrupt functions */
|
||||
/* enable USART interrupt */
|
||||
void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag);
|
||||
/* disable USART interrupt */
|
||||
void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag);
|
||||
/* get USART interrupt and flag status */
|
||||
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag);
|
||||
/* clear interrupt flag in STAT register */
|
||||
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag);
|
||||
#endif /* GD32VF103_USART_H */
|
||||
@@ -0,0 +1,86 @@
|
||||
/*!
|
||||
\file gd32vf103_wwdgt.h
|
||||
\brief definitions for the WWDGT
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_WWDGT_H
|
||||
#define GD32VF103_WWDGT_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* WWDGT definitions */
|
||||
#define WWDGT WWDGT_BASE /*!< WWDGT base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */
|
||||
#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */
|
||||
#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* WWDGT_CTL */
|
||||
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
|
||||
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
|
||||
|
||||
/* WWDGT_CFG */
|
||||
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
|
||||
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
|
||||
#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */
|
||||
|
||||
/* WWDGT_STAT */
|
||||
#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */
|
||||
|
||||
/* constants definitions */
|
||||
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */
|
||||
#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
|
||||
#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
|
||||
#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
|
||||
#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
|
||||
|
||||
/* function declarations */
|
||||
/* reset the window watchdog timer configuration */
|
||||
void wwdgt_deinit(void);
|
||||
/* start the window watchdog timer counter */
|
||||
void wwdgt_enable(void);
|
||||
|
||||
/* configure the window watchdog timer counter value */
|
||||
void wwdgt_counter_update(uint16_t counter_value);
|
||||
/* configure counter value, window value, and prescaler divider value */
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
|
||||
|
||||
/* enable early wakeup interrupt of WWDGT */
|
||||
void wwdgt_interrupt_enable(void);
|
||||
/* check early wakeup interrupt state of WWDGT */
|
||||
FlagStatus wwdgt_flag_get(void);
|
||||
/* clear early wakeup interrupt state of WWDGT */
|
||||
void wwdgt_flag_clear(void);
|
||||
|
||||
#endif /* GD32VF103_WWDGT_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,292 @@
|
||||
/*!
|
||||
\file gd32vf103_bkp.c
|
||||
\brief BKP driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_bkp.h"
|
||||
|
||||
/* BKP register bits offset */
|
||||
#define BKP_TAMPER_BITS_OFFSET ((uint32_t)8U)
|
||||
|
||||
/*!
|
||||
\brief reset BKP registers
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_deinit(void)
|
||||
{
|
||||
/* reset BKP domain register*/
|
||||
rcu_bkp_reset_enable();
|
||||
rcu_bkp_reset_disable();
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write BKP data register
|
||||
\param[in] register_number: refer to bkp_data_register_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg BKP_DATA_x(x = 0..41): bkp data register number x
|
||||
\param[in] data: the data to be write in BKP data register
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_data_write(bkp_data_register_enum register_number, uint16_t data)
|
||||
{
|
||||
if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
|
||||
BKP_DATA10_41(register_number - 1U) = data;
|
||||
}else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
|
||||
BKP_DATA0_9(register_number - 1U) = data;
|
||||
}else{
|
||||
/* illegal parameters */
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read BKP data register
|
||||
\param[in] register_number: refer to bkp_data_register_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg BKP_DATA_x(x = 0..41): bkp data register number x
|
||||
\param[out] none
|
||||
\retval data of BKP data register
|
||||
*/
|
||||
uint16_t bkp_data_read(bkp_data_register_enum register_number)
|
||||
{
|
||||
uint16_t data = 0U;
|
||||
|
||||
/* get the data from the BKP data register */
|
||||
if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
|
||||
data = BKP_DATA10_41(register_number - 1U);
|
||||
}else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
|
||||
data = BKP_DATA0_9(register_number - 1U);
|
||||
}else{
|
||||
/* illegal parameters */
|
||||
}
|
||||
return data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable RTC clock calibration output
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_rtc_calibration_output_enable(void)
|
||||
{
|
||||
BKP_OCTL |= (uint16_t)BKP_OCTL_COEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable RTC clock calibration output
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_rtc_calibration_output_disable(void)
|
||||
{
|
||||
BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable RTC alarm or second signal output
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_rtc_signal_output_enable(void)
|
||||
{
|
||||
BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable RTC alarm or second signal output
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_rtc_signal_output_disable(void)
|
||||
{
|
||||
BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief select RTC output
|
||||
\param[in] outputsel: RTC output selection
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output
|
||||
\arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_rtc_output_select(uint16_t outputsel)
|
||||
{
|
||||
uint16_t ctl = 0U;
|
||||
|
||||
/* configure BKP_OCTL_ROSEL with outputsel */
|
||||
ctl = BKP_OCTL;
|
||||
ctl &= (uint16_t)~BKP_OCTL_ROSEL;
|
||||
ctl |= outputsel;
|
||||
BKP_OCTL = ctl;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set RTC clock calibration value
|
||||
\param[in] value: RTC clock calibration value
|
||||
\arg 0x00 - 0x7F
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_rtc_calibration_value_set(uint8_t value)
|
||||
{
|
||||
uint16_t ctl;
|
||||
|
||||
/* configure BKP_OCTL_RCCV with value */
|
||||
ctl = BKP_OCTL;
|
||||
ctl &= (uint16_t)~BKP_OCTL_RCCV;
|
||||
ctl |= (uint16_t)OCTL_RCCV(value);
|
||||
BKP_OCTL = ctl;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable tamper detection
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_tamper_detection_enable(void)
|
||||
{
|
||||
BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable tamper detection
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_tamper_detection_disable(void)
|
||||
{
|
||||
BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set tamper pin active level
|
||||
\param[in] level: tamper active level
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high
|
||||
\arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_tamper_active_level_set(uint16_t level)
|
||||
{
|
||||
uint16_t ctl = 0U;
|
||||
|
||||
/* configure BKP_TPCTL_TPAL with level */
|
||||
ctl = BKP_TPCTL;
|
||||
ctl &= (uint16_t)~BKP_TPCTL_TPAL;
|
||||
ctl |= level;
|
||||
BKP_TPCTL = ctl;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable tamper interrupt
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_interrupt_enable(void)
|
||||
{
|
||||
BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable tamper interrupt
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_interrupt_disable(void)
|
||||
{
|
||||
BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get tamper flag state
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus bkp_flag_get(void)
|
||||
{
|
||||
if(RESET != (BKP_TPCS & BKP_FLAG_TAMPER)){
|
||||
return SET;
|
||||
}else{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear tamper flag state
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_flag_clear(void)
|
||||
{
|
||||
BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get tamper interrupt flag state
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus bkp_interrupt_flag_get(void)
|
||||
{
|
||||
if(RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)){
|
||||
return SET;
|
||||
}else{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear tamper interrupt flag state
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void bkp_interrupt_flag_clear(void)
|
||||
{
|
||||
BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,127 @@
|
||||
/*!
|
||||
\file gd32vf103_crc.c
|
||||
\brief CRC driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_crc.h"
|
||||
|
||||
#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU)
|
||||
#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U)
|
||||
|
||||
/*!
|
||||
\brief deinit CRC calculation unit
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_deinit(void)
|
||||
{
|
||||
CRC_DATA = CRC_DATA_RESET_VALUE;
|
||||
CRC_FDATA = CRC_FDATA_RESET_VALUE;
|
||||
CRC_CTL = (uint32_t)CRC_CTL_RST;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_data_register_reset(void)
|
||||
{
|
||||
CRC_CTL |= (uint32_t)CRC_CTL_RST;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the value of the data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval 32-bit value of the data register
|
||||
*/
|
||||
uint32_t crc_data_register_read(void)
|
||||
{
|
||||
uint32_t data;
|
||||
data = CRC_DATA;
|
||||
return (data);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the value of the free data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval 8-bit value of the free data register
|
||||
*/
|
||||
uint8_t crc_free_data_register_read(void)
|
||||
{
|
||||
uint8_t fdata;
|
||||
fdata = (uint8_t)CRC_FDATA;
|
||||
return (fdata);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write data to the free data register
|
||||
\param[in] free_data: specified 8-bit data
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_free_data_register_write(uint8_t free_data)
|
||||
{
|
||||
CRC_FDATA = (uint32_t)free_data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief calculate the CRC value of a 32-bit data
|
||||
\param[in] sdata: specified 32-bit data
|
||||
\param[out] none
|
||||
\retval 32-bit value calculated by CRC
|
||||
*/
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata)
|
||||
{
|
||||
CRC_DATA = sdata;
|
||||
return (CRC_DATA);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief calculate the CRC value of an array of 32-bit values
|
||||
\param[in] array: pointer to an array of 32-bit values
|
||||
\param[in] size: size of the array
|
||||
\param[out] none
|
||||
\retval 32-bit value calculated by CRC
|
||||
*/
|
||||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
|
||||
{
|
||||
uint32_t index;
|
||||
for(index = 0U; index < size; index++){
|
||||
CRC_DATA = array[index];
|
||||
}
|
||||
return (CRC_DATA);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,110 @@
|
||||
/*!
|
||||
\file gd32vf103_dbg.c
|
||||
\brief DBG driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_dbg.h"
|
||||
|
||||
/*!
|
||||
\brief read DBG_ID code register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval DBG_ID code
|
||||
*/
|
||||
uint32_t dbg_id_get(void)
|
||||
{
|
||||
return DBG_ID;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL |= dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL &= ~dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: refer to dbg_periph_enum
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
|
||||
\arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted
|
||||
\arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
|
||||
\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_CTL |= (uint32_t)dbg_periph;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: refer to dbg_periph_enum
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
|
||||
\arg DBG_CANx_HOLD (x=0,1): hold CAN0 counter when core is halted
|
||||
\arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
|
||||
\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_CTL &= ~(uint32_t)dbg_periph;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,121 @@
|
||||
/*!
|
||||
\file gd32vf103_eclic.c
|
||||
\brief ECLIC(Enhancement Core-Local Interrupt Controller) driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_eclic.h"
|
||||
#include "riscv_encoding.h"
|
||||
|
||||
#define REG_DBGMCU2 ((uint32_t)0xE0042008)
|
||||
#define REG_DBGMCU2EN ((uint32_t)0xE004200C)
|
||||
|
||||
/*!
|
||||
\brief enable the global interrupt
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void eclic_global_interrupt_enable(void){
|
||||
/* set machine interrupt enable bit */
|
||||
set_csr(mstatus, MSTATUS_MIE);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the global interrupt
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void eclic_global_interrupt_disable(void){
|
||||
/* clear machine interrupt enable bit */
|
||||
clear_csr(mstatus, MSTATUS_MIE);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the priority group
|
||||
\param[in] prigroup: specify the priority group
|
||||
\arg ECLIC_PRIGROUP_LEVEL0_PRIO4
|
||||
\arg ECLIC_PRIGROUP_LEVEL1_PRIO3
|
||||
\arg ECLIC_PRIGROUP_LEVEL2_PRIO2
|
||||
\arg ECLIC_PRIGROUP_LEVEL3_PRIO1
|
||||
\arg ECLIC_PRIGROUP_LEVEL4_PRIO0
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void eclic_priority_group_set(uint32_t prigroup) {
|
||||
eclic_set_nlbits(prigroup);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the interrupt request
|
||||
\param[in] source: interrupt request, detailed in IRQn_Type
|
||||
\param[in] level: the level needed to set (maximum is 15, refer to the priority group)
|
||||
\param[in] priority: the priority needed to set (maximum is 15, refer to the priority group)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void eclic_irq_enable(uint32_t source, uint8_t lvl_abs, uint8_t priority) {
|
||||
eclic_enable_interrupt(source);
|
||||
eclic_set_irq_lvl_abs(source, lvl_abs);
|
||||
eclic_set_irq_priority(source, priority);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the interrupt request
|
||||
\param[in] source: interrupt request, detailed in IRQn_Type
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void eclic_irq_disable(uint32_t source) {
|
||||
eclic_disable_interrupt(source);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset system
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void eclic_system_reset(void) {
|
||||
REG32(REG_DBGMCU2EN) = 0x4b5a6978;
|
||||
REG32(REG_DBGMCU2) = 0x1;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief send event(SEV)
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void eclic_send_event(void) {
|
||||
set_csr(0x812, 0x1);
|
||||
}
|
||||
@@ -0,0 +1,164 @@
|
||||
/*!
|
||||
\file gd32vf103_exmc.c
|
||||
\brief EXMC driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_exmc.h"
|
||||
|
||||
/* EXMC bank0 register reset value */
|
||||
#define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DAU)
|
||||
#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU)
|
||||
|
||||
/* EXMC register bit offset */
|
||||
#define SNCTL_NRMUX_OFFSET ((uint32_t)1U)
|
||||
#define SNCTL_WREN_OFFSET ((uint32_t)12U)
|
||||
#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U)
|
||||
#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U)
|
||||
|
||||
#define SNTCFG_AHLD_OFFSET ((uint32_t)4U)
|
||||
#define SNTCFG_DSET_OFFSET ((uint32_t)8U)
|
||||
#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U)
|
||||
|
||||
/*!
|
||||
\brief deinitialize EXMC NOR/SRAM region
|
||||
\param[in] norsram_region: select the region of bank0
|
||||
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exmc_norsram_deinit(uint32_t norsram_region)
|
||||
{
|
||||
/* reset the registers */
|
||||
if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){
|
||||
EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET;
|
||||
}
|
||||
|
||||
EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief initialize the structure exmc_norsram_parameter_struct
|
||||
\param[in] none
|
||||
\param[out] exmc_norsram_init_struct: the initialized structure exmc_norsram_parameter_struct pointer
|
||||
\retval none
|
||||
*/
|
||||
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
|
||||
{
|
||||
/* configure the structure with default value */
|
||||
exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0;
|
||||
exmc_norsram_init_struct->address_data_mux = ENABLE;
|
||||
exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM;
|
||||
exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_16B;
|
||||
exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
|
||||
exmc_norsram_init_struct->memory_write = ENABLE;
|
||||
exmc_norsram_init_struct->nwait_signal = ENABLE;
|
||||
exmc_norsram_init_struct->asyn_wait = DISABLE;
|
||||
|
||||
/* read/write timing configure */
|
||||
exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU;
|
||||
exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU;
|
||||
exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU;
|
||||
exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief initialize EXMC NOR/SRAM region
|
||||
\param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter
|
||||
norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0
|
||||
asyn_wait: ENABLE or DISABLE
|
||||
nwait_signal: ENABLE or DISABLE
|
||||
memory_write: ENABLE or DISABLE
|
||||
nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH
|
||||
databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B
|
||||
memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR
|
||||
address_data_mux: ENABLE
|
||||
read_write_timing: structure exmc_norsram_timing_parameter_struct set the time
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
|
||||
{
|
||||
uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U;
|
||||
|
||||
/* get the register value */
|
||||
snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
|
||||
|
||||
/* clear relative bits */
|
||||
snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL |
|
||||
EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX));
|
||||
|
||||
snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
|
||||
exmc_norsram_init_struct->memory_type |
|
||||
exmc_norsram_init_struct->databus_width |
|
||||
exmc_norsram_init_struct->nwait_polarity |
|
||||
(exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
|
||||
(exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
|
||||
(exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET);
|
||||
|
||||
sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )|
|
||||
(((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) |
|
||||
(((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) |
|
||||
(((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT );
|
||||
|
||||
/* nor flash access enable */
|
||||
if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){
|
||||
snctl |= (uint32_t)EXMC_SNCTL_NREN;
|
||||
}
|
||||
|
||||
/* configure the registers */
|
||||
EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl;
|
||||
EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable EXMC NOR/PSRAM bank region
|
||||
\param[in] norsram_region: specify the region of NOR/PSRAM bank
|
||||
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exmc_norsram_enable(uint32_t norsram_region)
|
||||
{
|
||||
EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable EXMC NOR/PSRAM bank region
|
||||
\param[in] norsram_region: specify the region of NOR/PSRAM bank
|
||||
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exmc_norsram_disable(uint32_t norsram_region)
|
||||
{
|
||||
EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN;
|
||||
}
|
||||
@@ -0,0 +1,254 @@
|
||||
/*!
|
||||
\file gd32vf103_exti.c
|
||||
\brief EXTI driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_exti.h"
|
||||
|
||||
#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U)
|
||||
|
||||
/*!
|
||||
\brief deinitialize the EXTI
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_deinit(void)
|
||||
{
|
||||
/* reset the value of all the EXTI registers */
|
||||
EXTI_INTEN = EXTI_REG_RESET_VALUE;
|
||||
EXTI_EVEN = EXTI_REG_RESET_VALUE;
|
||||
EXTI_RTEN = EXTI_REG_RESET_VALUE;
|
||||
EXTI_FTEN = EXTI_REG_RESET_VALUE;
|
||||
EXTI_SWIEV = EXTI_REG_RESET_VALUE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief initialize the EXTI
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..18): EXTI line x
|
||||
\param[in] mode: interrupt or event mode, refer to exti_mode_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_INTERRUPT: interrupt mode
|
||||
\arg EXTI_EVENT: event mode
|
||||
\param[in] trig_type: trigger type, refer to exti_trig_type_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_TRIG_RISING: rising edge trigger
|
||||
\arg EXTI_TRIG_FALLING: falling edge trigger
|
||||
\arg EXTI_TRIG_BOTH: rising edge and falling edge trigger
|
||||
\arg EXTI_TRIG_NONE: without rising edge or falling edge trigger
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
|
||||
{
|
||||
/* reset the EXTI line x */
|
||||
EXTI_INTEN &= ~(uint32_t) linex;
|
||||
EXTI_EVEN &= ~(uint32_t) linex;
|
||||
EXTI_RTEN &= ~(uint32_t) linex;
|
||||
EXTI_FTEN &= ~(uint32_t) linex;
|
||||
|
||||
/* set the EXTI mode and enable the interrupts or events from EXTI line x */
|
||||
switch (mode) {
|
||||
case EXTI_INTERRUPT:
|
||||
EXTI_INTEN |= (uint32_t) linex;
|
||||
break;
|
||||
case EXTI_EVENT:
|
||||
EXTI_EVEN |= (uint32_t) linex;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* set the EXTI trigger type */
|
||||
switch (trig_type) {
|
||||
case EXTI_TRIG_RISING:
|
||||
EXTI_RTEN |= (uint32_t) linex;
|
||||
EXTI_FTEN &= ~(uint32_t) linex;
|
||||
break;
|
||||
case EXTI_TRIG_FALLING:
|
||||
EXTI_RTEN &= ~(uint32_t) linex;
|
||||
EXTI_FTEN |= (uint32_t) linex;
|
||||
break;
|
||||
case EXTI_TRIG_BOTH:
|
||||
EXTI_RTEN |= (uint32_t) linex;
|
||||
EXTI_FTEN |= (uint32_t) linex;
|
||||
break;
|
||||
case EXTI_TRIG_NONE:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the interrupts from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..18): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_interrupt_enable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_INTEN |= (uint32_t) linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the events from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..18): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_event_enable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_EVEN |= (uint32_t) linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the interrupt from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..18): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_interrupt_disable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_INTEN &= ~(uint32_t) linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the events from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..18): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_event_disable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_EVEN &= ~(uint32_t) linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get EXTI lines flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..18): EXTI line x
|
||||
\param[out] none
|
||||
\retval FlagStatus: status of flag (RESET or SET)
|
||||
*/
|
||||
FlagStatus exti_flag_get(exti_line_enum linex)
|
||||
{
|
||||
if (RESET != (EXTI_PD & (uint32_t) linex)) {
|
||||
return SET;
|
||||
} else {
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear EXTI lines pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..18): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_flag_clear(exti_line_enum linex)
|
||||
{
|
||||
EXTI_PD = (uint32_t) linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get EXTI lines flag when the interrupt flag is set
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..18): EXTI line x
|
||||
\param[out] none
|
||||
\retval FlagStatus: status of flag (RESET or SET)
|
||||
*/
|
||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
|
||||
{
|
||||
uint32_t flag_left, flag_right;
|
||||
|
||||
flag_left = EXTI_PD & (uint32_t) linex;
|
||||
flag_right = EXTI_INTEN & (uint32_t) linex;
|
||||
|
||||
if ((RESET != flag_left) && (RESET != flag_right)) {
|
||||
return SET;
|
||||
} else {
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear EXTI lines pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..18): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_interrupt_flag_clear(exti_line_enum linex)
|
||||
{
|
||||
EXTI_PD = (uint32_t) linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable EXTI software interrupt event
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..18): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_software_interrupt_enable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_SWIEV |= (uint32_t) linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable EXTI software interrupt event
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..18): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_software_interrupt_disable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_SWIEV &= ~(uint32_t) linex;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,151 @@
|
||||
/*!
|
||||
\file gd32vf103_fwdgt.c
|
||||
\brief FWDGT driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_fwdgt.h"
|
||||
|
||||
/* write value to FWDGT_CTL_CMD bit field */
|
||||
#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
|
||||
/* write value to FWDGT_RLD_RLD bit field */
|
||||
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/*!
|
||||
\brief enable write access to FWDGT_PSC and FWDGT_RLD
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_write_enable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable write access to FWDGT_PSC and FWDGT_RLD
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_write_disable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief start the free watchdog timer counter
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_enable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_KEY_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reload the counter of FWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_counter_reload(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure counter reload value, and prescaler divider value
|
||||
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
||||
\param[in] prescaler_div: FWDGT prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
|
||||
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
|
||||
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
|
||||
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
|
||||
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
|
||||
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
|
||||
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
|
||||
{
|
||||
uint32_t timeout = FWDGT_PSC_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_PSC,and FWDGT_RLD */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
/* wait until the PUD flag to be reset */
|
||||
do{
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
|
||||
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status){
|
||||
return ERROR;
|
||||
}
|
||||
/* configure FWDGT */
|
||||
FWDGT_PSC = (uint32_t)prescaler_div;
|
||||
|
||||
timeout = FWDGT_RLD_TIMEOUT;
|
||||
/* wait until the RUD flag to be reset */
|
||||
do{
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
|
||||
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status){
|
||||
return ERROR;
|
||||
}
|
||||
FWDGT_RLD = RLD_RLD(reload_value);
|
||||
/* reload the counter */
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get flag state of FWDGT
|
||||
\param[in] flag: flag to get
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
|
||||
\arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag)
|
||||
{
|
||||
if(FWDGT_STAT & flag){
|
||||
return SET;
|
||||
}
|
||||
|
||||
return RESET;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user