mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-24 06:45:03 +08:00
Gedare Bloom
8e6ded473c
This is an update of many lingering embedded brains GmbH licenses from the RTEMS License to the 2-BSD license where possible depending on the joint copyrights. Updates #3053.
149 lines
4.9 KiB
C
149 lines
4.9 KiB
C
/*
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* Copyright (C) 2016 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_ARM_ATSAM_SC16IS752_H
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#define LIBBSP_ARM_ATSAM_SC16IS752_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* General register set */
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#define SC16IS752_RHR 0x0
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#define SC16IS752_THR 0x0
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#define SC16IS752_IER 0x1
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#define SC16IS752_FCR 0x2
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#define SC16IS752_IIR 0x2
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#define SC16IS752_LCR 0x3
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#define SC16IS752_MCR 0x4
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#define SC16IS752_LSR 0x5
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#define SC16IS752_MSR 0x6
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#define SC16IS752_TCR 0x6
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#define SC16IS752_SPR 0x7
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#define SC16IS752_TLR 0x7
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#define SC16IS752_TXLVL 0x8
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#define SC16IS752_RXLVL 0x9
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#define SC16IS752_IODIR 0xA
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#define SC16IS752_IOSTATE 0xB
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#define SC16IS752_IOINTENA 0xC
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#define SC16IS752_IOCONTROL 0xE
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#define SC16IS752_EFCR 0xF
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/* Special register set */
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#define SC16IS752_DLL 0x0
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#define SC16IS752_DLH 0x1
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/* Enhanced register set */
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#define SC16IS752_EFR 0x2
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#define SC16IS752_XON1 0x4
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#define SC16IS752_XON2 0x5
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#define SC16IS752_XOFF1 0x6
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#define SC16IS752_XOFF2 0x7
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/* FCR */
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#define SC16IS752_FCR_FIFO_EN 0x01
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#define SC16IS752_FCR_RX_FIFO_RST 0x02
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#define SC16IS752_FCR_TX_FIFO_RST 0x04
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#define SC16IS752_FCR_TX_FIFO_TRG_8 0x00
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#define SC16IS752_FCR_TX_FIFO_TRG_16 0x10
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#define SC16IS752_FCR_TX_FIFO_TRG_32 0x20
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#define SC16IS752_FCR_TX_FIFO_TRG_56 0x30
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#define SC16IS752_FCR_RX_FIFO_TRG_8 0x00
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#define SC16IS752_FCR_RX_FIFO_TRG_16 0x40
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#define SC16IS752_FCR_RX_FIFO_TRG_56 0x80
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#define SC16IS752_FCR_RX_FIFO_TRG_60 0xc0
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/* EFCR */
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#define SC16IS752_EFCR_RS485_ENABLE (1u << 0)
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#define SC16IS752_EFCR_RX_DISABLE (1u << 1)
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#define SC16IS752_EFCR_TX_DISABLE (1u << 2)
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#define SC16IS752_EFCR_RTSCON (1u << 4)
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#define SC16IS752_EFCR_RTSINVER (1u << 5)
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/* IER */
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#define SC16IS752_IER_RHR (1u << 0)
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#define SC16IS752_IER_THR (1u << 1)
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#define SC16IS752_IER_RECEIVE_LINE_STATUS (1u << 2)
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#define SC16IS752_IER_MODEM_STATUS (1u << 3)
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#define SC16IS752_IER_SLEEP_MODE (1u << 4)
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#define SC16IS752_IER_XOFF (1u << 5)
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#define SC16IS752_IER_RTS (1u << 6)
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#define SC16IS752_IER_CTS (1u << 7)
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/* IIR */
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#define SC16IS752_IIR_TX_INTERRUPT (1u << 1)
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#define SC16IS752_IIR_RX_INTERRUPT (1u << 2)
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/* LCR */
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#define SC16IS752_LCR_CHRL_5_BIT (0u << 1) | (0u << 0)
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#define SC16IS752_LCR_CHRL_6_BIT (0u << 1) | (1u << 0)
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#define SC16IS752_LCR_CHRL_7_BIT (1u << 1) | (0u << 0)
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#define SC16IS752_LCR_CHRL_8_BIT (1u << 1) | (1u << 0)
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#define SC16IS752_LCR_2_STOP_BIT (1u << 2)
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#define SC16IS752_LCR_SET_PARITY (1u << 3)
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#define SC16IS752_LCR_EVEN_PARITY (1u << 4)
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#define SC16IS752_LCR_BREAK (1u << 5)
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#define SC16IS752_LCR_ENABLE_DIVISOR (1u << 7)
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/* LSR */
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#define SC16IS752_LSR_TXEMPTY (1u << 5)
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#define SC16IS752_LSR_RXRDY (1u << 0)
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#define SC16IS752_LSR_ERROR_BITS (7u << 2)
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/* MCR */
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#define SC16IS752_MCR_DTR (1u << 0)
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#define SC16IS752_MCR_RTS (1u << 1)
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#define SC16IS752_MCR_TCR_TLR (1u << 2)
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#define SC16IS752_MCR_LOOPBACK (1u << 4)
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#define SC16IS752_MCR_XON_ANY (1u << 5)
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#define SC16IS752_MCR_IRDA_ENABLE (1u << 6)
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#define SC16IS752_MCR_PRESCALE_NEEDED (1u << 7)
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/* MSR */
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#define SC16IS752_MSR_dCTS (1u << 0)
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#define SC16IS752_MSR_dDSR (1u << 1)
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#define SC16IS752_MSR_dRI (1u << 2)
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#define SC16IS752_MSR_dCD (1u << 3)
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#define SC16IS752_MSR_CTS (1u << 4)
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#define SC16IS752_MSR_DSR (1u << 5)
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#define SC16IS752_MSR_RI (1u << 6)
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#define SC16IS752_MSR_CD (1u << 7)
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/* EFR */
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#define SC16IS752_EFR_ENHANCED_FUNC_ENABLE (1u << 4)
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#define SC16IS752_EFR_SPECIAL_CHAR_DETECT (1u << 5)
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#define SC16IS752_EFR_RTS_FLOW_CTRL_EN (1u << 6)
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#define SC16IS752_EFR_CTS_FLOW_CTRL_EN (1u << 7)
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/* IOCONTROL: User accessible. Therefore see sc16is752.h for the defines. */
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#define SC16IS752_FIFO_DEPTH 64
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_ATSAM_SC16IS752_H */
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