Ralf Kirchner f73cfe99d0 bsp/altera-cyclone-v: New BSP ...

Implemented so far:
- nocache heap for uncached RAM
- basic timer
- level 1 cache handling for arm cache controller
  in arm-cache-l1.h
- level 2 L2C-310 cache controller
- MMU
- DWMAC 1000 ethernet controller
- basic errata handling
- smp startup for second core

2014-03-13 16:22:00 +01:00

..

src

bsp/altera-cyclone-v: New BSP

2014-03-13 16:22:00 +01:00

acinclude.m4

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ACKNOWLEDGEMENTS

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configure.ac

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Makefile.am

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TOOL_TARGETS

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