mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-22 06:35:55 +08:00
Christian Mauderer
48f6a6c302
The following files have been imported:
cp ${SDK}/boards/evkbimxrt1050/project_template/clock_config.c nxp/boards/evkbimxrt1050
cp ${SDK}/boards/evkbimxrt1050/project_template/clock_config.h include/fsl_clock_config.h
cp ${SDK}/boards/evkbimxrt1050/project_template/dcd.c start/flash-dcd.c
cp ${SDK}/boards/evkbimxrt1050/project_template/pin_mux.c nxp/boards/evkbimxrt1050
cp ${SDK}/boards/evkbimxrt1050/project_template/pin_mux.h include/fsl_pin_mux.h
cp ${SDK}/boards/evkbimxrt1050/xip/evkbimxrt1050_flexspi_nor_config.h include/fsl_flexspi_nor_config.h
cp ${SDK}/devices/MIMXRT1052/MIMXRT1052.h include
cp ${SDK}/devices/MIMXRT1052/MIMXRT1052_features.h include
cp ${SDK}/devices/MIMXRT1052/drivers/fsl_*.c nxp/devices/MIMXRT1052/drivers
cp ${SDK}/devices/MIMXRT1052/drivers/fsl_*.h include
cp ${SDK}/devices/MIMXRT1052/fsl_device_registers.h include
cp ${SDK}/devices/MIMXRT1052/system_MIMXRT1052.h include/
cp ${SDK}/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.c nxp/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.c
cp ${SDK}/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.h include
Update #4180
135 lines
5.0 KiB
C
135 lines
5.0 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_AIPSTZ_H_
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#define _FSL_AIPSTZ_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup aipstz
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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#define FSL_AIPSTZ_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */
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/*@}*/
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/*! @brief List of AIPSTZ privilege configuration.*/
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typedef enum _aipstz_master_privilege_level
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{
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kAIPSTZ_MasterBufferedWriteEnable = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */
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kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */
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kAIPSTZ_MasterTrustedForWriteEnable = (1U << 1), /*!< This master is trusted for write accesses. */
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kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */
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} aipstz_master_privilege_level_t;
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/*! @brief List of AIPSTZ masters. Organized by width for the 8-15 bits and shift for lower 8 bits.*/
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typedef enum _aipstz_master
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{
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kAIPSTZ_Master0 = (0x400U | 28U),
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kAIPSTZ_Master1 = (0x400U | 24U),
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kAIPSTZ_Master2 = (0x400U | 20U),
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kAIPSTZ_Master3 = (0x400U | 16U),
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kAIPSTZ_Master5 = (0x400U | 8U)
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} aipstz_master_t;
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/*! @brief List of AIPSTZ peripheral access control configuration.*/
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typedef enum _aipstz_peripheral_access_control
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{
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kAIPSTZ_PeripheralAllowUntrustedMaster = 1U,
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kAIPSTZ_PeripheralWriteProtected = (1U << 1),
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kAIPSTZ_PeripheralRequireSupervisor = (1U << 2),
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kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3)
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} aipstz_peripheral_access_control_t;
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/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and
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* shift for lower 8 bits.*/
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typedef enum _aipstz_peripheral
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{
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kAIPSTZ_Peripheral0 = ((0x40 << 16) | (4 << 8) | 28),
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kAIPSTZ_Peripheral1 = ((0x40 << 16) | (4 << 8) | 24),
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kAIPSTZ_Peripheral2 = ((0x40 << 16) | (4 << 8) | 20),
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kAIPSTZ_Peripheral3 = ((0x40 << 16) | (4 << 8) | 16),
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kAIPSTZ_Peripheral4 = ((0x40 << 16) | (4 << 8) | 12),
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kAIPSTZ_Peripheral5 = ((0x40 << 16) | (4 << 8) | 8),
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kAIPSTZ_Peripheral6 = ((0x40 << 16) | (4 << 8) | 4),
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kAIPSTZ_Peripheral7 = ((0x40 << 16) | (4 << 8) | 0),
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kAIPSTZ_Peripheral8 = ((0x44 << 16) | (4 << 8) | 28),
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kAIPSTZ_Peripheral9 = ((0x44 << 16) | (4 << 8) | 24),
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kAIPSTZ_Peripheral10 = ((0x44 << 16) | (4 << 8) | 20),
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kAIPSTZ_Peripheral11 = ((0x44 << 16) | (4 << 8) | 16),
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kAIPSTZ_Peripheral12 = ((0x44 << 16) | (4 << 8) | 12),
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kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8),
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kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4),
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kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0),
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kAIPSTZ_Peripheral16 = ((0x48 << 16) | (4 << 8) | 28),
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kAIPSTZ_Peripheral17 = ((0x48 << 16) | (4 << 8) | 24),
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kAIPSTZ_Peripheral18 = ((0x48 << 16) | (4 << 8) | 20),
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kAIPSTZ_Peripheral19 = ((0x48 << 16) | (4 << 8) | 16),
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kAIPSTZ_Peripheral20 = ((0x48 << 16) | (4 << 8) | 12),
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kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8),
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kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4),
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kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0),
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kAIPSTZ_Peripheral24 = ((0x4C << 16) | (4 << 8) | 28),
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kAIPSTZ_Peripheral25 = ((0x4C << 16) | (4 << 8) | 24),
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kAIPSTZ_Peripheral26 = ((0x4C << 16) | (4 << 8) | 20),
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kAIPSTZ_Peripheral27 = ((0x4C << 16) | (4 << 8) | 16),
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kAIPSTZ_Peripheral28 = ((0x4C << 16) | (4 << 8) | 12),
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kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8),
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kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4),
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kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0),
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kAIPSTZ_Peripheral32 = ((0x50 << 16) | (4 << 8) | 28),
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kAIPSTZ_Peripheral33 = ((0x50 << 16) | (4 << 8) | 24)
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} aipstz_peripheral_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name Initialization and deinitialization
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* @{
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*/
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/*!
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* @brief Configure the privilege level for master.
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*
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* @param base AIPSTZ peripheral base pointer
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* @param master Masters for AIPSTZ.
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* @param privilegeConfig Configuration is ORed from @ref aipstz_master_privilege_level_t.
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*/
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void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig);
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/*!
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* @brief Configure the access for peripheral.
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*
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* @param base AIPSTZ peripheral base pointer
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* @param peripheral Peripheral for AIPSTZ.
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* @param accessControl Configuration is ORed from @ref aipstz_peripheral_access_control_t.
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*/
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void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl);
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/*! @}*/
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#if defined(__cplusplus)
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}
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#endif
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/*! @}*/
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#endif /* _FSL_AIPSTZ_H_ */
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